1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 AES register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_AES_H 31 #define EFR32MG24_AES_H 32 33 /**************************************************************************//** 34 * @addtogroup Parts 35 * @{ 36 ******************************************************************************/ 37 /**************************************************************************//** 38 * @defgroup EFR32MG24_AES AES 39 * @{ 40 * @brief EFR32MG24 AES Register Declaration. 41 *****************************************************************************/ 42 43 /** AES Register Declaration. */ 44 typedef struct { 45 __IOM uint32_t FETCHADDR; /**< Fetcher Address */ 46 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 47 __IOM uint32_t FETCHLEN; /**< Fetcher Length */ 48 __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ 49 __IOM uint32_t PUSHADDR; /**< Pusher Address */ 50 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 51 __IOM uint32_t PUSHLEN; /**< Pusher Length */ 52 __IOM uint32_t IEN; /**< Interrupt Enable */ 53 uint32_t RESERVED2[2U]; /**< Reserved for future use */ 54 __IM uint32_t IF; /**< Interrupt Flags */ 55 uint32_t RESERVED3[1U]; /**< Reserved for future use */ 56 __IOM uint32_t IF_CLR; /**< Interrupt status clear */ 57 __IOM uint32_t CTRL; /**< Control register */ 58 __IOM uint32_t CMD; /**< Command register */ 59 __IM uint32_t STATUS; /**< Status register */ 60 uint32_t RESERVED4[240U]; /**< Reserved for future use */ 61 __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ 62 __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ 63 __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ 64 __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ 65 __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ 66 __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ 67 } AES_TypeDef; 68 /** @} End of group EFR32MG24_AES */ 69 70 /**************************************************************************//** 71 * @addtogroup EFR32MG24_AES 72 * @{ 73 * @defgroup EFR32MG24_AES_BitFields AES Bit Fields 74 * @{ 75 *****************************************************************************/ 76 77 /* Bit fields for AES FETCHADDR */ 78 #define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ 79 #define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ 80 #define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ 81 #define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ 82 #define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ 83 #define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ 84 85 /* Bit fields for AES FETCHLEN */ 86 #define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ 87 #define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ 88 #define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ 89 #define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ 90 #define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ 91 #define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ 92 #define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ 93 #define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ 94 #define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ 95 #define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ 96 #define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ 97 #define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ 98 #define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ 99 #define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ 100 #define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ 101 #define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ 102 103 /* Bit fields for AES FETCHTAG */ 104 #define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ 105 #define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ 106 #define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ 107 #define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ 108 #define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ 109 #define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ 110 111 /* Bit fields for AES PUSHADDR */ 112 #define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ 113 #define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ 114 #define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ 115 #define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ 116 #define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ 117 #define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ 118 119 /* Bit fields for AES PUSHLEN */ 120 #define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ 121 #define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ 122 #define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ 123 #define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ 124 #define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ 125 #define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ 126 #define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ 127 #define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ 128 #define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ 129 #define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ 130 #define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ 131 #define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ 132 #define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ 133 #define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ 134 #define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ 135 #define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ 136 #define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ 137 #define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ 138 #define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ 139 #define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ 140 #define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ 141 142 /* Bit fields for AES IEN */ 143 #define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ 144 #define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ 145 #define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ 146 #define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ 147 #define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ 148 #define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 149 #define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ 150 #define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ 151 #define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ 152 #define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ 153 #define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 154 #define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ 155 #define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ 156 #define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ 157 #define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ 158 #define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 159 #define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ 160 #define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ 161 #define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ 162 #define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ 163 #define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 164 #define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ 165 #define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ 166 #define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ 167 #define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ 168 #define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 169 #define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ 170 #define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ 171 #define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ 172 #define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ 173 #define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 174 #define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ 175 176 /* Bit fields for AES IF */ 177 #define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ 178 #define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ 179 #define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ 180 #define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ 181 #define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ 182 #define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 183 #define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ 184 #define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ 185 #define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ 186 #define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ 187 #define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 188 #define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ 189 #define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ 190 #define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ 191 #define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ 192 #define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 193 #define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ 194 #define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ 195 #define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ 196 #define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ 197 #define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 198 #define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ 199 #define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ 200 #define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ 201 #define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ 202 #define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 203 #define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ 204 #define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ 205 #define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ 206 #define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ 207 #define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 208 #define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ 209 210 /* Bit fields for AES IF_CLR */ 211 #define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ 212 #define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ 213 #define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ 214 #define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ 215 #define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ 216 #define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ 217 #define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ 218 #define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ 219 #define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ 220 #define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ 221 #define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ 222 #define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ 223 #define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ 224 #define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ 225 #define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ 226 #define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ 227 #define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ 228 #define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ 229 #define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ 230 #define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ 231 #define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ 232 #define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ 233 #define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ 234 #define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ 235 #define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ 236 #define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ 237 #define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ 238 #define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ 239 #define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ 240 #define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ 241 #define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ 242 #define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ 243 244 /* Bit fields for AES CTRL */ 245 #define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ 246 #define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ 247 #define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ 248 #define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ 249 #define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ 250 #define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 251 #define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ 252 #define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ 253 #define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ 254 #define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ 255 #define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 256 #define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ 257 #define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ 258 #define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ 259 #define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ 260 #define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 261 #define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ 262 #define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ 263 #define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ 264 #define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ 265 #define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 266 #define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ 267 #define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ 268 #define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ 269 #define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ 270 #define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 271 #define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ 272 273 /* Bit fields for AES CMD */ 274 #define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ 275 #define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ 276 #define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ 277 #define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ 278 #define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ 279 #define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ 280 #define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ 281 #define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ 282 #define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ 283 #define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ 284 #define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ 285 #define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ 286 287 /* Bit fields for AES STATUS */ 288 #define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ 289 #define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ 290 #define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ 291 #define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ 292 #define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ 293 #define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 294 #define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ 295 #define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ 296 #define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ 297 #define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ 298 #define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 299 #define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ 300 #define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ 301 #define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ 302 #define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ 303 #define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 304 #define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ 305 #define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ 306 #define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ 307 #define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ 308 #define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 309 #define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ 310 #define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ 311 #define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ 312 #define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ 313 #define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 314 #define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ 315 #define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ 316 #define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ 317 #define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 318 #define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ 319 320 /* Bit fields for AES INCL_IPS_HW_CFG */ 321 #define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ 322 #define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ 323 #define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ 324 #define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ 325 #define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ 326 #define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ 327 #define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ 328 #define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ 329 #define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ 330 #define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ 331 #define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ 332 #define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ 333 #define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ 334 #define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ 335 #define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ 336 #define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ 337 #define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ 338 #define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ 339 #define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ 340 #define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ 341 #define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ 342 #define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ 343 #define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ 344 #define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ 345 #define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ 346 #define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ 347 #define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ 348 #define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ 349 #define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ 350 #define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ 351 #define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ 352 #define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ 353 #define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ 354 #define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ 355 #define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ 356 #define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ 357 #define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ 358 #define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ 359 #define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ 360 #define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ 361 #define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ 362 #define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ 363 #define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ 364 #define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ 365 #define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ 366 #define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ 367 #define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ 368 #define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ 369 #define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ 370 #define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ 371 #define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ 372 #define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ 373 #define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ 374 #define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ 375 #define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ 376 #define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ 377 #define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ 378 379 /* Bit fields for AES BA411E_HW_CFG_1 */ 380 #define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ 381 #define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ 382 #define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ 383 #define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ 384 #define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ 385 #define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ 386 #define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ 387 #define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ 388 #define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ 389 #define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ 390 #define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ 391 #define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ 392 #define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ 393 #define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ 394 #define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ 395 #define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ 396 #define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ 397 #define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ 398 #define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ 399 #define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ 400 401 /* Bit fields for AES BA411E_HW_CFG_2 */ 402 #define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ 403 #define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ 404 #define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ 405 #define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ 406 #define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ 407 #define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ 408 409 /* Bit fields for AES BA413_HW_CFG */ 410 #define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ 411 #define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ 412 #define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ 413 #define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ 414 #define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ 415 #define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ 416 #define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ 417 #define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ 418 #define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ 419 #define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ 420 #define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ 421 #define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ 422 #define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ 423 #define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ 424 #define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ 425 #define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ 426 #define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ 427 #define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ 428 #define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ 429 #define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ 430 #define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ 431 432 /* Bit fields for AES BA418_HW_CFG */ 433 #define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ 434 #define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ 435 #define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ 436 #define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ 437 #define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ 438 #define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ 439 #define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ 440 441 /* Bit fields for AES BA419_HW_CFG */ 442 #define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ 443 #define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ 444 #define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ 445 #define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ 446 #define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ 447 #define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ 448 449 /** @} End of group EFR32MG24_AES_BitFields */ 450 /** @} End of group EFR32MG24_AES */ 451 /** @} End of group Parts */ 452 453 #endif /* EFR32MG24_AES_H */ 454
