1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 ULFRCO register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_ULFRCO_H 31 #define EFR32MG21_ULFRCO_H 32 #define ULFRCO_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG21_ULFRCO ULFRCO 40 * @{ 41 * @brief EFR32MG21 ULFRCO Register Declaration. 42 *****************************************************************************/ 43 44 /** ULFRCO Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP version */ 47 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 48 __IM uint32_t STATUS; /**< Status Register */ 49 uint32_t RESERVED1[2U]; /**< Reserved for future use */ 50 __IOM uint32_t IF; /**< Interrupt Flag Register */ 51 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 52 uint32_t RESERVED2[1017U]; /**< Reserved for future use */ 53 __IM uint32_t IPVERSION_SET; /**< IP version */ 54 uint32_t RESERVED3[1U]; /**< Reserved for future use */ 55 __IM uint32_t STATUS_SET; /**< Status Register */ 56 uint32_t RESERVED4[2U]; /**< Reserved for future use */ 57 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 58 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 59 uint32_t RESERVED5[1017U]; /**< Reserved for future use */ 60 __IM uint32_t IPVERSION_CLR; /**< IP version */ 61 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 62 __IM uint32_t STATUS_CLR; /**< Status Register */ 63 uint32_t RESERVED7[2U]; /**< Reserved for future use */ 64 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 65 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 66 uint32_t RESERVED8[1017U]; /**< Reserved for future use */ 67 __IM uint32_t IPVERSION_TGL; /**< IP version */ 68 uint32_t RESERVED9[1U]; /**< Reserved for future use */ 69 __IM uint32_t STATUS_TGL; /**< Status Register */ 70 uint32_t RESERVED10[2U]; /**< Reserved for future use */ 71 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 72 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 73 } ULFRCO_TypeDef; 74 /** @} End of group EFR32MG21_ULFRCO */ 75 76 /**************************************************************************//** 77 * @addtogroup EFR32MG21_ULFRCO 78 * @{ 79 * @defgroup EFR32MG21_ULFRCO_BitFields ULFRCO Bit Fields 80 * @{ 81 *****************************************************************************/ 82 83 /* Bit fields for ULFRCO IPVERSION */ 84 #define _ULFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IPVERSION */ 85 #define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ 86 #define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ 87 #define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ 88 #define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ 89 #define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ 90 91 /* Bit fields for ULFRCO STATUS */ 92 #define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ 93 #define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ 94 #define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ 95 #define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ 96 #define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ 97 #define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ 98 #define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ 99 #define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ 100 #define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ 101 #define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ 102 #define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ 103 #define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ 104 105 /* Bit fields for ULFRCO IF */ 106 #define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ 107 #define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ 108 #define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ 109 #define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ 110 #define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ 111 #define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ 112 #define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ 113 #define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ 114 #define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ 115 #define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ 116 #define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ 117 #define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ 118 #define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ 119 #define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ 120 #define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ 121 #define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ 122 #define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ 123 124 /* Bit fields for ULFRCO IEN */ 125 #define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ 126 #define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ 127 #define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ 128 #define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ 129 #define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ 130 #define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ 131 #define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ 132 #define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ 133 #define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ 134 #define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ 135 #define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ 136 #define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ 137 #define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ 138 #define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ 139 #define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ 140 #define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ 141 #define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ 142 143 /** @} End of group EFR32MG21_ULFRCO_BitFields */ 144 /** @} End of group EFR32MG21_ULFRCO */ 145 /** @} End of group Parts */ 146 147 #endif /* EFR32MG21_ULFRCO_H */ 148
