1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 RTCC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_RTCC_H 31 #define EFR32MG21_RTCC_H 32 #define RTCC_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG21_RTCC RTCC 40 * @{ 41 * @brief EFR32MG21 RTCC Register Declaration. 42 *****************************************************************************/ 43 44 /** RTCC CC Register Group Declaration. */ 45 typedef struct { 46 __IOM uint32_t CTRL; /**< CC Channel Control Register */ 47 __IOM uint32_t OCVALUE; /**< Output Compare Value Register */ 48 __IM uint32_t ICVALUE; /**< Input Capture Value Register */ 49 } RTCC_CC_TypeDef; 50 51 /** RTCC Register Declaration. */ 52 typedef struct { 53 __IM uint32_t IPVERSION; /**< IP VERSION */ 54 __IOM uint32_t EN; /**< Module Enable Register */ 55 __IOM uint32_t CFG; /**< Configuration Register */ 56 __IOM uint32_t CMD; /**< Command Register */ 57 __IM uint32_t STATUS; /**< Status register */ 58 __IOM uint32_t IF; /**< RTCC Interrupt Flags */ 59 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 60 __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ 61 __IOM uint32_t CNT; /**< Counter Value Register */ 62 __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Valu... */ 63 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 64 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 65 RTCC_CC_TypeDef CC[3U]; /**< Capture/Compare Channel */ 66 uint32_t RESERVED0[1003U]; /**< Reserved for future use */ 67 __IM uint32_t IPVERSION_SET; /**< IP VERSION */ 68 __IOM uint32_t EN_SET; /**< Module Enable Register */ 69 __IOM uint32_t CFG_SET; /**< Configuration Register */ 70 __IOM uint32_t CMD_SET; /**< Command Register */ 71 __IM uint32_t STATUS_SET; /**< Status register */ 72 __IOM uint32_t IF_SET; /**< RTCC Interrupt Flags */ 73 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 74 __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ 75 __IOM uint32_t CNT_SET; /**< Counter Value Register */ 76 __IM uint32_t COMBCNT_SET; /**< Combined Pre-Counter and Counter Valu... */ 77 __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ 78 __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ 79 RTCC_CC_TypeDef CC_SET[3U]; /**< Capture/Compare Channel */ 80 uint32_t RESERVED1[1003U]; /**< Reserved for future use */ 81 __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ 82 __IOM uint32_t EN_CLR; /**< Module Enable Register */ 83 __IOM uint32_t CFG_CLR; /**< Configuration Register */ 84 __IOM uint32_t CMD_CLR; /**< Command Register */ 85 __IM uint32_t STATUS_CLR; /**< Status register */ 86 __IOM uint32_t IF_CLR; /**< RTCC Interrupt Flags */ 87 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 88 __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ 89 __IOM uint32_t CNT_CLR; /**< Counter Value Register */ 90 __IM uint32_t COMBCNT_CLR; /**< Combined Pre-Counter and Counter Valu... */ 91 __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ 92 __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ 93 RTCC_CC_TypeDef CC_CLR[3U]; /**< Capture/Compare Channel */ 94 uint32_t RESERVED2[1003U]; /**< Reserved for future use */ 95 __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ 96 __IOM uint32_t EN_TGL; /**< Module Enable Register */ 97 __IOM uint32_t CFG_TGL; /**< Configuration Register */ 98 __IOM uint32_t CMD_TGL; /**< Command Register */ 99 __IM uint32_t STATUS_TGL; /**< Status register */ 100 __IOM uint32_t IF_TGL; /**< RTCC Interrupt Flags */ 101 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 102 __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ 103 __IOM uint32_t CNT_TGL; /**< Counter Value Register */ 104 __IM uint32_t COMBCNT_TGL; /**< Combined Pre-Counter and Counter Valu... */ 105 __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ 106 __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ 107 RTCC_CC_TypeDef CC_TGL[3U]; /**< Capture/Compare Channel */ 108 } RTCC_TypeDef; 109 /** @} End of group EFR32MG21_RTCC */ 110 111 /**************************************************************************//** 112 * @addtogroup EFR32MG21_RTCC 113 * @{ 114 * @defgroup EFR32MG21_RTCC_BitFields RTCC Bit Fields 115 * @{ 116 *****************************************************************************/ 117 118 /* Bit fields for RTCC IPVERSION */ 119 #define _RTCC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for RTCC_IPVERSION */ 120 #define _RTCC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for RTCC_IPVERSION */ 121 #define _RTCC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for RTCC_IPVERSION */ 122 #define _RTCC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_IPVERSION */ 123 #define _RTCC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IPVERSION */ 124 #define RTCC_IPVERSION_IPVERSION_DEFAULT (_RTCC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IPVERSION */ 125 126 /* Bit fields for RTCC EN */ 127 #define _RTCC_EN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EN */ 128 #define _RTCC_EN_MASK 0x00000001UL /**< Mask for RTCC_EN */ 129 #define RTCC_EN_EN (0x1UL << 0) /**< RTCC Enable */ 130 #define _RTCC_EN_EN_SHIFT 0 /**< Shift value for RTCC_EN */ 131 #define _RTCC_EN_EN_MASK 0x1UL /**< Bit mask for RTCC_EN */ 132 #define _RTCC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EN */ 133 #define RTCC_EN_EN_DEFAULT (_RTCC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EN */ 134 135 /* Bit fields for RTCC CFG */ 136 #define _RTCC_CFG_RESETVALUE 0x00000000UL /**< Default value for RTCC_CFG */ 137 #define _RTCC_CFG_MASK 0x000000FFUL /**< Mask for RTCC_CFG */ 138 #define RTCC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ 139 #define _RTCC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for RTCC_DEBUGRUN */ 140 #define _RTCC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for RTCC_DEBUGRUN */ 141 #define _RTCC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ 142 #define _RTCC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for RTCC_CFG */ 143 #define _RTCC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for RTCC_CFG */ 144 #define RTCC_CFG_DEBUGRUN_DEFAULT (_RTCC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CFG */ 145 #define RTCC_CFG_DEBUGRUN_X0 (_RTCC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for RTCC_CFG */ 146 #define RTCC_CFG_DEBUGRUN_X1 (_RTCC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for RTCC_CFG */ 147 #define RTCC_CFG_PRECNTCCV0TOP (0x1UL << 1) /**< Pre-counter CCV0 top value enable. */ 148 #define _RTCC_CFG_PRECNTCCV0TOP_SHIFT 1 /**< Shift value for RTCC_PRECNTCCV0TOP */ 149 #define _RTCC_CFG_PRECNTCCV0TOP_MASK 0x2UL /**< Bit mask for RTCC_PRECNTCCV0TOP */ 150 #define _RTCC_CFG_PRECNTCCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ 151 #define RTCC_CFG_PRECNTCCV0TOP_DEFAULT (_RTCC_CFG_PRECNTCCV0TOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_CFG */ 152 #define RTCC_CFG_CNTCCV1TOP (0x1UL << 2) /**< CCV1 top value enable */ 153 #define _RTCC_CFG_CNTCCV1TOP_SHIFT 2 /**< Shift value for RTCC_CNTCCV1TOP */ 154 #define _RTCC_CFG_CNTCCV1TOP_MASK 0x4UL /**< Bit mask for RTCC_CNTCCV1TOP */ 155 #define _RTCC_CFG_CNTCCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ 156 #define RTCC_CFG_CNTCCV1TOP_DEFAULT (_RTCC_CFG_CNTCCV1TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CFG */ 157 #define RTCC_CFG_CNTTICK (0x1UL << 3) /**< Counter prescaler mode. */ 158 #define _RTCC_CFG_CNTTICK_SHIFT 3 /**< Shift value for RTCC_CNTTICK */ 159 #define _RTCC_CFG_CNTTICK_MASK 0x8UL /**< Bit mask for RTCC_CNTTICK */ 160 #define _RTCC_CFG_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ 161 #define _RTCC_CFG_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CFG */ 162 #define _RTCC_CFG_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CFG */ 163 #define RTCC_CFG_CNTTICK_DEFAULT (_RTCC_CFG_CNTTICK_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_CFG */ 164 #define RTCC_CFG_CNTTICK_PRESC (_RTCC_CFG_CNTTICK_PRESC << 3) /**< Shifted mode PRESC for RTCC_CFG */ 165 #define RTCC_CFG_CNTTICK_CCV0MATCH (_RTCC_CFG_CNTTICK_CCV0MATCH << 3) /**< Shifted mode CCV0MATCH for RTCC_CFG */ 166 #define _RTCC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for RTCC_CNTPRESC */ 167 #define _RTCC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for RTCC_CNTPRESC */ 168 #define _RTCC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ 169 #define _RTCC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CFG */ 170 #define _RTCC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CFG */ 171 #define _RTCC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CFG */ 172 #define _RTCC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CFG */ 173 #define _RTCC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CFG */ 174 #define _RTCC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CFG */ 175 #define _RTCC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CFG */ 176 #define _RTCC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CFG */ 177 #define _RTCC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CFG */ 178 #define _RTCC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CFG */ 179 #define _RTCC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CFG */ 180 #define _RTCC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CFG */ 181 #define _RTCC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CFG */ 182 #define _RTCC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CFG */ 183 #define _RTCC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CFG */ 184 #define _RTCC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CFG */ 185 #define RTCC_CFG_CNTPRESC_DEFAULT (_RTCC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CFG */ 186 #define RTCC_CFG_CNTPRESC_DIV1 (_RTCC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for RTCC_CFG */ 187 #define RTCC_CFG_CNTPRESC_DIV2 (_RTCC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for RTCC_CFG */ 188 #define RTCC_CFG_CNTPRESC_DIV4 (_RTCC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for RTCC_CFG */ 189 #define RTCC_CFG_CNTPRESC_DIV8 (_RTCC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for RTCC_CFG */ 190 #define RTCC_CFG_CNTPRESC_DIV16 (_RTCC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for RTCC_CFG */ 191 #define RTCC_CFG_CNTPRESC_DIV32 (_RTCC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for RTCC_CFG */ 192 #define RTCC_CFG_CNTPRESC_DIV64 (_RTCC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for RTCC_CFG */ 193 #define RTCC_CFG_CNTPRESC_DIV128 (_RTCC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for RTCC_CFG */ 194 #define RTCC_CFG_CNTPRESC_DIV256 (_RTCC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for RTCC_CFG */ 195 #define RTCC_CFG_CNTPRESC_DIV512 (_RTCC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for RTCC_CFG */ 196 #define RTCC_CFG_CNTPRESC_DIV1024 (_RTCC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for RTCC_CFG */ 197 #define RTCC_CFG_CNTPRESC_DIV2048 (_RTCC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for RTCC_CFG */ 198 #define RTCC_CFG_CNTPRESC_DIV4096 (_RTCC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for RTCC_CFG */ 199 #define RTCC_CFG_CNTPRESC_DIV8192 (_RTCC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for RTCC_CFG */ 200 #define RTCC_CFG_CNTPRESC_DIV16384 (_RTCC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for RTCC_CFG */ 201 #define RTCC_CFG_CNTPRESC_DIV32768 (_RTCC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for RTCC_CFG */ 202 203 /* Bit fields for RTCC CMD */ 204 #define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ 205 #define _RTCC_CMD_MASK 0x00000003UL /**< Mask for RTCC_CMD */ 206 #define RTCC_CMD_START (0x1UL << 0) /**< Start RTCC main counter */ 207 #define _RTCC_CMD_START_SHIFT 0 /**< Shift value for RTCC_START */ 208 #define _RTCC_CMD_START_MASK 0x1UL /**< Bit mask for RTCC_START */ 209 #define _RTCC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ 210 #define RTCC_CMD_START_DEFAULT (_RTCC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ 211 #define RTCC_CMD_STOP (0x1UL << 1) /**< Stop RTCC main counter */ 212 #define _RTCC_CMD_STOP_SHIFT 1 /**< Shift value for RTCC_STOP */ 213 #define _RTCC_CMD_STOP_MASK 0x2UL /**< Bit mask for RTCC_STOP */ 214 #define _RTCC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ 215 #define RTCC_CMD_STOP_DEFAULT (_RTCC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_CMD */ 216 217 /* Bit fields for RTCC STATUS */ 218 #define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ 219 #define _RTCC_STATUS_MASK 0x00000003UL /**< Mask for RTCC_STATUS */ 220 #define RTCC_STATUS_RUNNING (0x1UL << 0) /**< RTCC running status */ 221 #define _RTCC_STATUS_RUNNING_SHIFT 0 /**< Shift value for RTCC_RUNNING */ 222 #define _RTCC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for RTCC_RUNNING */ 223 #define _RTCC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_STATUS */ 224 #define RTCC_STATUS_RUNNING_DEFAULT (_RTCC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_STATUS */ 225 #define RTCC_STATUS_RTCCLOCKSTATUS (0x1UL << 1) /**< Lock Status */ 226 #define _RTCC_STATUS_RTCCLOCKSTATUS_SHIFT 1 /**< Shift value for RTCC_RTCCLOCKSTATUS */ 227 #define _RTCC_STATUS_RTCCLOCKSTATUS_MASK 0x2UL /**< Bit mask for RTCC_RTCCLOCKSTATUS */ 228 #define _RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_STATUS */ 229 #define _RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_STATUS */ 230 #define _RTCC_STATUS_RTCCLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_STATUS */ 231 #define RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT (_RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_STATUS */ 232 #define RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED (_RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for RTCC_STATUS */ 233 #define RTCC_STATUS_RTCCLOCKSTATUS_LOCKED (_RTCC_STATUS_RTCCLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for RTCC_STATUS */ 234 235 /* Bit fields for RTCC IF */ 236 #define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ 237 #define _RTCC_IF_MASK 0x0000001FUL /**< Mask for RTCC_IF */ 238 #define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ 239 #define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ 240 #define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ 241 #define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 242 #define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ 243 #define RTCC_IF_CNTTICK (0x1UL << 1) /**< Main counter tick */ 244 #define _RTCC_IF_CNTTICK_SHIFT 1 /**< Shift value for RTCC_CNTTICK */ 245 #define _RTCC_IF_CNTTICK_MASK 0x2UL /**< Bit mask for RTCC_CNTTICK */ 246 #define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 247 #define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ 248 #define RTCC_IF_CC0 (0x1UL << 2) /**< CC Channel n Interrupt Flag */ 249 #define _RTCC_IF_CC0_SHIFT 2 /**< Shift value for RTCC_CC0 */ 250 #define _RTCC_IF_CC0_MASK 0x4UL /**< Bit mask for RTCC_CC0 */ 251 #define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 252 #define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */ 253 #define RTCC_IF_CC1 (0x1UL << 3) /**< CC Channel n Interrupt Flag */ 254 #define _RTCC_IF_CC1_SHIFT 3 /**< Shift value for RTCC_CC1 */ 255 #define _RTCC_IF_CC1_MASK 0x8UL /**< Bit mask for RTCC_CC1 */ 256 #define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 257 #define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */ 258 #define RTCC_IF_CC2 (0x1UL << 4) /**< CC Channel n Interrupt Flag */ 259 #define _RTCC_IF_CC2_SHIFT 4 /**< Shift value for RTCC_CC2 */ 260 #define _RTCC_IF_CC2_MASK 0x10UL /**< Bit mask for RTCC_CC2 */ 261 #define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 262 #define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ 263 264 /* Bit fields for RTCC IEN */ 265 #define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ 266 #define _RTCC_IEN_MASK 0x0000001FUL /**< Mask for RTCC_IEN */ 267 #define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ 268 #define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ 269 #define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ 270 #define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 271 #define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ 272 #define RTCC_IEN_CNTTICK (0x1UL << 1) /**< CNTTICK Interrupt Enable */ 273 #define _RTCC_IEN_CNTTICK_SHIFT 1 /**< Shift value for RTCC_CNTTICK */ 274 #define _RTCC_IEN_CNTTICK_MASK 0x2UL /**< Bit mask for RTCC_CNTTICK */ 275 #define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 276 #define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ 277 #define RTCC_IEN_CC0 (0x1UL << 2) /**< CC Channel n Interrupt Enable */ 278 #define _RTCC_IEN_CC0_SHIFT 2 /**< Shift value for RTCC_CC0 */ 279 #define _RTCC_IEN_CC0_MASK 0x4UL /**< Bit mask for RTCC_CC0 */ 280 #define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 281 #define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */ 282 #define RTCC_IEN_CC1 (0x1UL << 3) /**< CC Channel n Interrupt Enable */ 283 #define _RTCC_IEN_CC1_SHIFT 3 /**< Shift value for RTCC_CC1 */ 284 #define _RTCC_IEN_CC1_MASK 0x8UL /**< Bit mask for RTCC_CC1 */ 285 #define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 286 #define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */ 287 #define RTCC_IEN_CC2 (0x1UL << 4) /**< CC Channel n Interrupt Enable */ 288 #define _RTCC_IEN_CC2_SHIFT 4 /**< Shift value for RTCC_CC2 */ 289 #define _RTCC_IEN_CC2_MASK 0x10UL /**< Bit mask for RTCC_CC2 */ 290 #define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 291 #define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ 292 293 /* Bit fields for RTCC PRECNT */ 294 #define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ 295 #define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ 296 #define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ 297 #define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ 298 #define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ 299 #define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ 300 301 /* Bit fields for RTCC CNT */ 302 #define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ 303 #define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ 304 #define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ 305 #define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ 306 #define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ 307 #define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ 308 309 /* Bit fields for RTCC COMBCNT */ 310 #define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ 311 #define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ 312 #define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ 313 #define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ 314 #define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ 315 #define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ 316 #define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ 317 #define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ 318 #define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ 319 #define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ 320 321 /* Bit fields for RTCC SYNCBUSY */ 322 #define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ 323 #define _RTCC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for RTCC_SYNCBUSY */ 324 #define RTCC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ 325 #define _RTCC_SYNCBUSY_START_SHIFT 0 /**< Shift value for RTCC_START */ 326 #define _RTCC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for RTCC_START */ 327 #define _RTCC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ 328 #define RTCC_SYNCBUSY_START_DEFAULT (_RTCC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ 329 #define RTCC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ 330 #define _RTCC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for RTCC_STOP */ 331 #define _RTCC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for RTCC_STOP */ 332 #define _RTCC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ 333 #define RTCC_SYNCBUSY_STOP_DEFAULT (_RTCC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ 334 #define RTCC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ 335 #define _RTCC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for RTCC_PRECNT */ 336 #define _RTCC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for RTCC_PRECNT */ 337 #define _RTCC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ 338 #define RTCC_SYNCBUSY_PRECNT_DEFAULT (_RTCC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ 339 #define RTCC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ 340 #define _RTCC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for RTCC_CNT */ 341 #define _RTCC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for RTCC_CNT */ 342 #define _RTCC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ 343 #define RTCC_SYNCBUSY_CNT_DEFAULT (_RTCC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ 344 345 /* Bit fields for RTCC LOCK */ 346 #define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ 347 #define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ 348 #define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ 349 #define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ 350 #define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ 351 #define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ 352 #define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ 353 #define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ 354 355 /* Bit fields for RTCC CC_CTRL */ 356 #define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ 357 #define _RTCC_CC_CTRL_MASK 0x0000007FUL /**< Mask for RTCC_CC_CTRL */ 358 #define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for RTCC_MODE */ 359 #define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for RTCC_MODE */ 360 #define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ 361 #define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ 362 #define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ 363 #define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ 364 #define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ 365 #define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ 366 #define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ 367 #define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ 368 #define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for RTCC_CMOA */ 369 #define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for RTCC_CMOA */ 370 #define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ 371 #define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ 372 #define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ 373 #define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ 374 #define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ 375 #define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ 376 #define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ 377 #define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ 378 #define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ 379 #define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ 380 #define RTCC_CC_CTRL_COMPBASE (0x1UL << 4) /**< Capture compare channel comparison base. */ 381 #define _RTCC_CC_CTRL_COMPBASE_SHIFT 4 /**< Shift value for RTCC_COMPBASE */ 382 #define _RTCC_CC_CTRL_COMPBASE_MASK 0x10UL /**< Bit mask for RTCC_COMPBASE */ 383 #define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ 384 #define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ 385 #define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ 386 #define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ 387 #define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 4) /**< Shifted mode CNT for RTCC_CC_CTRL */ 388 #define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 4) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ 389 #define _RTCC_CC_CTRL_ICEDGE_SHIFT 5 /**< Shift value for RTCC_ICEDGE */ 390 #define _RTCC_CC_CTRL_ICEDGE_MASK 0x60UL /**< Bit mask for RTCC_ICEDGE */ 391 #define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ 392 #define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ 393 #define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ 394 #define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ 395 #define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ 396 #define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ 397 #define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 5) /**< Shifted mode RISING for RTCC_CC_CTRL */ 398 #define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 5) /**< Shifted mode FALLING for RTCC_CC_CTRL */ 399 #define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 5) /**< Shifted mode BOTH for RTCC_CC_CTRL */ 400 #define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 5) /**< Shifted mode NONE for RTCC_CC_CTRL */ 401 402 /* Bit fields for RTCC CC_OCVALUE */ 403 #define _RTCC_CC_OCVALUE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_OCVALUE */ 404 #define _RTCC_CC_OCVALUE_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_OCVALUE */ 405 #define _RTCC_CC_OCVALUE_OC_SHIFT 0 /**< Shift value for RTCC_OC */ 406 #define _RTCC_CC_OCVALUE_OC_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_OC */ 407 #define _RTCC_CC_OCVALUE_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_OCVALUE */ 408 #define RTCC_CC_OCVALUE_OC_DEFAULT (_RTCC_CC_OCVALUE_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_OCVALUE */ 409 410 /* Bit fields for RTCC CC_ICVALUE */ 411 #define _RTCC_CC_ICVALUE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_ICVALUE */ 412 #define _RTCC_CC_ICVALUE_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_ICVALUE */ 413 #define _RTCC_CC_ICVALUE_IC_SHIFT 0 /**< Shift value for RTCC_IC */ 414 #define _RTCC_CC_ICVALUE_IC_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_IC */ 415 #define _RTCC_CC_ICVALUE_IC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_ICVALUE */ 416 #define RTCC_CC_ICVALUE_IC_DEFAULT (_RTCC_CC_ICVALUE_IC_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_ICVALUE */ 417 418 /** @} End of group EFR32MG21_RTCC_BitFields */ 419 /** @} End of group EFR32MG21_RTCC */ 420 /** @} End of group Parts */ 421 422 #endif /* EFR32MG21_RTCC_H */ 423
