1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 LFRCO register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_LFRCO_H 31 #define EFR32MG21_LFRCO_H 32 #define LFRCO_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG21_LFRCO LFRCO 40 * @{ 41 * @brief EFR32MG21 LFRCO Register Declaration. 42 *****************************************************************************/ 43 44 /** LFRCO Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP version */ 47 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 48 __IM uint32_t STATUS; /**< Status Register */ 49 __IOM uint32_t CAL; /**< Calibration Register */ 50 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 51 __IOM uint32_t IF; /**< Interrupt Flag Register */ 52 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 53 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 54 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 55 uint32_t RESERVED2[1015U]; /**< Reserved for future use */ 56 __IM uint32_t IPVERSION_SET; /**< IP version */ 57 uint32_t RESERVED3[1U]; /**< Reserved for future use */ 58 __IM uint32_t STATUS_SET; /**< Status Register */ 59 __IOM uint32_t CAL_SET; /**< Calibration Register */ 60 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 61 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 62 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 63 __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ 64 __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ 65 uint32_t RESERVED5[1015U]; /**< Reserved for future use */ 66 __IM uint32_t IPVERSION_CLR; /**< IP version */ 67 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 68 __IM uint32_t STATUS_CLR; /**< Status Register */ 69 __IOM uint32_t CAL_CLR; /**< Calibration Register */ 70 uint32_t RESERVED7[1U]; /**< Reserved for future use */ 71 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 72 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 73 __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ 74 __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ 75 uint32_t RESERVED8[1015U]; /**< Reserved for future use */ 76 __IM uint32_t IPVERSION_TGL; /**< IP version */ 77 uint32_t RESERVED9[1U]; /**< Reserved for future use */ 78 __IM uint32_t STATUS_TGL; /**< Status Register */ 79 __IOM uint32_t CAL_TGL; /**< Calibration Register */ 80 uint32_t RESERVED10[1U]; /**< Reserved for future use */ 81 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 82 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 83 __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ 84 __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ 85 } LFRCO_TypeDef; 86 /** @} End of group EFR32MG21_LFRCO */ 87 88 /**************************************************************************//** 89 * @addtogroup EFR32MG21_LFRCO 90 * @{ 91 * @defgroup EFR32MG21_LFRCO_BitFields LFRCO Bit Fields 92 * @{ 93 *****************************************************************************/ 94 95 /* Bit fields for LFRCO IPVERSION */ 96 #define _LFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IPVERSION */ 97 #define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ 98 #define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ 99 #define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ 100 #define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IPVERSION */ 101 #define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ 102 103 /* Bit fields for LFRCO STATUS */ 104 #define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ 105 #define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ 106 #define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ 107 #define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ 108 #define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ 109 #define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ 110 #define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ 111 #define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ 112 #define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ 113 #define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ 114 #define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ 115 #define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ 116 #define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ 117 #define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ 118 #define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ 119 #define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ 120 #define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ 121 #define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ 122 #define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ 123 #define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ 124 #define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ 125 126 /* Bit fields for LFRCO CAL */ 127 #define _LFRCO_CAL_RESETVALUE 0x000000A5UL /**< Default value for LFRCO_CAL */ 128 #define _LFRCO_CAL_MASK 0x000000FFUL /**< Mask for LFRCO_CAL */ 129 #define _LFRCO_CAL_FREQTRIM_SHIFT 0 /**< Shift value for LFRCO_FREQTRIM */ 130 #define _LFRCO_CAL_FREQTRIM_MASK 0xFFUL /**< Bit mask for LFRCO_FREQTRIM */ 131 #define _LFRCO_CAL_FREQTRIM_DEFAULT 0x000000A5UL /**< Mode DEFAULT for LFRCO_CAL */ 132 #define LFRCO_CAL_FREQTRIM_DEFAULT (_LFRCO_CAL_FREQTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CAL */ 133 134 /* Bit fields for LFRCO IF */ 135 #define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ 136 #define _LFRCO_IF_MASK 0x00000007UL /**< Mask for LFRCO_IF */ 137 #define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ 138 #define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ 139 #define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ 140 #define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ 141 #define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ 142 #define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ 143 #define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ 144 #define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ 145 #define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ 146 #define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ 147 #define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ 148 #define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ 149 #define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ 150 #define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ 151 #define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ 152 153 /* Bit fields for LFRCO IEN */ 154 #define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ 155 #define _LFRCO_IEN_MASK 0x00000007UL /**< Mask for LFRCO_IEN */ 156 #define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Interrupt Enable */ 157 #define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ 158 #define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ 159 #define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ 160 #define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ 161 #define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ 162 #define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ 163 #define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ 164 #define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ 165 #define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ 166 #define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ 167 #define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ 168 #define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ 169 #define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ 170 #define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ 171 172 /* Bit fields for LFRCO SYNCBUSY */ 173 #define _LFRCO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFRCO_SYNCBUSY */ 174 #define _LFRCO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFRCO_SYNCBUSY */ 175 #define LFRCO_SYNCBUSY_CAL (0x1UL << 0) /**< CAL Busy */ 176 #define _LFRCO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFRCO_CAL */ 177 #define _LFRCO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFRCO_CAL */ 178 #define _LFRCO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_SYNCBUSY */ 179 #define LFRCO_SYNCBUSY_CAL_DEFAULT (_LFRCO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_SYNCBUSY */ 180 181 /* Bit fields for LFRCO LOCK */ 182 #define _LFRCO_LOCK_RESETVALUE 0x00002603UL /**< Default value for LFRCO_LOCK */ 183 #define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ 184 #define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ 185 #define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ 186 #define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00002603UL /**< Mode DEFAULT for LFRCO_LOCK */ 187 #define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ 188 #define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00002603UL /**< Mode UNLOCK for LFRCO_LOCK */ 189 #define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ 190 #define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ 191 #define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ 192 193 /** @} End of group EFR32MG21_LFRCO_BitFields */ 194 /** @} End of group EFR32MG21_LFRCO */ 195 /** @} End of group Parts */ 196 197 #endif /* EFR32MG21_LFRCO_H */ 198
