1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 LDMA register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_LDMA_H 31 #define EFR32MG21_LDMA_H 32 #define LDMA_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG21_LDMA LDMA 40 * @{ 41 * @brief EFR32MG21 LDMA Register Declaration. 42 *****************************************************************************/ 43 44 /** LDMA CH Register Group Declaration. */ 45 typedef struct { 46 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 47 __IOM uint32_t CFG; /**< Channel Configuration Register */ 48 __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ 49 __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ 50 __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ 51 __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ 52 __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ 53 uint32_t RESERVED1[5U]; /**< Reserved for future use */ 54 } LDMA_CH_TypeDef; 55 56 /** LDMA Register Declaration. */ 57 typedef struct { 58 __IM uint32_t IPVERSION; /**< DMA Channel Request Clear Register */ 59 __IOM uint32_t EN; /**< DMA module enable disable Register */ 60 __IOM uint32_t CTRL; /**< DMA Control Register */ 61 __IM uint32_t STATUS; /**< DMA Status Register */ 62 __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ 63 __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ 64 __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ 65 __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ 66 __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ 67 __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ 68 __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ 69 __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ 70 __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ 71 __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ 72 __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ 73 __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ 74 __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ 75 __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ 76 __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ 77 __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ 78 __IOM uint32_t IF; /**< Interrupt Flag Register */ 79 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 80 LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ 81 uint32_t RESERVED0[906U]; /**< Reserved for future use */ 82 __IM uint32_t IPVERSION_SET; /**< DMA Channel Request Clear Register */ 83 __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ 84 __IOM uint32_t CTRL_SET; /**< DMA Control Register */ 85 __IM uint32_t STATUS_SET; /**< DMA Status Register */ 86 __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ 87 __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ 88 __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ 89 __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ 90 __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ 91 __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ 92 __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ 93 __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ 94 __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ 95 __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ 96 __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ 97 __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ 98 __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ 99 __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ 100 __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ 101 __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ 102 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 103 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 104 LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ 105 uint32_t RESERVED1[906U]; /**< Reserved for future use */ 106 __IM uint32_t IPVERSION_CLR; /**< DMA Channel Request Clear Register */ 107 __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ 108 __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ 109 __IM uint32_t STATUS_CLR; /**< DMA Status Register */ 110 __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ 111 __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ 112 __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ 113 __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ 114 __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ 115 __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ 116 __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ 117 __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ 118 __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ 119 __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ 120 __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ 121 __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ 122 __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ 123 __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ 124 __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ 125 __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ 126 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 127 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 128 LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ 129 uint32_t RESERVED2[906U]; /**< Reserved for future use */ 130 __IM uint32_t IPVERSION_TGL; /**< DMA Channel Request Clear Register */ 131 __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ 132 __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ 133 __IM uint32_t STATUS_TGL; /**< DMA Status Register */ 134 __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ 135 __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ 136 __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ 137 __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ 138 __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ 139 __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ 140 __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ 141 __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ 142 __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ 143 __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ 144 __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ 145 __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ 146 __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ 147 __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ 148 __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ 149 __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ 150 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 151 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 152 LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ 153 } LDMA_TypeDef; 154 /** @} End of group EFR32MG21_LDMA */ 155 156 /**************************************************************************//** 157 * @addtogroup EFR32MG21_LDMA 158 * @{ 159 * @defgroup EFR32MG21_LDMA_BitFields LDMA Bit Fields 160 * @{ 161 *****************************************************************************/ 162 163 /* Bit fields for LDMA IPVERSION */ 164 #define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ 165 #define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ 166 #define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ 167 #define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ 168 #define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ 169 #define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */ 170 171 /* Bit fields for LDMA EN */ 172 #define _LDMA_EN_RESETVALUE 0x00000000UL /**< Default value for LDMA_EN */ 173 #define _LDMA_EN_MASK 0x00000001UL /**< Mask for LDMA_EN */ 174 #define LDMA_EN_EN (0x1UL << 0) /**< LDMA module enable and disable register */ 175 #define _LDMA_EN_EN_SHIFT 0 /**< Shift value for LDMA_EN */ 176 #define _LDMA_EN_EN_MASK 0x1UL /**< Bit mask for LDMA_EN */ 177 #define _LDMA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_EN */ 178 #define LDMA_EN_EN_DEFAULT (_LDMA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_EN */ 179 180 /* Bit fields for LDMA CTRL */ 181 #define _LDMA_CTRL_RESETVALUE 0x1E000000UL /**< Default value for LDMA_CTRL */ 182 #define _LDMA_CTRL_MASK 0x9F000000UL /**< Mask for LDMA_CTRL */ 183 #define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ 184 #define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */ 185 #define _LDMA_CTRL_NUMFIXED_DEFAULT 0x0000001EUL /**< Mode DEFAULT for LDMA_CTRL */ 186 #define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ 187 #define LDMA_CTRL_CORERST (0x1UL << 31) /**< Reset DMA controller */ 188 #define _LDMA_CTRL_CORERST_SHIFT 31 /**< Shift value for LDMA_CORERST */ 189 #define _LDMA_CTRL_CORERST_MASK 0x80000000UL /**< Bit mask for LDMA_CORERST */ 190 #define _LDMA_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ 191 #define LDMA_CTRL_CORERST_DEFAULT (_LDMA_CTRL_CORERST_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CTRL */ 192 193 /* Bit fields for LDMA STATUS */ 194 #define _LDMA_STATUS_RESETVALUE 0x1F100000UL /**< Default value for LDMA_STATUS */ 195 #define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */ 196 #define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ 197 #define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ 198 #define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ 199 #define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ 200 #define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ 201 #define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ 202 #define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ 203 #define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ 204 #define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ 205 #define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ 206 #define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ 207 #define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */ 208 #define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ 209 #define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ 210 #define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ 211 #define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */ 212 #define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ 213 #define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ 214 #define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ 215 #define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ 216 #define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ 217 #define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ 218 #define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ 219 #define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ 220 #define _LDMA_STATUS_CHNUM_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LDMA_STATUS */ 221 #define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ 222 223 /* Bit fields for LDMA SYNCSWSET */ 224 #define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ 225 #define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ 226 #define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ 227 #define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ 228 #define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ 229 #define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */ 230 231 /* Bit fields for LDMA SYNCSWCLR */ 232 #define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ 233 #define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ 234 #define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ 235 #define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ 236 #define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ 237 #define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */ 238 239 /* Bit fields for LDMA SYNCHWEN */ 240 #define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ 241 #define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ 242 #define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ 243 #define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ 244 #define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ 245 #define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ 246 #define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ 247 #define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ 248 #define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ 249 #define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ 250 251 /* Bit fields for LDMA SYNCHWSEL */ 252 #define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ 253 #define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ 254 #define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ 255 #define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ 256 #define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ 257 #define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ 258 #define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ 259 #define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ 260 #define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ 261 #define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ 262 #define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ 263 #define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ 264 #define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ 265 #define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ 266 #define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ 267 #define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ 268 #define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ 269 #define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ 270 271 /* Bit fields for LDMA SYNCSTATUS */ 272 #define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ 273 #define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ 274 #define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ 275 #define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ 276 #define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ 277 #define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */ 278 279 /* Bit fields for LDMA CHEN */ 280 #define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ 281 #define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ 282 #define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ 283 #define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ 284 #define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ 285 #define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ 286 287 /* Bit fields for LDMA CHDIS */ 288 #define _LDMA_CHDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDIS */ 289 #define _LDMA_CHDIS_MASK 0x000000FFUL /**< Mask for LDMA_CHDIS */ 290 #define _LDMA_CHDIS_CHDIS_SHIFT 0 /**< Shift value for LDMA_CHDIS */ 291 #define _LDMA_CHDIS_CHDIS_MASK 0xFFUL /**< Bit mask for LDMA_CHDIS */ 292 #define _LDMA_CHDIS_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDIS */ 293 #define LDMA_CHDIS_CHDIS_DEFAULT (_LDMA_CHDIS_CHDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDIS */ 294 295 /* Bit fields for LDMA CHSTATUS */ 296 #define _LDMA_CHSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHSTATUS */ 297 #define _LDMA_CHSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_CHSTATUS */ 298 #define _LDMA_CHSTATUS_CHSTATUS_SHIFT 0 /**< Shift value for LDMA_CHSTATUS */ 299 #define _LDMA_CHSTATUS_CHSTATUS_MASK 0xFFUL /**< Bit mask for LDMA_CHSTATUS */ 300 #define _LDMA_CHSTATUS_CHSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHSTATUS */ 301 #define LDMA_CHSTATUS_CHSTATUS_DEFAULT (_LDMA_CHSTATUS_CHSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHSTATUS */ 302 303 /* Bit fields for LDMA CHBUSY */ 304 #define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ 305 #define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ 306 #define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ 307 #define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ 308 #define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ 309 #define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ 310 311 /* Bit fields for LDMA CHDONE */ 312 #define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ 313 #define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ 314 #define LDMA_CHDONE_CHDONE0 (0x1UL << 0) /**< DMA Channel Link done intr flag */ 315 #define _LDMA_CHDONE_CHDONE0_SHIFT 0 /**< Shift value for LDMA_CHDONE0 */ 316 #define _LDMA_CHDONE_CHDONE0_MASK 0x1UL /**< Bit mask for LDMA_CHDONE0 */ 317 #define _LDMA_CHDONE_CHDONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ 318 #define LDMA_CHDONE_CHDONE0_DEFAULT (_LDMA_CHDONE_CHDONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ 319 #define LDMA_CHDONE_CHDONE1 (0x1UL << 1) /**< DMA Channel Link done intr flag */ 320 #define _LDMA_CHDONE_CHDONE1_SHIFT 1 /**< Shift value for LDMA_CHDONE1 */ 321 #define _LDMA_CHDONE_CHDONE1_MASK 0x2UL /**< Bit mask for LDMA_CHDONE1 */ 322 #define _LDMA_CHDONE_CHDONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ 323 #define LDMA_CHDONE_CHDONE1_DEFAULT (_LDMA_CHDONE_CHDONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CHDONE */ 324 #define LDMA_CHDONE_CHDONE2 (0x1UL << 2) /**< DMA Channel Link done intr flag */ 325 #define _LDMA_CHDONE_CHDONE2_SHIFT 2 /**< Shift value for LDMA_CHDONE2 */ 326 #define _LDMA_CHDONE_CHDONE2_MASK 0x4UL /**< Bit mask for LDMA_CHDONE2 */ 327 #define _LDMA_CHDONE_CHDONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ 328 #define LDMA_CHDONE_CHDONE2_DEFAULT (_LDMA_CHDONE_CHDONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CHDONE */ 329 #define LDMA_CHDONE_CHDONE3 (0x1UL << 3) /**< DMA Channel Link done intr flag */ 330 #define _LDMA_CHDONE_CHDONE3_SHIFT 3 /**< Shift value for LDMA_CHDONE3 */ 331 #define _LDMA_CHDONE_CHDONE3_MASK 0x8UL /**< Bit mask for LDMA_CHDONE3 */ 332 #define _LDMA_CHDONE_CHDONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ 333 #define LDMA_CHDONE_CHDONE3_DEFAULT (_LDMA_CHDONE_CHDONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CHDONE */ 334 #define LDMA_CHDONE_CHDONE4 (0x1UL << 4) /**< DMA Channel Link done intr flag */ 335 #define _LDMA_CHDONE_CHDONE4_SHIFT 4 /**< Shift value for LDMA_CHDONE4 */ 336 #define _LDMA_CHDONE_CHDONE4_MASK 0x10UL /**< Bit mask for LDMA_CHDONE4 */ 337 #define _LDMA_CHDONE_CHDONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ 338 #define LDMA_CHDONE_CHDONE4_DEFAULT (_LDMA_CHDONE_CHDONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CHDONE */ 339 #define LDMA_CHDONE_CHDONE5 (0x1UL << 5) /**< DMA Channel Link done intr flag */ 340 #define _LDMA_CHDONE_CHDONE5_SHIFT 5 /**< Shift value for LDMA_CHDONE5 */ 341 #define _LDMA_CHDONE_CHDONE5_MASK 0x20UL /**< Bit mask for LDMA_CHDONE5 */ 342 #define _LDMA_CHDONE_CHDONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ 343 #define LDMA_CHDONE_CHDONE5_DEFAULT (_LDMA_CHDONE_CHDONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_CHDONE */ 344 #define LDMA_CHDONE_CHDONE6 (0x1UL << 6) /**< DMA Channel Link done intr flag */ 345 #define _LDMA_CHDONE_CHDONE6_SHIFT 6 /**< Shift value for LDMA_CHDONE6 */ 346 #define _LDMA_CHDONE_CHDONE6_MASK 0x40UL /**< Bit mask for LDMA_CHDONE6 */ 347 #define _LDMA_CHDONE_CHDONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ 348 #define LDMA_CHDONE_CHDONE6_DEFAULT (_LDMA_CHDONE_CHDONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_CHDONE */ 349 #define LDMA_CHDONE_CHDONE7 (0x1UL << 7) /**< DMA Channel Link done intr flag */ 350 #define _LDMA_CHDONE_CHDONE7_SHIFT 7 /**< Shift value for LDMA_CHDONE7 */ 351 #define _LDMA_CHDONE_CHDONE7_MASK 0x80UL /**< Bit mask for LDMA_CHDONE7 */ 352 #define _LDMA_CHDONE_CHDONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ 353 #define LDMA_CHDONE_CHDONE7_DEFAULT (_LDMA_CHDONE_CHDONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_CHDONE */ 354 355 /* Bit fields for LDMA DBGHALT */ 356 #define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ 357 #define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ 358 #define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ 359 #define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ 360 #define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ 361 #define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ 362 363 /* Bit fields for LDMA SWREQ */ 364 #define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ 365 #define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ 366 #define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ 367 #define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ 368 #define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ 369 #define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ 370 371 /* Bit fields for LDMA REQDIS */ 372 #define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ 373 #define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ 374 #define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ 375 #define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ 376 #define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ 377 #define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ 378 379 /* Bit fields for LDMA REQPEND */ 380 #define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ 381 #define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ 382 #define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ 383 #define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ 384 #define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ 385 #define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ 386 387 /* Bit fields for LDMA LINKLOAD */ 388 #define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ 389 #define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ 390 #define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ 391 #define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ 392 #define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ 393 #define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ 394 395 /* Bit fields for LDMA REQCLEAR */ 396 #define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ 397 #define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ 398 #define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ 399 #define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ 400 #define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ 401 #define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ 402 403 /* Bit fields for LDMA IF */ 404 #define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ 405 #define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ 406 #define LDMA_IF_DONE0 (0x1UL << 0) /**< DMA Structure Operation Done */ 407 #define _LDMA_IF_DONE0_SHIFT 0 /**< Shift value for LDMA_DONE0 */ 408 #define _LDMA_IF_DONE0_MASK 0x1UL /**< Bit mask for LDMA_DONE0 */ 409 #define _LDMA_IF_DONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ 410 #define LDMA_IF_DONE0_DEFAULT (_LDMA_IF_DONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ 411 #define LDMA_IF_DONE1 (0x1UL << 1) /**< DMA Structure Operation Done */ 412 #define _LDMA_IF_DONE1_SHIFT 1 /**< Shift value for LDMA_DONE1 */ 413 #define _LDMA_IF_DONE1_MASK 0x2UL /**< Bit mask for LDMA_DONE1 */ 414 #define _LDMA_IF_DONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ 415 #define LDMA_IF_DONE1_DEFAULT (_LDMA_IF_DONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_IF */ 416 #define LDMA_IF_DONE2 (0x1UL << 2) /**< DMA Structure Operation Done */ 417 #define _LDMA_IF_DONE2_SHIFT 2 /**< Shift value for LDMA_DONE2 */ 418 #define _LDMA_IF_DONE2_MASK 0x4UL /**< Bit mask for LDMA_DONE2 */ 419 #define _LDMA_IF_DONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ 420 #define LDMA_IF_DONE2_DEFAULT (_LDMA_IF_DONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_IF */ 421 #define LDMA_IF_DONE3 (0x1UL << 3) /**< DMA Structure Operation Done */ 422 #define _LDMA_IF_DONE3_SHIFT 3 /**< Shift value for LDMA_DONE3 */ 423 #define _LDMA_IF_DONE3_MASK 0x8UL /**< Bit mask for LDMA_DONE3 */ 424 #define _LDMA_IF_DONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ 425 #define LDMA_IF_DONE3_DEFAULT (_LDMA_IF_DONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_IF */ 426 #define LDMA_IF_DONE4 (0x1UL << 4) /**< DMA Structure Operation Done */ 427 #define _LDMA_IF_DONE4_SHIFT 4 /**< Shift value for LDMA_DONE4 */ 428 #define _LDMA_IF_DONE4_MASK 0x10UL /**< Bit mask for LDMA_DONE4 */ 429 #define _LDMA_IF_DONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ 430 #define LDMA_IF_DONE4_DEFAULT (_LDMA_IF_DONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_IF */ 431 #define LDMA_IF_DONE5 (0x1UL << 5) /**< DMA Structure Operation Done */ 432 #define _LDMA_IF_DONE5_SHIFT 5 /**< Shift value for LDMA_DONE5 */ 433 #define _LDMA_IF_DONE5_MASK 0x20UL /**< Bit mask for LDMA_DONE5 */ 434 #define _LDMA_IF_DONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ 435 #define LDMA_IF_DONE5_DEFAULT (_LDMA_IF_DONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_IF */ 436 #define LDMA_IF_DONE6 (0x1UL << 6) /**< DMA Structure Operation Done */ 437 #define _LDMA_IF_DONE6_SHIFT 6 /**< Shift value for LDMA_DONE6 */ 438 #define _LDMA_IF_DONE6_MASK 0x40UL /**< Bit mask for LDMA_DONE6 */ 439 #define _LDMA_IF_DONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ 440 #define LDMA_IF_DONE6_DEFAULT (_LDMA_IF_DONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_IF */ 441 #define LDMA_IF_DONE7 (0x1UL << 7) /**< DMA Structure Operation Done */ 442 #define _LDMA_IF_DONE7_SHIFT 7 /**< Shift value for LDMA_DONE7 */ 443 #define _LDMA_IF_DONE7_MASK 0x80UL /**< Bit mask for LDMA_DONE7 */ 444 #define _LDMA_IF_DONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ 445 #define LDMA_IF_DONE7_DEFAULT (_LDMA_IF_DONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_IF */ 446 #define LDMA_IF_ERROR (0x1UL << 31) /**< Error Flag */ 447 #define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ 448 #define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ 449 #define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ 450 #define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ 451 452 /* Bit fields for LDMA IEN */ 453 #define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ 454 #define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ 455 #define _LDMA_IEN_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ 456 #define _LDMA_IEN_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ 457 #define _LDMA_IEN_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ 458 #define LDMA_IEN_CHDONE_DEFAULT (_LDMA_IEN_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ 459 #define LDMA_IEN_ERROR (0x1UL << 31) /**< Enable or disable the error interrupt */ 460 #define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ 461 #define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ 462 #define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ 463 #define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ 464 465 /* Bit fields for LDMA CH_CFG */ 466 #define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ 467 #define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ 468 #define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ 469 #define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ 470 #define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ 471 #define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ 472 #define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ 473 #define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ 474 #define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ 475 #define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ 476 #define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ 477 #define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ 478 #define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ 479 #define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ 480 #define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ 481 #define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ 482 #define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ 483 #define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ 484 #define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ 485 #define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ 486 #define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ 487 #define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ 488 #define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ 489 #define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ 490 #define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ 491 #define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ 492 #define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ 493 #define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ 494 #define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ 495 #define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ 496 #define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ 497 #define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ 498 499 /* Bit fields for LDMA CH_LOOP */ 500 #define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ 501 #define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ 502 #define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ 503 #define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ 504 #define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ 505 #define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ 506 507 /* Bit fields for LDMA CH_CTRL */ 508 #define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ 509 #define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ 510 #define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ 511 #define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ 512 #define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 513 #define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ 514 #define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ 515 #define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ 516 #define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 517 #define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ 518 #define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ 519 #define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ 520 #define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ 521 #define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ 522 #define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ 523 #define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 524 #define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 525 #define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ 526 #define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ 527 #define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 528 #define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 529 #define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ 530 #define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ 531 #define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ 532 #define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 533 #define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 534 #define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ 535 #define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ 536 #define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 537 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ 538 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ 539 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ 540 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ 541 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ 542 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ 543 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ 544 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ 545 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ 546 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ 547 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ 548 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ 549 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ 550 #define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ 551 #define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 552 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ 553 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ 554 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ 555 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ 556 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ 557 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ 558 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ 559 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ 560 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ 561 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ 562 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ 563 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ 564 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ 565 #define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ 566 #define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ 567 #define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ 568 #define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ 569 #define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 570 #define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 571 #define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ 572 #define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ 573 #define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ 574 #define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 575 #define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ 576 #define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ 577 #define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 578 #define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ 579 #define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ 580 #define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ 581 #define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ 582 #define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ 583 #define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 584 #define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 585 #define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ 586 #define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ 587 #define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ 588 #define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 589 #define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 590 #define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ 591 #define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ 592 #define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 593 #define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ 594 #define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ 595 #define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ 596 #define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ 597 #define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 598 #define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ 599 #define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ 600 #define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ 601 #define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ 602 #define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ 603 #define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ 604 #define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 605 #define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ 606 #define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ 607 #define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ 608 #define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 609 #define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ 610 #define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ 611 #define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ 612 #define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ 613 #define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ 614 #define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 615 #define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ 616 #define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ 617 #define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ 618 #define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ 619 #define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 620 #define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ 621 #define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ 622 #define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ 623 #define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ 624 #define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ 625 #define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ 626 #define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ 627 #define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 628 #define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ 629 #define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ 630 #define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 631 #define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ 632 #define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ 633 #define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ 634 #define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ 635 #define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ 636 #define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 637 #define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ 638 #define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ 639 #define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 640 #define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ 641 #define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ 642 643 /* Bit fields for LDMA CH_SRC */ 644 #define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ 645 #define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ 646 #define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ 647 #define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ 648 #define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ 649 #define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ 650 651 /* Bit fields for LDMA CH_DST */ 652 #define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ 653 #define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ 654 #define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ 655 #define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ 656 #define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ 657 #define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ 658 659 /* Bit fields for LDMA CH_LINK */ 660 #define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ 661 #define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ 662 #define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ 663 #define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ 664 #define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ 665 #define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ 666 #define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ 667 #define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ 668 #define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ 669 #define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ 670 #define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ 671 #define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ 672 #define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ 673 #define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ 674 #define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ 675 #define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ 676 #define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ 677 #define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ 678 #define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ 679 #define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ 680 681 /** @} End of group EFR32MG21_LDMA_BitFields */ 682 /** @} End of group EFR32MG21_LDMA */ 683 /** @} End of group Parts */ 684 685 #endif /* EFR32MG21_LDMA_H */ 686
