1 /***************************************************************************//** 2 * @file 3 * @brief EFR32FG13P_CMU register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFR32FG13P_CMU CMU 43 * @{ 44 * @brief EFR32FG13P_CMU Register Declaration 45 ******************************************************************************/ 46 /** CMU Register Declaration */ 47 typedef struct { 48 __IOM uint32_t CTRL; /**< CMU Control Register */ 49 50 uint32_t RESERVED0[3U]; /**< Reserved for future use **/ 51 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ 52 53 uint32_t RESERVED1[1U]; /**< Reserved for future use **/ 54 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ 55 56 uint32_t RESERVED2[1U]; /**< Reserved for future use **/ 57 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ 58 __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ 59 60 uint32_t RESERVED3[1U]; /**< Reserved for future use **/ 61 __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ 62 __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ 63 __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ 64 __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ 65 66 uint32_t RESERVED4[1U]; /**< Reserved for future use **/ 67 __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ 68 __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ 69 uint32_t RESERVED5[2U]; /**< Reserved for future use **/ 70 __IOM uint32_t CALCTRL; /**< Calibration Control Register */ 71 __IOM uint32_t CALCNT; /**< Calibration Counter Register */ 72 uint32_t RESERVED6[2U]; /**< Reserved for future use **/ 73 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ 74 __IOM uint32_t CMD; /**< Command Register */ 75 uint32_t RESERVED7[2U]; /**< Reserved for future use **/ 76 __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ 77 __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ 78 uint32_t RESERVED8[2U]; /**< Reserved for future use **/ 79 __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ 80 __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ 81 __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ 82 83 uint32_t RESERVED9[1U]; /**< Reserved for future use **/ 84 __IM uint32_t STATUS; /**< Status Register */ 85 __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ 86 uint32_t RESERVED10[1U]; /**< Reserved for future use **/ 87 __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ 88 __IM uint32_t IF; /**< Interrupt Flag Register */ 89 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 90 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 91 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 92 __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ 93 94 uint32_t RESERVED11[3U]; /**< Reserved for future use **/ 95 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ 96 97 uint32_t RESERVED12[7U]; /**< Reserved for future use **/ 98 __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ 99 uint32_t RESERVED13[1U]; /**< Reserved for future use **/ 100 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ 101 102 uint32_t RESERVED14[1U]; /**< Reserved for future use **/ 103 __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ 104 uint32_t RESERVED15[3U]; /**< Reserved for future use **/ 105 __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ 106 107 uint32_t RESERVED16[1U]; /**< Reserved for future use **/ 108 __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ 109 __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ 110 111 uint32_t RESERVED17[1U]; /**< Reserved for future use **/ 112 __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ 113 114 uint32_t RESERVED18[2U]; /**< Reserved for future use **/ 115 __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ 116 uint32_t RESERVED19[1U]; /**< Reserved for future use **/ 117 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ 118 uint32_t RESERVED20[1U]; /**< Reserved for future use **/ 119 __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ 120 121 uint32_t RESERVED21[3U]; /**< Reserved for future use **/ 122 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 123 __IOM uint32_t FREEZE; /**< Freeze Register */ 124 uint32_t RESERVED22[2U]; /**< Reserved for future use **/ 125 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ 126 127 uint32_t RESERVED23[2U]; /**< Reserved for future use **/ 128 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ 129 130 uint32_t RESERVED24[4U]; /**< Reserved for future use **/ 131 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ 132 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ 133 __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ 134 uint32_t RESERVED25[1U]; /**< Reserved for future use **/ 135 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 136 __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ 137 138 uint32_t RESERVED26[30U]; /**< Reserved for future use **/ 139 __IOM uint32_t LFRCLKSEL; /**< Low Frequency R Clock Select Register */ 140 uint32_t RESERVED27[3U]; /**< Reserved for future use **/ 141 __IOM uint32_t LFRCLKEN0; /**< Low Frequency R Clock Enable Register 0 (Async Reg) */ 142 uint32_t RESERVED28[1U]; /**< Reserved for future use **/ 143 __IOM uint32_t LFRPRESC0; /**< Low Frequency R Prescaler Register 0 (Async Reg) */ 144 } CMU_TypeDef; /** @} */ 145 146 /***************************************************************************//** 147 * @addtogroup EFR32FG13P_CMU 148 * @{ 149 * @defgroup EFR32FG13P_CMU_BitFields CMU Bit Fields 150 * @{ 151 ******************************************************************************/ 152 153 /* Bit fields for CMU CTRL */ 154 #define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */ 155 #define _CMU_CTRL_MASK 0x001103FFUL /**< Mask for CMU_CTRL */ 156 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ 157 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ 158 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 159 #define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ 160 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ 161 #define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ 162 #define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ 163 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ 164 #define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ 165 #define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ 166 #define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ 167 #define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ 168 #define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ 169 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ 170 #define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ 171 #define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ 172 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ 173 #define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ 174 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ 175 #define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ 176 #define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ 177 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ 178 #define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ 179 #define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ 180 #define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ 181 #define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ 182 #define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ 183 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ 184 #define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ 185 #define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ 186 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ 187 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ 188 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 189 #define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ 190 #define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ 191 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ 192 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ 193 #define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ 194 #define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ 195 #define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ 196 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ 197 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ 198 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ 199 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ 200 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ 201 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ 202 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ 203 #define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ 204 #define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ 205 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ 206 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ 207 #define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ 208 #define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ 209 #define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ 210 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ 211 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ 212 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ 213 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ 214 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ 215 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ 216 #define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ 217 #define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ 218 #define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ 219 #define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 220 #define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ 221 #define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ 222 #define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ 223 #define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ 224 #define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ 225 #define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ 226 227 /* Bit fields for CMU HFRCOCTRL */ 228 #define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ 229 #define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ 230 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 231 #define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 232 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 233 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 234 #define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ 235 #define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ 236 #define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 237 #define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 238 #define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ 239 #define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ 240 #define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 241 #define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 242 #define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ 243 #define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ 244 #define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 245 #define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 246 #define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ 247 #define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ 248 #define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ 249 #define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 250 #define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 251 #define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ 252 #define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ 253 #define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 254 #define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ 255 #define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ 256 #define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ 257 #define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 258 #define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ 259 #define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ 260 #define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ 261 #define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ 262 #define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ 263 #define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ 264 #define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 265 #define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 266 #define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ 267 #define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ 268 #define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 269 #define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 270 271 /* Bit fields for CMU AUXHFRCOCTRL */ 272 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ 273 #define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ 274 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 275 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 276 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 277 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 278 #define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ 279 #define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ 280 #define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 281 #define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 282 #define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ 283 #define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ 284 #define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 285 #define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 286 #define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ 287 #define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ 288 #define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 289 #define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 290 #define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ 291 #define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ 292 #define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ 293 #define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 294 #define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 295 #define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ 296 #define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ 297 #define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 298 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ 299 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ 300 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ 301 #define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 302 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ 303 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ 304 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ 305 #define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ 306 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ 307 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ 308 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 309 #define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 310 #define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ 311 #define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ 312 #define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 313 #define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 314 315 /* Bit fields for CMU LFRCOCTRL */ 316 #define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ 317 #define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ 318 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 319 #define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ 320 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 321 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 322 #define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ 323 #define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ 324 #define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ 325 #define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 326 #define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 327 #define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ 328 #define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ 329 #define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ 330 #define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 331 #define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 332 #define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ 333 #define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ 334 #define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ 335 #define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 336 #define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 337 #define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ 338 #define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ 339 #define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 340 #define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ 341 #define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ 342 #define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ 343 #define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ 344 #define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 345 #define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ 346 #define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ 347 #define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ 348 #define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ 349 #define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ 350 #define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ 351 #define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ 352 #define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 353 #define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ 354 #define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ 355 #define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ 356 #define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 357 #define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ 358 #define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ 359 #define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ 360 #define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ 361 #define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 362 #define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 363 364 /* Bit fields for CMU HFXOCTRL */ 365 #define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOCTRL */ 366 #define _CMU_HFXOCTRL_MASK 0x37000731UL /**< Mask for CMU_HFXOCTRL */ 367 #define CMU_HFXOCTRL_MODE (0x1UL << 0) /**< HFXO Mode */ 368 #define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ 369 #define _CMU_HFXOCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ 370 #define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 371 #define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ 372 #define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for CMU_HFXOCTRL */ 373 #define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 374 #define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ 375 #define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for CMU_HFXOCTRL */ 376 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETSHUNTOPTMODE */ 377 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETSHUNTOPTMODE */ 378 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 379 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ 380 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL /**< Mode CMD for CMU_HFXOCTRL */ 381 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL /**< Mode MANUAL for CMU_HFXOCTRL */ 382 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 383 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ 384 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ 385 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ 386 #define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low Power Mode Control */ 387 #define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */ 388 #define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */ 389 #define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 390 #define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 391 #define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N Pin to Ground When HFXO Oscillator is Off */ 392 #define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */ 393 #define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */ 394 #define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 395 #define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 396 #define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P Pin to Ground When HFXO Oscillator is Off */ 397 #define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */ 398 #define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */ 399 #define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 400 #define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 401 #define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ 402 #define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ 403 #define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 404 #define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ 405 #define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ 406 #define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ 407 #define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ 408 #define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ 409 #define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ 410 #define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ 411 #define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ 412 #define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 413 #define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ 414 #define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ 415 #define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ 416 #define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ 417 #define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ 418 #define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ 419 #define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ 420 #define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ 421 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ 422 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ 423 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ 424 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 425 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 426 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ 427 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ 428 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ 429 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 430 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 431 432 /* Bit fields for CMU HFXOSTARTUPCTRL */ 433 #define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00050020UL /**< Default value for CMU_HFXOSTARTUPCTRL */ 434 #define _CMU_HFXOSTARTUPCTRL_MASK 0x000FF87FUL /**< Mask for CMU_HFXOSTARTUPCTRL */ 435 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ 436 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ 437 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 438 #define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 439 #define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ 440 #define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ 441 #define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 442 #define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 443 444 /* Bit fields for CMU HFXOSTEADYSTATECTRL */ 445 #define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30B4507UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ 446 #define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ 447 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ 448 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ 449 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 450 #define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 451 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ 452 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ 453 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 454 #define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 455 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ 456 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ 457 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000168UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 458 #define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 459 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24 /**< Shift value for CMU_REGSELILOW */ 460 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */ 461 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 462 #define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 463 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ 464 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ 465 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ 466 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 467 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 468 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28 /**< Shift value for CMU_REGISHUPPER */ 469 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL /**< Bit mask for CMU_REGISHUPPER */ 470 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 471 #define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 472 473 /* Bit fields for CMU HFXOTIMEOUTCTRL */ 474 #define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0002A067UL /**< Default value for CMU_HFXOTIMEOUTCTRL */ 475 #define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FF0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ 476 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ 477 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ 478 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 479 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 480 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 481 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 482 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 483 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 484 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 485 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 486 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 487 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 488 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 489 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 490 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 491 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 492 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 493 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 494 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 495 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 496 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 497 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 498 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 499 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 500 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 501 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 502 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ 503 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ 504 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 505 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 506 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 507 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 508 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 509 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 510 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 511 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 512 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 513 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 514 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 515 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 516 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 517 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 518 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 519 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 520 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 521 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 522 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 523 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 524 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 525 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 526 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 527 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 528 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ 529 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ 530 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 531 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 532 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 533 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 534 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 535 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 536 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 537 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 538 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 539 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 540 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 541 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 542 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 543 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 544 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 545 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 546 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 547 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 548 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 549 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 550 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 551 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 552 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 553 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 554 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16 /**< Shift value for CMU_SHUNTOPTTIMEOUT */ 555 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL /**< Bit mask for CMU_SHUNTOPTTIMEOUT */ 556 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 557 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 558 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 559 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 560 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 561 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 562 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 563 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 564 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 565 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 566 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 567 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 568 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 569 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 570 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 571 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 572 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 573 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 574 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 575 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 576 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 577 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 578 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 579 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 580 581 /* Bit fields for CMU LFXOCTRL */ 582 #define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ 583 #define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ 584 #define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 585 #define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 586 #define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 587 #define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 588 #define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ 589 #define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ 590 #define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 591 #define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ 592 #define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ 593 #define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ 594 #define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 595 #define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ 596 #define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ 597 #define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ 598 #define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ 599 #define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ 600 #define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 601 #define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 602 #define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ 603 #define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ 604 #define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ 605 #define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 606 #define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 607 #define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ 608 #define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ 609 #define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ 610 #define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 611 #define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 612 #define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ 613 #define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ 614 #define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 615 #define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 616 #define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ 617 #define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ 618 #define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ 619 #define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 620 #define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 621 #define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ 622 #define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ 623 #define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ 624 #define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ 625 #define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ 626 #define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ 627 #define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ 628 #define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ 629 #define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ 630 #define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 631 #define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ 632 #define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ 633 #define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ 634 #define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ 635 #define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ 636 #define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ 637 #define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ 638 #define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ 639 #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 640 #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ 641 642 /* Bit fields for CMU DPLLCTRL */ 643 #define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ 644 #define _CMU_DPLLCTRL_MASK 0x0000001FUL /**< Mask for CMU_DPLLCTRL */ 645 #define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ 646 #define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ 647 #define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ 648 #define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 649 #define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ 650 #define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ 651 #define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 652 #define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ 653 #define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ 654 #define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ 655 #define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ 656 #define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ 657 #define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 658 #define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ 659 #define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ 660 #define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 661 #define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ 662 #define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ 663 #define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ 664 #define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ 665 #define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ 666 #define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 667 #define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 668 #define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ 669 #define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ 670 #define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 671 #define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ 672 #define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ 673 #define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ 674 #define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 675 #define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ 676 #define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ 677 #define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ 678 679 /* Bit fields for CMU DPLLCTRL1 */ 680 #define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ 681 #define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ 682 #define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ 683 #define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ 684 #define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ 685 #define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ 686 #define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ 687 #define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ 688 #define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ 689 #define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ 690 691 /* Bit fields for CMU CALCTRL */ 692 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ 693 #define _CMU_CALCTRL_MASK 0x0F0F01FFUL /**< Mask for CMU_CALCTRL */ 694 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ 695 #define _CMU_CALCTRL_UPSEL_MASK 0xFUL /**< Bit mask for CMU_UPSEL */ 696 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 697 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ 698 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ 699 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ 700 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ 701 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ 702 #define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ 703 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 704 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ 705 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ 706 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ 707 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ 708 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ 709 #define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ 710 #define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ 711 #define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ 712 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 713 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ 714 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ 715 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ 716 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ 717 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ 718 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ 719 #define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ 720 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 721 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ 722 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ 723 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ 724 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ 725 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ 726 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ 727 #define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ 728 #define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ 729 #define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ 730 #define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ 731 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 732 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 733 #define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ 734 #define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL /**< Bit mask for CMU_PRSUPSEL */ 735 #define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 736 #define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ 737 #define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ 738 #define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ 739 #define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ 740 #define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ 741 #define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ 742 #define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ 743 #define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ 744 #define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ 745 #define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ 746 #define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ 747 #define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ 748 #define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 749 #define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ 750 #define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ 751 #define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ 752 #define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ 753 #define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ 754 #define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ 755 #define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ 756 #define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ 757 #define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ 758 #define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ 759 #define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ 760 #define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ 761 #define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ 762 #define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL /**< Bit mask for CMU_PRSDOWNSEL */ 763 #define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 764 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ 765 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ 766 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ 767 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ 768 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ 769 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ 770 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ 771 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ 772 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ 773 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ 774 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ 775 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ 776 #define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 777 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ 778 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ 779 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ 780 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ 781 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ 782 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ 783 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ 784 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ 785 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ 786 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ 787 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ 788 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ 789 790 /* Bit fields for CMU CALCNT */ 791 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ 792 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ 793 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ 794 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ 795 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ 796 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ 797 798 /* Bit fields for CMU OSCENCMD */ 799 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ 800 #define _CMU_OSCENCMD_MASK 0x000033FFUL /**< Mask for CMU_OSCENCMD */ 801 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ 802 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ 803 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ 804 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 805 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 806 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ 807 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ 808 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ 809 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 810 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 811 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ 812 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ 813 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ 814 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 815 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 816 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ 817 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ 818 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ 819 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 820 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 821 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ 822 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ 823 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ 824 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 825 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 826 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ 827 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ 828 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ 829 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 830 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 831 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ 832 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ 833 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ 834 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 835 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 836 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ 837 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ 838 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ 839 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 840 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 841 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ 842 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ 843 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ 844 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 845 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 846 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ 847 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ 848 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ 849 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 850 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 851 #define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ 852 #define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ 853 #define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ 854 #define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 855 #define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 856 #define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ 857 #define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ 858 #define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ 859 #define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 860 #define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 861 862 /* Bit fields for CMU CMD */ 863 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ 864 #define _CMU_CMD_MASK 0x00000033UL /**< Mask for CMU_CMD */ 865 #define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ 866 #define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ 867 #define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ 868 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 869 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ 870 #define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ 871 #define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ 872 #define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ 873 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 874 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ 875 #define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ 876 #define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ 877 #define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ 878 #define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 879 #define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ 880 #define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5) /**< HFXO Shunt Current Optimization Start */ 881 #define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5 /**< Shift value for CMU_HFXOSHUNTOPTSTART */ 882 #define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL /**< Bit mask for CMU_HFXOSHUNTOPTSTART */ 883 #define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 884 #define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */ 885 886 /* Bit fields for CMU DBGCLKSEL */ 887 #define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ 888 #define _CMU_DBGCLKSEL_MASK 0x00000001UL /**< Mask for CMU_DBGCLKSEL */ 889 #define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ 890 #define _CMU_DBGCLKSEL_DBG_MASK 0x1UL /**< Bit mask for CMU_DBG */ 891 #define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ 892 #define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ 893 #define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ 894 #define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ 895 #define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ 896 #define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ 897 898 /* Bit fields for CMU HFCLKSEL */ 899 #define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ 900 #define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ 901 #define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ 902 #define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ 903 #define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ 904 #define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ 905 #define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ 906 #define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ 907 #define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ 908 #define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ 909 #define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ 910 #define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ 911 #define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ 912 #define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ 913 #define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ 914 #define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ 915 #define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ 916 #define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ 917 918 /* Bit fields for CMU LFACLKSEL */ 919 #define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ 920 #define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ 921 #define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ 922 #define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ 923 #define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ 924 #define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ 925 #define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ 926 #define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ 927 #define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ 928 #define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ 929 #define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ 930 #define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ 931 #define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ 932 #define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ 933 934 /* Bit fields for CMU LFBCLKSEL */ 935 #define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ 936 #define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ 937 #define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ 938 #define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ 939 #define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ 940 #define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ 941 #define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ 942 #define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ 943 #define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ 944 #define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ 945 #define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ 946 #define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ 947 #define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ 948 #define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ 949 #define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ 950 #define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ 951 952 /* Bit fields for CMU LFECLKSEL */ 953 #define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ 954 #define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ 955 #define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ 956 #define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ 957 #define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ 958 #define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ 959 #define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ 960 #define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ 961 #define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ 962 #define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ 963 #define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ 964 #define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ 965 #define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ 966 #define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ 967 968 /* Bit fields for CMU STATUS */ 969 #define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ 970 #define _CMU_STATUS_MASK 0x3FE133FFUL /**< Mask for CMU_STATUS */ 971 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ 972 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ 973 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ 974 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 975 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ 976 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ 977 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ 978 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ 979 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 980 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ 981 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ 982 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ 983 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ 984 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 985 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ 986 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ 987 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ 988 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ 989 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 990 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ 991 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ 992 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ 993 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ 994 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 995 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ 996 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ 997 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ 998 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ 999 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1000 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ 1001 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ 1002 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ 1003 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ 1004 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1005 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ 1006 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ 1007 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ 1008 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ 1009 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1010 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ 1011 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ 1012 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ 1013 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ 1014 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1015 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ 1016 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ 1017 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ 1018 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ 1019 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1020 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ 1021 #define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ 1022 #define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ 1023 #define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ 1024 #define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1025 #define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ 1026 #define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ 1027 #define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ 1028 #define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ 1029 #define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1030 #define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ 1031 #define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ 1032 #define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ 1033 #define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ 1034 #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 1035 #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ 1036 #define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required By Hardware */ 1037 #define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */ 1038 #define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */ 1039 #define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1040 #define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ 1041 #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ 1042 #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ 1043 #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 1044 #define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1045 #define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ 1046 #define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization Ready */ 1047 #define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ 1048 #define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ 1049 #define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1050 #define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */ 1051 #define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO Oscillation Amplitude is Too High */ 1052 #define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */ 1053 #define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */ 1054 #define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1055 #define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */ 1056 #define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ 1057 #define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ 1058 #define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ 1059 #define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1060 #define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ 1061 #define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO Regulator Shunt Current Too Low */ 1062 #define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */ 1063 #define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */ 1064 #define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1065 #define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */ 1066 #define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ 1067 #define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ 1068 #define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ 1069 #define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1070 #define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ 1071 #define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ 1072 #define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ 1073 #define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ 1074 #define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1075 #define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ 1076 #define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ 1077 #define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ 1078 #define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ 1079 #define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1080 #define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ 1081 1082 /* Bit fields for CMU HFCLKSTATUS */ 1083 #define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ 1084 #define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ 1085 #define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ 1086 #define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ 1087 #define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ 1088 #define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ 1089 #define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ 1090 #define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ 1091 #define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ 1092 #define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ 1093 #define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ 1094 #define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ 1095 #define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ 1096 #define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ 1097 #define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ 1098 #define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ 1099 #define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ 1100 #define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ 1101 1102 /* Bit fields for CMU HFXOTRIMSTATUS */ 1103 #define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL /**< Default value for CMU_HFXOTRIMSTATUS */ 1104 #define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ 1105 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ 1106 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ 1107 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ 1108 #define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ 1109 #define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ 1110 #define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ 1111 #define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ 1112 #define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ 1113 1114 /* Bit fields for CMU IF */ 1115 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ 1116 #define _CMU_IF_MASK 0xB803FF7FUL /**< Mask for CMU_IF */ 1117 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ 1118 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1119 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1120 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ 1121 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ 1122 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ 1123 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1124 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1125 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1126 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ 1127 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ 1128 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1129 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1130 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1131 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ 1132 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ 1133 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1134 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1135 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1136 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ 1137 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ 1138 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1139 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1140 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1141 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ 1142 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ 1143 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1144 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1145 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1146 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ 1147 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ 1148 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1149 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1150 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1151 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ 1152 #define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ 1153 #define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 1154 #define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 1155 #define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1156 #define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ 1157 #define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ 1158 #define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 1159 #define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 1160 #define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1161 #define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ 1162 #define CMU_IF_HFXOPEAKDETERR (0x1UL << 10) /**< HFXO Automatic Peak Detection Error Interrupt Flag */ 1163 #define _CMU_IF_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ 1164 #define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ 1165 #define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1166 #define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IF */ 1167 #define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ 1168 #define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 1169 #define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 1170 #define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1171 #define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ 1172 #define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXO Automatic Shunt Current Optimization Ready Interrupt Flag */ 1173 #define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ 1174 #define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ 1175 #define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1176 #define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IF */ 1177 #define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ 1178 #define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 1179 #define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 1180 #define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1181 #define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ 1182 #define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ 1183 #define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 1184 #define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 1185 #define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1186 #define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ 1187 #define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ 1188 #define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 1189 #define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 1190 #define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1191 #define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ 1192 #define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ 1193 #define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 1194 #define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 1195 #define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1196 #define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ 1197 #define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ 1198 #define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 1199 #define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 1200 #define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1201 #define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ 1202 #define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ 1203 #define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 1204 #define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 1205 #define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1206 #define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ 1207 #define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ 1208 #define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 1209 #define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 1210 #define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1211 #define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ 1212 #define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ 1213 #define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 1214 #define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 1215 #define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1216 #define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ 1217 #define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ 1218 #define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 1219 #define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 1220 #define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1221 #define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ 1222 1223 /* Bit fields for CMU IFS */ 1224 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ 1225 #define _CMU_IFS_MASK 0xB803FF7FUL /**< Mask for CMU_IFS */ 1226 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ 1227 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1228 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1229 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1230 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ 1231 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ 1232 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1233 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1234 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1235 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ 1236 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ 1237 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1238 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1239 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1240 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ 1241 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ 1242 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1243 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1244 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1245 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ 1246 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ 1247 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1248 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1249 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1250 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ 1251 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ 1252 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1253 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1254 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1255 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ 1256 #define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ 1257 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1258 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1259 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1260 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ 1261 #define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ 1262 #define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 1263 #define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 1264 #define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1265 #define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ 1266 #define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ 1267 #define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 1268 #define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 1269 #define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1270 #define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ 1271 #define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10) /**< Set HFXOPEAKDETERR Interrupt Flag */ 1272 #define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ 1273 #define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ 1274 #define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1275 #define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFS */ 1276 #define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ 1277 #define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 1278 #define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 1279 #define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1280 #define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ 1281 #define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Set HFXOSHUNTOPTRDY Interrupt Flag */ 1282 #define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ 1283 #define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ 1284 #define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1285 #define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFS */ 1286 #define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ 1287 #define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 1288 #define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 1289 #define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1290 #define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ 1291 #define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ 1292 #define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 1293 #define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 1294 #define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1295 #define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ 1296 #define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ 1297 #define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 1298 #define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 1299 #define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1300 #define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ 1301 #define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ 1302 #define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 1303 #define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 1304 #define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1305 #define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ 1306 #define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ 1307 #define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 1308 #define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 1309 #define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1310 #define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ 1311 #define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ 1312 #define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 1313 #define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 1314 #define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1315 #define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ 1316 #define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ 1317 #define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 1318 #define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 1319 #define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1320 #define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ 1321 #define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ 1322 #define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 1323 #define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 1324 #define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1325 #define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ 1326 #define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ 1327 #define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 1328 #define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 1329 #define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1330 #define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ 1331 1332 /* Bit fields for CMU IFC */ 1333 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ 1334 #define _CMU_IFC_MASK 0xB803FF7FUL /**< Mask for CMU_IFC */ 1335 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ 1336 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1337 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1338 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1339 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ 1340 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ 1341 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1342 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1343 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1344 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ 1345 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ 1346 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1347 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1348 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1349 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ 1350 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ 1351 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1352 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1353 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1354 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ 1355 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ 1356 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1357 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1358 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1359 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ 1360 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ 1361 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1362 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1363 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1364 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ 1365 #define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ 1366 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1367 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1368 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1369 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ 1370 #define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ 1371 #define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 1372 #define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 1373 #define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1374 #define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ 1375 #define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ 1376 #define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 1377 #define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 1378 #define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1379 #define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ 1380 #define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10) /**< Clear HFXOPEAKDETERR Interrupt Flag */ 1381 #define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ 1382 #define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ 1383 #define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1384 #define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFC */ 1385 #define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ 1386 #define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 1387 #define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 1388 #define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1389 #define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ 1390 #define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Clear HFXOSHUNTOPTRDY Interrupt Flag */ 1391 #define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ 1392 #define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ 1393 #define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1394 #define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFC */ 1395 #define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ 1396 #define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 1397 #define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 1398 #define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1399 #define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ 1400 #define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ 1401 #define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 1402 #define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 1403 #define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1404 #define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ 1405 #define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ 1406 #define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 1407 #define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 1408 #define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1409 #define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ 1410 #define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ 1411 #define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 1412 #define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 1413 #define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1414 #define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ 1415 #define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ 1416 #define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 1417 #define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 1418 #define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1419 #define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ 1420 #define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ 1421 #define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 1422 #define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 1423 #define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1424 #define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ 1425 #define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ 1426 #define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 1427 #define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 1428 #define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1429 #define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ 1430 #define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ 1431 #define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 1432 #define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 1433 #define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1434 #define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ 1435 #define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ 1436 #define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 1437 #define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 1438 #define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1439 #define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ 1440 1441 /* Bit fields for CMU IEN */ 1442 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ 1443 #define _CMU_IEN_MASK 0xB803FF7FUL /**< Mask for CMU_IEN */ 1444 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ 1445 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1446 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1447 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1448 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ 1449 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ 1450 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1451 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1452 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1453 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ 1454 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ 1455 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1456 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1457 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1458 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ 1459 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ 1460 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1461 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1462 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1463 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ 1464 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ 1465 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1466 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1467 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1468 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ 1469 #define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ 1470 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1471 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1472 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1473 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ 1474 #define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ 1475 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1476 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1477 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1478 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ 1479 #define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ 1480 #define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 1481 #define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 1482 #define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1483 #define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ 1484 #define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ 1485 #define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 1486 #define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 1487 #define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1488 #define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ 1489 #define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10) /**< HFXOPEAKDETERR Interrupt Enable */ 1490 #define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ 1491 #define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ 1492 #define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1493 #define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IEN */ 1494 #define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ 1495 #define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 1496 #define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 1497 #define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1498 #define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ 1499 #define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXOSHUNTOPTRDY Interrupt Enable */ 1500 #define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ 1501 #define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ 1502 #define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1503 #define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IEN */ 1504 #define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ 1505 #define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 1506 #define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 1507 #define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1508 #define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ 1509 #define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ 1510 #define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 1511 #define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 1512 #define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1513 #define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ 1514 #define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ 1515 #define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 1516 #define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 1517 #define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1518 #define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ 1519 #define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ 1520 #define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 1521 #define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 1522 #define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1523 #define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ 1524 #define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ 1525 #define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 1526 #define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 1527 #define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1528 #define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ 1529 #define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ 1530 #define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 1531 #define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 1532 #define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1533 #define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ 1534 #define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ 1535 #define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 1536 #define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 1537 #define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1538 #define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ 1539 #define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ 1540 #define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 1541 #define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 1542 #define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1543 #define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ 1544 #define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ 1545 #define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 1546 #define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 1547 #define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1548 #define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ 1549 1550 /* Bit fields for CMU HFBUSCLKEN0 */ 1551 #define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ 1552 #define _CMU_HFBUSCLKEN0_MASK 0x0000007FUL /**< Mask for CMU_HFBUSCLKEN0 */ 1553 #define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 0) /**< Advanced Encryption Standard Accelerator 0 Clock Enable */ 1554 #define CMU_HFBUSCLKEN0_CRYPTO CMU_HFBUSCLKEN0_CRYPTO0 /**< Alias for CRYPTO0 */ 1555 #define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 0 /**< Shift value for CMU_CRYPTO0 */ 1556 #define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x1UL /**< Bit mask for CMU_CRYPTO0 */ 1557 #define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT /**< Alias for CMU_CRYPTO0 */ 1558 #define _CMU_HFBUSCLKEN0_CRYPTO_MASK _CMU_HFBUSCLKEN0_CRYPTO0_MASK /**< Alias for CMU_CRYPTO0 */ 1559 #define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1560 #define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT */ 1561 #define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1562 #define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT*/ 1563 #define CMU_HFBUSCLKEN0_CRYPTO1 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator 1 Clock Enable */ 1564 #define _CMU_HFBUSCLKEN0_CRYPTO1_SHIFT 1 /**< Shift value for CMU_CRYPTO1 */ 1565 #define _CMU_HFBUSCLKEN0_CRYPTO1_MASK 0x2UL /**< Bit mask for CMU_CRYPTO1 */ 1566 #define _CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1567 #define CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1568 #define CMU_HFBUSCLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */ 1569 #define _CMU_HFBUSCLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */ 1570 #define _CMU_HFBUSCLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */ 1571 #define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1572 #define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1573 #define CMU_HFBUSCLKEN0_GPIO (0x1UL << 3) /**< General purpose Input/Output Clock Enable */ 1574 #define _CMU_HFBUSCLKEN0_GPIO_SHIFT 3 /**< Shift value for CMU_GPIO */ 1575 #define _CMU_HFBUSCLKEN0_GPIO_MASK 0x8UL /**< Bit mask for CMU_GPIO */ 1576 #define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1577 #define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1578 #define CMU_HFBUSCLKEN0_PRS (0x1UL << 4) /**< Peripheral Reflex System Clock Enable */ 1579 #define _CMU_HFBUSCLKEN0_PRS_SHIFT 4 /**< Shift value for CMU_PRS */ 1580 #define _CMU_HFBUSCLKEN0_PRS_MASK 0x10UL /**< Bit mask for CMU_PRS */ 1581 #define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1582 #define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1583 #define CMU_HFBUSCLKEN0_LDMA (0x1UL << 5) /**< Linked Direct Memory Access Controller Clock Enable */ 1584 #define _CMU_HFBUSCLKEN0_LDMA_SHIFT 5 /**< Shift value for CMU_LDMA */ 1585 #define _CMU_HFBUSCLKEN0_LDMA_MASK 0x20UL /**< Bit mask for CMU_LDMA */ 1586 #define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1587 #define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1588 #define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 6) /**< General Purpose CRC Clock Enable */ 1589 #define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 6 /**< Shift value for CMU_GPCRC */ 1590 #define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x40UL /**< Bit mask for CMU_GPCRC */ 1591 #define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1592 #define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1593 1594 /* Bit fields for CMU HFPERCLKEN0 */ 1595 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ 1596 #define _CMU_HFPERCLKEN0_MASK 0x0000FFFFUL /**< Mask for CMU_HFPERCLKEN0 */ 1597 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ 1598 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ 1599 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ 1600 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1601 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1602 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ 1603 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ 1604 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ 1605 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1606 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1607 #define CMU_HFPERCLKEN0_WTIMER0 (0x1UL << 2) /**< Wide Timer 0 Clock Enable */ 1608 #define _CMU_HFPERCLKEN0_WTIMER0_SHIFT 2 /**< Shift value for CMU_WTIMER0 */ 1609 #define _CMU_HFPERCLKEN0_WTIMER0_MASK 0x4UL /**< Bit mask for CMU_WTIMER0 */ 1610 #define _CMU_HFPERCLKEN0_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1611 #define CMU_HFPERCLKEN0_WTIMER0_DEFAULT (_CMU_HFPERCLKEN0_WTIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1612 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 3) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ 1613 #define _CMU_HFPERCLKEN0_USART0_SHIFT 3 /**< Shift value for CMU_USART0 */ 1614 #define _CMU_HFPERCLKEN0_USART0_MASK 0x8UL /**< Bit mask for CMU_USART0 */ 1615 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1616 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1617 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ 1618 #define _CMU_HFPERCLKEN0_USART1_SHIFT 4 /**< Shift value for CMU_USART1 */ 1619 #define _CMU_HFPERCLKEN0_USART1_MASK 0x10UL /**< Bit mask for CMU_USART1 */ 1620 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1621 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1622 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 5) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ 1623 #define _CMU_HFPERCLKEN0_USART2_SHIFT 5 /**< Shift value for CMU_USART2 */ 1624 #define _CMU_HFPERCLKEN0_USART2_MASK 0x20UL /**< Bit mask for CMU_USART2 */ 1625 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1626 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1627 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 6) /**< I2C 0 Clock Enable */ 1628 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 6 /**< Shift value for CMU_I2C0 */ 1629 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x40UL /**< Bit mask for CMU_I2C0 */ 1630 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1631 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1632 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 7) /**< I2C 1 Clock Enable */ 1633 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 7 /**< Shift value for CMU_I2C1 */ 1634 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x80UL /**< Bit mask for CMU_I2C1 */ 1635 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1636 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1637 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 8) /**< Analog Comparator 0 Clock Enable */ 1638 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 8 /**< Shift value for CMU_ACMP0 */ 1639 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x100UL /**< Bit mask for CMU_ACMP0 */ 1640 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1641 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1642 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 9) /**< Analog Comparator 1 Clock Enable */ 1643 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 9 /**< Shift value for CMU_ACMP1 */ 1644 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x200UL /**< Bit mask for CMU_ACMP1 */ 1645 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1646 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1647 #define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 10) /**< CRYOTIMER Clock Enable */ 1648 #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 10 /**< Shift value for CMU_CRYOTIMER */ 1649 #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400UL /**< Bit mask for CMU_CRYOTIMER */ 1650 #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1651 #define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1652 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 11) /**< Analog to Digital Converter 0 Clock Enable */ 1653 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 11 /**< Shift value for CMU_ADC0 */ 1654 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x800UL /**< Bit mask for CMU_ADC0 */ 1655 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1656 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1657 #define CMU_HFPERCLKEN0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 Clock Enable */ 1658 #define _CMU_HFPERCLKEN0_VDAC0_SHIFT 12 /**< Shift value for CMU_VDAC0 */ 1659 #define _CMU_HFPERCLKEN0_VDAC0_MASK 0x1000UL /**< Bit mask for CMU_VDAC0 */ 1660 #define _CMU_HFPERCLKEN0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1661 #define CMU_HFPERCLKEN0_VDAC0_DEFAULT (_CMU_HFPERCLKEN0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1662 #define CMU_HFPERCLKEN0_CSEN (0x1UL << 13) /**< Capacitive touch sense module Clock Enable */ 1663 #define _CMU_HFPERCLKEN0_CSEN_SHIFT 13 /**< Shift value for CMU_CSEN */ 1664 #define _CMU_HFPERCLKEN0_CSEN_MASK 0x2000UL /**< Bit mask for CMU_CSEN */ 1665 #define _CMU_HFPERCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1666 #define CMU_HFPERCLKEN0_CSEN_DEFAULT (_CMU_HFPERCLKEN0_CSEN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1667 #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 14) /**< Current Digital to Analog Converter 0 Clock Enable */ 1668 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 14 /**< Shift value for CMU_IDAC0 */ 1669 #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x4000UL /**< Bit mask for CMU_IDAC0 */ 1670 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1671 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1672 #define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 15) /**< True Random Number Generator 0 Clock Enable */ 1673 #define _CMU_HFPERCLKEN0_TRNG0_SHIFT 15 /**< Shift value for CMU_TRNG0 */ 1674 #define _CMU_HFPERCLKEN0_TRNG0_MASK 0x8000UL /**< Bit mask for CMU_TRNG0 */ 1675 #define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1676 #define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1677 1678 /* Bit fields for CMU LFACLKEN0 */ 1679 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ 1680 #define _CMU_LFACLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFACLKEN0 */ 1681 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ 1682 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ 1683 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ 1684 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 1685 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 1686 #define CMU_LFACLKEN0_LESENSE (0x1UL << 1) /**< Low Energy Sensor Interface Clock Enable */ 1687 #define _CMU_LFACLKEN0_LESENSE_SHIFT 1 /**< Shift value for CMU_LESENSE */ 1688 #define _CMU_LFACLKEN0_LESENSE_MASK 0x2UL /**< Bit mask for CMU_LESENSE */ 1689 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 1690 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 1691 1692 /* Bit fields for CMU LFBCLKEN0 */ 1693 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ 1694 #define _CMU_LFBCLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFBCLKEN0 */ 1695 #define CMU_LFBCLKEN0_SYSTICK (0x1UL << 0) /**< Clock Enable */ 1696 #define _CMU_LFBCLKEN0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ 1697 #define _CMU_LFBCLKEN0_SYSTICK_MASK 0x1UL /**< Bit mask for CMU_SYSTICK */ 1698 #define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 1699 #define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 1700 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 1) /**< Low Energy UART 0 Clock Enable */ 1701 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 1 /**< Shift value for CMU_LEUART0 */ 1702 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x2UL /**< Bit mask for CMU_LEUART0 */ 1703 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 1704 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 1705 #define CMU_LFBCLKEN0_CSEN (0x1UL << 2) /**< Capacitive touch sense module Clock Enable */ 1706 #define _CMU_LFBCLKEN0_CSEN_SHIFT 2 /**< Shift value for CMU_CSEN */ 1707 #define _CMU_LFBCLKEN0_CSEN_MASK 0x4UL /**< Bit mask for CMU_CSEN */ 1708 #define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 1709 #define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 1710 1711 /* Bit fields for CMU LFECLKEN0 */ 1712 #define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ 1713 #define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ 1714 #define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ 1715 #define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ 1716 #define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ 1717 #define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ 1718 #define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ 1719 1720 /* Bit fields for CMU HFPRESC */ 1721 #define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ 1722 #define _CMU_HFPRESC_MASK 0x01001F00UL /**< Mask for CMU_HFPRESC */ 1723 #define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 1724 #define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ 1725 #define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ 1726 #define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ 1727 #define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ 1728 #define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ 1729 #define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ 1730 #define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ 1731 #define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ 1732 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ 1733 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ 1734 #define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ 1735 #define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ 1736 #define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ 1737 1738 /* Bit fields for CMU HFCOREPRESC */ 1739 #define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ 1740 #define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ 1741 #define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 1742 #define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 1743 #define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ 1744 #define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ 1745 #define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ 1746 #define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ 1747 1748 /* Bit fields for CMU HFPERPRESC */ 1749 #define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ 1750 #define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ 1751 #define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 1752 #define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 1753 #define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ 1754 #define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ 1755 #define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ 1756 #define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ 1757 1758 /* Bit fields for CMU HFEXPPRESC */ 1759 #define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ 1760 #define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ 1761 #define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 1762 #define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ 1763 #define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ 1764 #define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ 1765 #define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ 1766 #define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ 1767 1768 /* Bit fields for CMU LFAPRESC0 */ 1769 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ 1770 #define _CMU_LFAPRESC0_MASK 0x0000003FUL /**< Mask for CMU_LFAPRESC0 */ 1771 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ 1772 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ 1773 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 1774 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 1775 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 1776 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 1777 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 1778 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 1779 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 1780 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 1781 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ 1782 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ 1783 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ 1784 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ 1785 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ 1786 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ 1787 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ 1788 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ 1789 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 1790 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 1791 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 1792 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 1793 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 1794 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 1795 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 1796 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 1797 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ 1798 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ 1799 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ 1800 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ 1801 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ 1802 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ 1803 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ 1804 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ 1805 #define _CMU_LFAPRESC0_LESENSE_SHIFT 4 /**< Shift value for CMU_LESENSE */ 1806 #define _CMU_LFAPRESC0_LESENSE_MASK 0x30UL /**< Bit mask for CMU_LESENSE */ 1807 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 1808 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 1809 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 1810 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 1811 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 1812 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 1813 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 1814 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 1815 1816 /* Bit fields for CMU LFBPRESC0 */ 1817 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ 1818 #define _CMU_LFBPRESC0_MASK 0x0000033FUL /**< Mask for CMU_LFBPRESC0 */ 1819 #define _CMU_LFBPRESC0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ 1820 #define _CMU_LFBPRESC0_SYSTICK_MASK 0xFUL /**< Bit mask for CMU_SYSTICK */ 1821 #define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 1822 #define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 1823 #define _CMU_LFBPRESC0_LEUART0_SHIFT 4 /**< Shift value for CMU_LEUART0 */ 1824 #define _CMU_LFBPRESC0_LEUART0_MASK 0x30UL /**< Bit mask for CMU_LEUART0 */ 1825 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 1826 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ 1827 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ 1828 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ 1829 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 1830 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ 1831 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ 1832 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ 1833 #define _CMU_LFBPRESC0_CSEN_SHIFT 8 /**< Shift value for CMU_CSEN */ 1834 #define _CMU_LFBPRESC0_CSEN_MASK 0x300UL /**< Bit mask for CMU_CSEN */ 1835 #define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ 1836 #define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ 1837 #define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ 1838 #define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ 1839 #define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ 1840 #define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ 1841 #define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ 1842 #define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ 1843 1844 /* Bit fields for CMU LFEPRESC0 */ 1845 #define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ 1846 #define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ 1847 #define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ 1848 #define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ 1849 #define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ 1850 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ 1851 #define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ 1852 #define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ 1853 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ 1854 #define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ 1855 1856 /* Bit fields for CMU SYNCBUSY */ 1857 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ 1858 #define _CMU_SYNCBUSY_MASK 0x3F055055UL /**< Mask for CMU_SYNCBUSY */ 1859 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ 1860 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ 1861 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ 1862 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1863 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1864 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ 1865 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ 1866 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ 1867 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1868 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1869 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ 1870 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ 1871 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ 1872 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1873 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1874 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ 1875 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ 1876 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ 1877 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1878 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1879 #define CMU_SYNCBUSY_LFRCLKEN0 (0x1UL << 12) /**< Low Frequency R Clock Enable 0 Busy */ 1880 #define _CMU_SYNCBUSY_LFRCLKEN0_SHIFT 12 /**< Shift value for CMU_LFRCLKEN0 */ 1881 #define _CMU_SYNCBUSY_LFRCLKEN0_MASK 0x1000UL /**< Bit mask for CMU_LFRCLKEN0 */ 1882 #define _CMU_SYNCBUSY_LFRCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1883 #define CMU_SYNCBUSY_LFRCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFRCLKEN0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1884 #define CMU_SYNCBUSY_LFRPRESC0 (0x1UL << 14) /**< Low Frequency R Prescaler 0 Busy */ 1885 #define _CMU_SYNCBUSY_LFRPRESC0_SHIFT 14 /**< Shift value for CMU_LFRPRESC0 */ 1886 #define _CMU_SYNCBUSY_LFRPRESC0_MASK 0x4000UL /**< Bit mask for CMU_LFRPRESC0 */ 1887 #define _CMU_SYNCBUSY_LFRPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1888 #define CMU_SYNCBUSY_LFRPRESC0_DEFAULT (_CMU_SYNCBUSY_LFRPRESC0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1889 #define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ 1890 #define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ 1891 #define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ 1892 #define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1893 #define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1894 #define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ 1895 #define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ 1896 #define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ 1897 #define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1898 #define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1899 #define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ 1900 #define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ 1901 #define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ 1902 #define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1903 #define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1904 #define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ 1905 #define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ 1906 #define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ 1907 #define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1908 #define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1909 #define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ 1910 #define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ 1911 #define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ 1912 #define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1913 #define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1914 #define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ 1915 #define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ 1916 #define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ 1917 #define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1918 #define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1919 #define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ 1920 #define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ 1921 #define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ 1922 #define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1923 #define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1924 #define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ 1925 #define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ 1926 #define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ 1927 #define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1928 #define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1929 1930 /* Bit fields for CMU FREEZE */ 1931 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ 1932 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ 1933 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ 1934 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ 1935 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ 1936 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ 1937 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ 1938 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ 1939 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ 1940 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ 1941 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ 1942 1943 /* Bit fields for CMU PCNTCTRL */ 1944 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ 1945 #define _CMU_PCNTCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNTCTRL */ 1946 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ 1947 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ 1948 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ 1949 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 1950 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 1951 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ 1952 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ 1953 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ 1954 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 1955 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ 1956 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ 1957 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 1958 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ 1959 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ 1960 1961 /* Bit fields for CMU ADCCTRL */ 1962 #define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ 1963 #define _CMU_ADCCTRL_MASK 0x00000130UL /**< Mask for CMU_ADCCTRL */ 1964 #define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ 1965 #define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ 1966 #define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 1967 #define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ 1968 #define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ 1969 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ 1970 #define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ 1971 #define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 1972 #define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ 1973 #define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ 1974 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ 1975 #define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ 1976 #define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ 1977 #define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ 1978 #define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ 1979 #define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 1980 #define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 1981 1982 /* Bit fields for CMU ROUTEPEN */ 1983 #define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ 1984 #define _CMU_ROUTEPEN_MASK 0x10000003UL /**< Mask for CMU_ROUTEPEN */ 1985 #define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ 1986 #define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ 1987 #define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ 1988 #define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 1989 #define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 1990 #define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ 1991 #define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ 1992 #define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ 1993 #define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 1994 #define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 1995 #define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ 1996 #define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ 1997 #define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ 1998 #define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 1999 #define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 2000 2001 /* Bit fields for CMU ROUTELOC0 */ 2002 #define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ 2003 #define _CMU_ROUTELOC0_MASK 0x00000707UL /**< Mask for CMU_ROUTELOC0 */ 2004 #define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ 2005 #define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ 2006 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ 2007 #define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ 2008 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ 2009 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ 2010 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ 2011 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ 2012 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ 2013 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ 2014 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ 2015 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ 2016 #define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ 2017 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ 2018 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ 2019 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ 2020 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ 2021 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ 2022 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ 2023 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ 2024 #define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ 2025 #define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ 2026 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ 2027 #define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ 2028 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ 2029 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ 2030 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ 2031 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ 2032 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ 2033 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ 2034 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ 2035 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ 2036 #define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ 2037 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ 2038 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ 2039 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ 2040 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ 2041 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ 2042 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ 2043 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ 2044 2045 /* Bit fields for CMU ROUTELOC1 */ 2046 #define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ 2047 #define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ 2048 #define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ 2049 #define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ 2050 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ 2051 #define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ 2052 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ 2053 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ 2054 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ 2055 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ 2056 #define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ 2057 #define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ 2058 #define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ 2059 #define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ 2060 #define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ 2061 #define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ 2062 2063 /* Bit fields for CMU LOCK */ 2064 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ 2065 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ 2066 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ 2067 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ 2068 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ 2069 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ 2070 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ 2071 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ 2072 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ 2073 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ 2074 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ 2075 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ 2076 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ 2077 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ 2078 2079 /* Bit fields for CMU HFRCOSS */ 2080 #define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ 2081 #define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ 2082 #define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ 2083 #define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ 2084 #define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ 2085 #define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ 2086 #define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ 2087 #define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ 2088 #define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ 2089 #define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ 2090 2091 /* Bit fields for CMU LFRCLKSEL */ 2092 #define _CMU_LFRCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFRCLKSEL */ 2093 #define _CMU_LFRCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFRCLKSEL */ 2094 #define _CMU_LFRCLKSEL_LFR_SHIFT 0 /**< Shift value for CMU_LFR */ 2095 #define _CMU_LFRCLKSEL_LFR_MASK 0x7UL /**< Bit mask for CMU_LFR */ 2096 #define _CMU_LFRCLKSEL_LFR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCLKSEL */ 2097 #define _CMU_LFRCLKSEL_LFR_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFRCLKSEL */ 2098 #define _CMU_LFRCLKSEL_LFR_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFRCLKSEL */ 2099 #define _CMU_LFRCLKSEL_LFR_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFRCLKSEL */ 2100 #define _CMU_LFRCLKSEL_LFR_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFRCLKSEL */ 2101 #define CMU_LFRCLKSEL_LFR_DEFAULT (_CMU_LFRCLKSEL_LFR_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCLKSEL */ 2102 #define CMU_LFRCLKSEL_LFR_DISABLED (_CMU_LFRCLKSEL_LFR_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFRCLKSEL */ 2103 #define CMU_LFRCLKSEL_LFR_LFRCO (_CMU_LFRCLKSEL_LFR_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFRCLKSEL */ 2104 #define CMU_LFRCLKSEL_LFR_LFXO (_CMU_LFRCLKSEL_LFR_LFXO << 0) /**< Shifted mode LFXO for CMU_LFRCLKSEL */ 2105 #define CMU_LFRCLKSEL_LFR_ULFRCO (_CMU_LFRCLKSEL_LFR_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFRCLKSEL */ 2106 2107 /* Bit fields for CMU LFRCLKEN0 */ 2108 #define _CMU_LFRCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFRCLKEN0 */ 2109 #define _CMU_LFRCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFRCLKEN0 */ 2110 #define CMU_LFRCLKEN0_PRORTC (0x1UL << 0) /**< Protocol Real-Time Counter Clock Enable */ 2111 #define _CMU_LFRCLKEN0_PRORTC_SHIFT 0 /**< Shift value for CMU_PRORTC */ 2112 #define _CMU_LFRCLKEN0_PRORTC_MASK 0x1UL /**< Bit mask for CMU_PRORTC */ 2113 #define _CMU_LFRCLKEN0_PRORTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCLKEN0 */ 2114 #define CMU_LFRCLKEN0_PRORTC_DEFAULT (_CMU_LFRCLKEN0_PRORTC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCLKEN0 */ 2115 2116 /* Bit fields for CMU LFRPRESC0 */ 2117 #define _CMU_LFRPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFRPRESC0 */ 2118 #define _CMU_LFRPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFRPRESC0 */ 2119 #define _CMU_LFRPRESC0_PRORTC_SHIFT 0 /**< Shift value for CMU_PRORTC */ 2120 #define _CMU_LFRPRESC0_PRORTC_MASK 0x3UL /**< Bit mask for CMU_PRORTC */ 2121 #define _CMU_LFRPRESC0_PRORTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFRPRESC0 */ 2122 #define _CMU_LFRPRESC0_PRORTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFRPRESC0 */ 2123 #define _CMU_LFRPRESC0_PRORTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFRPRESC0 */ 2124 #define CMU_LFRPRESC0_PRORTC_DIV1 (_CMU_LFRPRESC0_PRORTC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFRPRESC0 */ 2125 #define CMU_LFRPRESC0_PRORTC_DIV2 (_CMU_LFRPRESC0_PRORTC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFRPRESC0 */ 2126 #define CMU_LFRPRESC0_PRORTC_DIV4 (_CMU_LFRPRESC0_PRORTC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFRPRESC0 */ 2127 2128 /** @} */ 2129 /** @} End of group EFR32FG13P_CMU */ 2130 /** @} End of group Parts */ 2131
