1/* 2 * Copyright (c) 2021 Sateesh Kotapati 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv8-m.dtsi> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/i2c/i2c.h> 10#include <dt-bindings/pinctrl/gecko-pinctrl.h> 11#include <dt-bindings/adc/adc.h> 12#include <freq.h> 13 14/ { 15 chosen { 16 zephyr,flash-controller = &msc; 17 zephyr,entropy = &trng; 18 }; 19 20 clocks { 21 clk_hfxo: clk-hfxo { 22 #clock-cells = <0>; 23 compatible = "silabs,hfxo"; 24 clock-frequency = <DT_FREQ_K(38400)>; 25 ctune = <120>; 26 precision = <50>; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-m33"; 36 reg = <0>; 37 /* 38 * EM1 is enabled by default because it is 39 * unconditionally safe. 40 * 41 * EM2/3 can be enabled by the board code if proper 42 * timing configuration is ensured: 43 * - for EM2, EM3: BURTC used as sys_clock 44 * - for EM3: BURTC clocked from ULFRCO 45 * Using BURTC as sys_clock instead of SysTick 46 * has implications on system performance. Read 47 * KConfig documentation entry before enabling it. 48 */ 49 cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>; 50 }; 51 52 power-states { 53 /* 54 * EM1 is a basic "CPU WFI idle", all high-freq clocks remain 55 * enabled. 56 */ 57 pstate_em1: em1 { 58 compatible = "zephyr,power-state"; 59 power-state-name = "runtime-idle"; 60 min-residency-us = <4>; 61 /* HFXO remains active */ 62 exit-latency-us = <2>; 63 }; 64 65 /* 66 * EM2 is a deepsleep with HF clocks disabled by HW, voltages 67 * scaled down, etc. 68 */ 69 pstate_em2: em2 { 70 compatible = "zephyr,power-state"; 71 power-state-name = "suspend-to-idle"; 72 min-residency-us = <260>; 73 exit-latency-us = <250>; 74 }; 75 76 /* 77 * EM3 seems to be exactly the same as EM2 except that 78 * LFXO & LFRCO should be disabled, so you must use ULFRCO 79 * as BURTC clock for the system to not lose track of time and 80 * wake up. 81 */ 82 pstate_em3: em3 { 83 compatible = "zephyr,power-state"; 84 power-state-name = "standby"; 85 min-residency-us = <20000>; 86 exit-latency-us = <2000>; 87 }; 88 }; 89 }; 90 91 sram0: memory@20000000 { 92 compatible = "mmio-sram"; 93 }; 94 95 soc { 96 msc: flash-controller@50030000 { 97 compatible = "silabs,gecko-flash-controller"; 98 reg = <0x50030000 0xC69>; 99 interrupts = <49 0>; 100 101 #address-cells = <1>; 102 #size-cells = <1>; 103 }; 104 105 usart0: usart@5005c000 { 106 compatible = "silabs,gecko-spi-usart"; 107 reg = <0x5005C000 0x400>; 108 interrupt-names = "rx", "tx"; 109 #address-cells = <1>; 110 #size-cells = <0>; 111 status = "disabled"; 112 }; 113 114 usart1: usart@50060000 { 115 compatible = "silabs,gecko-usart"; 116 reg = <0x50060000 0x400>; 117 interrupt-names = "rx", "tx"; 118 status = "disabled"; 119 }; 120 121 burtc0: burtc@50064000 { 122 compatible = "silabs,gecko-burtc"; 123 reg = <0x50064000 0x3034>; 124 status = "disabled"; 125 }; 126 127 stimer0: stimer@58000000 { 128 compatible = "silabs,gecko-stimer"; 129 reg = <0x58000000 0x3054>; 130 clock-frequency = <32768>; 131 prescaler = <1>; 132 status = "disabled"; 133 }; 134 135 trng: trng@4c021000 { 136 compatible = "silabs,gecko-trng"; 137 reg = <0x4C021000 0x1000>; 138 status = "disabled"; 139 interrupts = <0x1 0x0>; 140 }; 141 142 i2c0: i2c@5a010000 { 143 compatible = "silabs,gecko-i2c"; 144 clock-frequency = <I2C_BITRATE_STANDARD>; 145 reg = <0x5a010000 0x3044>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 status = "disabled"; 149 }; 150 151 i2c1: i2c@50068000 { 152 compatible = "silabs,gecko-i2c"; 153 clock-frequency = <I2C_BITRATE_STANDARD>; 154 reg = <0x50068000 0x3044>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 status = "disabled"; 158 }; 159 160 gpio: gpio@5003c000 { 161 compatible = "silabs,gecko-gpio"; 162 reg = <0x5003C000 0x3660>; 163 interrupt-names = "GPIO_EVEN", "GPIO_ODD"; 164 165 ranges; 166 #address-cells = <1>; 167 #size-cells = <1>; 168 169 gpioa: gpio@5003c000 { 170 compatible = "silabs,gecko-gpio-port"; 171 reg = <0x5003C000 0x30>; 172 gpio-controller; 173 #gpio-cells = <2>; 174 status = "disabled"; 175 }; 176 177 gpiob: gpio@5003c030 { 178 compatible = "silabs,gecko-gpio-port"; 179 reg = <0x5003C030 0x30>; 180 gpio-controller; 181 #gpio-cells = <2>; 182 status = "disabled"; 183 }; 184 185 gpioc: gpio@5003c060 { 186 compatible = "silabs,gecko-gpio-port"; 187 reg = <0x5003C060 0x30>; 188 gpio-controller; 189 #gpio-cells = <2>; 190 status = "disabled"; 191 }; 192 193 gpiod: gpio@5003c090 { 194 compatible = "silabs,gecko-gpio-port"; 195 reg = <0x5003C090 0x30>; 196 gpio-controller; 197 #gpio-cells = <2>; 198 status = "disabled"; 199 }; 200 201 gpiof: gpio@5003c0c0 { 202 compatible = "silabs,gecko-gpio-port"; 203 reg = <0x5003C0C0 0x30>; 204 gpio-controller; 205 #gpio-cells = <2>; 206 status = "disabled"; 207 }; 208 209 }; 210 211 wdog0: wdog@4a018000 { 212 compatible = "silabs,gecko-wdog"; 213 reg = <0x4A018000 0x3028>; 214 peripheral-id = <0>; 215 interrupts = <43 0>; 216 status = "disabled"; 217 }; 218 219 adc0: adc@5a004000 { 220 compatible = "silabs,gecko-iadc"; 221 reg = <0x5a004000 0x4000>; 222 interrupts = <48 0>; 223 status = "disabled"; 224 #io-channel-cells = <1>; 225 }; 226 }; 227 228 bt_hci_silabs: bt_hci_silabs { 229 compatible = "silabs,bt-hci"; 230 status = "disabled"; 231 }; 232}; 233 234/ { 235 pinctrl: pin-controller { 236 /* Pin controller is a "virtual" device since SiLabs SoCs do pin 237 * control in a distributed way (GPIO registers and PSEL 238 * registers on each peripheral). 239 */ 240 compatible = "silabs,gecko-pinctrl"; 241 }; 242}; 243 244&nvic { 245 arm,num-irq-priority-bits = <4>; 246}; 247
