1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG29 MPAHBRAM register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG29_MPAHBRAM_H 31 #define EFR32BG29_MPAHBRAM_H 32 #define MPAHBRAM_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG29_MPAHBRAM MPAHBRAM 40 * @{ 41 * @brief EFR32BG29 MPAHBRAM Register Declaration. 42 *****************************************************************************/ 43 44 /** MPAHBRAM Register Declaration. */ 45 typedef struct mpahbram_typedef{ 46 __IM uint32_t IPVERSION; /**< IP version ID */ 47 __IOM uint32_t CMD; /**< Command register */ 48 __IOM uint32_t CTRL; /**< Control register */ 49 __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */ 50 __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */ 51 uint32_t RESERVED0[2U]; /**< Reserved for future use */ 52 __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */ 53 __IOM uint32_t IF; /**< Interrupt Flags */ 54 __IOM uint32_t IEN; /**< Interrupt Enable */ 55 uint32_t RESERVED1[7U]; /**< Reserved for future use */ 56 uint32_t RESERVED2[1U]; /**< Reserved for future use */ 57 uint32_t RESERVED3[1006U]; /**< Reserved for future use */ 58 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 59 __IOM uint32_t CMD_SET; /**< Command register */ 60 __IOM uint32_t CTRL_SET; /**< Control register */ 61 __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */ 62 __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */ 63 uint32_t RESERVED4[2U]; /**< Reserved for future use */ 64 __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */ 65 __IOM uint32_t IF_SET; /**< Interrupt Flags */ 66 __IOM uint32_t IEN_SET; /**< Interrupt Enable */ 67 uint32_t RESERVED5[7U]; /**< Reserved for future use */ 68 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 69 uint32_t RESERVED7[1006U]; /**< Reserved for future use */ 70 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 71 __IOM uint32_t CMD_CLR; /**< Command register */ 72 __IOM uint32_t CTRL_CLR; /**< Control register */ 73 __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */ 74 __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */ 75 uint32_t RESERVED8[2U]; /**< Reserved for future use */ 76 __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */ 77 __IOM uint32_t IF_CLR; /**< Interrupt Flags */ 78 __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ 79 uint32_t RESERVED9[7U]; /**< Reserved for future use */ 80 uint32_t RESERVED10[1U]; /**< Reserved for future use */ 81 uint32_t RESERVED11[1006U]; /**< Reserved for future use */ 82 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 83 __IOM uint32_t CMD_TGL; /**< Command register */ 84 __IOM uint32_t CTRL_TGL; /**< Control register */ 85 __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */ 86 __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */ 87 uint32_t RESERVED12[2U]; /**< Reserved for future use */ 88 __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */ 89 __IOM uint32_t IF_TGL; /**< Interrupt Flags */ 90 __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ 91 uint32_t RESERVED13[7U]; /**< Reserved for future use */ 92 uint32_t RESERVED14[1U]; /**< Reserved for future use */ 93 } MPAHBRAM_TypeDef; 94 /** @} End of group EFR32BG29_MPAHBRAM */ 95 96 /**************************************************************************//** 97 * @addtogroup EFR32BG29_MPAHBRAM 98 * @{ 99 * @defgroup EFR32BG29_MPAHBRAM_BitFields MPAHBRAM Bit Fields 100 * @{ 101 *****************************************************************************/ 102 103 /* Bit fields for MPAHBRAM IPVERSION */ 104 #define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for MPAHBRAM_IPVERSION */ 105 #define _MPAHBRAM_IPVERSION_MASK 0x00000003UL /**< Mask for MPAHBRAM_IPVERSION */ 106 #define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */ 107 #define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x3UL /**< Bit mask for MPAHBRAM_IPVERSION */ 108 #define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */ 109 #define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */ 110 111 /* Bit fields for MPAHBRAM CMD */ 112 #define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */ 113 #define _MPAHBRAM_CMD_MASK 0x00000003UL /**< Mask for MPAHBRAM_CMD */ 114 #define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */ 115 #define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */ 116 #define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */ 117 #define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ 118 #define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ 119 #define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */ 120 #define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */ 121 #define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */ 122 #define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ 123 #define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ 124 125 /* Bit fields for MPAHBRAM CTRL */ 126 #define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */ 127 #define _MPAHBRAM_CTRL_MASK 0x000000FFUL /**< Mask for MPAHBRAM_CTRL */ 128 #define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */ 129 #define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */ 130 #define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */ 131 #define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 132 #define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 133 #define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */ 134 #define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */ 135 #define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */ 136 #define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 137 #define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 138 #define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */ 139 #define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */ 140 #define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */ 141 #define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 142 #define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 143 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */ 144 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */ 145 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 146 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */ 147 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */ 148 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */ 149 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 150 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */ 151 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */ 152 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */ 153 #define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */ 154 #define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */ 155 #define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */ 156 #define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 157 #define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 158 #define MPAHBRAM_CTRL_WAITSTATES (0x1UL << 7) /**< RAM read wait states */ 159 #define _MPAHBRAM_CTRL_WAITSTATES_SHIFT 7 /**< Shift value for MPAHBRAM_WAITSTATES */ 160 #define _MPAHBRAM_CTRL_WAITSTATES_MASK 0x80UL /**< Bit mask for MPAHBRAM_WAITSTATES */ 161 #define _MPAHBRAM_CTRL_WAITSTATES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 162 #define MPAHBRAM_CTRL_WAITSTATES_DEFAULT (_MPAHBRAM_CTRL_WAITSTATES_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 163 164 /* Bit fields for MPAHBRAM ECCERRADDR0 */ 165 #define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */ 166 #define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */ 167 #define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ 168 #define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ 169 #define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */ 170 #define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/ 171 172 /* Bit fields for MPAHBRAM ECCERRADDR1 */ 173 #define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */ 174 #define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */ 175 #define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ 176 #define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ 177 #define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */ 178 #define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/ 179 180 /* Bit fields for MPAHBRAM ECCMERRIND */ 181 #define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */ 182 #define _MPAHBRAM_ECCMERRIND_MASK 0x00000003UL /**< Mask for MPAHBRAM_ECCMERRIND */ 183 #define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */ 184 #define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */ 185 #define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */ 186 #define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ 187 #define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ 188 #define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */ 189 #define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */ 190 #define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */ 191 #define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ 192 #define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ 193 194 /* Bit fields for MPAHBRAM IF */ 195 #define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */ 196 #define _MPAHBRAM_IF_MASK 0x00000033UL /**< Mask for MPAHBRAM_IF */ 197 #define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */ 198 #define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ 199 #define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ 200 #define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 201 #define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 202 #define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */ 203 #define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ 204 #define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ 205 #define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 206 #define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 207 #define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */ 208 #define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ 209 #define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ 210 #define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 211 #define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 212 #define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */ 213 #define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ 214 #define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ 215 #define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 216 #define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 217 218 /* Bit fields for MPAHBRAM IEN */ 219 #define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */ 220 #define _MPAHBRAM_IEN_MASK 0x00000033UL /**< Mask for MPAHBRAM_IEN */ 221 #define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */ 222 #define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ 223 #define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ 224 #define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 225 #define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 226 #define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */ 227 #define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ 228 #define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ 229 #define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 230 #define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 231 #define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */ 232 #define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ 233 #define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ 234 #define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 235 #define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 236 #define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */ 237 #define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ 238 #define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ 239 #define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 240 #define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 241 242 /** @} End of group EFR32BG29_MPAHBRAM_BitFields */ 243 /** @} End of group EFR32BG29_MPAHBRAM */ 244 /** @} End of group Parts */ 245 246 #endif // EFR32BG29_MPAHBRAM_H 247
