1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG27 PRS register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG27_PRS_H 31 #define EFR32BG27_PRS_H 32 #define PRS_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG27_PRS PRS 40 * @{ 41 * @brief EFR32BG27 PRS Register Declaration. 42 *****************************************************************************/ 43 44 /** PRS ASYNC_CH Register Group Declaration. */ 45 typedef struct prs_async_ch_typedef{ 46 __IOM uint32_t CTRL; /**< Async Channel Control Register */ 47 } PRS_ASYNC_CH_TypeDef; 48 49 /** PRS SYNC_CH Register Group Declaration. */ 50 typedef struct prs_sync_ch_typedef{ 51 __IOM uint32_t CTRL; /**< Sync Channel Control Register */ 52 } PRS_SYNC_CH_TypeDef; 53 54 /** PRS Register Declaration. */ 55 typedef struct prs_typedef{ 56 __IM uint32_t IPVERSION; /**< IP version ID */ 57 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 58 __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ 59 __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ 60 __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ 61 __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ 62 PRS_ASYNC_CH_TypeDef ASYNC_CH[12U]; /**< Async Channel registers */ 63 PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ 64 __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */ 65 __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */ 66 __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */ 67 __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */ 68 __IOM uint32_t CONSUMER_EUSART0_TRIGGER; /**< TRIGGER Consumer register */ 69 __IOM uint32_t CONSUMER_FRC_RXRAW; /**< RXRAW consumer register */ 70 __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< SCAN consumer register */ 71 __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< SINGLE Consumer register */ 72 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 consumer register */ 73 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer register */ 74 __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< CLEAR consumer register */ 75 __IOM uint32_t CONSUMER_LETIMER0_START; /**< START Consumer register */ 76 __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */ 77 __IOM uint32_t CONSUMER_MODEM_DIN; /**< DIN consumer register */ 78 __IOM uint32_t CONSUMER_PRORTC_CC0; /**< CC0 consumer register */ 79 __IOM uint32_t CONSUMER_PRORTC_CC1; /**< CC1 Consumer register */ 80 uint32_t RESERVED1[11U]; /**< Reserved for future use */ 81 __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */ 82 __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */ 83 __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */ 84 __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */ 85 __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */ 86 __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */ 87 __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */ 88 __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */ 89 __IOM uint32_t CONSUMER_RAC_SEQ; /**< SEQ Consumer register */ 90 __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */ 91 __IOM uint32_t CONSUMER_RTCC_CC0; /**< CC0 consumer register */ 92 __IOM uint32_t CONSUMER_RTCC_CC1; /**< CC1 Consumer register */ 93 __IOM uint32_t CONSUMER_RTCC_CC2; /**< CC2 Consumer register */ 94 uint32_t RESERVED2[1U]; /**< Reserved for future use */ 95 __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI consumer register */ 96 __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI Consumer register */ 97 __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI Consumer register */ 98 __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI Consumer register */ 99 __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer register */ 100 __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */ 101 __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */ 102 __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */ 103 __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */ 104 __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */ 105 __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */ 106 __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */ 107 __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */ 108 __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */ 109 __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */ 110 __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */ 111 __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */ 112 __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */ 113 __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */ 114 __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */ 115 __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */ 116 __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */ 117 __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */ 118 __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */ 119 __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */ 120 __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */ 121 __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */ 122 __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */ 123 __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */ 124 __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */ 125 __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */ 126 __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */ 127 __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */ 128 __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */ 129 __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */ 130 __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */ 131 __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */ 132 __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */ 133 __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< TRIGGER Consumer register */ 134 uint32_t RESERVED3[3U]; /**< Reserved for future use */ 135 __IOM uint32_t CONSUMER_USART1_CLK; /**< CLK consumer register */ 136 __IOM uint32_t CONSUMER_USART1_IR; /**< IR Consumer register */ 137 __IOM uint32_t CONSUMER_USART1_RX; /**< RX Consumer register */ 138 __IOM uint32_t CONSUMER_USART1_TRIGGER; /**< TRIGGER Consumer register */ 139 __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */ 140 __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */ 141 uint32_t RESERVED4[913U]; /**< Reserved for future use */ 142 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 143 uint32_t RESERVED5[1U]; /**< Reserved for future use */ 144 __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ 145 __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ 146 __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ 147 __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ 148 PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[12U]; /**< Async Channel registers */ 149 PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ 150 __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */ 151 __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */ 152 __IOM uint32_t CONSUMER_EUSART0_CLK_SET; /**< CLK consumer register */ 153 __IOM uint32_t CONSUMER_EUSART0_RX_SET; /**< RX Consumer register */ 154 __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET; /**< TRIGGER Consumer register */ 155 __IOM uint32_t CONSUMER_FRC_RXRAW_SET; /**< RXRAW consumer register */ 156 __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< SCAN consumer register */ 157 __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< SINGLE Consumer register */ 158 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 consumer register */ 159 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer register */ 160 __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< CLEAR consumer register */ 161 __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< START Consumer register */ 162 __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< STOP Consumer register */ 163 __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< DIN consumer register */ 164 __IOM uint32_t CONSUMER_PRORTC_CC0_SET; /**< CC0 consumer register */ 165 __IOM uint32_t CONSUMER_PRORTC_CC1_SET; /**< CC1 Consumer register */ 166 uint32_t RESERVED6[11U]; /**< Reserved for future use */ 167 __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */ 168 __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< CTI Consumer register */ 169 __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< CTI Consumer register */ 170 __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< CTI Consumer register */ 171 __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< CTI Consumer register */ 172 __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< FORCETX Consumer register */ 173 __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */ 174 __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */ 175 __IOM uint32_t CONSUMER_RAC_SEQ_SET; /**< SEQ Consumer register */ 176 __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */ 177 __IOM uint32_t CONSUMER_RTCC_CC0_SET; /**< CC0 consumer register */ 178 __IOM uint32_t CONSUMER_RTCC_CC1_SET; /**< CC1 Consumer register */ 179 __IOM uint32_t CONSUMER_RTCC_CC2_SET; /**< CC2 Consumer register */ 180 uint32_t RESERVED7[1U]; /**< Reserved for future use */ 181 __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI consumer register */ 182 __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI Consumer register */ 183 __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI Consumer register */ 184 __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI Consumer register */ 185 __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer register */ 186 __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< CC0 consumer register */ 187 __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< CC1 Consumer register */ 188 __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< CC2 Consumer register */ 189 __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< DTI Consumer register */ 190 __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< DTI Consumer register */ 191 __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< DTI Consumer register */ 192 __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< CC0 consumer register */ 193 __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< CC1 Consumer register */ 194 __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< CC2 Consumer register */ 195 __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< DTI Consumer register */ 196 __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< DTI Consumer register */ 197 __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< DTI Consumer register */ 198 __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< CC0 consumer register */ 199 __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< CC1 Consumer register */ 200 __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< CC2 Consumer register */ 201 __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< DTI Consumer register */ 202 __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< DTI Consumer register */ 203 __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< DTI Consumer register */ 204 __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< CC0 consumer register */ 205 __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< CC1 Consumer register */ 206 __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< CC2 Consumer register */ 207 __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< DTI Consumer register */ 208 __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< DTI Consumer register */ 209 __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< DTI Consumer register */ 210 __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< CC0 consumer register */ 211 __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< CC1 Consumer register */ 212 __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< CC2 Consumer register */ 213 __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< DTI Consumer register */ 214 __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< DTI Consumer register */ 215 __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< DTI Consumer register */ 216 __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< CLK consumer register */ 217 __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */ 218 __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */ 219 __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< TRIGGER Consumer register */ 220 uint32_t RESERVED8[3U]; /**< Reserved for future use */ 221 __IOM uint32_t CONSUMER_USART1_CLK_SET; /**< CLK consumer register */ 222 __IOM uint32_t CONSUMER_USART1_IR_SET; /**< IR Consumer register */ 223 __IOM uint32_t CONSUMER_USART1_RX_SET; /**< RX Consumer register */ 224 __IOM uint32_t CONSUMER_USART1_TRIGGER_SET; /**< TRIGGER Consumer register */ 225 __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< SRC0 consumer register */ 226 __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< SRC1 Consumer register */ 227 uint32_t RESERVED9[913U]; /**< Reserved for future use */ 228 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 229 uint32_t RESERVED10[1U]; /**< Reserved for future use */ 230 __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ 231 __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ 232 __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ 233 __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ 234 PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[12U]; /**< Async Channel registers */ 235 PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ 236 __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */ 237 __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */ 238 __IOM uint32_t CONSUMER_EUSART0_CLK_CLR; /**< CLK consumer register */ 239 __IOM uint32_t CONSUMER_EUSART0_RX_CLR; /**< RX Consumer register */ 240 __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ 241 __IOM uint32_t CONSUMER_FRC_RXRAW_CLR; /**< RXRAW consumer register */ 242 __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< SCAN consumer register */ 243 __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< SINGLE Consumer register */ 244 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 consumer register */ 245 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer register */ 246 __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< CLEAR consumer register */ 247 __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< START Consumer register */ 248 __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< STOP Consumer register */ 249 __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< DIN consumer register */ 250 __IOM uint32_t CONSUMER_PRORTC_CC0_CLR; /**< CC0 consumer register */ 251 __IOM uint32_t CONSUMER_PRORTC_CC1_CLR; /**< CC1 Consumer register */ 252 uint32_t RESERVED11[11U]; /**< Reserved for future use */ 253 __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */ 254 __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< CTI Consumer register */ 255 __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< CTI Consumer register */ 256 __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< CTI Consumer register */ 257 __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< CTI Consumer register */ 258 __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< FORCETX Consumer register */ 259 __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */ 260 __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */ 261 __IOM uint32_t CONSUMER_RAC_SEQ_CLR; /**< SEQ Consumer register */ 262 __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */ 263 __IOM uint32_t CONSUMER_RTCC_CC0_CLR; /**< CC0 consumer register */ 264 __IOM uint32_t CONSUMER_RTCC_CC1_CLR; /**< CC1 Consumer register */ 265 __IOM uint32_t CONSUMER_RTCC_CC2_CLR; /**< CC2 Consumer register */ 266 uint32_t RESERVED12[1U]; /**< Reserved for future use */ 267 __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI consumer register */ 268 __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI Consumer register */ 269 __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI Consumer register */ 270 __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI Consumer register */ 271 __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer register */ 272 __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< CC0 consumer register */ 273 __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< CC1 Consumer register */ 274 __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< CC2 Consumer register */ 275 __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< DTI Consumer register */ 276 __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< DTI Consumer register */ 277 __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< DTI Consumer register */ 278 __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< CC0 consumer register */ 279 __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< CC1 Consumer register */ 280 __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< CC2 Consumer register */ 281 __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< DTI Consumer register */ 282 __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< DTI Consumer register */ 283 __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< DTI Consumer register */ 284 __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< CC0 consumer register */ 285 __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< CC1 Consumer register */ 286 __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< CC2 Consumer register */ 287 __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< DTI Consumer register */ 288 __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< DTI Consumer register */ 289 __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< DTI Consumer register */ 290 __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< CC0 consumer register */ 291 __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< CC1 Consumer register */ 292 __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< CC2 Consumer register */ 293 __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< DTI Consumer register */ 294 __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< DTI Consumer register */ 295 __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< DTI Consumer register */ 296 __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< CC0 consumer register */ 297 __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< CC1 Consumer register */ 298 __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< CC2 Consumer register */ 299 __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< DTI Consumer register */ 300 __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< DTI Consumer register */ 301 __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< DTI Consumer register */ 302 __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< CLK consumer register */ 303 __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */ 304 __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */ 305 __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ 306 uint32_t RESERVED13[3U]; /**< Reserved for future use */ 307 __IOM uint32_t CONSUMER_USART1_CLK_CLR; /**< CLK consumer register */ 308 __IOM uint32_t CONSUMER_USART1_IR_CLR; /**< IR Consumer register */ 309 __IOM uint32_t CONSUMER_USART1_RX_CLR; /**< RX Consumer register */ 310 __IOM uint32_t CONSUMER_USART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ 311 __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< SRC0 consumer register */ 312 __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< SRC1 Consumer register */ 313 uint32_t RESERVED14[913U]; /**< Reserved for future use */ 314 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 315 uint32_t RESERVED15[1U]; /**< Reserved for future use */ 316 __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ 317 __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ 318 __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ 319 __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ 320 PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[12U]; /**< Async Channel registers */ 321 PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ 322 __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */ 323 __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */ 324 __IOM uint32_t CONSUMER_EUSART0_CLK_TGL; /**< CLK consumer register */ 325 __IOM uint32_t CONSUMER_EUSART0_RX_TGL; /**< RX Consumer register */ 326 __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ 327 __IOM uint32_t CONSUMER_FRC_RXRAW_TGL; /**< RXRAW consumer register */ 328 __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< SCAN consumer register */ 329 __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< SINGLE Consumer register */ 330 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 consumer register */ 331 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer register */ 332 __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< CLEAR consumer register */ 333 __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< START Consumer register */ 334 __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< STOP Consumer register */ 335 __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< DIN consumer register */ 336 __IOM uint32_t CONSUMER_PRORTC_CC0_TGL; /**< CC0 consumer register */ 337 __IOM uint32_t CONSUMER_PRORTC_CC1_TGL; /**< CC1 Consumer register */ 338 uint32_t RESERVED16[11U]; /**< Reserved for future use */ 339 __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */ 340 __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< CTI Consumer register */ 341 __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< CTI Consumer register */ 342 __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< CTI Consumer register */ 343 __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< CTI Consumer register */ 344 __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< FORCETX Consumer register */ 345 __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */ 346 __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */ 347 __IOM uint32_t CONSUMER_RAC_SEQ_TGL; /**< SEQ Consumer register */ 348 __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */ 349 __IOM uint32_t CONSUMER_RTCC_CC0_TGL; /**< CC0 consumer register */ 350 __IOM uint32_t CONSUMER_RTCC_CC1_TGL; /**< CC1 Consumer register */ 351 __IOM uint32_t CONSUMER_RTCC_CC2_TGL; /**< CC2 Consumer register */ 352 uint32_t RESERVED17[1U]; /**< Reserved for future use */ 353 __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI consumer register */ 354 __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI Consumer register */ 355 __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI Consumer register */ 356 __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI Consumer register */ 357 __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer register */ 358 __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< CC0 consumer register */ 359 __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< CC1 Consumer register */ 360 __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< CC2 Consumer register */ 361 __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< DTI Consumer register */ 362 __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< DTI Consumer register */ 363 __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< DTI Consumer register */ 364 __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< CC0 consumer register */ 365 __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< CC1 Consumer register */ 366 __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< CC2 Consumer register */ 367 __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< DTI Consumer register */ 368 __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< DTI Consumer register */ 369 __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< DTI Consumer register */ 370 __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< CC0 consumer register */ 371 __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< CC1 Consumer register */ 372 __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< CC2 Consumer register */ 373 __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< DTI Consumer register */ 374 __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< DTI Consumer register */ 375 __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< DTI Consumer register */ 376 __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< CC0 consumer register */ 377 __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< CC1 Consumer register */ 378 __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< CC2 Consumer register */ 379 __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< DTI Consumer register */ 380 __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< DTI Consumer register */ 381 __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< DTI Consumer register */ 382 __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< CC0 consumer register */ 383 __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< CC1 Consumer register */ 384 __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< CC2 Consumer register */ 385 __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< DTI Consumer register */ 386 __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< DTI Consumer register */ 387 __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< DTI Consumer register */ 388 __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< CLK consumer register */ 389 __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */ 390 __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */ 391 __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ 392 uint32_t RESERVED18[3U]; /**< Reserved for future use */ 393 __IOM uint32_t CONSUMER_USART1_CLK_TGL; /**< CLK consumer register */ 394 __IOM uint32_t CONSUMER_USART1_IR_TGL; /**< IR Consumer register */ 395 __IOM uint32_t CONSUMER_USART1_RX_TGL; /**< RX Consumer register */ 396 __IOM uint32_t CONSUMER_USART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ 397 __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< SRC0 consumer register */ 398 __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< SRC1 Consumer register */ 399 } PRS_TypeDef; 400 /** @} End of group EFR32BG27_PRS */ 401 402 /**************************************************************************//** 403 * @addtogroup EFR32BG27_PRS 404 * @{ 405 * @defgroup EFR32BG27_PRS_BitFields PRS Bit Fields 406 * @{ 407 *****************************************************************************/ 408 409 /* Bit fields for PRS IPVERSION */ 410 #define _PRS_IPVERSION_RESETVALUE 0x00000005UL /**< Default value for PRS_IPVERSION */ 411 #define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ 412 #define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ 413 #define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ 414 #define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000005UL /**< Mode DEFAULT for PRS_IPVERSION */ 415 #define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ 416 417 /* Bit fields for PRS ASYNC_SWPULSE */ 418 #define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ 419 #define _PRS_ASYNC_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWPULSE */ 420 #define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ 421 #define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ 422 #define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ 423 #define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 424 #define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 425 #define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ 426 #define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ 427 #define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ 428 #define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 429 #define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 430 #define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ 431 #define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ 432 #define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ 433 #define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 434 #define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 435 #define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ 436 #define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ 437 #define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ 438 #define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 439 #define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 440 #define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ 441 #define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ 442 #define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ 443 #define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 444 #define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 445 #define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ 446 #define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ 447 #define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ 448 #define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 449 #define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 450 #define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ 451 #define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ 452 #define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ 453 #define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 454 #define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 455 #define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ 456 #define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ 457 #define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ 458 #define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 459 #define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 460 #define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ 461 #define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ 462 #define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ 463 #define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 464 #define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 465 #define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ 466 #define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ 467 #define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ 468 #define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 469 #define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 470 #define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ 471 #define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ 472 #define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ 473 #define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 474 #define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 475 #define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ 476 #define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ 477 #define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ 478 #define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 479 #define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 480 481 /* Bit fields for PRS ASYNC_SWLEVEL */ 482 #define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ 483 #define _PRS_ASYNC_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ 484 #define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ 485 #define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ 486 #define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ 487 #define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 488 #define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 489 #define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ 490 #define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ 491 #define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ 492 #define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 493 #define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 494 #define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ 495 #define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ 496 #define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ 497 #define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 498 #define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 499 #define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ 500 #define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ 501 #define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ 502 #define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 503 #define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 504 #define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ 505 #define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ 506 #define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ 507 #define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 508 #define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 509 #define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ 510 #define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ 511 #define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ 512 #define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 513 #define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 514 #define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ 515 #define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ 516 #define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ 517 #define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 518 #define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 519 #define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ 520 #define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ 521 #define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ 522 #define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 523 #define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 524 #define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ 525 #define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ 526 #define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ 527 #define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 528 #define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 529 #define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ 530 #define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ 531 #define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ 532 #define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 533 #define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 534 #define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ 535 #define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ 536 #define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ 537 #define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 538 #define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 539 #define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ 540 #define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ 541 #define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ 542 #define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 543 #define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 544 545 /* Bit fields for PRS ASYNC_PEEK */ 546 #define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ 547 #define _PRS_ASYNC_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_PEEK */ 548 #define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ 549 #define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ 550 #define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ 551 #define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 552 #define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 553 #define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ 554 #define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ 555 #define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ 556 #define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 557 #define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 558 #define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ 559 #define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ 560 #define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ 561 #define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 562 #define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 563 #define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ 564 #define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ 565 #define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ 566 #define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 567 #define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 568 #define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ 569 #define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ 570 #define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ 571 #define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 572 #define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 573 #define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ 574 #define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ 575 #define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ 576 #define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 577 #define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 578 #define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ 579 #define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ 580 #define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ 581 #define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 582 #define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 583 #define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ 584 #define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ 585 #define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ 586 #define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 587 #define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 588 #define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ 589 #define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ 590 #define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ 591 #define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 592 #define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 593 #define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ 594 #define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ 595 #define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ 596 #define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 597 #define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 598 #define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ 599 #define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ 600 #define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ 601 #define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 602 #define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 603 #define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ 604 #define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ 605 #define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ 606 #define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 607 #define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 608 609 /* Bit fields for PRS SYNC_PEEK */ 610 #define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ 611 #define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ 612 #define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ 613 #define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ 614 #define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ 615 #define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ 616 #define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ 617 #define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ 618 #define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ 619 #define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ 620 #define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ 621 #define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ 622 #define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ 623 #define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ 624 #define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ 625 #define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ 626 #define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ 627 #define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ 628 #define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ 629 #define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ 630 #define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ 631 #define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ 632 633 /* Bit fields for PRS ASYNC_CH_CTRL */ 634 #define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ 635 #define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ 636 #define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ 637 #define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ 638 #define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ 639 #define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ 640 #define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ 641 #define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ 642 #define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ 643 #define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ 644 #define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ 645 #define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ 646 #define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ 647 #define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ 648 #define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ 649 #define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ 650 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ 651 #define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ 652 #define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ 653 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ 654 #define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ 655 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ 656 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ 657 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ 658 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ 659 #define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ 660 #define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ 661 #define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ 662 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ 663 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ 664 #define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ 665 #define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ 666 #define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ 667 #define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ 668 #define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ 669 #define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ 670 #define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ 671 #define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ 672 #define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ 673 #define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ 674 #define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ 675 #define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ 676 #define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ 677 #define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ 678 #define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ 679 #define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ 680 #define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ 681 #define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ 682 #define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ 683 #define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ 684 #define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ 685 #define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ 686 687 /* Bit fields for PRS SYNC_CH_CTRL */ 688 #define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ 689 #define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ 690 #define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ 691 #define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ 692 #define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ 693 #define _PRS_SYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_SYNC_CH_CTRL */ 694 #define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ 695 #define PRS_SYNC_CH_CTRL_SIGSEL_NONE (_PRS_SYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_SYNC_CH_CTRL */ 696 #define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ 697 #define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ 698 #define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ 699 #define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ 700 701 /* Bit fields for PRS CONSUMER_CMU_CALDN */ 702 #define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ 703 #define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ 704 #define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 705 #define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 706 #define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ 707 #define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ 708 709 /* Bit fields for PRS CONSUMER_CMU_CALUP */ 710 #define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ 711 #define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ 712 #define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 713 #define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 714 #define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ 715 #define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ 716 717 /* Bit fields for PRS CONSUMER_EUSART0_CLK */ 718 #define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */ 719 #define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */ 720 #define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 721 #define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 722 #define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */ 723 #define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/ 724 725 /* Bit fields for PRS CONSUMER_EUSART0_RX */ 726 #define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */ 727 #define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */ 728 #define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 729 #define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 730 #define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */ 731 #define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/ 732 733 /* Bit fields for PRS CONSUMER_EUSART0_TRIGGER */ 734 #define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/ 735 #define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */ 736 #define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 737 #define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 738 #define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ 739 #define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ 740 741 /* Bit fields for PRS CONSUMER_FRC_RXRAW */ 742 #define _PRS_CONSUMER_FRC_RXRAW_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_FRC_RXRAW */ 743 #define _PRS_CONSUMER_FRC_RXRAW_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_FRC_RXRAW */ 744 #define _PRS_CONSUMER_FRC_RXRAW_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 745 #define _PRS_CONSUMER_FRC_RXRAW_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 746 #define _PRS_CONSUMER_FRC_RXRAW_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_FRC_RXRAW */ 747 #define PRS_CONSUMER_FRC_RXRAW_PRSSEL_DEFAULT (_PRS_CONSUMER_FRC_RXRAW_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_FRC_RXRAW*/ 748 749 /* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ 750 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ 751 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ 752 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 753 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 754 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ 755 #define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ 756 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 757 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 758 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ 759 #define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ 760 761 /* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ 762 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ 763 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ 764 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 765 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 766 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ 767 #define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ 768 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 769 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 770 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ 771 #define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ 772 773 /* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ 774 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ 775 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ 776 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 777 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 778 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ 779 #define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ 780 781 /* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ 782 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ 783 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ 784 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 785 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 786 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ 787 #define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ 788 789 /* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ 790 #define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ 791 #define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ 792 #define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 793 #define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 794 #define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ 795 #define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ 796 797 /* Bit fields for PRS CONSUMER_LETIMER0_START */ 798 #define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ 799 #define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ 800 #define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 801 #define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 802 #define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ 803 #define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ 804 805 /* Bit fields for PRS CONSUMER_LETIMER0_STOP */ 806 #define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ 807 #define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ 808 #define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 809 #define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 810 #define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ 811 #define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ 812 813 /* Bit fields for PRS CONSUMER_MODEM_DIN */ 814 #define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ 815 #define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ 816 #define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 817 #define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 818 #define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ 819 #define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ 820 821 /* Bit fields for PRS CONSUMER_PRORTC_CC0 */ 822 #define _PRS_CONSUMER_PRORTC_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PRORTC_CC0 */ 823 #define _PRS_CONSUMER_PRORTC_CC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PRORTC_CC0 */ 824 #define _PRS_CONSUMER_PRORTC_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 825 #define _PRS_CONSUMER_PRORTC_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 826 #define _PRS_CONSUMER_PRORTC_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PRORTC_CC0 */ 827 #define PRS_CONSUMER_PRORTC_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_PRORTC_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PRORTC_CC0*/ 828 829 /* Bit fields for PRS CONSUMER_PRORTC_CC1 */ 830 #define _PRS_CONSUMER_PRORTC_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PRORTC_CC1 */ 831 #define _PRS_CONSUMER_PRORTC_CC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PRORTC_CC1 */ 832 #define _PRS_CONSUMER_PRORTC_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 833 #define _PRS_CONSUMER_PRORTC_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 834 #define _PRS_CONSUMER_PRORTC_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PRORTC_CC1 */ 835 #define PRS_CONSUMER_PRORTC_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_PRORTC_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PRORTC_CC1*/ 836 837 /* Bit fields for PRS CONSUMER_RAC_CLR */ 838 #define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ 839 #define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ 840 #define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 841 #define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 842 #define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ 843 #define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ 844 845 /* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ 846 #define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ 847 #define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ 848 #define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 849 #define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 850 #define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ 851 #define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ 852 853 /* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ 854 #define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ 855 #define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ 856 #define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 857 #define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 858 #define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ 859 #define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ 860 861 /* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ 862 #define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ 863 #define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ 864 #define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 865 #define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 866 #define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ 867 #define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ 868 869 /* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ 870 #define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ 871 #define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ 872 #define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 873 #define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 874 #define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ 875 #define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ 876 877 /* Bit fields for PRS CONSUMER_RAC_FORCETX */ 878 #define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ 879 #define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ 880 #define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 881 #define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 882 #define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ 883 #define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ 884 885 /* Bit fields for PRS CONSUMER_RAC_RXDIS */ 886 #define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ 887 #define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ 888 #define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 889 #define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 890 #define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ 891 #define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ 892 893 /* Bit fields for PRS CONSUMER_RAC_RXEN */ 894 #define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ 895 #define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ 896 #define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 897 #define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 898 #define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ 899 #define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ 900 901 /* Bit fields for PRS CONSUMER_RAC_SEQ */ 902 #define _PRS_CONSUMER_RAC_SEQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_SEQ */ 903 #define _PRS_CONSUMER_RAC_SEQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_SEQ */ 904 #define _PRS_CONSUMER_RAC_SEQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 905 #define _PRS_CONSUMER_RAC_SEQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 906 #define _PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_SEQ */ 907 #define PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_SEQ*/ 908 909 /* Bit fields for PRS CONSUMER_RAC_TXEN */ 910 #define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ 911 #define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ 912 #define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 913 #define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 914 #define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ 915 #define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ 916 917 /* Bit fields for PRS CONSUMER_RTCC_CC0 */ 918 #define _PRS_CONSUMER_RTCC_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC0 */ 919 #define _PRS_CONSUMER_RTCC_CC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC0 */ 920 #define _PRS_CONSUMER_RTCC_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 921 #define _PRS_CONSUMER_RTCC_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 922 #define _PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC0 */ 923 #define PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC0*/ 924 925 /* Bit fields for PRS CONSUMER_RTCC_CC1 */ 926 #define _PRS_CONSUMER_RTCC_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC1 */ 927 #define _PRS_CONSUMER_RTCC_CC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC1 */ 928 #define _PRS_CONSUMER_RTCC_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 929 #define _PRS_CONSUMER_RTCC_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 930 #define _PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC1 */ 931 #define PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC1*/ 932 933 /* Bit fields for PRS CONSUMER_RTCC_CC2 */ 934 #define _PRS_CONSUMER_RTCC_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC2 */ 935 #define _PRS_CONSUMER_RTCC_CC2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC2 */ 936 #define _PRS_CONSUMER_RTCC_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 937 #define _PRS_CONSUMER_RTCC_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 938 #define _PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC2 */ 939 #define PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC2*/ 940 941 /* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ 942 #define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ 943 #define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ 944 #define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 945 #define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 946 #define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ 947 #define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ 948 949 /* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ 950 #define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ 951 #define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ 952 #define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 953 #define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 954 #define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ 955 #define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ 956 957 /* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ 958 #define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ 959 #define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ 960 #define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 961 #define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 962 #define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ 963 #define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ 964 965 /* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ 966 #define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ 967 #define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ 968 #define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 969 #define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 970 #define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ 971 #define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ 972 973 /* Bit fields for PRS CONSUMER_CORE_M33RXEV */ 974 #define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ 975 #define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ 976 #define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 977 #define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 978 #define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ 979 #define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ 980 981 /* Bit fields for PRS CONSUMER_TIMER0_CC0 */ 982 #define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ 983 #define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ 984 #define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 985 #define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 986 #define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ 987 #define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ 988 #define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 989 #define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 990 #define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ 991 #define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ 992 993 /* Bit fields for PRS CONSUMER_TIMER0_CC1 */ 994 #define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ 995 #define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ 996 #define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 997 #define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 998 #define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ 999 #define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ 1000 #define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1001 #define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1002 #define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ 1003 #define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ 1004 1005 /* Bit fields for PRS CONSUMER_TIMER0_CC2 */ 1006 #define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ 1007 #define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ 1008 #define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1009 #define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1010 #define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ 1011 #define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ 1012 #define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1013 #define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1014 #define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ 1015 #define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ 1016 1017 /* Bit fields for PRS CONSUMER_TIMER0_DTI */ 1018 #define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ 1019 #define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ 1020 #define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1021 #define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1022 #define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ 1023 #define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ 1024 1025 /* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ 1026 #define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ 1027 #define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ 1028 #define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1029 #define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1030 #define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ 1031 #define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ 1032 1033 /* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ 1034 #define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ 1035 #define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ 1036 #define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1037 #define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1038 #define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ 1039 #define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ 1040 1041 /* Bit fields for PRS CONSUMER_TIMER1_CC0 */ 1042 #define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ 1043 #define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ 1044 #define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1045 #define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1046 #define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ 1047 #define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ 1048 #define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1049 #define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1050 #define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ 1051 #define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ 1052 1053 /* Bit fields for PRS CONSUMER_TIMER1_CC1 */ 1054 #define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ 1055 #define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ 1056 #define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1057 #define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1058 #define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ 1059 #define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ 1060 #define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1061 #define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1062 #define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ 1063 #define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ 1064 1065 /* Bit fields for PRS CONSUMER_TIMER1_CC2 */ 1066 #define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ 1067 #define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ 1068 #define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1069 #define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1070 #define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ 1071 #define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ 1072 #define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1073 #define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1074 #define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ 1075 #define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ 1076 1077 /* Bit fields for PRS CONSUMER_TIMER1_DTI */ 1078 #define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ 1079 #define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ 1080 #define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1081 #define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1082 #define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ 1083 #define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ 1084 1085 /* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ 1086 #define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ 1087 #define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ 1088 #define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1089 #define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1090 #define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ 1091 #define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ 1092 1093 /* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ 1094 #define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ 1095 #define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ 1096 #define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1097 #define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1098 #define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ 1099 #define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ 1100 1101 /* Bit fields for PRS CONSUMER_TIMER2_CC0 */ 1102 #define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ 1103 #define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ 1104 #define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1105 #define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1106 #define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ 1107 #define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ 1108 #define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1109 #define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1110 #define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ 1111 #define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ 1112 1113 /* Bit fields for PRS CONSUMER_TIMER2_CC1 */ 1114 #define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ 1115 #define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ 1116 #define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1117 #define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1118 #define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ 1119 #define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ 1120 #define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1121 #define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1122 #define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ 1123 #define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ 1124 1125 /* Bit fields for PRS CONSUMER_TIMER2_CC2 */ 1126 #define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ 1127 #define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ 1128 #define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1129 #define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1130 #define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ 1131 #define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ 1132 #define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1133 #define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1134 #define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ 1135 #define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ 1136 1137 /* Bit fields for PRS CONSUMER_TIMER2_DTI */ 1138 #define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ 1139 #define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ 1140 #define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1141 #define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1142 #define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ 1143 #define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ 1144 1145 /* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ 1146 #define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ 1147 #define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ 1148 #define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1149 #define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1150 #define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ 1151 #define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ 1152 1153 /* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ 1154 #define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ 1155 #define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ 1156 #define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1157 #define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1158 #define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ 1159 #define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ 1160 1161 /* Bit fields for PRS CONSUMER_TIMER3_CC0 */ 1162 #define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ 1163 #define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ 1164 #define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1165 #define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1166 #define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ 1167 #define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ 1168 #define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1169 #define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1170 #define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ 1171 #define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ 1172 1173 /* Bit fields for PRS CONSUMER_TIMER3_CC1 */ 1174 #define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ 1175 #define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ 1176 #define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1177 #define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1178 #define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ 1179 #define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ 1180 #define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1181 #define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1182 #define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ 1183 #define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ 1184 1185 /* Bit fields for PRS CONSUMER_TIMER3_CC2 */ 1186 #define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ 1187 #define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ 1188 #define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1189 #define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1190 #define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ 1191 #define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ 1192 #define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1193 #define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1194 #define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ 1195 #define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ 1196 1197 /* Bit fields for PRS CONSUMER_TIMER3_DTI */ 1198 #define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ 1199 #define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ 1200 #define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1201 #define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1202 #define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ 1203 #define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ 1204 1205 /* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ 1206 #define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ 1207 #define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ 1208 #define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1209 #define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1210 #define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ 1211 #define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ 1212 1213 /* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ 1214 #define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ 1215 #define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ 1216 #define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1217 #define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1218 #define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ 1219 #define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ 1220 1221 /* Bit fields for PRS CONSUMER_TIMER4_CC0 */ 1222 #define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ 1223 #define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ 1224 #define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1225 #define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1226 #define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ 1227 #define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ 1228 #define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1229 #define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1230 #define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ 1231 #define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ 1232 1233 /* Bit fields for PRS CONSUMER_TIMER4_CC1 */ 1234 #define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ 1235 #define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ 1236 #define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1237 #define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1238 #define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ 1239 #define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ 1240 #define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1241 #define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1242 #define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ 1243 #define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ 1244 1245 /* Bit fields for PRS CONSUMER_TIMER4_CC2 */ 1246 #define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ 1247 #define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ 1248 #define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1249 #define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1250 #define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ 1251 #define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ 1252 #define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1253 #define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1254 #define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ 1255 #define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ 1256 1257 /* Bit fields for PRS CONSUMER_TIMER4_DTI */ 1258 #define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ 1259 #define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ 1260 #define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1261 #define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1262 #define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ 1263 #define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ 1264 1265 /* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ 1266 #define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ 1267 #define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ 1268 #define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1269 #define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1270 #define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ 1271 #define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ 1272 1273 /* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ 1274 #define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ 1275 #define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ 1276 #define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1277 #define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1278 #define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ 1279 #define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ 1280 1281 /* Bit fields for PRS CONSUMER_USART0_CLK */ 1282 #define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ 1283 #define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ 1284 #define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1285 #define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1286 #define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ 1287 #define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ 1288 1289 /* Bit fields for PRS CONSUMER_USART0_IR */ 1290 #define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ 1291 #define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ 1292 #define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1293 #define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1294 #define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ 1295 #define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ 1296 1297 /* Bit fields for PRS CONSUMER_USART0_RX */ 1298 #define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ 1299 #define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ 1300 #define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1301 #define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1302 #define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ 1303 #define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ 1304 1305 /* Bit fields for PRS CONSUMER_USART0_TRIGGER */ 1306 #define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ 1307 #define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ 1308 #define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1309 #define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1310 #define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ 1311 #define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ 1312 1313 /* Bit fields for PRS CONSUMER_USART1_CLK */ 1314 #define _PRS_CONSUMER_USART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_CLK */ 1315 #define _PRS_CONSUMER_USART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_CLK */ 1316 #define _PRS_CONSUMER_USART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1317 #define _PRS_CONSUMER_USART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1318 #define _PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_CLK */ 1319 #define PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_CLK*/ 1320 1321 /* Bit fields for PRS CONSUMER_USART1_IR */ 1322 #define _PRS_CONSUMER_USART1_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_IR */ 1323 #define _PRS_CONSUMER_USART1_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_IR */ 1324 #define _PRS_CONSUMER_USART1_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1325 #define _PRS_CONSUMER_USART1_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1326 #define _PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_IR */ 1327 #define PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_IR*/ 1328 1329 /* Bit fields for PRS CONSUMER_USART1_RX */ 1330 #define _PRS_CONSUMER_USART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_RX */ 1331 #define _PRS_CONSUMER_USART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_RX */ 1332 #define _PRS_CONSUMER_USART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1333 #define _PRS_CONSUMER_USART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1334 #define _PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_RX */ 1335 #define PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_RX*/ 1336 1337 /* Bit fields for PRS CONSUMER_USART1_TRIGGER */ 1338 #define _PRS_CONSUMER_USART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_TRIGGER*/ 1339 #define _PRS_CONSUMER_USART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_TRIGGER */ 1340 #define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1341 #define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1342 #define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ 1343 #define PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ 1344 1345 /* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ 1346 #define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ 1347 #define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ 1348 #define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1349 #define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1350 #define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ 1351 #define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ 1352 1353 /* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ 1354 #define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ 1355 #define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ 1356 #define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1357 #define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1358 #define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ 1359 #define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ 1360 1361 /** @} End of group EFR32BG27_PRS_BitFields */ 1362 /** @} End of group EFR32BG27_PRS */ 1363 /** @} End of group Parts */ 1364 1365 #endif // EFR32BG27_PRS_H 1366
