1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG27 EUSART register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG27_EUSART_H 31 #define EFR32BG27_EUSART_H 32 #define EUSART_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG27_EUSART EUSART 40 * @{ 41 * @brief EFR32BG27 EUSART Register Declaration. 42 *****************************************************************************/ 43 44 /** EUSART Register Declaration. */ 45 typedef struct eusart_typedef{ 46 __IM uint32_t IPVERSION; /**< IP version ID */ 47 __IOM uint32_t EN; /**< Enable Register */ 48 __IOM uint32_t CFG0; /**< Configuration 0 Register */ 49 __IOM uint32_t CFG1; /**< Configuration 1 Register */ 50 __IOM uint32_t CFG2; /**< Configuration 2 Register */ 51 __IOM uint32_t FRAMECFG; /**< Frame Format Register */ 52 __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */ 53 __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ 54 __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ 55 __IOM uint32_t TIMINGCFG; /**< Timing Register */ 56 __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ 57 __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ 58 __IOM uint32_t CLKDIV; /**< Clock Divider Register */ 59 __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ 60 __IOM uint32_t CMD; /**< Command Register */ 61 __IM uint32_t RXDATA; /**< RX Data Register */ 62 __IM uint32_t RXDATAP; /**< RX Data Peek Register */ 63 __IOM uint32_t TXDATA; /**< TX Data Register */ 64 __IM uint32_t STATUS; /**< Status Register */ 65 __IOM uint32_t IF; /**< Interrupt Flag Register */ 66 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 67 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 68 uint32_t RESERVED0[42U]; /**< Reserved for future use */ 69 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 70 uint32_t RESERVED2[959U]; /**< Reserved for future use */ 71 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 72 __IOM uint32_t EN_SET; /**< Enable Register */ 73 __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ 74 __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ 75 __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */ 76 __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ 77 __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */ 78 __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ 79 __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ 80 __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ 81 __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ 82 __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ 83 __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ 84 __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ 85 __IOM uint32_t CMD_SET; /**< Command Register */ 86 __IM uint32_t RXDATA_SET; /**< RX Data Register */ 87 __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ 88 __IOM uint32_t TXDATA_SET; /**< TX Data Register */ 89 __IM uint32_t STATUS_SET; /**< Status Register */ 90 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 91 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 92 __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ 93 uint32_t RESERVED3[42U]; /**< Reserved for future use */ 94 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 95 uint32_t RESERVED5[959U]; /**< Reserved for future use */ 96 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 97 __IOM uint32_t EN_CLR; /**< Enable Register */ 98 __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ 99 __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ 100 __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */ 101 __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ 102 __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */ 103 __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ 104 __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ 105 __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ 106 __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ 107 __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ 108 __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ 109 __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ 110 __IOM uint32_t CMD_CLR; /**< Command Register */ 111 __IM uint32_t RXDATA_CLR; /**< RX Data Register */ 112 __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ 113 __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ 114 __IM uint32_t STATUS_CLR; /**< Status Register */ 115 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 116 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 117 __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ 118 uint32_t RESERVED6[42U]; /**< Reserved for future use */ 119 uint32_t RESERVED7[1U]; /**< Reserved for future use */ 120 uint32_t RESERVED8[959U]; /**< Reserved for future use */ 121 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 122 __IOM uint32_t EN_TGL; /**< Enable Register */ 123 __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ 124 __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ 125 __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */ 126 __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ 127 __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */ 128 __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ 129 __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ 130 __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ 131 __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ 132 __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ 133 __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ 134 __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ 135 __IOM uint32_t CMD_TGL; /**< Command Register */ 136 __IM uint32_t RXDATA_TGL; /**< RX Data Register */ 137 __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ 138 __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ 139 __IM uint32_t STATUS_TGL; /**< Status Register */ 140 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 141 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 142 __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ 143 uint32_t RESERVED9[42U]; /**< Reserved for future use */ 144 uint32_t RESERVED10[1U]; /**< Reserved for future use */ 145 } EUSART_TypeDef; 146 /** @} End of group EFR32BG27_EUSART */ 147 148 /**************************************************************************//** 149 * @addtogroup EFR32BG27_EUSART 150 * @{ 151 * @defgroup EFR32BG27_EUSART_BitFields EUSART Bit Fields 152 * @{ 153 *****************************************************************************/ 154 155 /* Bit fields for EUSART IPVERSION */ 156 #define _EUSART_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for EUSART_IPVERSION */ 157 #define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ 158 #define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ 159 #define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ 160 #define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_IPVERSION */ 161 #define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ 162 163 /* Bit fields for EUSART EN */ 164 #define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ 165 #define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */ 166 #define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ 167 #define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ 168 #define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ 169 #define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ 170 #define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ 171 #define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ 172 #define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */ 173 #define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */ 174 #define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ 175 #define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */ 176 177 /* Bit fields for EUSART CFG0 */ 178 #define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ 179 #define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */ 180 #define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */ 181 #define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */ 182 #define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */ 183 #define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 184 #define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */ 185 #define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */ 186 #define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 187 #define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */ 188 #define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */ 189 #define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ 190 #define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ 191 #define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ 192 #define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 193 #define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 194 #define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 195 #define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 196 #define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ 197 #define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ 198 #define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ 199 #define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ 200 #define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ 201 #define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 202 #define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 203 #define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 204 #define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 205 #define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ 206 #define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ 207 #define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ 208 #define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ 209 #define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ 210 #define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 211 #define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 212 #define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 213 #define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 214 #define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ 215 #define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ 216 #define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ 217 #define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ 218 #define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ 219 #define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 220 #define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 221 #define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ 222 #define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ 223 #define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 224 #define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ 225 #define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ 226 #define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ 227 #define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ 228 #define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ 229 #define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 230 #define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ 231 #define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ 232 #define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ 233 #define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ 234 #define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ 235 #define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ 236 #define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ 237 #define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ 238 #define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 239 #define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 240 #define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 241 #define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 242 #define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ 243 #define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ 244 #define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ 245 #define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ 246 #define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ 247 #define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 248 #define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 249 #define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 250 #define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 251 #define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ 252 #define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ 253 #define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ 254 #define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ 255 #define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ 256 #define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 257 #define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 258 #define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 259 #define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 260 #define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ 261 #define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ 262 #define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ 263 #define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ 264 #define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ 265 #define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 266 #define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 267 #define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 268 #define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 269 #define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ 270 #define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ 271 #define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ 272 #define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ 273 #define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ 274 #define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 275 #define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 276 #define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ 277 #define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ 278 #define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ 279 #define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 280 #define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 281 #define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 282 #define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 283 #define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ 284 #define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ 285 #define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ 286 #define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ 287 #define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ 288 #define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 289 #define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 290 #define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 291 #define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 292 #define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ 293 #define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ 294 #define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ 295 #define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ 296 #define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ 297 #define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 298 #define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 299 #define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 300 #define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 301 #define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ 302 #define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ 303 #define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ 304 #define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ 305 #define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ 306 #define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 307 #define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 308 #define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ 309 #define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ 310 #define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ 311 #define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 312 #define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 313 314 /* Bit fields for EUSART CFG1 */ 315 #define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ 316 #define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */ 317 #define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ 318 #define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ 319 #define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ 320 #define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 321 #define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ 322 #define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ 323 #define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 324 #define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ 325 #define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ 326 #define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ 327 #define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ 328 #define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ 329 #define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 330 #define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ 331 #define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ 332 #define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 333 #define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ 334 #define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ 335 #define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ 336 #define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ 337 #define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ 338 #define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 339 #define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ 340 #define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ 341 #define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 342 #define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ 343 #define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ 344 #define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ 345 #define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ 346 #define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ 347 #define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 348 #define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ 349 #define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ 350 #define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 351 #define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ 352 #define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ 353 #define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */ 354 #define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */ 355 #define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 356 #define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */ 357 #define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */ 358 #define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */ 359 #define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */ 360 #define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */ 361 #define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ 362 #define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */ 363 #define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ 364 #define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 365 #define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */ 366 #define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ 367 #define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ 368 #define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ 369 #define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ 370 #define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ 371 #define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ 372 #define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ 373 #define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ 374 #define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ 375 #define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ 376 #define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 377 #define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 378 #define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ 379 #define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ 380 #define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ 381 #define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 382 #define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 383 #define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ 384 #define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ 385 #define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ 386 #define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 387 #define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 388 #define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ 389 #define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ 390 #define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ 391 #define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 392 #define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 393 #define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ 394 #define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */ 395 #define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 396 #define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ 397 #define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ 398 #define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ 399 #define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ 400 #define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ 401 #define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ 402 #define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ 403 #define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ 404 #define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ 405 #define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ 406 #define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ 407 #define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ 408 #define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ 409 #define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ 410 #define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ 411 #define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ 412 #define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 413 #define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ 414 #define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ 415 #define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ 416 #define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ 417 #define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ 418 #define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ 419 #define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ 420 #define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ 421 #define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ 422 #define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ 423 #define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ 424 #define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ 425 #define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ 426 #define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ 427 #define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ 428 #define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ 429 #define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ 430 #define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */ 431 #define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 432 #define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ 433 #define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ 434 #define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ 435 #define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ 436 #define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ 437 #define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ 438 #define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ 439 #define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ 440 #define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ 441 #define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ 442 #define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ 443 #define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ 444 #define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ 445 #define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ 446 #define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ 447 #define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ 448 #define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 449 #define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ 450 #define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ 451 #define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ 452 #define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ 453 #define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ 454 #define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ 455 #define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ 456 #define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ 457 #define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ 458 #define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ 459 #define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ 460 #define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ 461 #define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ 462 #define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ 463 #define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ 464 #define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ 465 #define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */ 466 #define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */ 467 #define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 468 #define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ 469 #define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ 470 #define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ 471 #define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ 472 #define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ 473 #define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ 474 #define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ 475 #define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ 476 #define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ 477 #define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ 478 #define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ 479 #define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ 480 #define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ 481 #define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ 482 #define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ 483 #define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ 484 #define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 485 #define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ 486 #define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ 487 #define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ 488 #define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ 489 #define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ 490 #define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ 491 #define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ 492 #define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ 493 #define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ 494 #define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ 495 #define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ 496 #define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ 497 #define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ 498 #define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ 499 #define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ 500 #define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ 501 502 /* Bit fields for EUSART CFG2 */ 503 #define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */ 504 #define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */ 505 #define EUSART_CFG2_MASTER (0x1UL << 0) /**< Master mode */ 506 #define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */ 507 #define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */ 508 #define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ 509 #define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */ 510 #define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */ 511 #define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */ 512 #define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */ 513 #define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */ 514 #define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */ 515 #define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */ 516 #define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */ 517 #define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ 518 #define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */ 519 #define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */ 520 #define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */ 521 #define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */ 522 #define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */ 523 #define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */ 524 #define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */ 525 #define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */ 526 #define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ 527 #define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */ 528 #define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */ 529 #define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */ 530 #define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */ 531 #define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */ 532 #define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */ 533 #define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */ 534 #define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */ 535 #define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ 536 #define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */ 537 #define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */ 538 #define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */ 539 #define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */ 540 #define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */ 541 #define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */ 542 #define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */ 543 #define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */ 544 #define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ 545 #define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */ 546 #define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */ 547 #define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */ 548 #define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */ 549 #define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */ 550 #define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */ 551 #define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */ 552 #define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */ 553 #define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */ 554 #define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ 555 #define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */ 556 #define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */ 557 #define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */ 558 #define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */ 559 #define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ 560 #define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */ 561 #define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */ 562 #define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */ 563 #define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ 564 #define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */ 565 566 /* Bit fields for EUSART FRAMECFG */ 567 #define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ 568 #define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */ 569 #define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ 570 #define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */ 571 #define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ 572 #define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ 573 #define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ 574 #define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ 575 #define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */ 576 #define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */ 577 #define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */ 578 #define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */ 579 #define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */ 580 #define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */ 581 #define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */ 582 #define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ 583 #define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ 584 #define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ 585 #define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ 586 #define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */ 587 #define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */ 588 #define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */ 589 #define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */ 590 #define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */ 591 #define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */ 592 #define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */ 593 #define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ 594 #define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ 595 #define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ 596 #define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ 597 #define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ 598 #define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ 599 #define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ 600 #define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ 601 #define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ 602 #define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ 603 #define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ 604 #define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ 605 #define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ 606 #define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ 607 #define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ 608 #define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ 609 #define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ 610 #define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ 611 #define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ 612 #define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ 613 #define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ 614 #define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ 615 616 /* Bit fields for EUSART DTXDATCFG */ 617 #define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */ 618 #define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */ 619 #define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */ 620 #define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */ 621 #define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */ 622 #define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */ 623 624 /* Bit fields for EUSART IRHFCFG */ 625 #define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ 626 #define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ 627 #define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ 628 #define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ 629 #define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ 630 #define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ 631 #define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ 632 #define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ 633 #define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ 634 #define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ 635 #define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ 636 #define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ 637 #define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ 638 #define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ 639 #define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ 640 #define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ 641 #define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ 642 #define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ 643 #define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ 644 #define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ 645 #define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ 646 #define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ 647 #define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ 648 #define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ 649 #define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ 650 #define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ 651 #define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ 652 #define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ 653 654 /* Bit fields for EUSART IRLFCFG */ 655 #define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ 656 #define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ 657 #define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ 658 #define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ 659 #define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ 660 #define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ 661 #define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ 662 663 /* Bit fields for EUSART TIMINGCFG */ 664 #define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */ 665 #define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */ 666 #define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ 667 #define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ 668 #define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ 669 #define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ 670 #define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ 671 #define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ 672 #define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ 673 #define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ 674 #define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ 675 #define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ 676 #define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ 677 #define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ 678 #define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */ 679 #define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */ 680 #define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ 681 #define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ 682 #define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ 683 #define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ 684 #define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ 685 #define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ 686 #define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ 687 #define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ 688 #define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ 689 #define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ 690 #define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ 691 #define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */ 692 #define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */ 693 #define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */ 694 #define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ 695 #define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ 696 #define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */ 697 #define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ 698 #define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */ 699 #define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */ 700 #define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ 701 #define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ 702 #define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ 703 #define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ 704 #define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ 705 #define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ 706 #define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ 707 #define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ 708 #define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ 709 #define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ 710 #define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ 711 #define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */ 712 #define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */ 713 #define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */ 714 #define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ 715 #define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ 716 #define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */ 717 #define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ 718 #define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */ 719 #define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */ 720 #define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ 721 #define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ 722 #define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ 723 #define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ 724 #define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ 725 #define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ 726 #define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ 727 #define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ 728 #define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ 729 #define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ 730 #define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ 731 #define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */ 732 #define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */ 733 #define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */ 734 #define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ 735 #define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ 736 #define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */ 737 #define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ 738 #define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */ 739 #define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */ 740 #define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ 741 #define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ 742 743 /* Bit fields for EUSART STARTFRAMECFG */ 744 #define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ 745 #define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ 746 #define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ 747 #define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ 748 #define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ 749 #define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ 750 751 /* Bit fields for EUSART SIGFRAMECFG */ 752 #define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ 753 #define _EUSART_SIGFRAMECFG_MASK 0xFFFFFFFFUL /**< Mask for EUSART_SIGFRAMECFG */ 754 #define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ 755 #define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_SIGFRAME */ 756 #define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ 757 #define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ 758 759 /* Bit fields for EUSART CLKDIV */ 760 #define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ 761 #define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ 762 #define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ 763 #define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ 764 #define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ 765 #define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ 766 767 /* Bit fields for EUSART TRIGCTRL */ 768 #define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ 769 #define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */ 770 #define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ 771 #define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ 772 #define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ 773 #define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ 774 #define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ 775 #define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ 776 #define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ 777 #define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ 778 #define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ 779 #define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ 780 #define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */ 781 #define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */ 782 #define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */ 783 #define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ 784 #define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ 785 786 /* Bit fields for EUSART CMD */ 787 #define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ 788 #define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ 789 #define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ 790 #define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ 791 #define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ 792 #define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 793 #define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ 794 #define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ 795 #define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ 796 #define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ 797 #define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 798 #define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ 799 #define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ 800 #define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ 801 #define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ 802 #define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 803 #define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ 804 #define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ 805 #define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ 806 #define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ 807 #define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 808 #define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ 809 #define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ 810 #define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ 811 #define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ 812 #define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 813 #define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ 814 #define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ 815 #define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ 816 #define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ 817 #define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 818 #define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ 819 #define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ 820 #define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ 821 #define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ 822 #define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 823 #define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ 824 #define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ 825 #define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ 826 #define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ 827 #define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 828 #define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ 829 #define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ 830 #define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ 831 #define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ 832 #define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 833 #define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ 834 835 /* Bit fields for EUSART RXDATA */ 836 #define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ 837 #define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */ 838 #define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ 839 #define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */ 840 #define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ 841 #define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ 842 843 /* Bit fields for EUSART RXDATAP */ 844 #define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ 845 #define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */ 846 #define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ 847 #define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */ 848 #define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ 849 #define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ 850 851 /* Bit fields for EUSART TXDATA */ 852 #define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ 853 #define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */ 854 #define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ 855 #define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */ 856 #define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ 857 #define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ 858 859 /* Bit fields for EUSART STATUS */ 860 #define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ 861 #define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */ 862 #define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ 863 #define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ 864 #define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ 865 #define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 866 #define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ 867 #define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ 868 #define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ 869 #define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ 870 #define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 871 #define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ 872 #define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ 873 #define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ 874 #define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ 875 #define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 876 #define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ 877 #define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ 878 #define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ 879 #define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ 880 #define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 881 #define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ 882 #define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ 883 #define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ 884 #define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ 885 #define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 886 #define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ 887 #define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ 888 #define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ 889 #define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ 890 #define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ 891 #define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ 892 #define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ 893 #define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ 894 #define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ 895 #define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 896 #define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ 897 #define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ 898 #define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ 899 #define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ 900 #define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 901 #define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ 902 #define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ 903 #define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ 904 #define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ 905 #define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ 906 #define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ 907 #define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ 908 #define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ 909 #define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ 910 #define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ 911 #define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ 912 #define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ 913 #define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */ 914 #define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 915 #define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ 916 #define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ 917 #define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ 918 #define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ 919 #define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 920 #define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ 921 #define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */ 922 #define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */ 923 #define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */ 924 #define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 925 #define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */ 926 927 /* Bit fields for EUSART IF */ 928 #define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ 929 #define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */ 930 #define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ 931 #define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ 932 #define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ 933 #define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 934 #define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ 935 #define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ 936 #define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ 937 #define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ 938 #define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 939 #define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ 940 #define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ 941 #define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ 942 #define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ 943 #define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 944 #define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ 945 #define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ 946 #define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ 947 #define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ 948 #define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 949 #define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ 950 #define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ 951 #define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ 952 #define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ 953 #define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 954 #define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ 955 #define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ 956 #define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ 957 #define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ 958 #define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 959 #define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ 960 #define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ 961 #define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ 962 #define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ 963 #define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 964 #define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ 965 #define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */ 966 #define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ 967 #define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ 968 #define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 969 #define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */ 970 #define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ 971 #define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ 972 #define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ 973 #define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 974 #define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ 975 #define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ 976 #define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ 977 #define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ 978 #define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 979 #define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ 980 #define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ 981 #define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ 982 #define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ 983 #define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 984 #define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ 985 #define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */ 986 #define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ 987 #define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ 988 #define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 989 #define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */ 990 #define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ 991 #define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ 992 #define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ 993 #define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 994 #define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ 995 #define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ 996 #define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ 997 #define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ 998 #define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 999 #define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ 1000 #define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */ 1001 #define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ 1002 #define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ 1003 #define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 1004 #define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */ 1005 #define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ 1006 #define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ 1007 #define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ 1008 #define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 1009 #define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ 1010 #define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ 1011 #define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ 1012 #define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ 1013 #define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 1014 #define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ 1015 #define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ 1016 #define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ 1017 #define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ 1018 #define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 1019 #define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ 1020 #define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */ 1021 #define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ 1022 #define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ 1023 #define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 1024 #define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */ 1025 1026 /* Bit fields for EUSART IEN */ 1027 #define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ 1028 #define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */ 1029 #define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete IEN */ 1030 #define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ 1031 #define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ 1032 #define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1033 #define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ 1034 #define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level IEN */ 1035 #define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ 1036 #define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ 1037 #define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1038 #define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ 1039 #define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level IEN */ 1040 #define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ 1041 #define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ 1042 #define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1043 #define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ 1044 #define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full IEN */ 1045 #define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ 1046 #define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ 1047 #define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1048 #define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ 1049 #define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow IEN */ 1050 #define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ 1051 #define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ 1052 #define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1053 #define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ 1054 #define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow IEN */ 1055 #define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ 1056 #define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ 1057 #define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1058 #define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ 1059 #define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow IEN */ 1060 #define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ 1061 #define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ 1062 #define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1063 #define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ 1064 #define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow IEN */ 1065 #define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ 1066 #define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ 1067 #define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1068 #define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */ 1069 #define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error IEN */ 1070 #define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ 1071 #define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ 1072 #define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1073 #define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ 1074 #define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error IEN */ 1075 #define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ 1076 #define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ 1077 #define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1078 #define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ 1079 #define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame IEN */ 1080 #define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ 1081 #define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ 1082 #define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1083 #define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ 1084 #define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error IEN */ 1085 #define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ 1086 #define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ 1087 #define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1088 #define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */ 1089 #define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail IEN */ 1090 #define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ 1091 #define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ 1092 #define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1093 #define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ 1094 #define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE IEN */ 1095 #define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ 1096 #define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ 1097 #define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1098 #define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ 1099 #define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up IEN */ 1100 #define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ 1101 #define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ 1102 #define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1103 #define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */ 1104 #define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame IEN */ 1105 #define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ 1106 #define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ 1107 #define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1108 #define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ 1109 #define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame IEN */ 1110 #define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ 1111 #define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ 1112 #define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1113 #define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ 1114 #define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete IEN */ 1115 #define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ 1116 #define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ 1117 #define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1118 #define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ 1119 #define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout IEN */ 1120 #define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ 1121 #define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ 1122 #define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 1123 #define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */ 1124 1125 /* Bit fields for EUSART SYNCBUSY */ 1126 #define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ 1127 #define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */ 1128 #define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ 1129 #define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ 1130 #define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ 1131 #define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 1132 #define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 1133 #define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ 1134 #define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ 1135 #define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ 1136 #define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 1137 #define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 1138 #define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ 1139 #define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ 1140 #define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ 1141 #define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 1142 #define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 1143 #define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ 1144 #define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ 1145 #define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ 1146 #define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 1147 #define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 1148 #define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ 1149 #define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ 1150 #define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ 1151 #define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 1152 #define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 1153 #define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ 1154 #define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ 1155 #define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ 1156 #define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 1157 #define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 1158 #define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ 1159 #define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ 1160 #define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ 1161 #define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 1162 #define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 1163 #define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ 1164 #define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ 1165 #define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ 1166 #define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 1167 #define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 1168 #define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ 1169 #define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ 1170 #define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ 1171 #define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 1172 #define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 1173 #define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ 1174 #define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ 1175 #define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ 1176 #define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 1177 #define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 1178 #define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ 1179 #define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ 1180 #define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ 1181 #define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 1182 #define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 1183 #define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */ 1184 #define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */ 1185 #define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */ 1186 #define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 1187 #define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 1188 1189 /** @} End of group EFR32BG27_EUSART_BitFields */ 1190 /** @} End of group EFR32BG27_EUSART */ 1191 /** @} End of group Parts */ 1192 1193 #endif // EFR32BG27_EUSART_H 1194
