1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG27 DPLL register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG27_DPLL_H 31 #define EFR32BG27_DPLL_H 32 #define DPLL_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG27_DPLL DPLL 40 * @{ 41 * @brief EFR32BG27 DPLL Register Declaration. 42 *****************************************************************************/ 43 44 /** DPLL Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP Version */ 47 __IOM uint32_t EN; /**< Enable */ 48 __IOM uint32_t CFG; /**< Config */ 49 __IOM uint32_t CFG1; /**< Config1 */ 50 __IOM uint32_t IF; /**< Interrupt Flag */ 51 __IOM uint32_t IEN; /**< Interrupt Enable */ 52 __IM uint32_t STATUS; /**< Status */ 53 uint32_t RESERVED0[2U]; /**< Reserved for future use */ 54 __IOM uint32_t LOCK; /**< Lock */ 55 uint32_t RESERVED1[1014U]; /**< Reserved for future use */ 56 __IM uint32_t IPVERSION_SET; /**< IP Version */ 57 __IOM uint32_t EN_SET; /**< Enable */ 58 __IOM uint32_t CFG_SET; /**< Config */ 59 __IOM uint32_t CFG1_SET; /**< Config1 */ 60 __IOM uint32_t IF_SET; /**< Interrupt Flag */ 61 __IOM uint32_t IEN_SET; /**< Interrupt Enable */ 62 __IM uint32_t STATUS_SET; /**< Status */ 63 uint32_t RESERVED2[2U]; /**< Reserved for future use */ 64 __IOM uint32_t LOCK_SET; /**< Lock */ 65 uint32_t RESERVED3[1014U]; /**< Reserved for future use */ 66 __IM uint32_t IPVERSION_CLR; /**< IP Version */ 67 __IOM uint32_t EN_CLR; /**< Enable */ 68 __IOM uint32_t CFG_CLR; /**< Config */ 69 __IOM uint32_t CFG1_CLR; /**< Config1 */ 70 __IOM uint32_t IF_CLR; /**< Interrupt Flag */ 71 __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ 72 __IM uint32_t STATUS_CLR; /**< Status */ 73 uint32_t RESERVED4[2U]; /**< Reserved for future use */ 74 __IOM uint32_t LOCK_CLR; /**< Lock */ 75 uint32_t RESERVED5[1014U]; /**< Reserved for future use */ 76 __IM uint32_t IPVERSION_TGL; /**< IP Version */ 77 __IOM uint32_t EN_TGL; /**< Enable */ 78 __IOM uint32_t CFG_TGL; /**< Config */ 79 __IOM uint32_t CFG1_TGL; /**< Config1 */ 80 __IOM uint32_t IF_TGL; /**< Interrupt Flag */ 81 __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ 82 __IM uint32_t STATUS_TGL; /**< Status */ 83 uint32_t RESERVED6[2U]; /**< Reserved for future use */ 84 __IOM uint32_t LOCK_TGL; /**< Lock */ 85 } DPLL_TypeDef; 86 /** @} End of group EFR32BG27_DPLL */ 87 88 /**************************************************************************//** 89 * @addtogroup EFR32BG27_DPLL 90 * @{ 91 * @defgroup EFR32BG27_DPLL_BitFields DPLL Bit Fields 92 * @{ 93 *****************************************************************************/ 94 95 /* Bit fields for DPLL IPVERSION */ 96 #define _DPLL_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for DPLL_IPVERSION */ 97 #define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ 98 #define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ 99 #define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ 100 #define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IPVERSION */ 101 #define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ 102 103 /* Bit fields for DPLL EN */ 104 #define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ 105 #define _DPLL_EN_MASK 0x00000001UL /**< Mask for DPLL_EN */ 106 #define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ 107 #define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ 108 #define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ 109 #define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ 110 #define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ 111 112 /* Bit fields for DPLL CFG */ 113 #define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ 114 #define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ 115 #define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ 116 #define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ 117 #define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ 118 #define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ 119 #define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ 120 #define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ 121 #define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ 122 #define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ 123 #define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ 124 #define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ 125 #define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ 126 #define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ 127 #define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ 128 #define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ 129 #define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ 130 #define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ 131 #define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ 132 #define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ 133 #define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ 134 #define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ 135 #define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ 136 #define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ 137 #define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ 138 #define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ 139 140 /* Bit fields for DPLL CFG1 */ 141 #define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ 142 #define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ 143 #define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ 144 #define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ 145 #define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ 146 #define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ 147 #define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ 148 #define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ 149 #define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ 150 #define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ 151 152 /* Bit fields for DPLL IF */ 153 #define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ 154 #define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ 155 #define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ 156 #define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ 157 #define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ 158 #define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ 159 #define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ 160 #define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ 161 #define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ 162 #define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ 163 #define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ 164 #define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ 165 #define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ 166 #define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ 167 #define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ 168 #define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ 169 #define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ 170 171 /* Bit fields for DPLL IEN */ 172 #define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ 173 #define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ 174 #define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ 175 #define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ 176 #define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ 177 #define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ 178 #define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ 179 #define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ 180 #define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ 181 #define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ 182 #define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ 183 #define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ 184 #define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ 185 #define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ 186 #define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ 187 #define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ 188 #define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ 189 190 /* Bit fields for DPLL STATUS */ 191 #define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ 192 #define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ 193 #define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ 194 #define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ 195 #define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ 196 #define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ 197 #define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ 198 #define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ 199 #define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ 200 #define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ 201 #define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ 202 #define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ 203 #define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ 204 #define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ 205 #define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ 206 #define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ 207 #define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ 208 #define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ 209 #define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ 210 #define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ 211 #define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ 212 213 /* Bit fields for DPLL LOCK */ 214 #define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ 215 #define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ 216 #define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ 217 #define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ 218 #define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ 219 #define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ 220 #define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ 221 #define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ 222 223 /** @} End of group EFR32BG27_DPLL_BitFields */ 224 /** @} End of group EFR32BG27_DPLL */ 225 /** @} End of group Parts */ 226 227 #endif /* EFR32BG27_DPLL_H */ 228
