1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG27 CRYPTOACC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG27_CRYPTOACC_H 31 #define EFR32BG27_CRYPTOACC_H 32 33 /**************************************************************************//** 34 * @addtogroup Parts 35 * @{ 36 ******************************************************************************/ 37 /**************************************************************************//** 38 * @defgroup EFR32BG27_CRYPTOACC CRYPTOACC 39 * @{ 40 * @brief EFR32BG27 CRYPTOACC Register Declaration. 41 *****************************************************************************/ 42 43 /** CRYPTOACC Register Declaration. */ 44 typedef struct cryptoacc_typedef{ 45 __IOM uint32_t DMACTRL_FETCHADDR; /**< CRYPTOMASTER_DMACTRL_FETCH_ADDR_LSB */ 46 __IOM uint32_t DMACTRL_FETCHADDRMSB; /**< CRYPTOMASTER_DMACTRL_FETCH_ADDR_MSB */ 47 __IOM uint32_t DMACTRL_FETCHLEN; /**< CRYPTOMASTER_DMACTRL_FETCH_LEN */ 48 __IOM uint32_t DMACTRL_FETCHTAG; /**< CRYPTOMASTER_DMACTRL_FETCH_TAG */ 49 __IOM uint32_t DMACTRL_PUSHADDR; /**< CRYPTOMASTER_DMACTRL_PUSH_ADDR_LSB */ 50 __IOM uint32_t DMACTRL_PUSHADDR_MSB; /**< CRYPTOMASTER_DMACTRL_PUSH_ADDR_MSB */ 51 __IOM uint32_t DMACTRL_PUSHLEN; /**< CRYPTOMASTER_DMACTRL_PUSH_LEN */ 52 __IOM uint32_t DMACTRL_IEN; /**< CRYPTOMASTER_DMACTRL_INT_EN */ 53 __IOM uint32_t DMACTRL_IEN_SET; /**< CRYPTOMASTER_DMACTRL_INT_ENSET */ 54 __IOM uint32_t DMACTRL_IEN_CLR; /**< CRYPTOMASTER_DMACTRL_INT_ENCLR */ 55 __IM uint32_t DMACTRL_IF; /**< CRYPTOMASTER_DMACTRL_INT_STATRAW */ 56 __IM uint32_t DMACTRL_IFMASKED; /**< CRYPTOMASTER_DMACTRL_INT_STAT */ 57 __IOM uint32_t DMACTRL_IF_CLR; /**< CRYPTOMASTER_DMACTRL_INT_STATCLR */ 58 __IOM uint32_t DMACTRL_CONFIG; /**< CRYPTOMASTER_DMACTRL_CONFIG */ 59 __IOM uint32_t DMACTRL_START; /**< CRYPTOMASTER_DMACTRL_START */ 60 __IM uint32_t DMACTRL_STATUS; /**< CRYPTOMASTER_DMACTRL_STATUS */ 61 uint32_t RESERVED0[240U]; /**< Reserved for future use */ 62 __IM uint32_t INCLIPS_HWCFG; /**< CRYPTOMASTER_CRYPTOMASTER_REGISTERS_INCLIPS_HWCFG */ 63 __IM uint32_t BA411E_HWCFG1; /**< CRYPTOMASTER_CRYPTOMASTER_REGISTERS_BA411E_HWCFG_1 */ 64 __IM uint32_t BA411E_HWCFG2; /**< CRYPTOMASTER_CRYPTOMASTER_REGISTERS_BA411E_HWCFG_2 */ 65 __IM uint32_t BA413_HWCFG; /**< CRYPTOMASTER_CRYPTOMASTER_REGISTERS_BA413_HWCFG */ 66 __IM uint32_t BA418_HWCFG; /**< CRYPTOMASTER_CRYPTOMASTER_REGISTERS_BA418_HWCFG */ 67 __IM uint32_t BA419_HWCFG; /**< CRYPTOMASTER_CRYPTOMASTER_REGISTERS_BA419_HWCFG */ 68 uint32_t RESERVED1[762U]; /**< Reserved for future use */ 69 __IOM uint32_t NDRNG_CONTROL; /**< BA431_NDRNG_REGISTERS_CONTROL */ 70 __IOM uint32_t NDRNG_FIFOLEVEL; /**< BA431_NDRNG_REGISTERS_FIFOLEVEL */ 71 __IOM uint32_t NDRNG_FIFOTHRESH; /**< BA431_NDRNG_REGISTERS_FIFOTHRESHOLD */ 72 __IM uint32_t NDRNG_FIFODEPTH; /**< BA431_NDRNG_REGISTERS_FIFODEPTH */ 73 __IOM uint32_t NDRNG_KEY0; /**< BA431_NDRNG_REGISTERS_KEY0 */ 74 __IOM uint32_t NDRNG_KEY1; /**< BA431_NDRNG_REGISTERS_KEY1 */ 75 __IOM uint32_t NDRNG_KEY2; /**< BA431_NDRNG_REGISTERS_KEY2 */ 76 __IOM uint32_t NDRNG_KEY3; /**< BA431_NDRNG_REGISTERS_KEY3 */ 77 __IOM uint32_t NDRNG_TESTDATA; /**< BA431_NDRNG_REGISTERS_TESTDATA */ 78 __IOM uint32_t NDRNG_REPTHRES; /**< BA431_NDRNG_REGISTERS_REPEATTHRESHOLD */ 79 __IOM uint32_t NDRNG_PROPTHRES; /**< BA431_NDRNG_REGISTERS_PROPTHRESHOLD */ 80 uint32_t RESERVED2[1U]; /**< Reserved for future use */ 81 __IOM uint32_t NDRNG_STATUS; /**< BA431_NDRNG_REGISTERS_STATUS */ 82 __IOM uint32_t NDRNG_INITWAITVAL; /**< BA431_NDRNG_REGISTERS_INITWAITVAL */ 83 __IOM uint32_t NDRNG_DISABLEOSC0; /**< BA431_NDRNG_REGISTERS_DISABLEOSC0 */ 84 __IOM uint32_t NDRNG_DISABLEOSC1; /**< BA431_NDRNG_REGISTERS_DISABLEOSC1 */ 85 __IOM uint32_t NDRNG_SWOFFTMRVAL; /**< BA431_NDRNG_REGISTERS_SWOFFTMRVAL */ 86 __IOM uint32_t NDRNG_CLKDIV; /**< BA431_NDRNG_REGISTERS_CLKDIV */ 87 __IOM uint32_t NDRNG_AIS31CONF0; /**< BA431_NDRNG_REGISTERS_AIS31CONF0 */ 88 __IOM uint32_t NDRNG_AIS31CONF1; /**< BA431_NDRNG_REGISTERS_AIS31CONF1 */ 89 __IOM uint32_t NDRNG_AIS31CONF2; /**< BA431_NDRNG_REGISTERS_AIS31CONF2 */ 90 __IOM uint32_t NDRNG_AIS31STATUS; /**< BA431_NDRNG_REGISTERS_AIS31STATUS */ 91 __IM uint32_t NDRNG_HWCONFIG; /**< BA431_NDRNG_REGISTERS_HWCONFIG */ 92 uint32_t RESERVED3[9U]; /**< Reserved for future use */ 93 __IM uint32_t NDRNG_FIFOOUTPUTDATA; /**< BA431_NDRNG_DATA_FIFOOUTPUTDATA */ 94 uint32_t RESERVED4[991U]; /**< Reserved for future use */ 95 __IOM uint32_t PK_POINTERS; /**< BA414EP_PK_REGISTERS_POINTERS */ 96 __IOM uint32_t PK_COMMAND; /**< BA414EP_PK_REGISTERS_COMMAND */ 97 __IOM uint32_t PK_CONTROL; /**< BA414EP_PK_REGISTERS_CONTROL */ 98 __IM uint32_t PK_STATUS; /**< BA414EP_PK_REGISTERS_STATUS */ 99 uint32_t RESERVED5[1U]; /**< Reserved for future use */ 100 __IOM uint32_t PK_TIMER; /**< BA414EP_PK_REGISTERS_TIMER */ 101 __IM uint32_t PK_HWCONFIG; /**< BA414EP_PK_REGISTERS_HWCONFIG */ 102 } CRYPTOACC_TypeDef; 103 /** @} End of group EFR32BG27_CRYPTOACC */ 104 105 /**************************************************************************//** 106 * @addtogroup EFR32BG27_CRYPTOACC 107 * @{ 108 * @defgroup EFR32BG27_CRYPTOACC_BitFields CRYPTOACC Bit Fields 109 * @{ 110 *****************************************************************************/ 111 112 /* Bit fields for CRYPTOACC DMACTRL_FETCHADDR */ 113 #define _CRYPTOACC_DMACTRL_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_FETCHADDR*/ 114 #define _CRYPTOACC_DMACTRL_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_DMACTRL_FETCHADDR */ 115 #define _CRYPTOACC_DMACTRL_FETCHADDR_FETCH_ADDR_LSB_SHIFT 0 /**< Shift value for CRYPTOACC_FETCH_ADDR_LSB */ 116 #define _CRYPTOACC_DMACTRL_FETCHADDR_FETCH_ADDR_LSB_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FETCH_ADDR_LSB */ 117 #define _CRYPTOACC_DMACTRL_FETCHADDR_FETCH_ADDR_LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_FETCHADDR*/ 118 #define CRYPTOACC_DMACTRL_FETCHADDR_FETCH_ADDR_LSB_DEFAULT (_CRYPTOACC_DMACTRL_FETCHADDR_FETCH_ADDR_LSB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_FETCHADDR*/ 119 120 /* Bit fields for CRYPTOACC DMACTRL_FETCHADDRMSB */ 121 #define _CRYPTOACC_DMACTRL_FETCHADDRMSB_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_FETCHADDRMSB*/ 122 #define _CRYPTOACC_DMACTRL_FETCHADDRMSB_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_DMACTRL_FETCHADDRMSB */ 123 #define _CRYPTOACC_DMACTRL_FETCHADDRMSB_FETCH_ADDR_MSB_SHIFT 0 /**< Shift value for CRYPTOACC_FETCH_ADDR_MSB */ 124 #define _CRYPTOACC_DMACTRL_FETCHADDRMSB_FETCH_ADDR_MSB_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FETCH_ADDR_MSB */ 125 #define _CRYPTOACC_DMACTRL_FETCHADDRMSB_FETCH_ADDR_MSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_FETCHADDRMSB*/ 126 #define CRYPTOACC_DMACTRL_FETCHADDRMSB_FETCH_ADDR_MSB_DEFAULT (_CRYPTOACC_DMACTRL_FETCHADDRMSB_FETCH_ADDR_MSB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_FETCHADDRMSB*/ 127 128 /* Bit fields for CRYPTOACC DMACTRL_FETCHLEN */ 129 #define _CRYPTOACC_DMACTRL_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_FETCHLEN*/ 130 #define _CRYPTOACC_DMACTRL_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for CRYPTOACC_DMACTRL_FETCHLEN */ 131 #define _CRYPTOACC_DMACTRL_FETCHLEN_FETCH_LEN_SHIFT 0 /**< Shift value for CRYPTOACC_FETCH_LEN */ 132 #define _CRYPTOACC_DMACTRL_FETCHLEN_FETCH_LEN_MASK 0xFFFFFFFUL /**< Bit mask for CRYPTOACC_FETCH_LEN */ 133 #define _CRYPTOACC_DMACTRL_FETCHLEN_FETCH_LEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_FETCHLEN */ 134 #define CRYPTOACC_DMACTRL_FETCHLEN_FETCH_LEN_DEFAULT (_CRYPTOACC_DMACTRL_FETCHLEN_FETCH_LEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_FETCHLEN*/ 135 #define CRYPTOACC_DMACTRL_FETCHLEN_FETCH_CSTADDR (0x1UL << 28) /**< FETCH_CSTADDR */ 136 #define _CRYPTOACC_DMACTRL_FETCHLEN_FETCH_CSTADDR_SHIFT 28 /**< Shift value for CRYPTOACC_FETCH_CSTADDR */ 137 #define _CRYPTOACC_DMACTRL_FETCHLEN_FETCH_CSTADDR_MASK 0x10000000UL /**< Bit mask for CRYPTOACC_FETCH_CSTADDR */ 138 #define _CRYPTOACC_DMACTRL_FETCHLEN_FETCH_CSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_FETCHLEN */ 139 #define CRYPTOACC_DMACTRL_FETCHLEN_FETCH_CSTADDR_DEFAULT (_CRYPTOACC_DMACTRL_FETCHLEN_FETCH_CSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_FETCHLEN*/ 140 #define CRYPTOACC_DMACTRL_FETCHLEN_FETCH_REALIGN (0x1UL << 29) /**< FETCH_REALIGN */ 141 #define _CRYPTOACC_DMACTRL_FETCHLEN_FETCH_REALIGN_SHIFT 29 /**< Shift value for CRYPTOACC_FETCH_REALIGN */ 142 #define _CRYPTOACC_DMACTRL_FETCHLEN_FETCH_REALIGN_MASK 0x20000000UL /**< Bit mask for CRYPTOACC_FETCH_REALIGN */ 143 #define _CRYPTOACC_DMACTRL_FETCHLEN_FETCH_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_FETCHLEN */ 144 #define CRYPTOACC_DMACTRL_FETCHLEN_FETCH_REALIGN_DEFAULT (_CRYPTOACC_DMACTRL_FETCHLEN_FETCH_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_FETCHLEN*/ 145 146 /* Bit fields for CRYPTOACC DMACTRL_FETCHTAG */ 147 #define _CRYPTOACC_DMACTRL_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_FETCHTAG*/ 148 #define _CRYPTOACC_DMACTRL_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_DMACTRL_FETCHTAG */ 149 #define _CRYPTOACC_DMACTRL_FETCHTAG_FETCH_TAG_SHIFT 0 /**< Shift value for CRYPTOACC_FETCH_TAG */ 150 #define _CRYPTOACC_DMACTRL_FETCHTAG_FETCH_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FETCH_TAG */ 151 #define _CRYPTOACC_DMACTRL_FETCHTAG_FETCH_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_FETCHTAG */ 152 #define CRYPTOACC_DMACTRL_FETCHTAG_FETCH_TAG_DEFAULT (_CRYPTOACC_DMACTRL_FETCHTAG_FETCH_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_FETCHTAG*/ 153 154 /* Bit fields for CRYPTOACC DMACTRL_PUSHADDR */ 155 #define _CRYPTOACC_DMACTRL_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_PUSHADDR*/ 156 #define _CRYPTOACC_DMACTRL_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_DMACTRL_PUSHADDR */ 157 #define _CRYPTOACC_DMACTRL_PUSHADDR_PUSH_ADDR_LSB_SHIFT 0 /**< Shift value for CRYPTOACC_PUSH_ADDR_LSB */ 158 #define _CRYPTOACC_DMACTRL_PUSHADDR_PUSH_ADDR_LSB_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_PUSH_ADDR_LSB */ 159 #define _CRYPTOACC_DMACTRL_PUSHADDR_PUSH_ADDR_LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_PUSHADDR */ 160 #define CRYPTOACC_DMACTRL_PUSHADDR_PUSH_ADDR_LSB_DEFAULT (_CRYPTOACC_DMACTRL_PUSHADDR_PUSH_ADDR_LSB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_PUSHADDR*/ 161 162 /* Bit fields for CRYPTOACC DMACTRL_PUSHADDR_MSB */ 163 #define _CRYPTOACC_DMACTRL_PUSHADDR_MSB_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_PUSHADDR_MSB*/ 164 #define _CRYPTOACC_DMACTRL_PUSHADDR_MSB_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_DMACTRL_PUSHADDR_MSB */ 165 #define _CRYPTOACC_DMACTRL_PUSHADDR_MSB_PUSH_ADDR_MSB_SHIFT 0 /**< Shift value for CRYPTOACC_PUSH_ADDR_MSB */ 166 #define _CRYPTOACC_DMACTRL_PUSHADDR_MSB_PUSH_ADDR_MSB_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_PUSH_ADDR_MSB */ 167 #define _CRYPTOACC_DMACTRL_PUSHADDR_MSB_PUSH_ADDR_MSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_PUSHADDR_MSB*/ 168 #define CRYPTOACC_DMACTRL_PUSHADDR_MSB_PUSH_ADDR_MSB_DEFAULT (_CRYPTOACC_DMACTRL_PUSHADDR_MSB_PUSH_ADDR_MSB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_PUSHADDR_MSB*/ 169 170 /* Bit fields for CRYPTOACC DMACTRL_PUSHLEN */ 171 #define _CRYPTOACC_DMACTRL_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_PUSHLEN */ 172 #define _CRYPTOACC_DMACTRL_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for CRYPTOACC_DMACTRL_PUSHLEN */ 173 #define _CRYPTOACC_DMACTRL_PUSHLEN_PUSH_LEN_SHIFT 0 /**< Shift value for CRYPTOACC_PUSH_LEN */ 174 #define _CRYPTOACC_DMACTRL_PUSHLEN_PUSH_LEN_MASK 0xFFFFFFFUL /**< Bit mask for CRYPTOACC_PUSH_LEN */ 175 #define _CRYPTOACC_DMACTRL_PUSHLEN_PUSH_LEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_PUSHLEN */ 176 #define CRYPTOACC_DMACTRL_PUSHLEN_PUSH_LEN_DEFAULT (_CRYPTOACC_DMACTRL_PUSHLEN_PUSH_LEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_PUSHLEN*/ 177 #define CRYPTOACC_DMACTRL_PUSHLEN_PUSH_CSTADDR (0x1UL << 28) /**< PUSH_CSTADDR */ 178 #define _CRYPTOACC_DMACTRL_PUSHLEN_PUSH_CSTADDR_SHIFT 28 /**< Shift value for CRYPTOACC_PUSH_CSTADDR */ 179 #define _CRYPTOACC_DMACTRL_PUSHLEN_PUSH_CSTADDR_MASK 0x10000000UL /**< Bit mask for CRYPTOACC_PUSH_CSTADDR */ 180 #define _CRYPTOACC_DMACTRL_PUSHLEN_PUSH_CSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_PUSHLEN */ 181 #define CRYPTOACC_DMACTRL_PUSHLEN_PUSH_CSTADDR_DEFAULT (_CRYPTOACC_DMACTRL_PUSHLEN_PUSH_CSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_PUSHLEN*/ 182 #define CRYPTOACC_DMACTRL_PUSHLEN_PUSH_REALIGN (0x1UL << 29) /**< PUSH_REALIGN */ 183 #define _CRYPTOACC_DMACTRL_PUSHLEN_PUSH_REALIGN_SHIFT 29 /**< Shift value for CRYPTOACC_PUSH_REALIGN */ 184 #define _CRYPTOACC_DMACTRL_PUSHLEN_PUSH_REALIGN_MASK 0x20000000UL /**< Bit mask for CRYPTOACC_PUSH_REALIGN */ 185 #define _CRYPTOACC_DMACTRL_PUSHLEN_PUSH_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_PUSHLEN */ 186 #define CRYPTOACC_DMACTRL_PUSHLEN_PUSH_REALIGN_DEFAULT (_CRYPTOACC_DMACTRL_PUSHLEN_PUSH_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_PUSHLEN*/ 187 #define CRYPTOACC_DMACTRL_PUSHLEN_PUSH_DISCARD (0x1UL << 30) /**< PUSH_DISCARD */ 188 #define _CRYPTOACC_DMACTRL_PUSHLEN_PUSH_DISCARD_SHIFT 30 /**< Shift value for CRYPTOACC_PUSH_DISCARD */ 189 #define _CRYPTOACC_DMACTRL_PUSHLEN_PUSH_DISCARD_MASK 0x40000000UL /**< Bit mask for CRYPTOACC_PUSH_DISCARD */ 190 #define _CRYPTOACC_DMACTRL_PUSHLEN_PUSH_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_PUSHLEN */ 191 #define CRYPTOACC_DMACTRL_PUSHLEN_PUSH_DISCARD_DEFAULT (_CRYPTOACC_DMACTRL_PUSHLEN_PUSH_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_PUSHLEN*/ 192 193 /* Bit fields for CRYPTOACC DMACTRL_IEN */ 194 #define _CRYPTOACC_DMACTRL_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_IEN */ 195 #define _CRYPTOACC_DMACTRL_IEN_MASK 0x0000003FUL /**< Mask for CRYPTOACC_DMACTRL_IEN */ 196 #define _CRYPTOACC_DMACTRL_IEN_INT_EN_SHIFT 0 /**< Shift value for CRYPTOACC_INT_EN */ 197 #define _CRYPTOACC_DMACTRL_IEN_INT_EN_MASK 0x3FUL /**< Bit mask for CRYPTOACC_INT_EN */ 198 #define _CRYPTOACC_DMACTRL_IEN_INT_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_IEN */ 199 #define CRYPTOACC_DMACTRL_IEN_INT_EN_DEFAULT (_CRYPTOACC_DMACTRL_IEN_INT_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_IEN*/ 200 201 /* Bit fields for CRYPTOACC DMACTRL_IEN_SET */ 202 #define _CRYPTOACC_DMACTRL_IEN_SET_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_IEN_SET */ 203 #define _CRYPTOACC_DMACTRL_IEN_SET_MASK 0x0000003FUL /**< Mask for CRYPTOACC_DMACTRL_IEN_SET */ 204 #define _CRYPTOACC_DMACTRL_IEN_SET_INT_ENSET_SHIFT 0 /**< Shift value for CRYPTOACC_INT_ENSET */ 205 #define _CRYPTOACC_DMACTRL_IEN_SET_INT_ENSET_MASK 0x3FUL /**< Bit mask for CRYPTOACC_INT_ENSET */ 206 #define _CRYPTOACC_DMACTRL_IEN_SET_INT_ENSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_IEN_SET */ 207 #define CRYPTOACC_DMACTRL_IEN_SET_INT_ENSET_DEFAULT (_CRYPTOACC_DMACTRL_IEN_SET_INT_ENSET_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_IEN_SET*/ 208 209 /* Bit fields for CRYPTOACC DMACTRL_IEN_CLR */ 210 #define _CRYPTOACC_DMACTRL_IEN_CLR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_IEN_CLR */ 211 #define _CRYPTOACC_DMACTRL_IEN_CLR_MASK 0x0000003FUL /**< Mask for CRYPTOACC_DMACTRL_IEN_CLR */ 212 #define _CRYPTOACC_DMACTRL_IEN_CLR_INT_ENCLR_SHIFT 0 /**< Shift value for CRYPTOACC_INT_ENCLR */ 213 #define _CRYPTOACC_DMACTRL_IEN_CLR_INT_ENCLR_MASK 0x3FUL /**< Bit mask for CRYPTOACC_INT_ENCLR */ 214 #define _CRYPTOACC_DMACTRL_IEN_CLR_INT_ENCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_IEN_CLR */ 215 #define CRYPTOACC_DMACTRL_IEN_CLR_INT_ENCLR_DEFAULT (_CRYPTOACC_DMACTRL_IEN_CLR_INT_ENCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_IEN_CLR*/ 216 217 /* Bit fields for CRYPTOACC DMACTRL_IF */ 218 #define _CRYPTOACC_DMACTRL_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_IF */ 219 #define _CRYPTOACC_DMACTRL_IF_MASK 0x0000003FUL /**< Mask for CRYPTOACC_DMACTRL_IF */ 220 #define _CRYPTOACC_DMACTRL_IF_INT_STATRAW_SHIFT 0 /**< Shift value for CRYPTOACC_INT_STATRAW */ 221 #define _CRYPTOACC_DMACTRL_IF_INT_STATRAW_MASK 0x3FUL /**< Bit mask for CRYPTOACC_INT_STATRAW */ 222 #define _CRYPTOACC_DMACTRL_IF_INT_STATRAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_IF */ 223 #define CRYPTOACC_DMACTRL_IF_INT_STATRAW_DEFAULT (_CRYPTOACC_DMACTRL_IF_INT_STATRAW_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_IF*/ 224 225 /* Bit fields for CRYPTOACC DMACTRL_IFMASKED */ 226 #define _CRYPTOACC_DMACTRL_IFMASKED_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_IFMASKED*/ 227 #define _CRYPTOACC_DMACTRL_IFMASKED_MASK 0x0000003FUL /**< Mask for CRYPTOACC_DMACTRL_IFMASKED */ 228 #define _CRYPTOACC_DMACTRL_IFMASKED_INT_STAT_SHIFT 0 /**< Shift value for CRYPTOACC_INT_STAT */ 229 #define _CRYPTOACC_DMACTRL_IFMASKED_INT_STAT_MASK 0x3FUL /**< Bit mask for CRYPTOACC_INT_STAT */ 230 #define _CRYPTOACC_DMACTRL_IFMASKED_INT_STAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_IFMASKED */ 231 #define CRYPTOACC_DMACTRL_IFMASKED_INT_STAT_DEFAULT (_CRYPTOACC_DMACTRL_IFMASKED_INT_STAT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_IFMASKED*/ 232 233 /* Bit fields for CRYPTOACC DMACTRL_IF_CLR */ 234 #define _CRYPTOACC_DMACTRL_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_IF_CLR */ 235 #define _CRYPTOACC_DMACTRL_IF_CLR_MASK 0x0000003FUL /**< Mask for CRYPTOACC_DMACTRL_IF_CLR */ 236 #define _CRYPTOACC_DMACTRL_IF_CLR_INT_STATCLR_SHIFT 0 /**< Shift value for CRYPTOACC_INT_STATCLR */ 237 #define _CRYPTOACC_DMACTRL_IF_CLR_INT_STATCLR_MASK 0x3FUL /**< Bit mask for CRYPTOACC_INT_STATCLR */ 238 #define _CRYPTOACC_DMACTRL_IF_CLR_INT_STATCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_IF_CLR */ 239 #define CRYPTOACC_DMACTRL_IF_CLR_INT_STATCLR_DEFAULT (_CRYPTOACC_DMACTRL_IF_CLR_INT_STATCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_IF_CLR*/ 240 241 /* Bit fields for CRYPTOACC DMACTRL_CONFIG */ 242 #define _CRYPTOACC_DMACTRL_CONFIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_CONFIG */ 243 #define _CRYPTOACC_DMACTRL_CONFIG_MASK 0x0000001FUL /**< Mask for CRYPTOACC_DMACTRL_CONFIG */ 244 #define CRYPTOACC_DMACTRL_CONFIG_FETCH_CTRL_INDIRECT (0x1UL << 0) /**< FETCH_CTRL_INDIRECT */ 245 #define _CRYPTOACC_DMACTRL_CONFIG_FETCH_CTRL_INDIRECT_SHIFT 0 /**< Shift value for CRYPTOACC_FETCH_CTRL_INDIRECT*/ 246 #define _CRYPTOACC_DMACTRL_CONFIG_FETCH_CTRL_INDIRECT_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCH_CTRL_INDIRECT */ 247 #define _CRYPTOACC_DMACTRL_CONFIG_FETCH_CTRL_INDIRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_CONFIG */ 248 #define CRYPTOACC_DMACTRL_CONFIG_FETCH_CTRL_INDIRECT_DEFAULT (_CRYPTOACC_DMACTRL_CONFIG_FETCH_CTRL_INDIRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_CONFIG*/ 249 #define CRYPTOACC_DMACTRL_CONFIG_PUSH_CTRL_INDIRECT (0x1UL << 1) /**< PUSH_CTRL_INDIRECT */ 250 #define _CRYPTOACC_DMACTRL_CONFIG_PUSH_CTRL_INDIRECT_SHIFT 1 /**< Shift value for CRYPTOACC_PUSH_CTRL_INDIRECT*/ 251 #define _CRYPTOACC_DMACTRL_CONFIG_PUSH_CTRL_INDIRECT_MASK 0x2UL /**< Bit mask for CRYPTOACC_PUSH_CTRL_INDIRECT */ 252 #define _CRYPTOACC_DMACTRL_CONFIG_PUSH_CTRL_INDIRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_CONFIG */ 253 #define CRYPTOACC_DMACTRL_CONFIG_PUSH_CTRL_INDIRECT_DEFAULT (_CRYPTOACC_DMACTRL_CONFIG_PUSH_CTRL_INDIRECT_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_CONFIG*/ 254 #define CRYPTOACC_DMACTRL_CONFIG_FETCH_STOP (0x1UL << 2) /**< FETCH_STOP */ 255 #define _CRYPTOACC_DMACTRL_CONFIG_FETCH_STOP_SHIFT 2 /**< Shift value for CRYPTOACC_FETCH_STOP */ 256 #define _CRYPTOACC_DMACTRL_CONFIG_FETCH_STOP_MASK 0x4UL /**< Bit mask for CRYPTOACC_FETCH_STOP */ 257 #define _CRYPTOACC_DMACTRL_CONFIG_FETCH_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_CONFIG */ 258 #define CRYPTOACC_DMACTRL_CONFIG_FETCH_STOP_DEFAULT (_CRYPTOACC_DMACTRL_CONFIG_FETCH_STOP_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_CONFIG*/ 259 #define CRYPTOACC_DMACTRL_CONFIG_PUSH_STOP (0x1UL << 3) /**< PUSH_STOP */ 260 #define _CRYPTOACC_DMACTRL_CONFIG_PUSH_STOP_SHIFT 3 /**< Shift value for CRYPTOACC_PUSH_STOP */ 261 #define _CRYPTOACC_DMACTRL_CONFIG_PUSH_STOP_MASK 0x8UL /**< Bit mask for CRYPTOACC_PUSH_STOP */ 262 #define _CRYPTOACC_DMACTRL_CONFIG_PUSH_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_CONFIG */ 263 #define CRYPTOACC_DMACTRL_CONFIG_PUSH_STOP_DEFAULT (_CRYPTOACC_DMACTRL_CONFIG_PUSH_STOP_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_CONFIG*/ 264 #define CRYPTOACC_DMACTRL_CONFIG_SOFT_RST (0x1UL << 4) /**< SOFT_RST */ 265 #define _CRYPTOACC_DMACTRL_CONFIG_SOFT_RST_SHIFT 4 /**< Shift value for CRYPTOACC_SOFT_RST */ 266 #define _CRYPTOACC_DMACTRL_CONFIG_SOFT_RST_MASK 0x10UL /**< Bit mask for CRYPTOACC_SOFT_RST */ 267 #define _CRYPTOACC_DMACTRL_CONFIG_SOFT_RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_CONFIG */ 268 #define CRYPTOACC_DMACTRL_CONFIG_SOFT_RST_DEFAULT (_CRYPTOACC_DMACTRL_CONFIG_SOFT_RST_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_CONFIG*/ 269 270 /* Bit fields for CRYPTOACC DMACTRL_START */ 271 #define _CRYPTOACC_DMACTRL_START_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_START */ 272 #define _CRYPTOACC_DMACTRL_START_MASK 0x00000003UL /**< Mask for CRYPTOACC_DMACTRL_START */ 273 #define CRYPTOACC_DMACTRL_START_START_FETCH (0x1UL << 0) /**< START_FETCH */ 274 #define _CRYPTOACC_DMACTRL_START_START_FETCH_SHIFT 0 /**< Shift value for CRYPTOACC_START_FETCH */ 275 #define _CRYPTOACC_DMACTRL_START_START_FETCH_MASK 0x1UL /**< Bit mask for CRYPTOACC_START_FETCH */ 276 #define _CRYPTOACC_DMACTRL_START_START_FETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_START */ 277 #define CRYPTOACC_DMACTRL_START_START_FETCH_DEFAULT (_CRYPTOACC_DMACTRL_START_START_FETCH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_START*/ 278 #define CRYPTOACC_DMACTRL_START_START_PUSH (0x1UL << 1) /**< START_PUSH */ 279 #define _CRYPTOACC_DMACTRL_START_START_PUSH_SHIFT 1 /**< Shift value for CRYPTOACC_START_PUSH */ 280 #define _CRYPTOACC_DMACTRL_START_START_PUSH_MASK 0x2UL /**< Bit mask for CRYPTOACC_START_PUSH */ 281 #define _CRYPTOACC_DMACTRL_START_START_PUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_START */ 282 #define CRYPTOACC_DMACTRL_START_START_PUSH_DEFAULT (_CRYPTOACC_DMACTRL_START_START_PUSH_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_START*/ 283 284 /* Bit fields for CRYPTOACC DMACTRL_STATUS */ 285 #define _CRYPTOACC_DMACTRL_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_DMACTRL_STATUS */ 286 #define _CRYPTOACC_DMACTRL_STATUS_MASK 0xFFFF0073UL /**< Mask for CRYPTOACC_DMACTRL_STATUS */ 287 #define CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY (0x1UL << 0) /**< FETCH_BUSY */ 288 #define _CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY_SHIFT 0 /**< Shift value for CRYPTOACC_FETCH_BUSY */ 289 #define _CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCH_BUSY */ 290 #define _CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_STATUS */ 291 #define CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY_DEFAULT (_CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_STATUS*/ 292 #define CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY (0x1UL << 1) /**< PUSH_BUSY */ 293 #define _CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY_SHIFT 1 /**< Shift value for CRYPTOACC_PUSH_BUSY */ 294 #define _CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY_MASK 0x2UL /**< Bit mask for CRYPTOACC_PUSH_BUSY */ 295 #define _CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_STATUS */ 296 #define CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY_DEFAULT (_CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_STATUS*/ 297 #define CRYPTOACC_DMACTRL_STATUS_FETCH_NOT_EMPTY (0x1UL << 4) /**< FETCH_NOT_EMPTY */ 298 #define _CRYPTOACC_DMACTRL_STATUS_FETCH_NOT_EMPTY_SHIFT 4 /**< Shift value for CRYPTOACC_FETCH_NOT_EMPTY */ 299 #define _CRYPTOACC_DMACTRL_STATUS_FETCH_NOT_EMPTY_MASK 0x10UL /**< Bit mask for CRYPTOACC_FETCH_NOT_EMPTY */ 300 #define _CRYPTOACC_DMACTRL_STATUS_FETCH_NOT_EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_STATUS */ 301 #define CRYPTOACC_DMACTRL_STATUS_FETCH_NOT_EMPTY_DEFAULT (_CRYPTOACC_DMACTRL_STATUS_FETCH_NOT_EMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_STATUS*/ 302 #define CRYPTOACC_DMACTRL_STATUS_PUSH_WAITINGFIFO (0x1UL << 5) /**< PUSH_WAITINGFIFO */ 303 #define _CRYPTOACC_DMACTRL_STATUS_PUSH_WAITINGFIFO_SHIFT 5 /**< Shift value for CRYPTOACC_PUSH_WAITINGFIFO */ 304 #define _CRYPTOACC_DMACTRL_STATUS_PUSH_WAITINGFIFO_MASK 0x20UL /**< Bit mask for CRYPTOACC_PUSH_WAITINGFIFO */ 305 #define _CRYPTOACC_DMACTRL_STATUS_PUSH_WAITINGFIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_STATUS */ 306 #define CRYPTOACC_DMACTRL_STATUS_PUSH_WAITINGFIFO_DEFAULT (_CRYPTOACC_DMACTRL_STATUS_PUSH_WAITINGFIFO_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_STATUS*/ 307 #define CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY (0x1UL << 6) /**< SOFT_RST_BUSY */ 308 #define _CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY_SHIFT 6 /**< Shift value for CRYPTOACC_SOFT_RST_BUSY */ 309 #define _CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY_MASK 0x40UL /**< Bit mask for CRYPTOACC_SOFT_RST_BUSY */ 310 #define _CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_STATUS */ 311 #define CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY_DEFAULT (_CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_STATUS*/ 312 #define _CRYPTOACC_DMACTRL_STATUS_PUSH_NBDATA_SHIFT 16 /**< Shift value for CRYPTOACC_PUSH_NBDATA */ 313 #define _CRYPTOACC_DMACTRL_STATUS_PUSH_NBDATA_MASK 0xFFFF0000UL /**< Bit mask for CRYPTOACC_PUSH_NBDATA */ 314 #define _CRYPTOACC_DMACTRL_STATUS_PUSH_NBDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_DMACTRL_STATUS */ 315 #define CRYPTOACC_DMACTRL_STATUS_PUSH_NBDATA_DEFAULT (_CRYPTOACC_DMACTRL_STATUS_PUSH_NBDATA_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_DMACTRL_STATUS*/ 316 317 /* Bit fields for CRYPTOACC INCLIPS_HWCFG */ 318 #define _CRYPTOACC_INCLIPS_HWCFG_RESETVALUE 0x00000611UL /**< Default value for CRYPTOACC_INCLIPS_HWCFG */ 319 #define _CRYPTOACC_INCLIPS_HWCFG_MASK 0x00003FFFUL /**< Mask for CRYPTOACC_INCLIPS_HWCFG */ 320 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAES (0x1UL << 0) /**< G_INCLUDEAES */ 321 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAES_SHIFT 0 /**< Shift value for CRYPTOACC_G_INCLUDEAES */ 322 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAES_MASK 0x1UL /**< Bit mask for CRYPTOACC_G_INCLUDEAES */ 323 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 324 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAES_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 325 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAESGCM (0x1UL << 1) /**< G_INCLUDEAESGCM */ 326 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAESGCM_SHIFT 1 /**< Shift value for CRYPTOACC_G_INCLUDEAESGCM */ 327 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAESGCM_MASK 0x2UL /**< Bit mask for CRYPTOACC_G_INCLUDEAESGCM */ 328 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 329 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAESGCM_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 330 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAESXTS (0x1UL << 2) /**< G_INCLUDEAESXTS */ 331 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAESXTS_SHIFT 2 /**< Shift value for CRYPTOACC_G_INCLUDEAESXTS */ 332 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAESXTS_MASK 0x4UL /**< Bit mask for CRYPTOACC_G_INCLUDEAESXTS */ 333 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 334 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAESXTS_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 335 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEDES (0x1UL << 3) /**< G_INCLUDEDES */ 336 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEDES_SHIFT 3 /**< Shift value for CRYPTOACC_G_INCLUDEDES */ 337 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEDES_MASK 0x8UL /**< Bit mask for CRYPTOACC_G_INCLUDEDES */ 338 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 339 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEDES_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEDES_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 340 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEHASH (0x1UL << 4) /**< G_INCLUDEHASH */ 341 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEHASH_SHIFT 4 /**< Shift value for CRYPTOACC_G_INCLUDEHASH */ 342 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEHASH_MASK 0x10UL /**< Bit mask for CRYPTOACC_G_INCLUDEHASH */ 343 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEHASH_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 344 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEHASH_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 345 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDECHACHAPOLY (0x1UL << 5) /**< G_INCLUDECHACHAPOLY */ 346 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDECHACHAPOLY_SHIFT 5 /**< Shift value for CRYPTOACC_G_INCLUDECHACHAPOLY*/ 347 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDECHACHAPOLY_MASK 0x20UL /**< Bit mask for CRYPTOACC_G_INCLUDECHACHAPOLY */ 348 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDECHACHAPOLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 349 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDECHACHAPOLY_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDECHACHAPOLY_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 350 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESHA3 (0x1UL << 6) /**< G_INCLUDESHA3 */ 351 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESHA3_SHIFT 6 /**< Shift value for CRYPTOACC_G_INCLUDESHA3 */ 352 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESHA3_MASK 0x40UL /**< Bit mask for CRYPTOACC_G_INCLUDESHA3 */ 353 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 354 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESHA3_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 355 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEZUC (0x1UL << 7) /**< G_INCLUDEZUC */ 356 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEZUC_SHIFT 7 /**< Shift value for CRYPTOACC_G_INCLUDEZUC */ 357 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEZUC_MASK 0x80UL /**< Bit mask for CRYPTOACC_G_INCLUDEZUC */ 358 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 359 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEZUC_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 360 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESM4 (0x1UL << 8) /**< G_INCLUDESM4 */ 361 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESM4_SHIFT 8 /**< Shift value for CRYPTOACC_G_INCLUDESM4 */ 362 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESM4_MASK 0x100UL /**< Bit mask for CRYPTOACC_G_INCLUDESM4 */ 363 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 364 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESM4_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESM4_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 365 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEPKE (0x1UL << 9) /**< G_INCLUDEPKE */ 366 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEPKE_SHIFT 9 /**< Shift value for CRYPTOACC_G_INCLUDEPKE */ 367 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEPKE_MASK 0x200UL /**< Bit mask for CRYPTOACC_G_INCLUDEPKE */ 368 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEPKE_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 369 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEPKE_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEPKE_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 370 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDENDRNG (0x1UL << 10) /**< G_INCLUDENDRNG */ 371 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDENDRNG_SHIFT 10 /**< Shift value for CRYPTOACC_G_INCLUDENDRNG */ 372 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDENDRNG_MASK 0x400UL /**< Bit mask for CRYPTOACC_G_INCLUDENDRNG */ 373 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDENDRNG_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 374 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDENDRNG_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDENDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 375 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEHPCHACHAPOLY (0x1UL << 11) /**< G_INCLUDEHPCHACHAPOLY */ 376 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEHPCHACHAPOLY_SHIFT 11 /**< Shift value for CRYPTOACC_G_INCLUDEHPCHACHAPOLY*/ 377 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEHPCHACHAPOLY_MASK 0x800UL /**< Bit mask for CRYPTOACC_G_INCLUDEHPCHACHAPOLY*/ 378 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEHPCHACHAPOLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 379 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEHPCHACHAPOLY_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEHPCHACHAPOLY_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 380 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESNOW3G (0x1UL << 12) /**< G_INCLUDESNOW3G */ 381 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESNOW3G_SHIFT 12 /**< Shift value for CRYPTOACC_G_INCLUDESNOW3G */ 382 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESNOW3G_MASK 0x1000UL /**< Bit mask for CRYPTOACC_G_INCLUDESNOW3G */ 383 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESNOW3G_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 384 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESNOW3G_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDESNOW3G_DEFAULT << 12) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 385 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEKASUMI (0x1UL << 13) /**< G_INCLUDEKASUMI */ 386 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEKASUMI_SHIFT 13 /**< Shift value for CRYPTOACC_G_INCLUDEKASUMI */ 387 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEKASUMI_MASK 0x2000UL /**< Bit mask for CRYPTOACC_G_INCLUDEKASUMI */ 388 #define _CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEKASUMI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG */ 389 #define CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEKASUMI_DEFAULT (_CRYPTOACC_INCLIPS_HWCFG_G_INCLUDEKASUMI_DEFAULT << 13) /**< Shifted mode DEFAULT for CRYPTOACC_INCLIPS_HWCFG*/ 390 391 /* Bit fields for CRYPTOACC BA411E_HWCFG1 */ 392 #define _CRYPTOACC_BA411E_HWCFG1_RESETVALUE 0x0703017FUL /**< Default value for CRYPTOACC_BA411E_HWCFG1 */ 393 #define _CRYPTOACC_BA411E_HWCFG1_MASK 0x070301FFUL /**< Mask for CRYPTOACC_BA411E_HWCFG1 */ 394 #define _CRYPTOACC_BA411E_HWCFG1_G_AESMODESPOSS_SHIFT 0 /**< Shift value for CRYPTOACC_G_AESMODESPOSS */ 395 #define _CRYPTOACC_BA411E_HWCFG1_G_AESMODESPOSS_MASK 0x1FFUL /**< Bit mask for CRYPTOACC_G_AESMODESPOSS */ 396 #define _CRYPTOACC_BA411E_HWCFG1_G_AESMODESPOSS_DEFAULT 0x0000017FUL /**< Mode DEFAULT for CRYPTOACC_BA411E_HWCFG1 */ 397 #define CRYPTOACC_BA411E_HWCFG1_G_AESMODESPOSS_DEFAULT (_CRYPTOACC_BA411E_HWCFG1_G_AESMODESPOSS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HWCFG1*/ 398 #define CRYPTOACC_BA411E_HWCFG1_G_CS (0x1UL << 16) /**< G_CS */ 399 #define _CRYPTOACC_BA411E_HWCFG1_G_CS_SHIFT 16 /**< Shift value for CRYPTOACC_G_CS */ 400 #define _CRYPTOACC_BA411E_HWCFG1_G_CS_MASK 0x10000UL /**< Bit mask for CRYPTOACC_G_CS */ 401 #define _CRYPTOACC_BA411E_HWCFG1_G_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HWCFG1 */ 402 #define CRYPTOACC_BA411E_HWCFG1_G_CS_DEFAULT (_CRYPTOACC_BA411E_HWCFG1_G_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HWCFG1*/ 403 #define CRYPTOACC_BA411E_HWCFG1_G_USEMASKING (0x1UL << 17) /**< G_USEMASKING */ 404 #define _CRYPTOACC_BA411E_HWCFG1_G_USEMASKING_SHIFT 17 /**< Shift value for CRYPTOACC_G_USEMASKING */ 405 #define _CRYPTOACC_BA411E_HWCFG1_G_USEMASKING_MASK 0x20000UL /**< Bit mask for CRYPTOACC_G_USEMASKING */ 406 #define _CRYPTOACC_BA411E_HWCFG1_G_USEMASKING_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HWCFG1 */ 407 #define CRYPTOACC_BA411E_HWCFG1_G_USEMASKING_DEFAULT (_CRYPTOACC_BA411E_HWCFG1_G_USEMASKING_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HWCFG1*/ 408 #define _CRYPTOACC_BA411E_HWCFG1_G_KEYSIZE_SHIFT 24 /**< Shift value for CRYPTOACC_G_KEYSIZE */ 409 #define _CRYPTOACC_BA411E_HWCFG1_G_KEYSIZE_MASK 0x7000000UL /**< Bit mask for CRYPTOACC_G_KEYSIZE */ 410 #define _CRYPTOACC_BA411E_HWCFG1_G_KEYSIZE_DEFAULT 0x00000007UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HWCFG1 */ 411 #define CRYPTOACC_BA411E_HWCFG1_G_KEYSIZE_DEFAULT (_CRYPTOACC_BA411E_HWCFG1_G_KEYSIZE_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HWCFG1*/ 412 413 /* Bit fields for CRYPTOACC BA411E_HWCFG2 */ 414 #define _CRYPTOACC_BA411E_HWCFG2_RESETVALUE 0x00000080UL /**< Default value for CRYPTOACC_BA411E_HWCFG2 */ 415 #define _CRYPTOACC_BA411E_HWCFG2_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_BA411E_HWCFG2 */ 416 #define _CRYPTOACC_BA411E_HWCFG2_G_CTRSIZE_SHIFT 0 /**< Shift value for CRYPTOACC_G_CTRSIZE */ 417 #define _CRYPTOACC_BA411E_HWCFG2_G_CTRSIZE_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_G_CTRSIZE */ 418 #define _CRYPTOACC_BA411E_HWCFG2_G_CTRSIZE_DEFAULT 0x00000080UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HWCFG2 */ 419 #define CRYPTOACC_BA411E_HWCFG2_G_CTRSIZE_DEFAULT (_CRYPTOACC_BA411E_HWCFG2_G_CTRSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HWCFG2*/ 420 421 /* Bit fields for CRYPTOACC BA413_HWCFG */ 422 #define _CRYPTOACC_BA413_HWCFG_RESETVALUE 0x0003007FUL /**< Default value for CRYPTOACC_BA413_HWCFG */ 423 #define _CRYPTOACC_BA413_HWCFG_MASK 0x0007007FUL /**< Mask for CRYPTOACC_BA413_HWCFG */ 424 #define _CRYPTOACC_BA413_HWCFG_G_HASHMASKFUNC_SHIFT 0 /**< Shift value for CRYPTOACC_G_HASHMASKFUNC */ 425 #define _CRYPTOACC_BA413_HWCFG_G_HASHMASKFUNC_MASK 0x7FUL /**< Bit mask for CRYPTOACC_G_HASHMASKFUNC */ 426 #define _CRYPTOACC_BA413_HWCFG_G_HASHMASKFUNC_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CRYPTOACC_BA413_HWCFG */ 427 #define CRYPTOACC_BA413_HWCFG_G_HASHMASKFUNC_DEFAULT (_CRYPTOACC_BA413_HWCFG_G_HASHMASKFUNC_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HWCFG*/ 428 #define CRYPTOACC_BA413_HWCFG_G_HASHPADDING (0x1UL << 16) /**< G_HASHPADDING */ 429 #define _CRYPTOACC_BA413_HWCFG_G_HASHPADDING_SHIFT 16 /**< Shift value for CRYPTOACC_G_HASHPADDING */ 430 #define _CRYPTOACC_BA413_HWCFG_G_HASHPADDING_MASK 0x10000UL /**< Bit mask for CRYPTOACC_G_HASHPADDING */ 431 #define _CRYPTOACC_BA413_HWCFG_G_HASHPADDING_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA413_HWCFG */ 432 #define CRYPTOACC_BA413_HWCFG_G_HASHPADDING_DEFAULT (_CRYPTOACC_BA413_HWCFG_G_HASHPADDING_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HWCFG*/ 433 #define CRYPTOACC_BA413_HWCFG_G_HMAC_ENABLED (0x1UL << 17) /**< G_HMAC_ENABLED */ 434 #define _CRYPTOACC_BA413_HWCFG_G_HMAC_ENABLED_SHIFT 17 /**< Shift value for CRYPTOACC_G_HMAC_ENABLED */ 435 #define _CRYPTOACC_BA413_HWCFG_G_HMAC_ENABLED_MASK 0x20000UL /**< Bit mask for CRYPTOACC_G_HMAC_ENABLED */ 436 #define _CRYPTOACC_BA413_HWCFG_G_HMAC_ENABLED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA413_HWCFG */ 437 #define CRYPTOACC_BA413_HWCFG_G_HMAC_ENABLED_DEFAULT (_CRYPTOACC_BA413_HWCFG_G_HMAC_ENABLED_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HWCFG*/ 438 #define CRYPTOACC_BA413_HWCFG_G_HASHVERIFYDIGEST (0x1UL << 18) /**< G_HASHVERIFYDIGEST */ 439 #define _CRYPTOACC_BA413_HWCFG_G_HASHVERIFYDIGEST_SHIFT 18 /**< Shift value for CRYPTOACC_G_HASHVERIFYDIGEST*/ 440 #define _CRYPTOACC_BA413_HWCFG_G_HASHVERIFYDIGEST_MASK 0x40000UL /**< Bit mask for CRYPTOACC_G_HASHVERIFYDIGEST */ 441 #define _CRYPTOACC_BA413_HWCFG_G_HASHVERIFYDIGEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_BA413_HWCFG */ 442 #define CRYPTOACC_BA413_HWCFG_G_HASHVERIFYDIGEST_DEFAULT (_CRYPTOACC_BA413_HWCFG_G_HASHVERIFYDIGEST_DEFAULT << 18) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HWCFG*/ 443 444 /* Bit fields for CRYPTOACC BA418_HWCFG */ 445 #define _CRYPTOACC_BA418_HWCFG_RESETVALUE 0x00000001UL /**< Default value for CRYPTOACC_BA418_HWCFG */ 446 #define _CRYPTOACC_BA418_HWCFG_MASK 0x00000001UL /**< Mask for CRYPTOACC_BA418_HWCFG */ 447 #define CRYPTOACC_BA418_HWCFG_G_SHA3CTXTEN (0x1UL << 0) /**< G_SHA3CTXTEN */ 448 #define _CRYPTOACC_BA418_HWCFG_G_SHA3CTXTEN_SHIFT 0 /**< Shift value for CRYPTOACC_G_SHA3CTXTEN */ 449 #define _CRYPTOACC_BA418_HWCFG_G_SHA3CTXTEN_MASK 0x1UL /**< Bit mask for CRYPTOACC_G_SHA3CTXTEN */ 450 #define _CRYPTOACC_BA418_HWCFG_G_SHA3CTXTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA418_HWCFG */ 451 #define CRYPTOACC_BA418_HWCFG_G_SHA3CTXTEN_DEFAULT (_CRYPTOACC_BA418_HWCFG_G_SHA3CTXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA418_HWCFG*/ 452 453 /* Bit fields for CRYPTOACC BA419_HWCFG */ 454 #define _CRYPTOACC_BA419_HWCFG_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_BA419_HWCFG */ 455 #define _CRYPTOACC_BA419_HWCFG_MASK 0x0000007FUL /**< Mask for CRYPTOACC_BA419_HWCFG */ 456 #define _CRYPTOACC_BA419_HWCFG_G_SM4MODESPOSS_SHIFT 0 /**< Shift value for CRYPTOACC_G_SM4MODESPOSS */ 457 #define _CRYPTOACC_BA419_HWCFG_G_SM4MODESPOSS_MASK 0x7FUL /**< Bit mask for CRYPTOACC_G_SM4MODESPOSS */ 458 #define _CRYPTOACC_BA419_HWCFG_G_SM4MODESPOSS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_BA419_HWCFG */ 459 #define CRYPTOACC_BA419_HWCFG_G_SM4MODESPOSS_DEFAULT (_CRYPTOACC_BA419_HWCFG_G_SM4MODESPOSS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA419_HWCFG*/ 460 461 /* Bit fields for CRYPTOACC NDRNG_CONTROL */ 462 #define _CRYPTOACC_NDRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_CONTROL */ 463 #define _CRYPTOACC_NDRNG_CONTROL_MASK 0x001FFFFFUL /**< Mask for CRYPTOACC_NDRNG_CONTROL */ 464 #define CRYPTOACC_NDRNG_CONTROL_ENABLE (0x1UL << 0) /**< ENABLE */ 465 #define _CRYPTOACC_NDRNG_CONTROL_ENABLE_SHIFT 0 /**< Shift value for CRYPTOACC_ENABLE */ 466 #define _CRYPTOACC_NDRNG_CONTROL_ENABLE_MASK 0x1UL /**< Bit mask for CRYPTOACC_ENABLE */ 467 #define _CRYPTOACC_NDRNG_CONTROL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 468 #define CRYPTOACC_NDRNG_CONTROL_ENABLE_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 469 #define CRYPTOACC_NDRNG_CONTROL_LFSREN (0x1UL << 1) /**< LFSREN */ 470 #define _CRYPTOACC_NDRNG_CONTROL_LFSREN_SHIFT 1 /**< Shift value for CRYPTOACC_LFSREN */ 471 #define _CRYPTOACC_NDRNG_CONTROL_LFSREN_MASK 0x2UL /**< Bit mask for CRYPTOACC_LFSREN */ 472 #define _CRYPTOACC_NDRNG_CONTROL_LFSREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 473 #define CRYPTOACC_NDRNG_CONTROL_LFSREN_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_LFSREN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 474 #define CRYPTOACC_NDRNG_CONTROL_TESTEN (0x1UL << 2) /**< TESTEN */ 475 #define _CRYPTOACC_NDRNG_CONTROL_TESTEN_SHIFT 2 /**< Shift value for CRYPTOACC_TESTEN */ 476 #define _CRYPTOACC_NDRNG_CONTROL_TESTEN_MASK 0x4UL /**< Bit mask for CRYPTOACC_TESTEN */ 477 #define _CRYPTOACC_NDRNG_CONTROL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 478 #define CRYPTOACC_NDRNG_CONTROL_TESTEN_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 479 #define CRYPTOACC_NDRNG_CONTROL_CONDBYPASS (0x1UL << 3) /**< CONDBYPASS */ 480 #define _CRYPTOACC_NDRNG_CONTROL_CONDBYPASS_SHIFT 3 /**< Shift value for CRYPTOACC_CONDBYPASS */ 481 #define _CRYPTOACC_NDRNG_CONTROL_CONDBYPASS_MASK 0x8UL /**< Bit mask for CRYPTOACC_CONDBYPASS */ 482 #define _CRYPTOACC_NDRNG_CONTROL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 483 #define CRYPTOACC_NDRNG_CONTROL_CONDBYPASS_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 484 #define CRYPTOACC_NDRNG_CONTROL_INTENREP (0x1UL << 4) /**< INTENREP */ 485 #define _CRYPTOACC_NDRNG_CONTROL_INTENREP_SHIFT 4 /**< Shift value for CRYPTOACC_INTENREP */ 486 #define _CRYPTOACC_NDRNG_CONTROL_INTENREP_MASK 0x10UL /**< Bit mask for CRYPTOACC_INTENREP */ 487 #define _CRYPTOACC_NDRNG_CONTROL_INTENREP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 488 #define CRYPTOACC_NDRNG_CONTROL_INTENREP_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_INTENREP_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 489 #define CRYPTOACC_NDRNG_CONTROL_INTENPROP (0x1UL << 5) /**< INTENPROP */ 490 #define _CRYPTOACC_NDRNG_CONTROL_INTENPROP_SHIFT 5 /**< Shift value for CRYPTOACC_INTENPROP */ 491 #define _CRYPTOACC_NDRNG_CONTROL_INTENPROP_MASK 0x20UL /**< Bit mask for CRYPTOACC_INTENPROP */ 492 #define _CRYPTOACC_NDRNG_CONTROL_INTENPROP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 493 #define CRYPTOACC_NDRNG_CONTROL_INTENPROP_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_INTENPROP_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 494 #define CRYPTOACC_NDRNG_CONTROL_RESERVED (0x1UL << 6) /**< RESERVED */ 495 #define _CRYPTOACC_NDRNG_CONTROL_RESERVED_SHIFT 6 /**< Shift value for CRYPTOACC_RESERVED */ 496 #define _CRYPTOACC_NDRNG_CONTROL_RESERVED_MASK 0x40UL /**< Bit mask for CRYPTOACC_RESERVED */ 497 #define _CRYPTOACC_NDRNG_CONTROL_RESERVED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 498 #define CRYPTOACC_NDRNG_CONTROL_RESERVED_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_RESERVED_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 499 #define CRYPTOACC_NDRNG_CONTROL_INTENFULL (0x1UL << 7) /**< INTENFULL */ 500 #define _CRYPTOACC_NDRNG_CONTROL_INTENFULL_SHIFT 7 /**< Shift value for CRYPTOACC_INTENFULL */ 501 #define _CRYPTOACC_NDRNG_CONTROL_INTENFULL_MASK 0x80UL /**< Bit mask for CRYPTOACC_INTENFULL */ 502 #define _CRYPTOACC_NDRNG_CONTROL_INTENFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 503 #define CRYPTOACC_NDRNG_CONTROL_INTENFULL_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_INTENFULL_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 504 #define CRYPTOACC_NDRNG_CONTROL_SOFTRST (0x1UL << 8) /**< SOFTRST */ 505 #define _CRYPTOACC_NDRNG_CONTROL_SOFTRST_SHIFT 8 /**< Shift value for CRYPTOACC_SOFTRST */ 506 #define _CRYPTOACC_NDRNG_CONTROL_SOFTRST_MASK 0x100UL /**< Bit mask for CRYPTOACC_SOFTRST */ 507 #define _CRYPTOACC_NDRNG_CONTROL_SOFTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 508 #define CRYPTOACC_NDRNG_CONTROL_SOFTRST_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_SOFTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 509 #define CRYPTOACC_NDRNG_CONTROL_INTENPRE (0x1UL << 9) /**< INTENPRE */ 510 #define _CRYPTOACC_NDRNG_CONTROL_INTENPRE_SHIFT 9 /**< Shift value for CRYPTOACC_INTENPRE */ 511 #define _CRYPTOACC_NDRNG_CONTROL_INTENPRE_MASK 0x200UL /**< Bit mask for CRYPTOACC_INTENPRE */ 512 #define _CRYPTOACC_NDRNG_CONTROL_INTENPRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 513 #define CRYPTOACC_NDRNG_CONTROL_INTENPRE_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_INTENPRE_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 514 #define CRYPTOACC_NDRNG_CONTROL_INTENALM (0x1UL << 10) /**< INTENALM */ 515 #define _CRYPTOACC_NDRNG_CONTROL_INTENALM_SHIFT 10 /**< Shift value for CRYPTOACC_INTENALM */ 516 #define _CRYPTOACC_NDRNG_CONTROL_INTENALM_MASK 0x400UL /**< Bit mask for CRYPTOACC_INTENALM */ 517 #define _CRYPTOACC_NDRNG_CONTROL_INTENALM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 518 #define CRYPTOACC_NDRNG_CONTROL_INTENALM_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_INTENALM_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 519 #define CRYPTOACC_NDRNG_CONTROL_FORCEACTIVEROS (0x1UL << 11) /**< FORCEACTIVEROS */ 520 #define _CRYPTOACC_NDRNG_CONTROL_FORCEACTIVEROS_SHIFT 11 /**< Shift value for CRYPTOACC_FORCEACTIVEROS */ 521 #define _CRYPTOACC_NDRNG_CONTROL_FORCEACTIVEROS_MASK 0x800UL /**< Bit mask for CRYPTOACC_FORCEACTIVEROS */ 522 #define _CRYPTOACC_NDRNG_CONTROL_FORCEACTIVEROS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 523 #define CRYPTOACC_NDRNG_CONTROL_FORCEACTIVEROS_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_FORCEACTIVEROS_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 524 #define CRYPTOACC_NDRNG_CONTROL_HEALTHTESTBYPASS (0x1UL << 12) /**< HEALTHTESTBYPASS */ 525 #define _CRYPTOACC_NDRNG_CONTROL_HEALTHTESTBYPASS_SHIFT 12 /**< Shift value for CRYPTOACC_HEALTHTESTBYPASS */ 526 #define _CRYPTOACC_NDRNG_CONTROL_HEALTHTESTBYPASS_MASK 0x1000UL /**< Bit mask for CRYPTOACC_HEALTHTESTBYPASS */ 527 #define _CRYPTOACC_NDRNG_CONTROL_HEALTHTESTBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 528 #define CRYPTOACC_NDRNG_CONTROL_HEALTHTESTBYPASS_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_HEALTHTESTBYPASS_DEFAULT << 12) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 529 #define CRYPTOACC_NDRNG_CONTROL_AIS31BYPASS (0x1UL << 13) /**< AIS31BYPASS */ 530 #define _CRYPTOACC_NDRNG_CONTROL_AIS31BYPASS_SHIFT 13 /**< Shift value for CRYPTOACC_AIS31BYPASS */ 531 #define _CRYPTOACC_NDRNG_CONTROL_AIS31BYPASS_MASK 0x2000UL /**< Bit mask for CRYPTOACC_AIS31BYPASS */ 532 #define _CRYPTOACC_NDRNG_CONTROL_AIS31BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 533 #define CRYPTOACC_NDRNG_CONTROL_AIS31BYPASS_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_AIS31BYPASS_DEFAULT << 13) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 534 #define CRYPTOACC_NDRNG_CONTROL_HEALTHTESTSEL (0x1UL << 14) /**< HEALTHTESTSEL */ 535 #define _CRYPTOACC_NDRNG_CONTROL_HEALTHTESTSEL_SHIFT 14 /**< Shift value for CRYPTOACC_HEALTHTESTSEL */ 536 #define _CRYPTOACC_NDRNG_CONTROL_HEALTHTESTSEL_MASK 0x4000UL /**< Bit mask for CRYPTOACC_HEALTHTESTSEL */ 537 #define _CRYPTOACC_NDRNG_CONTROL_HEALTHTESTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 538 #define CRYPTOACC_NDRNG_CONTROL_HEALTHTESTSEL_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_HEALTHTESTSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 539 #define CRYPTOACC_NDRNG_CONTROL_AIS31TESTSEL (0x1UL << 15) /**< AIS31TESTSEL */ 540 #define _CRYPTOACC_NDRNG_CONTROL_AIS31TESTSEL_SHIFT 15 /**< Shift value for CRYPTOACC_AIS31TESTSEL */ 541 #define _CRYPTOACC_NDRNG_CONTROL_AIS31TESTSEL_MASK 0x8000UL /**< Bit mask for CRYPTOACC_AIS31TESTSEL */ 542 #define _CRYPTOACC_NDRNG_CONTROL_AIS31TESTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 543 #define CRYPTOACC_NDRNG_CONTROL_AIS31TESTSEL_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_AIS31TESTSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 544 #define _CRYPTOACC_NDRNG_CONTROL_NB128BITBLOCKS_SHIFT 16 /**< Shift value for CRYPTOACC_NB128BITBLOCKS */ 545 #define _CRYPTOACC_NDRNG_CONTROL_NB128BITBLOCKS_MASK 0xF0000UL /**< Bit mask for CRYPTOACC_NB128BITBLOCKS */ 546 #define _CRYPTOACC_NDRNG_CONTROL_NB128BITBLOCKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 547 #define CRYPTOACC_NDRNG_CONTROL_NB128BITBLOCKS_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_NB128BITBLOCKS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 548 #define CRYPTOACC_NDRNG_CONTROL_FIFOWRITESTARTUP (0x1UL << 20) /**< FIFOWRITESTARTUP */ 549 #define _CRYPTOACC_NDRNG_CONTROL_FIFOWRITESTARTUP_SHIFT 20 /**< Shift value for CRYPTOACC_FIFOWRITESTARTUP */ 550 #define _CRYPTOACC_NDRNG_CONTROL_FIFOWRITESTARTUP_MASK 0x100000UL /**< Bit mask for CRYPTOACC_FIFOWRITESTARTUP */ 551 #define _CRYPTOACC_NDRNG_CONTROL_FIFOWRITESTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CONTROL */ 552 #define CRYPTOACC_NDRNG_CONTROL_FIFOWRITESTARTUP_DEFAULT (_CRYPTOACC_NDRNG_CONTROL_FIFOWRITESTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CONTROL*/ 553 554 /* Bit fields for CRYPTOACC NDRNG_FIFOLEVEL */ 555 #define _CRYPTOACC_NDRNG_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_FIFOLEVEL */ 556 #define _CRYPTOACC_NDRNG_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_NDRNG_FIFOLEVEL */ 557 #define _CRYPTOACC_NDRNG_FIFOLEVEL_FIFOLEVEL_SHIFT 0 /**< Shift value for CRYPTOACC_FIFOLEVEL */ 558 #define _CRYPTOACC_NDRNG_FIFOLEVEL_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFOLEVEL */ 559 #define _CRYPTOACC_NDRNG_FIFOLEVEL_FIFOLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_FIFOLEVEL */ 560 #define CRYPTOACC_NDRNG_FIFOLEVEL_FIFOLEVEL_DEFAULT (_CRYPTOACC_NDRNG_FIFOLEVEL_FIFOLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_FIFOLEVEL*/ 561 562 /* Bit fields for CRYPTOACC NDRNG_FIFOTHRESH */ 563 #define _CRYPTOACC_NDRNG_FIFOTHRESH_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_FIFOTHRESH*/ 564 #define _CRYPTOACC_NDRNG_FIFOTHRESH_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_NDRNG_FIFOTHRESH */ 565 #define _CRYPTOACC_NDRNG_FIFOTHRESH_FIFOTHRESHOLD_SHIFT 0 /**< Shift value for CRYPTOACC_FIFOTHRESHOLD */ 566 #define _CRYPTOACC_NDRNG_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFOTHRESHOLD */ 567 #define _CRYPTOACC_NDRNG_FIFOTHRESH_FIFOTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_FIFOTHRESH */ 568 #define CRYPTOACC_NDRNG_FIFOTHRESH_FIFOTHRESHOLD_DEFAULT (_CRYPTOACC_NDRNG_FIFOTHRESH_FIFOTHRESHOLD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_FIFOTHRESH*/ 569 570 /* Bit fields for CRYPTOACC NDRNG_FIFODEPTH */ 571 #define _CRYPTOACC_NDRNG_FIFODEPTH_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_FIFODEPTH */ 572 #define _CRYPTOACC_NDRNG_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_NDRNG_FIFODEPTH */ 573 #define _CRYPTOACC_NDRNG_FIFODEPTH_FIFODEPTH_SHIFT 0 /**< Shift value for CRYPTOACC_FIFODEPTH */ 574 #define _CRYPTOACC_NDRNG_FIFODEPTH_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFODEPTH */ 575 #define _CRYPTOACC_NDRNG_FIFODEPTH_FIFODEPTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_FIFODEPTH */ 576 #define CRYPTOACC_NDRNG_FIFODEPTH_FIFODEPTH_DEFAULT (_CRYPTOACC_NDRNG_FIFODEPTH_FIFODEPTH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_FIFODEPTH*/ 577 578 /* Bit fields for CRYPTOACC NDRNG_KEY0 */ 579 #define _CRYPTOACC_NDRNG_KEY0_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_KEY0 */ 580 #define _CRYPTOACC_NDRNG_KEY0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_NDRNG_KEY0 */ 581 #define _CRYPTOACC_NDRNG_KEY0_KEY0_SHIFT 0 /**< Shift value for CRYPTOACC_KEY0 */ 582 #define _CRYPTOACC_NDRNG_KEY0_KEY0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_KEY0 */ 583 #define _CRYPTOACC_NDRNG_KEY0_KEY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_KEY0 */ 584 #define CRYPTOACC_NDRNG_KEY0_KEY0_DEFAULT (_CRYPTOACC_NDRNG_KEY0_KEY0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_KEY0*/ 585 586 /* Bit fields for CRYPTOACC NDRNG_KEY1 */ 587 #define _CRYPTOACC_NDRNG_KEY1_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_KEY1 */ 588 #define _CRYPTOACC_NDRNG_KEY1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_NDRNG_KEY1 */ 589 #define _CRYPTOACC_NDRNG_KEY1_KEY1_SHIFT 0 /**< Shift value for CRYPTOACC_KEY1 */ 590 #define _CRYPTOACC_NDRNG_KEY1_KEY1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_KEY1 */ 591 #define _CRYPTOACC_NDRNG_KEY1_KEY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_KEY1 */ 592 #define CRYPTOACC_NDRNG_KEY1_KEY1_DEFAULT (_CRYPTOACC_NDRNG_KEY1_KEY1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_KEY1*/ 593 594 /* Bit fields for CRYPTOACC NDRNG_KEY2 */ 595 #define _CRYPTOACC_NDRNG_KEY2_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_KEY2 */ 596 #define _CRYPTOACC_NDRNG_KEY2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_NDRNG_KEY2 */ 597 #define _CRYPTOACC_NDRNG_KEY2_KEY2_SHIFT 0 /**< Shift value for CRYPTOACC_KEY2 */ 598 #define _CRYPTOACC_NDRNG_KEY2_KEY2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_KEY2 */ 599 #define _CRYPTOACC_NDRNG_KEY2_KEY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_KEY2 */ 600 #define CRYPTOACC_NDRNG_KEY2_KEY2_DEFAULT (_CRYPTOACC_NDRNG_KEY2_KEY2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_KEY2*/ 601 602 /* Bit fields for CRYPTOACC NDRNG_KEY3 */ 603 #define _CRYPTOACC_NDRNG_KEY3_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_KEY3 */ 604 #define _CRYPTOACC_NDRNG_KEY3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_NDRNG_KEY3 */ 605 #define _CRYPTOACC_NDRNG_KEY3_KEY3_SHIFT 0 /**< Shift value for CRYPTOACC_KEY3 */ 606 #define _CRYPTOACC_NDRNG_KEY3_KEY3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_KEY3 */ 607 #define _CRYPTOACC_NDRNG_KEY3_KEY3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_KEY3 */ 608 #define CRYPTOACC_NDRNG_KEY3_KEY3_DEFAULT (_CRYPTOACC_NDRNG_KEY3_KEY3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_KEY3*/ 609 610 /* Bit fields for CRYPTOACC NDRNG_TESTDATA */ 611 #define _CRYPTOACC_NDRNG_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_TESTDATA */ 612 #define _CRYPTOACC_NDRNG_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_NDRNG_TESTDATA */ 613 #define _CRYPTOACC_NDRNG_TESTDATA_TESTDATA_SHIFT 0 /**< Shift value for CRYPTOACC_TESTDATA */ 614 #define _CRYPTOACC_NDRNG_TESTDATA_TESTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_TESTDATA */ 615 #define _CRYPTOACC_NDRNG_TESTDATA_TESTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_TESTDATA */ 616 #define CRYPTOACC_NDRNG_TESTDATA_TESTDATA_DEFAULT (_CRYPTOACC_NDRNG_TESTDATA_TESTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_TESTDATA*/ 617 618 /* Bit fields for CRYPTOACC NDRNG_REPTHRES */ 619 #define _CRYPTOACC_NDRNG_REPTHRES_RESETVALUE 0x00000029UL /**< Default value for CRYPTOACC_NDRNG_REPTHRES */ 620 #define _CRYPTOACC_NDRNG_REPTHRES_MASK 0x0000003FUL /**< Mask for CRYPTOACC_NDRNG_REPTHRES */ 621 #define _CRYPTOACC_NDRNG_REPTHRES_REPEATTHRESHOLD_SHIFT 0 /**< Shift value for CRYPTOACC_REPEATTHRESHOLD */ 622 #define _CRYPTOACC_NDRNG_REPTHRES_REPEATTHRESHOLD_MASK 0x3FUL /**< Bit mask for CRYPTOACC_REPEATTHRESHOLD */ 623 #define _CRYPTOACC_NDRNG_REPTHRES_REPEATTHRESHOLD_DEFAULT 0x00000029UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_REPTHRES */ 624 #define CRYPTOACC_NDRNG_REPTHRES_REPEATTHRESHOLD_DEFAULT (_CRYPTOACC_NDRNG_REPTHRES_REPEATTHRESHOLD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_REPTHRES*/ 625 626 /* Bit fields for CRYPTOACC NDRNG_PROPTHRES */ 627 #define _CRYPTOACC_NDRNG_PROPTHRES_RESETVALUE 0x00000319UL /**< Default value for CRYPTOACC_NDRNG_PROPTHRES */ 628 #define _CRYPTOACC_NDRNG_PROPTHRES_MASK 0x000003FFUL /**< Mask for CRYPTOACC_NDRNG_PROPTHRES */ 629 #define _CRYPTOACC_NDRNG_PROPTHRES_PROPTHRESHOLD_SHIFT 0 /**< Shift value for CRYPTOACC_PROPTHRESHOLD */ 630 #define _CRYPTOACC_NDRNG_PROPTHRES_PROPTHRESHOLD_MASK 0x3FFUL /**< Bit mask for CRYPTOACC_PROPTHRESHOLD */ 631 #define _CRYPTOACC_NDRNG_PROPTHRES_PROPTHRESHOLD_DEFAULT 0x00000319UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_PROPTHRES */ 632 #define CRYPTOACC_NDRNG_PROPTHRES_PROPTHRESHOLD_DEFAULT (_CRYPTOACC_NDRNG_PROPTHRES_PROPTHRESHOLD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_PROPTHRES*/ 633 634 /* Bit fields for CRYPTOACC NDRNG_STATUS */ 635 #define _CRYPTOACC_NDRNG_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_STATUS */ 636 #define _CRYPTOACC_NDRNG_STATUS_MASK 0x00000FBFUL /**< Mask for CRYPTOACC_NDRNG_STATUS */ 637 #define CRYPTOACC_NDRNG_STATUS_TESTDATABUSY (0x1UL << 0) /**< TESTDATABUSY */ 638 #define _CRYPTOACC_NDRNG_STATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for CRYPTOACC_TESTDATABUSY */ 639 #define _CRYPTOACC_NDRNG_STATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for CRYPTOACC_TESTDATABUSY */ 640 #define _CRYPTOACC_NDRNG_STATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_STATUS */ 641 #define CRYPTOACC_NDRNG_STATUS_TESTDATABUSY_DEFAULT (_CRYPTOACC_NDRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_STATUS*/ 642 #define _CRYPTOACC_NDRNG_STATUS_STATE_SHIFT 1 /**< Shift value for CRYPTOACC_STATE */ 643 #define _CRYPTOACC_NDRNG_STATUS_STATE_MASK 0xEUL /**< Bit mask for CRYPTOACC_STATE */ 644 #define _CRYPTOACC_NDRNG_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_STATUS */ 645 #define CRYPTOACC_NDRNG_STATUS_STATE_DEFAULT (_CRYPTOACC_NDRNG_STATUS_STATE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_STATUS*/ 646 #define CRYPTOACC_NDRNG_STATUS_REPFAIL (0x1UL << 4) /**< REPFAIL */ 647 #define _CRYPTOACC_NDRNG_STATUS_REPFAIL_SHIFT 4 /**< Shift value for CRYPTOACC_REPFAIL */ 648 #define _CRYPTOACC_NDRNG_STATUS_REPFAIL_MASK 0x10UL /**< Bit mask for CRYPTOACC_REPFAIL */ 649 #define _CRYPTOACC_NDRNG_STATUS_REPFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_STATUS */ 650 #define CRYPTOACC_NDRNG_STATUS_REPFAIL_DEFAULT (_CRYPTOACC_NDRNG_STATUS_REPFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_STATUS*/ 651 #define CRYPTOACC_NDRNG_STATUS_PROPFAIL (0x1UL << 5) /**< PROPFAIL */ 652 #define _CRYPTOACC_NDRNG_STATUS_PROPFAIL_SHIFT 5 /**< Shift value for CRYPTOACC_PROPFAIL */ 653 #define _CRYPTOACC_NDRNG_STATUS_PROPFAIL_MASK 0x20UL /**< Bit mask for CRYPTOACC_PROPFAIL */ 654 #define _CRYPTOACC_NDRNG_STATUS_PROPFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_STATUS */ 655 #define CRYPTOACC_NDRNG_STATUS_PROPFAIL_DEFAULT (_CRYPTOACC_NDRNG_STATUS_PROPFAIL_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_STATUS*/ 656 #define CRYPTOACC_NDRNG_STATUS_FULLINT (0x1UL << 7) /**< FULLINT */ 657 #define _CRYPTOACC_NDRNG_STATUS_FULLINT_SHIFT 7 /**< Shift value for CRYPTOACC_FULLINT */ 658 #define _CRYPTOACC_NDRNG_STATUS_FULLINT_MASK 0x80UL /**< Bit mask for CRYPTOACC_FULLINT */ 659 #define _CRYPTOACC_NDRNG_STATUS_FULLINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_STATUS */ 660 #define CRYPTOACC_NDRNG_STATUS_FULLINT_DEFAULT (_CRYPTOACC_NDRNG_STATUS_FULLINT_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_STATUS*/ 661 #define CRYPTOACC_NDRNG_STATUS_PREINT (0x1UL << 8) /**< PREINT */ 662 #define _CRYPTOACC_NDRNG_STATUS_PREINT_SHIFT 8 /**< Shift value for CRYPTOACC_PREINT */ 663 #define _CRYPTOACC_NDRNG_STATUS_PREINT_MASK 0x100UL /**< Bit mask for CRYPTOACC_PREINT */ 664 #define _CRYPTOACC_NDRNG_STATUS_PREINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_STATUS */ 665 #define CRYPTOACC_NDRNG_STATUS_PREINT_DEFAULT (_CRYPTOACC_NDRNG_STATUS_PREINT_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_STATUS*/ 666 #define CRYPTOACC_NDRNG_STATUS_ALMINT (0x1UL << 9) /**< ALMINT */ 667 #define _CRYPTOACC_NDRNG_STATUS_ALMINT_SHIFT 9 /**< Shift value for CRYPTOACC_ALMINT */ 668 #define _CRYPTOACC_NDRNG_STATUS_ALMINT_MASK 0x200UL /**< Bit mask for CRYPTOACC_ALMINT */ 669 #define _CRYPTOACC_NDRNG_STATUS_ALMINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_STATUS */ 670 #define CRYPTOACC_NDRNG_STATUS_ALMINT_DEFAULT (_CRYPTOACC_NDRNG_STATUS_ALMINT_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_STATUS*/ 671 #define CRYPTOACC_NDRNG_STATUS_STARTUPFAIL (0x1UL << 10) /**< STARTUPFAIL */ 672 #define _CRYPTOACC_NDRNG_STATUS_STARTUPFAIL_SHIFT 10 /**< Shift value for CRYPTOACC_STARTUPFAIL */ 673 #define _CRYPTOACC_NDRNG_STATUS_STARTUPFAIL_MASK 0x400UL /**< Bit mask for CRYPTOACC_STARTUPFAIL */ 674 #define _CRYPTOACC_NDRNG_STATUS_STARTUPFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_STATUS */ 675 #define CRYPTOACC_NDRNG_STATUS_STARTUPFAIL_DEFAULT (_CRYPTOACC_NDRNG_STATUS_STARTUPFAIL_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_STATUS*/ 676 #define CRYPTOACC_NDRNG_STATUS_FIFOACCFAIL (0x1UL << 11) /**< FIFOACCFAIL */ 677 #define _CRYPTOACC_NDRNG_STATUS_FIFOACCFAIL_SHIFT 11 /**< Shift value for CRYPTOACC_FIFOACCFAIL */ 678 #define _CRYPTOACC_NDRNG_STATUS_FIFOACCFAIL_MASK 0x800UL /**< Bit mask for CRYPTOACC_FIFOACCFAIL */ 679 #define _CRYPTOACC_NDRNG_STATUS_FIFOACCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_STATUS */ 680 #define CRYPTOACC_NDRNG_STATUS_FIFOACCFAIL_DEFAULT (_CRYPTOACC_NDRNG_STATUS_FIFOACCFAIL_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_STATUS*/ 681 682 /* Bit fields for CRYPTOACC NDRNG_INITWAITVAL */ 683 #define _CRYPTOACC_NDRNG_INITWAITVAL_RESETVALUE 0x0000FFFFUL /**< Default value for CRYPTOACC_NDRNG_INITWAITVAL*/ 684 #define _CRYPTOACC_NDRNG_INITWAITVAL_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_NDRNG_INITWAITVAL */ 685 #define _CRYPTOACC_NDRNG_INITWAITVAL_INITWAITVAL_SHIFT 0 /**< Shift value for CRYPTOACC_INITWAITVAL */ 686 #define _CRYPTOACC_NDRNG_INITWAITVAL_INITWAITVAL_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_INITWAITVAL */ 687 #define _CRYPTOACC_NDRNG_INITWAITVAL_INITWAITVAL_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for CRYPTOACC_NDRNG_INITWAITVAL*/ 688 #define CRYPTOACC_NDRNG_INITWAITVAL_INITWAITVAL_DEFAULT (_CRYPTOACC_NDRNG_INITWAITVAL_INITWAITVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_INITWAITVAL*/ 689 690 /* Bit fields for CRYPTOACC NDRNG_DISABLEOSC0 */ 691 #define _CRYPTOACC_NDRNG_DISABLEOSC0_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_DISABLEOSC0*/ 692 #define _CRYPTOACC_NDRNG_DISABLEOSC0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_NDRNG_DISABLEOSC0 */ 693 #define _CRYPTOACC_NDRNG_DISABLEOSC0_DISABLEOSC0_SHIFT 0 /**< Shift value for CRYPTOACC_DISABLEOSC0 */ 694 #define _CRYPTOACC_NDRNG_DISABLEOSC0_DISABLEOSC0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_DISABLEOSC0 */ 695 #define _CRYPTOACC_NDRNG_DISABLEOSC0_DISABLEOSC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_DISABLEOSC0*/ 696 #define CRYPTOACC_NDRNG_DISABLEOSC0_DISABLEOSC0_DEFAULT (_CRYPTOACC_NDRNG_DISABLEOSC0_DISABLEOSC0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_DISABLEOSC0*/ 697 698 /* Bit fields for CRYPTOACC NDRNG_DISABLEOSC1 */ 699 #define _CRYPTOACC_NDRNG_DISABLEOSC1_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_DISABLEOSC1*/ 700 #define _CRYPTOACC_NDRNG_DISABLEOSC1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_NDRNG_DISABLEOSC1 */ 701 #define _CRYPTOACC_NDRNG_DISABLEOSC1_DISABLEOSC1_SHIFT 0 /**< Shift value for CRYPTOACC_DISABLEOSC1 */ 702 #define _CRYPTOACC_NDRNG_DISABLEOSC1_DISABLEOSC1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_DISABLEOSC1 */ 703 #define _CRYPTOACC_NDRNG_DISABLEOSC1_DISABLEOSC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_DISABLEOSC1*/ 704 #define CRYPTOACC_NDRNG_DISABLEOSC1_DISABLEOSC1_DEFAULT (_CRYPTOACC_NDRNG_DISABLEOSC1_DISABLEOSC1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_DISABLEOSC1*/ 705 706 /* Bit fields for CRYPTOACC NDRNG_SWOFFTMRVAL */ 707 #define _CRYPTOACC_NDRNG_SWOFFTMRVAL_RESETVALUE 0x0000FFFFUL /**< Default value for CRYPTOACC_NDRNG_SWOFFTMRVAL*/ 708 #define _CRYPTOACC_NDRNG_SWOFFTMRVAL_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_NDRNG_SWOFFTMRVAL */ 709 #define _CRYPTOACC_NDRNG_SWOFFTMRVAL_SWOFFTMRVAL_SHIFT 0 /**< Shift value for CRYPTOACC_SWOFFTMRVAL */ 710 #define _CRYPTOACC_NDRNG_SWOFFTMRVAL_SWOFFTMRVAL_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_SWOFFTMRVAL */ 711 #define _CRYPTOACC_NDRNG_SWOFFTMRVAL_SWOFFTMRVAL_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for CRYPTOACC_NDRNG_SWOFFTMRVAL*/ 712 #define CRYPTOACC_NDRNG_SWOFFTMRVAL_SWOFFTMRVAL_DEFAULT (_CRYPTOACC_NDRNG_SWOFFTMRVAL_SWOFFTMRVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_SWOFFTMRVAL*/ 713 714 /* Bit fields for CRYPTOACC NDRNG_CLKDIV */ 715 #define _CRYPTOACC_NDRNG_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_CLKDIV */ 716 #define _CRYPTOACC_NDRNG_CLKDIV_MASK 0x000000FFUL /**< Mask for CRYPTOACC_NDRNG_CLKDIV */ 717 #define _CRYPTOACC_NDRNG_CLKDIV_CLKDIV_SHIFT 0 /**< Shift value for CRYPTOACC_CLKDIV */ 718 #define _CRYPTOACC_NDRNG_CLKDIV_CLKDIV_MASK 0xFFUL /**< Bit mask for CRYPTOACC_CLKDIV */ 719 #define _CRYPTOACC_NDRNG_CLKDIV_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_CLKDIV */ 720 #define CRYPTOACC_NDRNG_CLKDIV_CLKDIV_DEFAULT (_CRYPTOACC_NDRNG_CLKDIV_CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_CLKDIV*/ 721 722 /* Bit fields for CRYPTOACC NDRNG_AIS31CONF0 */ 723 #define _CRYPTOACC_NDRNG_AIS31CONF0_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_AIS31CONF0*/ 724 #define _CRYPTOACC_NDRNG_AIS31CONF0_MASK 0x7FFF7FFFUL /**< Mask for CRYPTOACC_NDRNG_AIS31CONF0 */ 725 #define _CRYPTOACC_NDRNG_AIS31CONF0_STARTUPTHRESHOLD_SHIFT 0 /**< Shift value for CRYPTOACC_STARTUPTHRESHOLD */ 726 #define _CRYPTOACC_NDRNG_AIS31CONF0_STARTUPTHRESHOLD_MASK 0x7FFFUL /**< Bit mask for CRYPTOACC_STARTUPTHRESHOLD */ 727 #define _CRYPTOACC_NDRNG_AIS31CONF0_STARTUPTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_AIS31CONF0 */ 728 #define CRYPTOACC_NDRNG_AIS31CONF0_STARTUPTHRESHOLD_DEFAULT (_CRYPTOACC_NDRNG_AIS31CONF0_STARTUPTHRESHOLD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_AIS31CONF0*/ 729 #define _CRYPTOACC_NDRNG_AIS31CONF0_ONLINETHRESHOLD_SHIFT 16 /**< Shift value for CRYPTOACC_ONLINETHRESHOLD */ 730 #define _CRYPTOACC_NDRNG_AIS31CONF0_ONLINETHRESHOLD_MASK 0x7FFF0000UL /**< Bit mask for CRYPTOACC_ONLINETHRESHOLD */ 731 #define _CRYPTOACC_NDRNG_AIS31CONF0_ONLINETHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_AIS31CONF0 */ 732 #define CRYPTOACC_NDRNG_AIS31CONF0_ONLINETHRESHOLD_DEFAULT (_CRYPTOACC_NDRNG_AIS31CONF0_ONLINETHRESHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_AIS31CONF0*/ 733 734 /* Bit fields for CRYPTOACC NDRNG_AIS31CONF1 */ 735 #define _CRYPTOACC_NDRNG_AIS31CONF1_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_AIS31CONF1*/ 736 #define _CRYPTOACC_NDRNG_AIS31CONF1_MASK 0x7FFF7FFFUL /**< Mask for CRYPTOACC_NDRNG_AIS31CONF1 */ 737 #define _CRYPTOACC_NDRNG_AIS31CONF1_ONLINEREPTHRESHOLD_SHIFT 0 /**< Shift value for CRYPTOACC_ONLINEREPTHRESHOLD*/ 738 #define _CRYPTOACC_NDRNG_AIS31CONF1_ONLINEREPTHRESHOLD_MASK 0x7FFFUL /**< Bit mask for CRYPTOACC_ONLINEREPTHRESHOLD */ 739 #define _CRYPTOACC_NDRNG_AIS31CONF1_ONLINEREPTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_AIS31CONF1 */ 740 #define CRYPTOACC_NDRNG_AIS31CONF1_ONLINEREPTHRESHOLD_DEFAULT (_CRYPTOACC_NDRNG_AIS31CONF1_ONLINEREPTHRESHOLD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_AIS31CONF1*/ 741 #define _CRYPTOACC_NDRNG_AIS31CONF1_HEXPECTEDVALUE_SHIFT 16 /**< Shift value for CRYPTOACC_HEXPECTEDVALUE */ 742 #define _CRYPTOACC_NDRNG_AIS31CONF1_HEXPECTEDVALUE_MASK 0x7FFF0000UL /**< Bit mask for CRYPTOACC_HEXPECTEDVALUE */ 743 #define _CRYPTOACC_NDRNG_AIS31CONF1_HEXPECTEDVALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_AIS31CONF1 */ 744 #define CRYPTOACC_NDRNG_AIS31CONF1_HEXPECTEDVALUE_DEFAULT (_CRYPTOACC_NDRNG_AIS31CONF1_HEXPECTEDVALUE_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_AIS31CONF1*/ 745 746 /* Bit fields for CRYPTOACC NDRNG_AIS31CONF2 */ 747 #define _CRYPTOACC_NDRNG_AIS31CONF2_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_AIS31CONF2*/ 748 #define _CRYPTOACC_NDRNG_AIS31CONF2_MASK 0x7FFF7FFFUL /**< Mask for CRYPTOACC_NDRNG_AIS31CONF2 */ 749 #define _CRYPTOACC_NDRNG_AIS31CONF2_HMIN_SHIFT 0 /**< Shift value for CRYPTOACC_HMIN */ 750 #define _CRYPTOACC_NDRNG_AIS31CONF2_HMIN_MASK 0x7FFFUL /**< Bit mask for CRYPTOACC_HMIN */ 751 #define _CRYPTOACC_NDRNG_AIS31CONF2_HMIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_AIS31CONF2 */ 752 #define CRYPTOACC_NDRNG_AIS31CONF2_HMIN_DEFAULT (_CRYPTOACC_NDRNG_AIS31CONF2_HMIN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_AIS31CONF2*/ 753 #define _CRYPTOACC_NDRNG_AIS31CONF2_HMAX_SHIFT 16 /**< Shift value for CRYPTOACC_HMAX */ 754 #define _CRYPTOACC_NDRNG_AIS31CONF2_HMAX_MASK 0x7FFF0000UL /**< Bit mask for CRYPTOACC_HMAX */ 755 #define _CRYPTOACC_NDRNG_AIS31CONF2_HMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_AIS31CONF2 */ 756 #define CRYPTOACC_NDRNG_AIS31CONF2_HMAX_DEFAULT (_CRYPTOACC_NDRNG_AIS31CONF2_HMAX_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_AIS31CONF2*/ 757 758 /* Bit fields for CRYPTOACC NDRNG_AIS31STATUS */ 759 #define _CRYPTOACC_NDRNG_AIS31STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_AIS31STATUS*/ 760 #define _CRYPTOACC_NDRNG_AIS31STATUS_MASK 0x0003FFFFUL /**< Mask for CRYPTOACC_NDRNG_AIS31STATUS */ 761 #define _CRYPTOACC_NDRNG_AIS31STATUS_NUMPRELIMALARMS_SHIFT 0 /**< Shift value for CRYPTOACC_NUMPRELIMALARMS */ 762 #define _CRYPTOACC_NDRNG_AIS31STATUS_NUMPRELIMALARMS_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_NUMPRELIMALARMS */ 763 #define _CRYPTOACC_NDRNG_AIS31STATUS_NUMPRELIMALARMS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_AIS31STATUS*/ 764 #define CRYPTOACC_NDRNG_AIS31STATUS_NUMPRELIMALARMS_DEFAULT (_CRYPTOACC_NDRNG_AIS31STATUS_NUMPRELIMALARMS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_AIS31STATUS*/ 765 #define CRYPTOACC_NDRNG_AIS31STATUS_PRELIMNOISEALARMRNG (0x1UL << 16) /**< PRELIMNOISEALARMRNG */ 766 #define _CRYPTOACC_NDRNG_AIS31STATUS_PRELIMNOISEALARMRNG_SHIFT 16 /**< Shift value for CRYPTOACC_PRELIMNOISEALARMRNG*/ 767 #define _CRYPTOACC_NDRNG_AIS31STATUS_PRELIMNOISEALARMRNG_MASK 0x10000UL /**< Bit mask for CRYPTOACC_PRELIMNOISEALARMRNG */ 768 #define _CRYPTOACC_NDRNG_AIS31STATUS_PRELIMNOISEALARMRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_AIS31STATUS*/ 769 #define CRYPTOACC_NDRNG_AIS31STATUS_PRELIMNOISEALARMRNG_DEFAULT (_CRYPTOACC_NDRNG_AIS31STATUS_PRELIMNOISEALARMRNG_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_AIS31STATUS*/ 770 #define CRYPTOACC_NDRNG_AIS31STATUS_PRELIMNOISEALARMREP (0x1UL << 17) /**< PRELIMNOISEALARMREP */ 771 #define _CRYPTOACC_NDRNG_AIS31STATUS_PRELIMNOISEALARMREP_SHIFT 17 /**< Shift value for CRYPTOACC_PRELIMNOISEALARMREP*/ 772 #define _CRYPTOACC_NDRNG_AIS31STATUS_PRELIMNOISEALARMREP_MASK 0x20000UL /**< Bit mask for CRYPTOACC_PRELIMNOISEALARMREP */ 773 #define _CRYPTOACC_NDRNG_AIS31STATUS_PRELIMNOISEALARMREP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_AIS31STATUS*/ 774 #define CRYPTOACC_NDRNG_AIS31STATUS_PRELIMNOISEALARMREP_DEFAULT (_CRYPTOACC_NDRNG_AIS31STATUS_PRELIMNOISEALARMREP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_AIS31STATUS*/ 775 776 /* Bit fields for CRYPTOACC NDRNG_HWCONFIG */ 777 #define _CRYPTOACC_NDRNG_HWCONFIG_RESETVALUE 0x00000317UL /**< Default value for CRYPTOACC_NDRNG_HWCONFIG */ 778 #define _CRYPTOACC_NDRNG_HWCONFIG_MASK 0x000003FFUL /**< Mask for CRYPTOACC_NDRNG_HWCONFIG */ 779 #define _CRYPTOACC_NDRNG_HWCONFIG_NUMBOFRINGS_SHIFT 0 /**< Shift value for CRYPTOACC_NUMBOFRINGS */ 780 #define _CRYPTOACC_NDRNG_HWCONFIG_NUMBOFRINGS_MASK 0xFFUL /**< Bit mask for CRYPTOACC_NUMBOFRINGS */ 781 #define _CRYPTOACC_NDRNG_HWCONFIG_NUMBOFRINGS_DEFAULT 0x00000017UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_HWCONFIG */ 782 #define CRYPTOACC_NDRNG_HWCONFIG_NUMBOFRINGS_DEFAULT (_CRYPTOACC_NDRNG_HWCONFIG_NUMBOFRINGS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_HWCONFIG*/ 783 #define CRYPTOACC_NDRNG_HWCONFIG_AIS31 (0x1UL << 8) /**< AIS31 */ 784 #define _CRYPTOACC_NDRNG_HWCONFIG_AIS31_SHIFT 8 /**< Shift value for CRYPTOACC_AIS31 */ 785 #define _CRYPTOACC_NDRNG_HWCONFIG_AIS31_MASK 0x100UL /**< Bit mask for CRYPTOACC_AIS31 */ 786 #define _CRYPTOACC_NDRNG_HWCONFIG_AIS31_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_HWCONFIG */ 787 #define CRYPTOACC_NDRNG_HWCONFIG_AIS31_DEFAULT (_CRYPTOACC_NDRNG_HWCONFIG_AIS31_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_HWCONFIG*/ 788 #define CRYPTOACC_NDRNG_HWCONFIG_AIS31FULL (0x1UL << 9) /**< AIS31FULL */ 789 #define _CRYPTOACC_NDRNG_HWCONFIG_AIS31FULL_SHIFT 9 /**< Shift value for CRYPTOACC_AIS31FULL */ 790 #define _CRYPTOACC_NDRNG_HWCONFIG_AIS31FULL_MASK 0x200UL /**< Bit mask for CRYPTOACC_AIS31FULL */ 791 #define _CRYPTOACC_NDRNG_HWCONFIG_AIS31FULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_HWCONFIG */ 792 #define CRYPTOACC_NDRNG_HWCONFIG_AIS31FULL_DEFAULT (_CRYPTOACC_NDRNG_HWCONFIG_AIS31FULL_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_HWCONFIG*/ 793 794 /* Bit fields for CRYPTOACC NDRNG_FIFOOUTPUTDATA */ 795 #define _CRYPTOACC_NDRNG_FIFOOUTPUTDATA_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_NDRNG_FIFOOUTPUTDATA*/ 796 #define _CRYPTOACC_NDRNG_FIFOOUTPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_NDRNG_FIFOOUTPUTDATA */ 797 #define _CRYPTOACC_NDRNG_FIFOOUTPUTDATA_FIFOOUTPUTDATA_SHIFT 0 /**< Shift value for CRYPTOACC_FIFOOUTPUTDATA */ 798 #define _CRYPTOACC_NDRNG_FIFOOUTPUTDATA_FIFOOUTPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFOOUTPUTDATA */ 799 #define _CRYPTOACC_NDRNG_FIFOOUTPUTDATA_FIFOOUTPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_NDRNG_FIFOOUTPUTDATA*/ 800 #define CRYPTOACC_NDRNG_FIFOOUTPUTDATA_FIFOOUTPUTDATA_DEFAULT (_CRYPTOACC_NDRNG_FIFOOUTPUTDATA_FIFOOUTPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_NDRNG_FIFOOUTPUTDATA*/ 801 802 /* Bit fields for CRYPTOACC PK_POINTERS */ 803 #define _CRYPTOACC_PK_POINTERS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PK_POINTERS */ 804 #define _CRYPTOACC_PK_POINTERS_MASK 0x0F0F0F0FUL /**< Mask for CRYPTOACC_PK_POINTERS */ 805 #define _CRYPTOACC_PK_POINTERS_OPPTRA_SHIFT 0 /**< Shift value for CRYPTOACC_OPPTRA */ 806 #define _CRYPTOACC_PK_POINTERS_OPPTRA_MASK 0xFUL /**< Bit mask for CRYPTOACC_OPPTRA */ 807 #define _CRYPTOACC_PK_POINTERS_OPPTRA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_POINTERS */ 808 #define CRYPTOACC_PK_POINTERS_OPPTRA_DEFAULT (_CRYPTOACC_PK_POINTERS_OPPTRA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PK_POINTERS*/ 809 #define _CRYPTOACC_PK_POINTERS_OPPTRB_SHIFT 8 /**< Shift value for CRYPTOACC_OPPTRB */ 810 #define _CRYPTOACC_PK_POINTERS_OPPTRB_MASK 0xF00UL /**< Bit mask for CRYPTOACC_OPPTRB */ 811 #define _CRYPTOACC_PK_POINTERS_OPPTRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_POINTERS */ 812 #define CRYPTOACC_PK_POINTERS_OPPTRB_DEFAULT (_CRYPTOACC_PK_POINTERS_OPPTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_PK_POINTERS*/ 813 #define _CRYPTOACC_PK_POINTERS_OPPTRC_SHIFT 16 /**< Shift value for CRYPTOACC_OPPTRC */ 814 #define _CRYPTOACC_PK_POINTERS_OPPTRC_MASK 0xF0000UL /**< Bit mask for CRYPTOACC_OPPTRC */ 815 #define _CRYPTOACC_PK_POINTERS_OPPTRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_POINTERS */ 816 #define CRYPTOACC_PK_POINTERS_OPPTRC_DEFAULT (_CRYPTOACC_PK_POINTERS_OPPTRC_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_PK_POINTERS*/ 817 #define _CRYPTOACC_PK_POINTERS_OPPTRN_SHIFT 24 /**< Shift value for CRYPTOACC_OPPTRN */ 818 #define _CRYPTOACC_PK_POINTERS_OPPTRN_MASK 0xF000000UL /**< Bit mask for CRYPTOACC_OPPTRN */ 819 #define _CRYPTOACC_PK_POINTERS_OPPTRN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_POINTERS */ 820 #define CRYPTOACC_PK_POINTERS_OPPTRN_DEFAULT (_CRYPTOACC_PK_POINTERS_OPPTRN_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTOACC_PK_POINTERS*/ 821 822 /* Bit fields for CRYPTOACC PK_COMMAND */ 823 #define _CRYPTOACC_PK_COMMAND_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PK_COMMAND */ 824 #define _CRYPTOACC_PK_COMMAND_MASK 0xFF77FFFFUL /**< Mask for CRYPTOACC_PK_COMMAND */ 825 #define _CRYPTOACC_PK_COMMAND_OPEADDR_SHIFT 0 /**< Shift value for CRYPTOACC_OPEADDR */ 826 #define _CRYPTOACC_PK_COMMAND_OPEADDR_MASK 0x7FUL /**< Bit mask for CRYPTOACC_OPEADDR */ 827 #define _CRYPTOACC_PK_COMMAND_OPEADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_COMMAND */ 828 #define CRYPTOACC_PK_COMMAND_OPEADDR_DEFAULT (_CRYPTOACC_PK_COMMAND_OPEADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PK_COMMAND*/ 829 #define CRYPTOACC_PK_COMMAND_FIELDF (0x1UL << 7) /**< FIELDF */ 830 #define _CRYPTOACC_PK_COMMAND_FIELDF_SHIFT 7 /**< Shift value for CRYPTOACC_FIELDF */ 831 #define _CRYPTOACC_PK_COMMAND_FIELDF_MASK 0x80UL /**< Bit mask for CRYPTOACC_FIELDF */ 832 #define _CRYPTOACC_PK_COMMAND_FIELDF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_COMMAND */ 833 #define CRYPTOACC_PK_COMMAND_FIELDF_DEFAULT (_CRYPTOACC_PK_COMMAND_FIELDF_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_PK_COMMAND*/ 834 #define _CRYPTOACC_PK_COMMAND_OPBYTESM1_SHIFT 8 /**< Shift value for CRYPTOACC_OPBYTESM1 */ 835 #define _CRYPTOACC_PK_COMMAND_OPBYTESM1_MASK 0x7FF00UL /**< Bit mask for CRYPTOACC_OPBYTESM1 */ 836 #define _CRYPTOACC_PK_COMMAND_OPBYTESM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_COMMAND */ 837 #define CRYPTOACC_PK_COMMAND_OPBYTESM1_DEFAULT (_CRYPTOACC_PK_COMMAND_OPBYTESM1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_PK_COMMAND*/ 838 #define _CRYPTOACC_PK_COMMAND_SELCURVE_SHIFT 20 /**< Shift value for CRYPTOACC_SELCURVE */ 839 #define _CRYPTOACC_PK_COMMAND_SELCURVE_MASK 0x700000UL /**< Bit mask for CRYPTOACC_SELCURVE */ 840 #define _CRYPTOACC_PK_COMMAND_SELCURVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_COMMAND */ 841 #define CRYPTOACC_PK_COMMAND_SELCURVE_DEFAULT (_CRYPTOACC_PK_COMMAND_SELCURVE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTOACC_PK_COMMAND*/ 842 #define CRYPTOACC_PK_COMMAND_RANDKE (0x1UL << 24) /**< RANDKE */ 843 #define _CRYPTOACC_PK_COMMAND_RANDKE_SHIFT 24 /**< Shift value for CRYPTOACC_RANDKE */ 844 #define _CRYPTOACC_PK_COMMAND_RANDKE_MASK 0x1000000UL /**< Bit mask for CRYPTOACC_RANDKE */ 845 #define _CRYPTOACC_PK_COMMAND_RANDKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_COMMAND */ 846 #define CRYPTOACC_PK_COMMAND_RANDKE_DEFAULT (_CRYPTOACC_PK_COMMAND_RANDKE_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTOACC_PK_COMMAND*/ 847 #define CRYPTOACC_PK_COMMAND_RANDPROJ (0x1UL << 25) /**< RANDPROJ */ 848 #define _CRYPTOACC_PK_COMMAND_RANDPROJ_SHIFT 25 /**< Shift value for CRYPTOACC_RANDPROJ */ 849 #define _CRYPTOACC_PK_COMMAND_RANDPROJ_MASK 0x2000000UL /**< Bit mask for CRYPTOACC_RANDPROJ */ 850 #define _CRYPTOACC_PK_COMMAND_RANDPROJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_COMMAND */ 851 #define CRYPTOACC_PK_COMMAND_RANDPROJ_DEFAULT (_CRYPTOACC_PK_COMMAND_RANDPROJ_DEFAULT << 25) /**< Shifted mode DEFAULT for CRYPTOACC_PK_COMMAND*/ 852 #define CRYPTOACC_PK_COMMAND_EDWARDS (0x1UL << 26) /**< EDWARDS */ 853 #define _CRYPTOACC_PK_COMMAND_EDWARDS_SHIFT 26 /**< Shift value for CRYPTOACC_EDWARDS */ 854 #define _CRYPTOACC_PK_COMMAND_EDWARDS_MASK 0x4000000UL /**< Bit mask for CRYPTOACC_EDWARDS */ 855 #define _CRYPTOACC_PK_COMMAND_EDWARDS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_COMMAND */ 856 #define CRYPTOACC_PK_COMMAND_EDWARDS_DEFAULT (_CRYPTOACC_PK_COMMAND_EDWARDS_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTOACC_PK_COMMAND*/ 857 #define CRYPTOACC_PK_COMMAND_BUFSEL (0x1UL << 27) /**< BUFSEL */ 858 #define _CRYPTOACC_PK_COMMAND_BUFSEL_SHIFT 27 /**< Shift value for CRYPTOACC_BUFSEL */ 859 #define _CRYPTOACC_PK_COMMAND_BUFSEL_MASK 0x8000000UL /**< Bit mask for CRYPTOACC_BUFSEL */ 860 #define _CRYPTOACC_PK_COMMAND_BUFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_COMMAND */ 861 #define CRYPTOACC_PK_COMMAND_BUFSEL_DEFAULT (_CRYPTOACC_PK_COMMAND_BUFSEL_DEFAULT << 27) /**< Shifted mode DEFAULT for CRYPTOACC_PK_COMMAND*/ 862 #define CRYPTOACC_PK_COMMAND_SWAPBYTES (0x1UL << 28) /**< SWAPBYTES */ 863 #define _CRYPTOACC_PK_COMMAND_SWAPBYTES_SHIFT 28 /**< Shift value for CRYPTOACC_SWAPBYTES */ 864 #define _CRYPTOACC_PK_COMMAND_SWAPBYTES_MASK 0x10000000UL /**< Bit mask for CRYPTOACC_SWAPBYTES */ 865 #define _CRYPTOACC_PK_COMMAND_SWAPBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_COMMAND */ 866 #define CRYPTOACC_PK_COMMAND_SWAPBYTES_DEFAULT (_CRYPTOACC_PK_COMMAND_SWAPBYTES_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTOACC_PK_COMMAND*/ 867 #define CRYPTOACC_PK_COMMAND_FLAGA (0x1UL << 29) /**< FLAGA */ 868 #define _CRYPTOACC_PK_COMMAND_FLAGA_SHIFT 29 /**< Shift value for CRYPTOACC_FLAGA */ 869 #define _CRYPTOACC_PK_COMMAND_FLAGA_MASK 0x20000000UL /**< Bit mask for CRYPTOACC_FLAGA */ 870 #define _CRYPTOACC_PK_COMMAND_FLAGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_COMMAND */ 871 #define CRYPTOACC_PK_COMMAND_FLAGA_DEFAULT (_CRYPTOACC_PK_COMMAND_FLAGA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTOACC_PK_COMMAND*/ 872 #define CRYPTOACC_PK_COMMAND_FLAGB (0x1UL << 30) /**< FLAGB */ 873 #define _CRYPTOACC_PK_COMMAND_FLAGB_SHIFT 30 /**< Shift value for CRYPTOACC_FLAGB */ 874 #define _CRYPTOACC_PK_COMMAND_FLAGB_MASK 0x40000000UL /**< Bit mask for CRYPTOACC_FLAGB */ 875 #define _CRYPTOACC_PK_COMMAND_FLAGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_COMMAND */ 876 #define CRYPTOACC_PK_COMMAND_FLAGB_DEFAULT (_CRYPTOACC_PK_COMMAND_FLAGB_DEFAULT << 30) /**< Shifted mode DEFAULT for CRYPTOACC_PK_COMMAND*/ 877 #define CRYPTOACC_PK_COMMAND_CALCR2 (0x1UL << 31) /**< CALCR2 */ 878 #define _CRYPTOACC_PK_COMMAND_CALCR2_SHIFT 31 /**< Shift value for CRYPTOACC_CALCR2 */ 879 #define _CRYPTOACC_PK_COMMAND_CALCR2_MASK 0x80000000UL /**< Bit mask for CRYPTOACC_CALCR2 */ 880 #define _CRYPTOACC_PK_COMMAND_CALCR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_COMMAND */ 881 #define CRYPTOACC_PK_COMMAND_CALCR2_DEFAULT (_CRYPTOACC_PK_COMMAND_CALCR2_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTOACC_PK_COMMAND*/ 882 883 /* Bit fields for CRYPTOACC PK_CONTROL */ 884 #define _CRYPTOACC_PK_CONTROL_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PK_CONTROL */ 885 #define _CRYPTOACC_PK_CONTROL_MASK 0x00000003UL /**< Mask for CRYPTOACC_PK_CONTROL */ 886 #define CRYPTOACC_PK_CONTROL_START (0x1UL << 0) /**< START */ 887 #define _CRYPTOACC_PK_CONTROL_START_SHIFT 0 /**< Shift value for CRYPTOACC_START */ 888 #define _CRYPTOACC_PK_CONTROL_START_MASK 0x1UL /**< Bit mask for CRYPTOACC_START */ 889 #define _CRYPTOACC_PK_CONTROL_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_CONTROL */ 890 #define CRYPTOACC_PK_CONTROL_START_DEFAULT (_CRYPTOACC_PK_CONTROL_START_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PK_CONTROL*/ 891 #define CRYPTOACC_PK_CONTROL_CLEARIRQ (0x1UL << 1) /**< CLEARIRQ */ 892 #define _CRYPTOACC_PK_CONTROL_CLEARIRQ_SHIFT 1 /**< Shift value for CRYPTOACC_CLEARIRQ */ 893 #define _CRYPTOACC_PK_CONTROL_CLEARIRQ_MASK 0x2UL /**< Bit mask for CRYPTOACC_CLEARIRQ */ 894 #define _CRYPTOACC_PK_CONTROL_CLEARIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_CONTROL */ 895 #define CRYPTOACC_PK_CONTROL_CLEARIRQ_DEFAULT (_CRYPTOACC_PK_CONTROL_CLEARIRQ_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_PK_CONTROL*/ 896 897 /* Bit fields for CRYPTOACC PK_STATUS */ 898 #define _CRYPTOACC_PK_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PK_STATUS */ 899 #define _CRYPTOACC_PK_STATUS_MASK 0x0003FFFFUL /**< Mask for CRYPTOACC_PK_STATUS */ 900 #define _CRYPTOACC_PK_STATUS_FAILPTR_SHIFT 0 /**< Shift value for CRYPTOACC_FAILPTR */ 901 #define _CRYPTOACC_PK_STATUS_FAILPTR_MASK 0xFUL /**< Bit mask for CRYPTOACC_FAILPTR */ 902 #define _CRYPTOACC_PK_STATUS_FAILPTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_STATUS */ 903 #define CRYPTOACC_PK_STATUS_FAILPTR_DEFAULT (_CRYPTOACC_PK_STATUS_FAILPTR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PK_STATUS*/ 904 #define _CRYPTOACC_PK_STATUS_ERRORFLAGS_SHIFT 4 /**< Shift value for CRYPTOACC_ERRORFLAGS */ 905 #define _CRYPTOACC_PK_STATUS_ERRORFLAGS_MASK 0xFFF0UL /**< Bit mask for CRYPTOACC_ERRORFLAGS */ 906 #define _CRYPTOACC_PK_STATUS_ERRORFLAGS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_STATUS */ 907 #define CRYPTOACC_PK_STATUS_ERRORFLAGS_DEFAULT (_CRYPTOACC_PK_STATUS_ERRORFLAGS_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_PK_STATUS*/ 908 #define CRYPTOACC_PK_STATUS_PK_BUSY (0x1UL << 16) /**< PK_BUSY */ 909 #define _CRYPTOACC_PK_STATUS_PK_BUSY_SHIFT 16 /**< Shift value for CRYPTOACC_PK_BUSY */ 910 #define _CRYPTOACC_PK_STATUS_PK_BUSY_MASK 0x10000UL /**< Bit mask for CRYPTOACC_PK_BUSY */ 911 #define _CRYPTOACC_PK_STATUS_PK_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_STATUS */ 912 #define CRYPTOACC_PK_STATUS_PK_BUSY_DEFAULT (_CRYPTOACC_PK_STATUS_PK_BUSY_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_PK_STATUS*/ 913 #define CRYPTOACC_PK_STATUS_INTRPTSTATUS (0x1UL << 17) /**< INTRPTSTATUS */ 914 #define _CRYPTOACC_PK_STATUS_INTRPTSTATUS_SHIFT 17 /**< Shift value for CRYPTOACC_INTRPTSTATUS */ 915 #define _CRYPTOACC_PK_STATUS_INTRPTSTATUS_MASK 0x20000UL /**< Bit mask for CRYPTOACC_INTRPTSTATUS */ 916 #define _CRYPTOACC_PK_STATUS_INTRPTSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_STATUS */ 917 #define CRYPTOACC_PK_STATUS_INTRPTSTATUS_DEFAULT (_CRYPTOACC_PK_STATUS_INTRPTSTATUS_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_PK_STATUS*/ 918 919 /* Bit fields for CRYPTOACC PK_TIMER */ 920 #define _CRYPTOACC_PK_TIMER_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PK_TIMER */ 921 #define _CRYPTOACC_PK_TIMER_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_PK_TIMER */ 922 #define _CRYPTOACC_PK_TIMER_TIMER_SHIFT 0 /**< Shift value for CRYPTOACC_TIMER */ 923 #define _CRYPTOACC_PK_TIMER_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_TIMER */ 924 #define _CRYPTOACC_PK_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_TIMER */ 925 #define CRYPTOACC_PK_TIMER_TIMER_DEFAULT (_CRYPTOACC_PK_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PK_TIMER */ 926 927 /* Bit fields for CRYPTOACC PK_HWCONFIG */ 928 #define _CRYPTOACC_PK_HWCONFIG_RESETVALUE 0x01F11021UL /**< Default value for CRYPTOACC_PK_HWCONFIG */ 929 #define _CRYPTOACC_PK_HWCONFIG_MASK 0x81F3FFFFUL /**< Mask for CRYPTOACC_PK_HWCONFIG */ 930 #define _CRYPTOACC_PK_HWCONFIG_MAXOPSIZE_SHIFT 0 /**< Shift value for CRYPTOACC_MAXOPSIZE */ 931 #define _CRYPTOACC_PK_HWCONFIG_MAXOPSIZE_MASK 0xFFFUL /**< Bit mask for CRYPTOACC_MAXOPSIZE */ 932 #define _CRYPTOACC_PK_HWCONFIG_MAXOPSIZE_DEFAULT 0x00000021UL /**< Mode DEFAULT for CRYPTOACC_PK_HWCONFIG */ 933 #define CRYPTOACC_PK_HWCONFIG_MAXOPSIZE_DEFAULT (_CRYPTOACC_PK_HWCONFIG_MAXOPSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PK_HWCONFIG*/ 934 #define _CRYPTOACC_PK_HWCONFIG_NBMULT_SHIFT 12 /**< Shift value for CRYPTOACC_NBMULT */ 935 #define _CRYPTOACC_PK_HWCONFIG_NBMULT_MASK 0xF000UL /**< Bit mask for CRYPTOACC_NBMULT */ 936 #define _CRYPTOACC_PK_HWCONFIG_NBMULT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_PK_HWCONFIG */ 937 #define CRYPTOACC_PK_HWCONFIG_NBMULT_DEFAULT (_CRYPTOACC_PK_HWCONFIG_NBMULT_DEFAULT << 12) /**< Shifted mode DEFAULT for CRYPTOACC_PK_HWCONFIG*/ 938 #define CRYPTOACC_PK_HWCONFIG_PRIMEFIELD (0x1UL << 16) /**< PRIMEFIELD */ 939 #define _CRYPTOACC_PK_HWCONFIG_PRIMEFIELD_SHIFT 16 /**< Shift value for CRYPTOACC_PRIMEFIELD */ 940 #define _CRYPTOACC_PK_HWCONFIG_PRIMEFIELD_MASK 0x10000UL /**< Bit mask for CRYPTOACC_PRIMEFIELD */ 941 #define _CRYPTOACC_PK_HWCONFIG_PRIMEFIELD_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_PK_HWCONFIG */ 942 #define CRYPTOACC_PK_HWCONFIG_PRIMEFIELD_DEFAULT (_CRYPTOACC_PK_HWCONFIG_PRIMEFIELD_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_PK_HWCONFIG*/ 943 #define CRYPTOACC_PK_HWCONFIG_BINARYFIELD (0x1UL << 17) /**< BINARYFIELD */ 944 #define _CRYPTOACC_PK_HWCONFIG_BINARYFIELD_SHIFT 17 /**< Shift value for CRYPTOACC_BINARYFIELD */ 945 #define _CRYPTOACC_PK_HWCONFIG_BINARYFIELD_MASK 0x20000UL /**< Bit mask for CRYPTOACC_BINARYFIELD */ 946 #define _CRYPTOACC_PK_HWCONFIG_BINARYFIELD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_HWCONFIG */ 947 #define CRYPTOACC_PK_HWCONFIG_BINARYFIELD_DEFAULT (_CRYPTOACC_PK_HWCONFIG_BINARYFIELD_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_PK_HWCONFIG*/ 948 #define CRYPTOACC_PK_HWCONFIG_P256 (0x1UL << 20) /**< P256 */ 949 #define _CRYPTOACC_PK_HWCONFIG_P256_SHIFT 20 /**< Shift value for CRYPTOACC_P256 */ 950 #define _CRYPTOACC_PK_HWCONFIG_P256_MASK 0x100000UL /**< Bit mask for CRYPTOACC_P256 */ 951 #define _CRYPTOACC_PK_HWCONFIG_P256_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_PK_HWCONFIG */ 952 #define CRYPTOACC_PK_HWCONFIG_P256_DEFAULT (_CRYPTOACC_PK_HWCONFIG_P256_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTOACC_PK_HWCONFIG*/ 953 #define CRYPTOACC_PK_HWCONFIG_P384 (0x1UL << 21) /**< P384 */ 954 #define _CRYPTOACC_PK_HWCONFIG_P384_SHIFT 21 /**< Shift value for CRYPTOACC_P384 */ 955 #define _CRYPTOACC_PK_HWCONFIG_P384_MASK 0x200000UL /**< Bit mask for CRYPTOACC_P384 */ 956 #define _CRYPTOACC_PK_HWCONFIG_P384_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_PK_HWCONFIG */ 957 #define CRYPTOACC_PK_HWCONFIG_P384_DEFAULT (_CRYPTOACC_PK_HWCONFIG_P384_DEFAULT << 21) /**< Shifted mode DEFAULT for CRYPTOACC_PK_HWCONFIG*/ 958 #define CRYPTOACC_PK_HWCONFIG_P521 (0x1UL << 22) /**< P521 */ 959 #define _CRYPTOACC_PK_HWCONFIG_P521_SHIFT 22 /**< Shift value for CRYPTOACC_P521 */ 960 #define _CRYPTOACC_PK_HWCONFIG_P521_MASK 0x400000UL /**< Bit mask for CRYPTOACC_P521 */ 961 #define _CRYPTOACC_PK_HWCONFIG_P521_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_PK_HWCONFIG */ 962 #define CRYPTOACC_PK_HWCONFIG_P521_DEFAULT (_CRYPTOACC_PK_HWCONFIG_P521_DEFAULT << 22) /**< Shifted mode DEFAULT for CRYPTOACC_PK_HWCONFIG*/ 963 #define CRYPTOACC_PK_HWCONFIG_P192 (0x1UL << 23) /**< P192 */ 964 #define _CRYPTOACC_PK_HWCONFIG_P192_SHIFT 23 /**< Shift value for CRYPTOACC_P192 */ 965 #define _CRYPTOACC_PK_HWCONFIG_P192_MASK 0x800000UL /**< Bit mask for CRYPTOACC_P192 */ 966 #define _CRYPTOACC_PK_HWCONFIG_P192_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_PK_HWCONFIG */ 967 #define CRYPTOACC_PK_HWCONFIG_P192_DEFAULT (_CRYPTOACC_PK_HWCONFIG_P192_DEFAULT << 23) /**< Shifted mode DEFAULT for CRYPTOACC_PK_HWCONFIG*/ 968 #define CRYPTOACC_PK_HWCONFIG_X25519 (0x1UL << 24) /**< X25519 */ 969 #define _CRYPTOACC_PK_HWCONFIG_X25519_SHIFT 24 /**< Shift value for CRYPTOACC_X25519 */ 970 #define _CRYPTOACC_PK_HWCONFIG_X25519_MASK 0x1000000UL /**< Bit mask for CRYPTOACC_X25519 */ 971 #define _CRYPTOACC_PK_HWCONFIG_X25519_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_PK_HWCONFIG */ 972 #define CRYPTOACC_PK_HWCONFIG_X25519_DEFAULT (_CRYPTOACC_PK_HWCONFIG_X25519_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTOACC_PK_HWCONFIG*/ 973 #define CRYPTOACC_PK_HWCONFIG_DISABLECM (0x1UL << 31) /**< DISABLECM */ 974 #define _CRYPTOACC_PK_HWCONFIG_DISABLECM_SHIFT 31 /**< Shift value for CRYPTOACC_DISABLECM */ 975 #define _CRYPTOACC_PK_HWCONFIG_DISABLECM_MASK 0x80000000UL /**< Bit mask for CRYPTOACC_DISABLECM */ 976 #define _CRYPTOACC_PK_HWCONFIG_DISABLECM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PK_HWCONFIG */ 977 #define CRYPTOACC_PK_HWCONFIG_DISABLECM_DEFAULT (_CRYPTOACC_PK_HWCONFIG_DISABLECM_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTOACC_PK_HWCONFIG*/ 978 979 /** @} End of group EFR32BG27_CRYPTOACC_BitFields */ 980 /** @} End of group EFR32BG27_CRYPTOACC */ 981 /** @} End of group Parts */ 982 983 #endif // EFR32BG27_CRYPTOACC_H 984
