1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG22 TIMER register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG22_TIMER_H 31 #define EFR32BG22_TIMER_H 32 #define TIMER_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG22_TIMER TIMER 40 * @{ 41 * @brief EFR32BG22 TIMER Register Declaration. 42 *****************************************************************************/ 43 44 /** TIMER CC Register Group Declaration. */ 45 typedef struct { 46 __IOM uint32_t CFG; /**< CC Channel Configuration Register */ 47 __IOM uint32_t CTRL; /**< CC Channel Control Register */ 48 __IOM uint32_t OC; /**< OC Channel Value Register */ 49 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 50 __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ 51 __IM uint32_t ICF; /**< IC Channel Value Register */ 52 __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ 53 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 54 } TIMER_CC_TypeDef; 55 56 /** TIMER Register Declaration. */ 57 typedef struct { 58 __IM uint32_t IPVERSION; /**< IP version ID */ 59 __IOM uint32_t CFG; /**< Configuration Register */ 60 __IOM uint32_t CTRL; /**< Control Register */ 61 __IOM uint32_t CMD; /**< Command Register */ 62 __IM uint32_t STATUS; /**< Status Register */ 63 __IOM uint32_t IF; /**< Interrupt Flag Register */ 64 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 65 __IOM uint32_t TOP; /**< Counter Top Value Register */ 66 __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ 67 __IOM uint32_t CNT; /**< Counter Value Register */ 68 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 69 __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ 70 __IOM uint32_t EN; /**< module en */ 71 uint32_t RESERVED1[11U]; /**< Reserved for future use */ 72 TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ 73 uint32_t RESERVED2[8U]; /**< Reserved for future use */ 74 __IOM uint32_t DTCFG; /**< DTI Configuration Register */ 75 __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ 76 __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ 77 __IOM uint32_t DTCTRL; /**< DTI Control Register */ 78 __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ 79 __IM uint32_t DTFAULT; /**< DTI Fault Register */ 80 __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ 81 __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ 82 uint32_t RESERVED3[960U]; /**< Reserved for future use */ 83 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 84 __IOM uint32_t CFG_SET; /**< Configuration Register */ 85 __IOM uint32_t CTRL_SET; /**< Control Register */ 86 __IOM uint32_t CMD_SET; /**< Command Register */ 87 __IM uint32_t STATUS_SET; /**< Status Register */ 88 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 89 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 90 __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ 91 __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ 92 __IOM uint32_t CNT_SET; /**< Counter Value Register */ 93 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 94 __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ 95 __IOM uint32_t EN_SET; /**< module en */ 96 uint32_t RESERVED5[11U]; /**< Reserved for future use */ 97 TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ 98 uint32_t RESERVED6[8U]; /**< Reserved for future use */ 99 __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ 100 __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ 101 __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ 102 __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ 103 __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ 104 __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ 105 __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ 106 __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ 107 uint32_t RESERVED7[960U]; /**< Reserved for future use */ 108 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 109 __IOM uint32_t CFG_CLR; /**< Configuration Register */ 110 __IOM uint32_t CTRL_CLR; /**< Control Register */ 111 __IOM uint32_t CMD_CLR; /**< Command Register */ 112 __IM uint32_t STATUS_CLR; /**< Status Register */ 113 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 114 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 115 __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ 116 __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ 117 __IOM uint32_t CNT_CLR; /**< Counter Value Register */ 118 uint32_t RESERVED8[1U]; /**< Reserved for future use */ 119 __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ 120 __IOM uint32_t EN_CLR; /**< module en */ 121 uint32_t RESERVED9[11U]; /**< Reserved for future use */ 122 TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ 123 uint32_t RESERVED10[8U]; /**< Reserved for future use */ 124 __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ 125 __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ 126 __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ 127 __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ 128 __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ 129 __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ 130 __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ 131 __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ 132 uint32_t RESERVED11[960U]; /**< Reserved for future use */ 133 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 134 __IOM uint32_t CFG_TGL; /**< Configuration Register */ 135 __IOM uint32_t CTRL_TGL; /**< Control Register */ 136 __IOM uint32_t CMD_TGL; /**< Command Register */ 137 __IM uint32_t STATUS_TGL; /**< Status Register */ 138 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 139 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 140 __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ 141 __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ 142 __IOM uint32_t CNT_TGL; /**< Counter Value Register */ 143 uint32_t RESERVED12[1U]; /**< Reserved for future use */ 144 __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ 145 __IOM uint32_t EN_TGL; /**< module en */ 146 uint32_t RESERVED13[11U]; /**< Reserved for future use */ 147 TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ 148 uint32_t RESERVED14[8U]; /**< Reserved for future use */ 149 __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ 150 __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ 151 __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ 152 __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ 153 __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ 154 __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ 155 __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ 156 __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ 157 } TIMER_TypeDef; 158 /** @} End of group EFR32BG22_TIMER */ 159 160 /**************************************************************************//** 161 * @addtogroup EFR32BG22_TIMER 162 * @{ 163 * @defgroup EFR32BG22_TIMER_BitFields TIMER Bit Fields 164 * @{ 165 *****************************************************************************/ 166 167 /* Bit fields for TIMER IPVERSION */ 168 #define _TIMER_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for TIMER_IPVERSION */ 169 #define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ 170 #define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ 171 #define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ 172 #define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IPVERSION */ 173 #define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ 174 175 /* Bit fields for TIMER CFG */ 176 #define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ 177 #define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ 178 #define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ 179 #define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ 180 #define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 181 #define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ 182 #define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ 183 #define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ 184 #define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ 185 #define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ 186 #define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ 187 #define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ 188 #define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ 189 #define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ 190 #define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ 191 #define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ 192 #define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ 193 #define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 194 #define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ 195 #define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ 196 #define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ 197 #define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ 198 #define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ 199 #define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ 200 #define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ 201 #define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ 202 #define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 203 #define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ 204 #define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ 205 #define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ 206 #define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ 207 #define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 208 #define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ 209 #define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ 210 #define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ 211 #define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ 212 #define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ 213 #define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ 214 #define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ 215 #define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ 216 #define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 217 #define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ 218 #define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ 219 #define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ 220 #define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ 221 #define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ 222 #define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ 223 #define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ 224 #define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ 225 #define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 226 #define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ 227 #define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ 228 #define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ 229 #define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 230 #define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ 231 #define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ 232 #define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ 233 #define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ 234 #define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ 235 #define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ 236 #define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ 237 #define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ 238 #define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ 239 #define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ 240 #define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 241 #define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ 242 #define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ 243 #define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ 244 #define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ 245 #define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ 246 #define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ 247 #define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ 248 #define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ 249 #define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 250 #define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ 251 #define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ 252 #define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ 253 #define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ 254 #define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ 255 #define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ 256 #define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ 257 #define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ 258 #define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 259 #define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ 260 #define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ 261 #define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ 262 #define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ 263 #define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 264 #define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ 265 #define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ 266 #define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ 267 #define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ 268 #define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 269 #define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ 270 #define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ 271 #define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ 272 #define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ 273 #define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ 274 #define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ 275 #define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ 276 #define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ 277 #define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ 278 #define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ 279 #define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ 280 #define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ 281 #define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ 282 #define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ 283 #define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ 284 #define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ 285 #define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ 286 #define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ 287 #define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ 288 #define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ 289 #define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ 290 #define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ 291 #define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ 292 #define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ 293 #define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ 294 #define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ 295 #define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ 296 297 /* Bit fields for TIMER CTRL */ 298 #define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ 299 #define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ 300 #define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ 301 #define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ 302 #define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ 303 #define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ 304 #define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ 305 #define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ 306 #define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ 307 #define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ 308 #define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ 309 #define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ 310 #define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ 311 #define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ 312 #define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ 313 #define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ 314 #define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ 315 #define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ 316 #define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ 317 #define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ 318 #define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ 319 #define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ 320 #define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ 321 #define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ 322 #define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ 323 #define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ 324 #define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ 325 #define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ 326 #define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ 327 #define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ 328 #define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ 329 330 /* Bit fields for TIMER CMD */ 331 #define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ 332 #define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ 333 #define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ 334 #define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ 335 #define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ 336 #define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ 337 #define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ 338 #define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ 339 #define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ 340 #define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ 341 #define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ 342 #define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ 343 344 /* Bit fields for TIMER STATUS */ 345 #define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ 346 #define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ 347 #define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ 348 #define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ 349 #define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ 350 #define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 351 #define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ 352 #define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ 353 #define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ 354 #define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ 355 #define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 356 #define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ 357 #define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ 358 #define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ 359 #define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ 360 #define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ 361 #define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ 362 #define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ 363 #define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ 364 #define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 365 #define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ 366 #define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ 367 #define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ 368 #define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ 369 #define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 370 #define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ 371 #define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ 372 #define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ 373 #define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ 374 #define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ 375 #define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ 376 #define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ 377 #define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ 378 #define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 379 #define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ 380 #define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ 381 #define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ 382 #define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ 383 #define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ 384 #define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ 385 #define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ 386 #define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ 387 #define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 388 #define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ 389 #define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ 390 #define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ 391 #define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ 392 #define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 393 #define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ 394 #define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ 395 #define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ 396 #define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ 397 #define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 398 #define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ 399 #define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ 400 #define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ 401 #define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ 402 #define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 403 #define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ 404 #define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ 405 #define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ 406 #define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ 407 #define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 408 #define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ 409 #define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ 410 #define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ 411 #define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ 412 #define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 413 #define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ 414 #define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ 415 #define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ 416 #define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ 417 #define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 418 #define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ 419 #define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ 420 #define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ 421 #define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ 422 #define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 423 #define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ 424 #define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ 425 #define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ 426 #define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ 427 #define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ 428 #define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ 429 #define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ 430 #define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ 431 #define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 432 #define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ 433 #define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ 434 #define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ 435 #define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ 436 #define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ 437 #define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ 438 #define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ 439 #define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ 440 #define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ 441 #define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ 442 #define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ 443 #define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ 444 #define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ 445 #define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ 446 447 /* Bit fields for TIMER IF */ 448 #define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ 449 #define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ 450 #define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ 451 #define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 452 #define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 453 #define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 454 #define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ 455 #define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ 456 #define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 457 #define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 458 #define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 459 #define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ 460 #define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ 461 #define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 462 #define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 463 #define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 464 #define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ 465 #define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ 466 #define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 467 #define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 468 #define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 469 #define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ 470 #define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ 471 #define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 472 #define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 473 #define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 474 #define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ 475 #define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ 476 #define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 477 #define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 478 #define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 479 #define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ 480 #define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ 481 #define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ 482 #define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ 483 #define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 484 #define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ 485 #define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ 486 #define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ 487 #define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ 488 #define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 489 #define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ 490 #define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ 491 #define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ 492 #define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ 493 #define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 494 #define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ 495 #define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ 496 #define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ 497 #define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ 498 #define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 499 #define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ 500 #define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ 501 #define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ 502 #define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ 503 #define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 504 #define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ 505 #define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ 506 #define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ 507 #define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ 508 #define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 509 #define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ 510 #define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ 511 #define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ 512 #define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ 513 #define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 514 #define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ 515 #define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ 516 #define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ 517 #define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ 518 #define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 519 #define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ 520 #define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ 521 #define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ 522 #define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ 523 #define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ 524 #define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ 525 526 /* Bit fields for TIMER IEN */ 527 #define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ 528 #define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ 529 #define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ 530 #define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 531 #define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 532 #define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 533 #define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ 534 #define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ 535 #define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 536 #define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 537 #define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 538 #define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ 539 #define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ 540 #define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 541 #define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 542 #define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 543 #define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ 544 #define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ 545 #define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 546 #define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 547 #define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 548 #define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ 549 #define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ 550 #define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 551 #define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 552 #define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 553 #define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ 554 #define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ 555 #define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 556 #define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 557 #define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 558 #define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ 559 #define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ 560 #define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ 561 #define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ 562 #define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 563 #define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ 564 #define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ 565 #define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ 566 #define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ 567 #define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 568 #define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ 569 #define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ 570 #define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ 571 #define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ 572 #define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 573 #define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ 574 #define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ 575 #define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ 576 #define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ 577 #define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 578 #define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ 579 #define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ 580 #define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ 581 #define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ 582 #define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 583 #define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ 584 #define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ 585 #define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ 586 #define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ 587 #define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 588 #define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ 589 #define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ 590 #define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ 591 #define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ 592 #define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 593 #define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ 594 #define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ 595 #define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ 596 #define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ 597 #define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 598 #define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ 599 #define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ 600 #define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ 601 #define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ 602 #define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ 603 #define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ 604 605 /* Bit fields for TIMER TOP */ 606 #define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ 607 #define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ 608 #define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ 609 #define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ 610 #define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ 611 #define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ 612 613 /* Bit fields for TIMER TOPB */ 614 #define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ 615 #define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ 616 #define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ 617 #define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ 618 #define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ 619 #define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ 620 621 /* Bit fields for TIMER CNT */ 622 #define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ 623 #define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ 624 #define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ 625 #define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ 626 #define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ 627 #define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ 628 629 /* Bit fields for TIMER LOCK */ 630 #define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ 631 #define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ 632 #define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ 633 #define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ 634 #define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ 635 #define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ 636 #define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ 637 #define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ 638 639 /* Bit fields for TIMER EN */ 640 #define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ 641 #define _TIMER_EN_MASK 0x00000001UL /**< Mask for TIMER_EN */ 642 #define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ 643 #define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ 644 #define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ 645 #define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ 646 #define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ 647 648 /* Bit fields for TIMER CC_CFG */ 649 #define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ 650 #define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ 651 #define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ 652 #define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ 653 #define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ 654 #define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ 655 #define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ 656 #define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ 657 #define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ 658 #define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ 659 #define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ 660 #define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ 661 #define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ 662 #define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ 663 #define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ 664 #define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ 665 #define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ 666 #define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ 667 #define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ 668 #define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ 669 #define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ 670 #define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ 671 #define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ 672 #define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ 673 #define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ 674 #define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ 675 #define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ 676 #define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ 677 #define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ 678 #define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ 679 #define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ 680 #define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ 681 #define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ 682 #define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ 683 #define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ 684 #define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ 685 #define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ 686 #define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ 687 #define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ 688 #define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ 689 #define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ 690 #define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ 691 #define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ 692 #define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ 693 #define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ 694 #define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ 695 #define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ 696 #define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ 697 #define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ 698 #define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ 699 #define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ 700 #define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ 701 #define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ 702 #define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ 703 704 /* Bit fields for TIMER CC_CTRL */ 705 #define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ 706 #define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ 707 #define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ 708 #define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ 709 #define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ 710 #define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ 711 #define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ 712 #define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ 713 #define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ 714 #define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ 715 #define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ 716 #define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ 717 #define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ 718 #define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ 719 #define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ 720 #define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ 721 #define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ 722 #define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ 723 #define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ 724 #define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ 725 #define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ 726 #define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ 727 #define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ 728 #define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ 729 #define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ 730 #define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ 731 #define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ 732 #define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ 733 #define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ 734 #define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ 735 #define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ 736 #define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ 737 #define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ 738 #define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ 739 #define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ 740 #define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ 741 #define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ 742 #define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ 743 #define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ 744 #define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ 745 #define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ 746 #define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ 747 #define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ 748 #define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ 749 #define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ 750 #define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ 751 #define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ 752 #define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ 753 #define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ 754 #define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ 755 #define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ 756 #define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ 757 #define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ 758 #define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ 759 #define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ 760 #define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ 761 #define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ 762 #define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ 763 #define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ 764 #define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ 765 #define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ 766 #define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ 767 #define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ 768 #define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ 769 #define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ 770 #define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ 771 #define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ 772 773 /* Bit fields for TIMER CC_OC */ 774 #define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ 775 #define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ 776 #define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ 777 #define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ 778 #define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ 779 #define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ 780 781 /* Bit fields for TIMER CC_OCB */ 782 #define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ 783 #define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ 784 #define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ 785 #define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ 786 #define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ 787 #define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ 788 789 /* Bit fields for TIMER CC_ICF */ 790 #define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ 791 #define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ 792 #define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ 793 #define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ 794 #define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ 795 #define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ 796 797 /* Bit fields for TIMER CC_ICOF */ 798 #define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ 799 #define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ 800 #define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ 801 #define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ 802 #define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ 803 #define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ 804 805 /* Bit fields for TIMER DTCFG */ 806 #define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ 807 #define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ 808 #define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ 809 #define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ 810 #define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ 811 #define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ 812 #define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ 813 #define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ 814 #define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ 815 #define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ 816 #define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ 817 #define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ 818 #define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ 819 #define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ 820 #define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ 821 #define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ 822 #define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ 823 #define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ 824 #define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ 825 #define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ 826 #define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ 827 #define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ 828 #define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ 829 #define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ 830 #define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ 831 #define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ 832 #define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ 833 #define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ 834 #define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ 835 #define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ 836 #define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ 837 838 /* Bit fields for TIMER DTTIMECFG */ 839 #define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ 840 #define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ 841 #define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ 842 #define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ 843 #define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ 844 #define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ 845 #define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ 846 #define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ 847 #define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ 848 #define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ 849 #define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ 850 #define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ 851 #define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ 852 #define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ 853 854 /* Bit fields for TIMER DTFCFG */ 855 #define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ 856 #define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ 857 #define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ 858 #define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ 859 #define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ 860 #define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ 861 #define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ 862 #define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ 863 #define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ 864 #define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ 865 #define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ 866 #define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ 867 #define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ 868 #define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ 869 #define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ 870 #define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ 871 #define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ 872 #define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ 873 #define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ 874 #define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ 875 #define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ 876 #define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ 877 #define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ 878 #define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ 879 #define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ 880 #define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ 881 #define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ 882 #define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ 883 #define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ 884 #define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ 885 #define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ 886 #define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ 887 #define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ 888 #define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ 889 #define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ 890 #define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ 891 #define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ 892 #define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ 893 #define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ 894 895 /* Bit fields for TIMER DTCTRL */ 896 #define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ 897 #define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ 898 #define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ 899 #define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ 900 #define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ 901 #define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ 902 #define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ 903 #define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ 904 #define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ 905 #define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ 906 #define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ 907 #define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ 908 909 /* Bit fields for TIMER DTOGEN */ 910 #define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ 911 #define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ 912 #define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ 913 #define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ 914 #define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ 915 #define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ 916 #define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ 917 #define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ 918 #define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ 919 #define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ 920 #define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ 921 #define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ 922 #define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ 923 #define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ 924 #define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ 925 #define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ 926 #define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ 927 #define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ 928 #define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ 929 #define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ 930 #define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ 931 #define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ 932 #define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ 933 #define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ 934 #define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ 935 #define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ 936 #define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ 937 #define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ 938 #define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ 939 #define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ 940 #define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ 941 #define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ 942 943 /* Bit fields for TIMER DTFAULT */ 944 #define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ 945 #define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ 946 #define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ 947 #define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ 948 #define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ 949 #define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ 950 #define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ 951 #define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ 952 #define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ 953 #define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ 954 #define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ 955 #define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ 956 #define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ 957 #define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ 958 #define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ 959 #define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ 960 #define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ 961 #define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ 962 #define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ 963 #define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ 964 #define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ 965 #define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ 966 #define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ 967 #define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ 968 #define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ 969 #define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ 970 #define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ 971 972 /* Bit fields for TIMER DTFAULTC */ 973 #define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ 974 #define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ 975 #define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ 976 #define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ 977 #define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ 978 #define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ 979 #define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ 980 #define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ 981 #define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ 982 #define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ 983 #define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ 984 #define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ 985 #define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ 986 #define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ 987 #define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ 988 #define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ 989 #define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ 990 #define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ 991 #define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ 992 #define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ 993 #define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ 994 #define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ 995 #define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ 996 #define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ 997 #define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ 998 #define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ 999 #define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ 1000 1001 /* Bit fields for TIMER DTLOCK */ 1002 #define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ 1003 #define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ 1004 #define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ 1005 #define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ 1006 #define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ 1007 #define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ 1008 #define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ 1009 #define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ 1010 1011 /** @} End of group EFR32BG22_TIMER_BitFields */ 1012 /** @} End of group EFR32BG22_TIMER */ 1013 /** @} End of group Parts */ 1014 1015 #endif /* EFR32BG22_TIMER_H */ 1016
