1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG22 SYSCFG register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG22_SYSCFG_H 31 #define EFR32BG22_SYSCFG_H 32 #define SYSCFG_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG22_SYSCFG SYSCFG 40 * @{ 41 * @brief EFR32BG22 SYSCFG Register Declaration. 42 *****************************************************************************/ 43 44 /** SYSCFG Register Declaration. */ 45 typedef struct { 46 __IOM uint32_t IF; /**< Interrupt Flag */ 47 __IOM uint32_t IEN; /**< Interrupt Enable */ 48 uint32_t RESERVED0[2U]; /**< Reserved for future use */ 49 __IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */ 50 __IOM uint32_t CHIPREV; /**< Part Family and Revision Values */ 51 uint32_t RESERVED1[2U]; /**< Reserved for future use */ 52 __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */ 53 uint32_t RESERVED2[55U]; /**< Reserved for future use */ 54 uint32_t RESERVED3[1U]; /**< Reserved for future use */ 55 uint32_t RESERVED4[63U]; /**< Reserved for future use */ 56 __IOM uint32_t CTRL; /**< Memory System Control */ 57 uint32_t RESERVED5[1U]; /**< Reserved for future use */ 58 __IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */ 59 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 60 __IM uint32_t DMEM0ECCADDR; /**< DMEM0 ECC Address */ 61 __IOM uint32_t DMEM0ECCCTRL; /**< DMEM0 ECC Control */ 62 uint32_t RESERVED7[122U]; /**< Reserved for future use */ 63 __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO RAM Retention Control Register */ 64 uint32_t RESERVED8[1U]; /**< Reserved for future use */ 65 __IOM uint32_t RADIOECCCTRL; /**< RADIO RAM ECC Control Register */ 66 uint32_t RESERVED9[1U]; /**< Reserved for future use */ 67 __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */ 68 __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */ 69 uint32_t RESERVED10[122U]; /**< Reserved for future use */ 70 __IOM uint32_t ROOTDATA0; /**< Root Data Register 0 */ 71 __IOM uint32_t ROOTDATA1; /**< Root Data Register 1 */ 72 __IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */ 73 uint32_t RESERVED11[637U]; /**< Reserved for future use */ 74 __IOM uint32_t IF_SET; /**< Interrupt Flag */ 75 __IOM uint32_t IEN_SET; /**< Interrupt Enable */ 76 uint32_t RESERVED12[2U]; /**< Reserved for future use */ 77 __IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */ 78 __IOM uint32_t CHIPREV_SET; /**< Part Family and Revision Values */ 79 uint32_t RESERVED13[2U]; /**< Reserved for future use */ 80 __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */ 81 uint32_t RESERVED14[55U]; /**< Reserved for future use */ 82 uint32_t RESERVED15[1U]; /**< Reserved for future use */ 83 uint32_t RESERVED16[63U]; /**< Reserved for future use */ 84 __IOM uint32_t CTRL_SET; /**< Memory System Control */ 85 uint32_t RESERVED17[1U]; /**< Reserved for future use */ 86 __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */ 87 uint32_t RESERVED18[1U]; /**< Reserved for future use */ 88 __IM uint32_t DMEM0ECCADDR_SET; /**< DMEM0 ECC Address */ 89 __IOM uint32_t DMEM0ECCCTRL_SET; /**< DMEM0 ECC Control */ 90 uint32_t RESERVED19[122U]; /**< Reserved for future use */ 91 __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO RAM Retention Control Register */ 92 uint32_t RESERVED20[1U]; /**< Reserved for future use */ 93 __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO RAM ECC Control Register */ 94 uint32_t RESERVED21[1U]; /**< Reserved for future use */ 95 __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */ 96 __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */ 97 uint32_t RESERVED22[122U]; /**< Reserved for future use */ 98 __IOM uint32_t ROOTDATA0_SET; /**< Root Data Register 0 */ 99 __IOM uint32_t ROOTDATA1_SET; /**< Root Data Register 1 */ 100 __IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */ 101 uint32_t RESERVED23[637U]; /**< Reserved for future use */ 102 __IOM uint32_t IF_CLR; /**< Interrupt Flag */ 103 __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ 104 uint32_t RESERVED24[2U]; /**< Reserved for future use */ 105 __IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */ 106 __IOM uint32_t CHIPREV_CLR; /**< Part Family and Revision Values */ 107 uint32_t RESERVED25[2U]; /**< Reserved for future use */ 108 __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */ 109 uint32_t RESERVED26[55U]; /**< Reserved for future use */ 110 uint32_t RESERVED27[1U]; /**< Reserved for future use */ 111 uint32_t RESERVED28[63U]; /**< Reserved for future use */ 112 __IOM uint32_t CTRL_CLR; /**< Memory System Control */ 113 uint32_t RESERVED29[1U]; /**< Reserved for future use */ 114 __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */ 115 uint32_t RESERVED30[1U]; /**< Reserved for future use */ 116 __IM uint32_t DMEM0ECCADDR_CLR; /**< DMEM0 ECC Address */ 117 __IOM uint32_t DMEM0ECCCTRL_CLR; /**< DMEM0 ECC Control */ 118 uint32_t RESERVED31[122U]; /**< Reserved for future use */ 119 __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO RAM Retention Control Register */ 120 uint32_t RESERVED32[1U]; /**< Reserved for future use */ 121 __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO RAM ECC Control Register */ 122 uint32_t RESERVED33[1U]; /**< Reserved for future use */ 123 __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */ 124 __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */ 125 uint32_t RESERVED34[122U]; /**< Reserved for future use */ 126 __IOM uint32_t ROOTDATA0_CLR; /**< Root Data Register 0 */ 127 __IOM uint32_t ROOTDATA1_CLR; /**< Root Data Register 1 */ 128 __IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */ 129 uint32_t RESERVED35[637U]; /**< Reserved for future use */ 130 __IOM uint32_t IF_TGL; /**< Interrupt Flag */ 131 __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ 132 uint32_t RESERVED36[2U]; /**< Reserved for future use */ 133 __IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */ 134 __IOM uint32_t CHIPREV_TGL; /**< Part Family and Revision Values */ 135 uint32_t RESERVED37[2U]; /**< Reserved for future use */ 136 __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */ 137 uint32_t RESERVED38[55U]; /**< Reserved for future use */ 138 uint32_t RESERVED39[1U]; /**< Reserved for future use */ 139 uint32_t RESERVED40[63U]; /**< Reserved for future use */ 140 __IOM uint32_t CTRL_TGL; /**< Memory System Control */ 141 uint32_t RESERVED41[1U]; /**< Reserved for future use */ 142 __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */ 143 uint32_t RESERVED42[1U]; /**< Reserved for future use */ 144 __IM uint32_t DMEM0ECCADDR_TGL; /**< DMEM0 ECC Address */ 145 __IOM uint32_t DMEM0ECCCTRL_TGL; /**< DMEM0 ECC Control */ 146 uint32_t RESERVED43[122U]; /**< Reserved for future use */ 147 __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO RAM Retention Control Register */ 148 uint32_t RESERVED44[1U]; /**< Reserved for future use */ 149 __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO RAM ECC Control Register */ 150 uint32_t RESERVED45[1U]; /**< Reserved for future use */ 151 __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */ 152 __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */ 153 uint32_t RESERVED46[122U]; /**< Reserved for future use */ 154 __IOM uint32_t ROOTDATA0_TGL; /**< Root Data Register 0 */ 155 __IOM uint32_t ROOTDATA1_TGL; /**< Root Data Register 1 */ 156 __IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */ 157 } SYSCFG_TypeDef; 158 /** @} End of group EFR32BG22_SYSCFG */ 159 160 /**************************************************************************//** 161 * @addtogroup EFR32BG22_SYSCFG 162 * @{ 163 * @defgroup EFR32BG22_SYSCFG_BitFields SYSCFG Bit Fields 164 * @{ 165 *****************************************************************************/ 166 167 /* Bit fields for SYSCFG IF */ 168 #define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ 169 #define _SYSCFG_IF_MASK 0x3303000FUL /**< Mask for SYSCFG_IF */ 170 #define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt 0 */ 171 #define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ 172 #define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ 173 #define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 174 #define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ 175 #define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt 1 */ 176 #define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ 177 #define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ 178 #define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 179 #define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ 180 #define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt 2 */ 181 #define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ 182 #define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ 183 #define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 184 #define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ 185 #define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt 3 */ 186 #define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ 187 #define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ 188 #define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 189 #define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ 190 #define SYSCFG_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-Bit Error Interrupt Flag */ 191 #define _SYSCFG_IF_RAMERR1B_SHIFT 16 /**< Shift value for SYSCFG_RAMERR1B */ 192 #define _SYSCFG_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for SYSCFG_RAMERR1B */ 193 #define _SYSCFG_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 194 #define SYSCFG_IF_RAMERR1B_DEFAULT (_SYSCFG_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IF */ 195 #define SYSCFG_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-Bit Error Interrupt Flag */ 196 #define _SYSCFG_IF_RAMERR2B_SHIFT 17 /**< Shift value for SYSCFG_RAMERR2B */ 197 #define _SYSCFG_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for SYSCFG_RAMERR2B */ 198 #define _SYSCFG_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 199 #define SYSCFG_IF_RAMERR2B_DEFAULT (_SYSCFG_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IF */ 200 #define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM 1-Bit Error Interrupt Flag */ 201 #define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ 202 #define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ 203 #define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 204 #define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ 205 #define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM 2-Bit Error Interrupt Flag */ 206 #define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ 207 #define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ 208 #define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 209 #define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ 210 #define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM 1-Bit Error Interrupt Flag */ 211 #define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ 212 #define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ 213 #define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 214 #define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ 215 #define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM 2-Bit Error Interrupt Flag */ 216 #define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ 217 #define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ 218 #define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 219 #define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ 220 221 /* Bit fields for SYSCFG IEN */ 222 #define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ 223 #define _SYSCFG_IEN_MASK 0x3303000FUL /**< Mask for SYSCFG_IEN */ 224 #define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software interrupt 0 */ 225 #define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ 226 #define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ 227 #define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 228 #define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 229 #define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software interrupt 1 */ 230 #define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ 231 #define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ 232 #define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 233 #define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 234 #define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software interrupt 2 */ 235 #define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ 236 #define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ 237 #define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 238 #define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 239 #define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software interrupt 3 */ 240 #define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ 241 #define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ 242 #define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 243 #define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 244 #define SYSCFG_IEN_RAMERR1B (0x1UL << 16) /**< RAM 1-bit Error Interrupt Enable */ 245 #define _SYSCFG_IEN_RAMERR1B_SHIFT 16 /**< Shift value for SYSCFG_RAMERR1B */ 246 #define _SYSCFG_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for SYSCFG_RAMERR1B */ 247 #define _SYSCFG_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 248 #define SYSCFG_IEN_RAMERR1B_DEFAULT (_SYSCFG_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 249 #define SYSCFG_IEN_RAMERR2B (0x1UL << 17) /**< RAM 2-bit Error Interrupt Enable */ 250 #define _SYSCFG_IEN_RAMERR2B_SHIFT 17 /**< Shift value for SYSCFG_RAMERR2B */ 251 #define _SYSCFG_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for SYSCFG_RAMERR2B */ 252 #define _SYSCFG_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 253 #define SYSCFG_IEN_RAMERR2B_DEFAULT (_SYSCFG_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 254 #define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM 1-bit Error Interrupt Enable */ 255 #define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ 256 #define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ 257 #define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 258 #define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 259 #define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM 2-bit Error Interrupt Enable */ 260 #define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ 261 #define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ 262 #define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 263 #define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 264 #define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM 1-bit Error Interrupt Enable */ 265 #define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ 266 #define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ 267 #define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 268 #define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 269 #define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM 2-bit Error Interrupt Enable */ 270 #define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ 271 #define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ 272 #define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 273 #define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 274 275 /* Bit fields for SYSCFG CHIPREVHW */ 276 #define _SYSCFG_CHIPREVHW_RESETVALUE 0x00000C01UL /**< Default value for SYSCFG_CHIPREVHW */ 277 #define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ 278 #define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ 279 #define _SYSCFG_CHIPREVHW_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ 280 #define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ 281 #define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ 282 #define _SYSCFG_CHIPREVHW_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ 283 #define _SYSCFG_CHIPREVHW_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ 284 #define _SYSCFG_CHIPREVHW_FAMILY_DEFAULT 0x00000030UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ 285 #define SYSCFG_CHIPREVHW_FAMILY_DEFAULT (_SYSCFG_CHIPREVHW_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ 286 #define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ 287 #define _SYSCFG_CHIPREVHW_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ 288 #define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ 289 #define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ 290 291 /* Bit fields for SYSCFG CHIPREV */ 292 #define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ 293 #define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ 294 #define _SYSCFG_CHIPREV_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ 295 #define _SYSCFG_CHIPREV_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ 296 #define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ 297 #define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ 298 #define _SYSCFG_CHIPREV_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ 299 #define _SYSCFG_CHIPREV_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ 300 #define _SYSCFG_CHIPREV_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ 301 #define SYSCFG_CHIPREV_FAMILY_DEFAULT (_SYSCFG_CHIPREV_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ 302 #define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ 303 #define _SYSCFG_CHIPREV_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ 304 #define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ 305 #define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ 306 307 /* Bit fields for SYSCFG CFGSYSTIC */ 308 #define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ 309 #define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ 310 #define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ 311 #define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ 312 #define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ 313 #define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ 314 #define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ 315 316 /* Bit fields for SYSCFG CTRL */ 317 #define _SYSCFG_CTRL_RESETVALUE 0x00000021UL /**< Default value for SYSCFG_CTRL */ 318 #define _SYSCFG_CTRL_MASK 0x00000021UL /**< Mask for SYSCFG_CTRL */ 319 #define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ 320 #define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ 321 #define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ 322 #define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ 323 #define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ 324 #define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC Error Bus Fault Response Enable */ 325 #define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ 326 #define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ 327 #define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ 328 #define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ 329 330 /* Bit fields for SYSCFG DMEM0RETNCTRL */ 331 #define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ 332 #define _SYSCFG_DMEM0RETNCTRL_MASK 0x00000003UL /**< Mask for SYSCFG_DMEM0RETNCTRL */ 333 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ 334 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ 335 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ 336 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ 337 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_DMEM0RETNCTRL */ 338 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_DMEM0RETNCTRL */ 339 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ 340 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ 341 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_DMEM0RETNCTRL */ 342 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_DMEM0RETNCTRL */ 343 344 /* Bit fields for SYSCFG DMEM0ECCADDR */ 345 #define _SYSCFG_DMEM0ECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0ECCADDR */ 346 #define _SYSCFG_DMEM0ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_DMEM0ECCADDR */ 347 #define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_SHIFT 0 /**< Shift value for SYSCFG_DMEM0ECCADDR */ 348 #define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DMEM0ECCADDR */ 349 #define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCADDR */ 350 #define SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT (_SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCADDR*/ 351 352 /* Bit fields for SYSCFG DMEM0ECCCTRL */ 353 #define _SYSCFG_DMEM0ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0ECCCTRL */ 354 #define _SYSCFG_DMEM0ECCCTRL_MASK 0x00000003UL /**< Mask for SYSCFG_DMEM0ECCCTRL */ 355 #define SYSCFG_DMEM0ECCCTRL_RAMECCEN (0x1UL << 0) /**< RAM ECC Enable */ 356 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_RAMECCEN */ 357 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_RAMECCEN */ 358 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCCTRL */ 359 #define SYSCFG_DMEM0ECCCTRL_RAMECCEN_DEFAULT (_SYSCFG_DMEM0ECCCTRL_RAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCCTRL*/ 360 #define SYSCFG_DMEM0ECCCTRL_RAMECCEWEN (0x1UL << 1) /**< RAM ECC Error Writeback Enable */ 361 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_RAMECCEWEN */ 362 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_RAMECCEWEN */ 363 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCCTRL */ 364 #define SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT (_SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCCTRL*/ 365 366 /* Bit fields for SYSCFG RADIORAMRETNCTRL */ 367 #define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ 368 #define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ 369 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ 370 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ 371 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ 372 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ 373 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ 374 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ 375 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ 376 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ 377 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ 378 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ 379 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ 380 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ 381 #define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ 382 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ 383 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ 384 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ 385 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ 386 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ 387 #define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ 388 #define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ 389 #define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ 390 391 /* Bit fields for SYSCFG RADIOECCCTRL */ 392 #define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ 393 #define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ 394 #define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ 395 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ 396 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ 397 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ 398 #define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ 399 #define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ 400 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ 401 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ 402 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ 403 #define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ 404 #define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ 405 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ 406 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ 407 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ 408 #define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ 409 #define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ 410 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ 411 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ 412 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ 413 #define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ 414 415 /* Bit fields for SYSCFG SEQRAMECCADDR */ 416 #define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ 417 #define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ 418 #define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ 419 #define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ 420 #define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ 421 #define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ 422 423 /* Bit fields for SYSCFG FRCRAMECCADDR */ 424 #define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ 425 #define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ 426 #define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ 427 #define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ 428 #define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ 429 #define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ 430 431 /* Bit fields for SYSCFG ROOTDATA0 */ 432 #define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ 433 #define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ 434 #define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ 435 #define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ 436 #define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ 437 #define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ 438 439 /* Bit fields for SYSCFG ROOTDATA1 */ 440 #define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ 441 #define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ 442 #define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ 443 #define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ 444 #define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ 445 #define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ 446 447 /* Bit fields for SYSCFG ROOTLOCKSTATUS */ 448 #define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x011F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ 449 #define _SYSCFG_ROOTLOCKSTATUS_MASK 0x011F0117UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ 450 #define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ 451 #define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ 452 #define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ 453 #define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 454 #define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 455 #define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ 456 #define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ 457 #define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ 458 #define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 459 #define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 460 #define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ 461 #define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ 462 #define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ 463 #define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 464 #define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 465 #define SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK (0x1UL << 4) /**< Root Mode Lock */ 466 #define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_SHIFT 4 /**< Shift value for SYSCFG_ROOTMODELOCK */ 467 #define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_MASK 0x10UL /**< Bit mask for SYSCFG_ROOTMODELOCK */ 468 #define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 469 #define SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 470 #define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ 471 #define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ 472 #define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ 473 #define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 474 #define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 475 #define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 16) /**< User Invasive Debug Lock */ 476 #define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGLOCK */ 477 #define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ 478 #define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 479 #define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 480 #define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 17) /**< User Non-invasive Debug Lock */ 481 #define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERNIDLOCK */ 482 #define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ 483 #define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 484 #define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 485 #define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 18) /**< User Secure Invasive Debug Lock */ 486 #define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERSPIDLOCK */ 487 #define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ 488 #define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 489 #define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 490 #define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 19) /**< User Secure Non-invasive Debug Lock */ 491 #define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPNIDLOCK */ 492 #define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ 493 #define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 494 #define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 495 #define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 20) /**< User Debug Access Port Lock */ 496 #define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERDBGAPLOCK */ 497 #define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ 498 #define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 499 #define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 500 #define SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK (0x1UL << 24) /**< Radio Debug Lock */ 501 #define _SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_SHIFT 24 /**< Shift value for SYSCFG_RADIODBGLOCK */ 502 #define _SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_MASK 0x1000000UL /**< Bit mask for SYSCFG_RADIODBGLOCK */ 503 #define _SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ 504 #define SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ 505 506 /** @} End of group EFR32BG22_SYSCFG_BitFields */ 507 /** @} End of group EFR32BG22_SYSCFG */ 508 /**************************************************************************//** 509 * @defgroup EFR32BG22_SYSCFG_CFGNS SYSCFG_CFGNS 510 * @{ 511 * @brief EFR32BG22 SYSCFG_CFGNS Register Declaration. 512 *****************************************************************************/ 513 514 /** SYSCFG_CFGNS Register Declaration. */ 515 typedef struct { 516 uint32_t RESERVED0[7U]; /**< Reserved for future use */ 517 __IOM uint32_t CFGNSTCALIB; /**< Configure Non-secure Sys-Tick Cal. */ 518 uint32_t RESERVED1[376U]; /**< Reserved for future use */ 519 __IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */ 520 __IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */ 521 uint32_t RESERVED2[638U]; /**< Reserved for future use */ 522 uint32_t RESERVED3[7U]; /**< Reserved for future use */ 523 __IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-secure Sys-Tick Cal. */ 524 uint32_t RESERVED4[376U]; /**< Reserved for future use */ 525 __IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */ 526 __IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */ 527 uint32_t RESERVED5[638U]; /**< Reserved for future use */ 528 uint32_t RESERVED6[7U]; /**< Reserved for future use */ 529 __IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-secure Sys-Tick Cal. */ 530 uint32_t RESERVED7[376U]; /**< Reserved for future use */ 531 __IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */ 532 __IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */ 533 uint32_t RESERVED8[638U]; /**< Reserved for future use */ 534 uint32_t RESERVED9[7U]; /**< Reserved for future use */ 535 __IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-secure Sys-Tick Cal. */ 536 uint32_t RESERVED10[376U]; /**< Reserved for future use */ 537 __IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */ 538 __IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */ 539 } SYSCFG_CFGNS_TypeDef; 540 /** @} End of group EFR32BG22_SYSCFG_CFGNS */ 541 542 /**************************************************************************//** 543 * @addtogroup EFR32BG22_SYSCFG_CFGNS 544 * @{ 545 * @defgroup EFR32BG22_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields 546 * @{ 547 *****************************************************************************/ 548 549 /* Bit fields for SYSCFG CFGNSTCALIB */ 550 #define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */ 551 #define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */ 552 #define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */ 553 #define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */ 554 #define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ 555 #define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ 556 #define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */ 557 #define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */ 558 #define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */ 559 #define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ 560 #define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ 561 #define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */ 562 #define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */ 563 #define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */ 564 #define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ 565 #define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */ 566 #define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */ 567 #define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ 568 #define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */ 569 #define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */ 570 571 /* Bit fields for SYSCFG ROOTNSDATA0 */ 572 #define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */ 573 #define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */ 574 #define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ 575 #define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ 576 #define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */ 577 #define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */ 578 579 /* Bit fields for SYSCFG ROOTNSDATA1 */ 580 #define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */ 581 #define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */ 582 #define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ 583 #define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ 584 #define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */ 585 #define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */ 586 587 /** @} End of group EFR32BG22_SYSCFG_CFGNS_BitFields */ 588 /** @} End of group EFR32BG22_SYSCFG_CFGNS */ 589 /** @} End of group Parts */ 590 591 #endif /* EFR32BG22_SYSCFG_H */ 592
