1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG22 EMU register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG22_EMU_H 31 #define EFR32BG22_EMU_H 32 #define EMU_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG22_EMU EMU 40 * @{ 41 * @brief EFR32BG22 EMU Register Declaration. 42 *****************************************************************************/ 43 44 /** EMU Register Declaration. */ 45 typedef struct { 46 uint32_t RESERVED0[4U]; /**< Reserved for future use */ 47 __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ 48 uint32_t RESERVED1[3U]; /**< Reserved for future use */ 49 __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ 50 uint32_t RESERVED2[6U]; /**< Reserved for future use */ 51 __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ 52 __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ 53 uint32_t RESERVED3[7U]; /**< Reserved for future use */ 54 __IOM uint32_t LOCK; /**< EMU Configuration lock register */ 55 __IOM uint32_t IF; /**< Interrupt Flags */ 56 __IOM uint32_t IEN; /**< Interrupt Enables */ 57 __IOM uint32_t EM4CTRL; /**< EM4 Control */ 58 __IOM uint32_t CMD; /**< EMU Command register */ 59 __IOM uint32_t CTRL; /**< EMU Control register */ 60 __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ 61 uint32_t RESERVED4[2U]; /**< Reserved for future use */ 62 __IM uint32_t STATUS; /**< EMU Status register */ 63 __IM uint32_t TEMP; /**< Temperature */ 64 uint32_t RESERVED5[1U]; /**< Reserved for future use */ 65 __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ 66 __IM uint32_t RSTCAUSE; /**< Reset cause */ 67 uint32_t RESERVED6[2U]; /**< Reserved for future use */ 68 __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ 69 __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ 70 uint32_t RESERVED7[6U]; /**< Reserved for future use */ 71 uint32_t RESERVED8[1U]; /**< Reserved for future use */ 72 uint32_t RESERVED9[15U]; /**< Reserved for future use */ 73 __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ 74 __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ 75 uint32_t RESERVED10[958U]; /**< Reserved for future use */ 76 uint32_t RESERVED11[4U]; /**< Reserved for future use */ 77 __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ 78 uint32_t RESERVED12[3U]; /**< Reserved for future use */ 79 __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ 80 uint32_t RESERVED13[6U]; /**< Reserved for future use */ 81 __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ 82 __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ 83 uint32_t RESERVED14[7U]; /**< Reserved for future use */ 84 __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ 85 __IOM uint32_t IF_SET; /**< Interrupt Flags */ 86 __IOM uint32_t IEN_SET; /**< Interrupt Enables */ 87 __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ 88 __IOM uint32_t CMD_SET; /**< EMU Command register */ 89 __IOM uint32_t CTRL_SET; /**< EMU Control register */ 90 __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ 91 uint32_t RESERVED15[2U]; /**< Reserved for future use */ 92 __IM uint32_t STATUS_SET; /**< EMU Status register */ 93 __IM uint32_t TEMP_SET; /**< Temperature */ 94 uint32_t RESERVED16[1U]; /**< Reserved for future use */ 95 __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ 96 __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ 97 uint32_t RESERVED17[2U]; /**< Reserved for future use */ 98 __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ 99 __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ 100 uint32_t RESERVED18[6U]; /**< Reserved for future use */ 101 uint32_t RESERVED19[1U]; /**< Reserved for future use */ 102 uint32_t RESERVED20[15U]; /**< Reserved for future use */ 103 __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ 104 __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ 105 uint32_t RESERVED21[958U]; /**< Reserved for future use */ 106 uint32_t RESERVED22[4U]; /**< Reserved for future use */ 107 __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ 108 uint32_t RESERVED23[3U]; /**< Reserved for future use */ 109 __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ 110 uint32_t RESERVED24[6U]; /**< Reserved for future use */ 111 __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ 112 __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ 113 uint32_t RESERVED25[7U]; /**< Reserved for future use */ 114 __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ 115 __IOM uint32_t IF_CLR; /**< Interrupt Flags */ 116 __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ 117 __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ 118 __IOM uint32_t CMD_CLR; /**< EMU Command register */ 119 __IOM uint32_t CTRL_CLR; /**< EMU Control register */ 120 __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ 121 uint32_t RESERVED26[2U]; /**< Reserved for future use */ 122 __IM uint32_t STATUS_CLR; /**< EMU Status register */ 123 __IM uint32_t TEMP_CLR; /**< Temperature */ 124 uint32_t RESERVED27[1U]; /**< Reserved for future use */ 125 __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ 126 __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ 127 uint32_t RESERVED28[2U]; /**< Reserved for future use */ 128 __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ 129 __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ 130 uint32_t RESERVED29[6U]; /**< Reserved for future use */ 131 uint32_t RESERVED30[1U]; /**< Reserved for future use */ 132 uint32_t RESERVED31[15U]; /**< Reserved for future use */ 133 __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ 134 __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ 135 uint32_t RESERVED32[958U]; /**< Reserved for future use */ 136 uint32_t RESERVED33[4U]; /**< Reserved for future use */ 137 __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ 138 uint32_t RESERVED34[3U]; /**< Reserved for future use */ 139 __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ 140 uint32_t RESERVED35[6U]; /**< Reserved for future use */ 141 __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ 142 __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ 143 uint32_t RESERVED36[7U]; /**< Reserved for future use */ 144 __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ 145 __IOM uint32_t IF_TGL; /**< Interrupt Flags */ 146 __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ 147 __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ 148 __IOM uint32_t CMD_TGL; /**< EMU Command register */ 149 __IOM uint32_t CTRL_TGL; /**< EMU Control register */ 150 __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ 151 uint32_t RESERVED37[2U]; /**< Reserved for future use */ 152 __IM uint32_t STATUS_TGL; /**< EMU Status register */ 153 __IM uint32_t TEMP_TGL; /**< Temperature */ 154 uint32_t RESERVED38[1U]; /**< Reserved for future use */ 155 __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ 156 __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ 157 uint32_t RESERVED39[2U]; /**< Reserved for future use */ 158 __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ 159 __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ 160 uint32_t RESERVED40[6U]; /**< Reserved for future use */ 161 uint32_t RESERVED41[1U]; /**< Reserved for future use */ 162 uint32_t RESERVED42[15U]; /**< Reserved for future use */ 163 __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ 164 __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ 165 } EMU_TypeDef; 166 /** @} End of group EFR32BG22_EMU */ 167 168 /**************************************************************************//** 169 * @addtogroup EFR32BG22_EMU 170 * @{ 171 * @defgroup EFR32BG22_EMU_BitFields EMU Bit Fields 172 * @{ 173 *****************************************************************************/ 174 175 /* Bit fields for EMU DECBOD */ 176 #define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ 177 #define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ 178 #define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ 179 #define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ 180 #define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ 181 #define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ 182 #define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ 183 #define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ 184 #define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ 185 #define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ 186 #define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ 187 #define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ 188 #define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ 189 #define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ 190 #define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ 191 #define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ 192 #define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ 193 #define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ 194 #define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ 195 #define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ 196 #define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ 197 #define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ 198 199 /* Bit fields for EMU BOD3SENSE */ 200 #define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ 201 #define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ 202 #define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ 203 #define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ 204 #define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ 205 #define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ 206 #define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ 207 #define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ 208 #define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ 209 #define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ 210 #define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ 211 #define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ 212 #define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ 213 #define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ 214 #define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ 215 #define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ 216 #define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ 217 218 /* Bit fields for EMU VREGVDDCMPCTRL */ 219 #define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ 220 #define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ 221 #define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ 222 #define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ 223 #define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ 224 #define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ 225 #define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ 226 #define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ 227 #define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ 228 #define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ 229 #define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ 230 231 /* Bit fields for EMU PD1PARETCTRL */ 232 #define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ 233 #define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ 234 #define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ 235 #define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ 236 #define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ 237 #define _EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN 0x00000000UL /**< Mode RETAIN for EMU_PD1PARETCTRL */ 238 #define _EMU_PD1PARETCTRL_PD1PARETDIS_NORETAIN 0x00000001UL /**< Mode NORETAIN for EMU_PD1PARETCTRL */ 239 #define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ 240 #define EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN << 0) /**< Shifted mode RETAIN for EMU_PD1PARETCTRL */ 241 #define EMU_PD1PARETCTRL_PD1PARETDIS_NORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_NORETAIN << 0) /**< Shifted mode NORETAIN for EMU_PD1PARETCTRL */ 242 243 /* Bit fields for EMU LOCK */ 244 #define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ 245 #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ 246 #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ 247 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ 248 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ 249 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ 250 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ 251 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ 252 253 /* Bit fields for EMU IF */ 254 #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ 255 #define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */ 256 #define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ 257 #define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ 258 #define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ 259 #define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 260 #define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ 261 #define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ 262 #define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ 263 #define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ 264 #define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 265 #define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ 266 #define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ 267 #define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 268 #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 269 #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 270 #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ 271 #define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ 272 #define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ 273 #define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ 274 #define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 275 #define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ 276 #define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ 277 #define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ 278 #define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ 279 #define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 280 #define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ 281 #define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ 282 #define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 283 #define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 284 #define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 285 #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ 286 #define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ 287 #define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 288 #define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 289 #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 290 #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ 291 #define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ 292 #define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 293 #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 294 #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 295 #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ 296 297 /* Bit fields for EMU IEN */ 298 #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ 299 #define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */ 300 #define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ 301 #define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ 302 #define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ 303 #define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 304 #define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ 305 #define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ 306 #define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ 307 #define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ 308 #define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 309 #define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ 310 #define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ 311 #define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 312 #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 313 #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 314 #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ 315 #define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ 316 #define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ 317 #define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ 318 #define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 319 #define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ 320 #define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ 321 #define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ 322 #define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ 323 #define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 324 #define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ 325 #define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ 326 #define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 327 #define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 328 #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 329 #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ 330 #define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ 331 #define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 332 #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 333 #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 334 #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ 335 #define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ 336 #define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 337 #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 338 #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 339 #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ 340 341 /* Bit fields for EMU EM4CTRL */ 342 #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ 343 #define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ 344 #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ 345 #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ 346 #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 347 #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 348 #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ 349 #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ 350 #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 351 #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ 352 #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ 353 #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ 354 #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 355 #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ 356 #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ 357 #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ 358 #define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ 359 #define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ 360 #define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ 361 #define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 362 #define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 363 364 /* Bit fields for EMU CMD */ 365 #define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ 366 #define _EMU_CMD_MASK 0x00020E12UL /**< Mask for EMU_CMD */ 367 #define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ 368 #define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ 369 #define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ 370 #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 371 #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ 372 #define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ 373 #define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ 374 #define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ 375 #define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 376 #define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ 377 #define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ 378 #define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ 379 #define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ 380 #define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 381 #define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ 382 #define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ 383 #define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ 384 #define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ 385 #define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 386 #define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ 387 #define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ 388 #define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ 389 #define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ 390 #define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 391 #define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ 392 393 /* Bit fields for EMU CTRL */ 394 #define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */ 395 #define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */ 396 #define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ 397 #define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ 398 #define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ 399 #define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 400 #define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ 401 #define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ 402 #define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ 403 #define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ 404 #define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 405 #define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ 406 #define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ 407 #define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ 408 #define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ 409 #define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ 410 #define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ 411 #define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ 412 #define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ 413 #define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ 414 #define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ 415 #define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ 416 #define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ 417 #define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ 418 #define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ 419 #define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ 420 #define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ 421 #define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ 422 #define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ 423 #define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 424 #define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ 425 #define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ 426 #define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ 427 #define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ 428 #define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 429 #define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ 430 #define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ 431 #define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ 432 #define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ 433 #define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 434 #define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ 435 #define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ 436 #define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ 437 #define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ 438 #define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 439 #define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ 440 441 /* Bit fields for EMU TEMPLIMITS */ 442 #define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ 443 #define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ 444 #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ 445 #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ 446 #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ 447 #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ 448 #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ 449 #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ 450 #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ 451 #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ 452 453 /* Bit fields for EMU STATUS */ 454 #define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ 455 #define _EMU_STATUS_MASK 0xFF0054FFUL /**< Mask for EMU_STATUS */ 456 #define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ 457 #define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ 458 #define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ 459 #define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 460 #define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ 461 #define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ 462 #define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ 463 #define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ 464 #define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ 465 #define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ 466 #define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ 467 #define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ 468 #define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 469 #define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ 470 #define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ 471 #define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ 472 #define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ 473 #define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 474 #define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ 475 #define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ 476 #define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ 477 #define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ 478 #define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 479 #define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ 480 #define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ 481 #define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ 482 #define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ 483 #define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 484 #define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ 485 #define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ 486 #define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ 487 #define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ 488 #define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 489 #define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ 490 #define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ 491 #define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ 492 #define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ 493 #define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ 494 #define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ 495 #define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ 496 #define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ 497 #define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ 498 #define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ 499 #define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ 500 #define EMU_STATUS_RACACTIVE (0x1UL << 10) /**< RAC active */ 501 #define _EMU_STATUS_RACACTIVE_SHIFT 10 /**< Shift value for EMU_RACACTIVE */ 502 #define _EMU_STATUS_RACACTIVE_MASK 0x400UL /**< Bit mask for EMU_RACACTIVE */ 503 #define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 504 #define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ 505 #define EMU_STATUS_EM4IORET (0x1UL << 12) /**< EM4 IO retention status */ 506 #define _EMU_STATUS_EM4IORET_SHIFT 12 /**< Shift value for EMU_EM4IORET */ 507 #define _EMU_STATUS_EM4IORET_MASK 0x1000UL /**< Bit mask for EMU_EM4IORET */ 508 #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 509 #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ 510 #define EMU_STATUS_EM2ENTERED (0x1UL << 14) /**< EM2 entered */ 511 #define _EMU_STATUS_EM2ENTERED_SHIFT 14 /**< Shift value for EMU_EM2ENTERED */ 512 #define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL /**< Bit mask for EMU_EM2ENTERED */ 513 #define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 514 #define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_STATUS */ 515 516 /* Bit fields for EMU TEMP */ 517 #define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ 518 #define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ 519 #define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ 520 #define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ 521 #define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ 522 #define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ 523 #define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ 524 #define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ 525 #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ 526 #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ 527 #define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ 528 #define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ 529 #define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ 530 #define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ 531 532 /* Bit fields for EMU RSTCTRL */ 533 #define _EMU_RSTCTRL_RESETVALUE 0x40010407UL /**< Default value for EMU_RSTCTRL */ 534 #define _EMU_RSTCTRL_MASK 0xC001C5CFUL /**< Mask for EMU_RSTCTRL */ 535 #define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ 536 #define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ 537 #define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ 538 #define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ 539 #define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 540 #define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 541 #define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 542 #define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 543 #define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 544 #define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ 545 #define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ 546 #define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ 547 #define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ 548 #define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 549 #define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 550 #define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 551 #define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 552 #define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 553 #define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ 554 #define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ 555 #define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ 556 #define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ 557 #define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 558 #define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 559 #define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 560 #define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 561 #define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 562 #define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ 563 #define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ 564 #define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ 565 #define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ 566 #define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 567 #define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 568 #define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 569 #define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 570 #define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 571 #define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ 572 #define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ 573 #define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ 574 #define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ 575 #define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 576 #define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 577 #define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 578 #define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 579 #define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 580 #define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ 581 #define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ 582 #define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ 583 #define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ 584 #define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 585 #define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 586 #define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 587 #define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 588 #define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 589 #define EMU_RSTCTRL_DCIRMODE (0x1UL << 16) /**< DCI System reset */ 590 #define _EMU_RSTCTRL_DCIRMODE_SHIFT 16 /**< Shift value for EMU_DCIRMODE */ 591 #define _EMU_RSTCTRL_DCIRMODE_MASK 0x10000UL /**< Bit mask for EMU_DCIRMODE */ 592 #define _EMU_RSTCTRL_DCIRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ 593 #define _EMU_RSTCTRL_DCIRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 594 #define _EMU_RSTCTRL_DCIRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 595 #define EMU_RSTCTRL_DCIRMODE_DEFAULT (_EMU_RSTCTRL_DCIRMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 596 #define EMU_RSTCTRL_DCIRMODE_DISABLED (_EMU_RSTCTRL_DCIRMODE_DISABLED << 16) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 597 #define EMU_RSTCTRL_DCIRMODE_ENABLED (_EMU_RSTCTRL_DCIRMODE_ENABLED << 16) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 598 599 /* Bit fields for EMU RSTCAUSE */ 600 #define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ 601 #define _EMU_RSTCAUSE_MASK 0x8001FFFFUL /**< Mask for EMU_RSTCAUSE */ 602 #define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ 603 #define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ 604 #define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ 605 #define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 606 #define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 607 #define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ 608 #define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ 609 #define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ 610 #define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 611 #define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 612 #define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ 613 #define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ 614 #define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ 615 #define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 616 #define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 617 #define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ 618 #define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ 619 #define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ 620 #define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 621 #define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 622 #define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ 623 #define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ 624 #define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ 625 #define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 626 #define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 627 #define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ 628 #define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ 629 #define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ 630 #define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 631 #define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 632 #define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ 633 #define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ 634 #define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ 635 #define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 636 #define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 637 #define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ 638 #define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ 639 #define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ 640 #define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 641 #define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 642 #define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ 643 #define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ 644 #define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ 645 #define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 646 #define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 647 #define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ 648 #define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ 649 #define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ 650 #define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 651 #define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 652 #define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ 653 #define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ 654 #define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ 655 #define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 656 #define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 657 #define EMU_RSTCAUSE_DCI (0x1UL << 16) /**< DCI reset */ 658 #define _EMU_RSTCAUSE_DCI_SHIFT 16 /**< Shift value for EMU_DCI */ 659 #define _EMU_RSTCAUSE_DCI_MASK 0x10000UL /**< Bit mask for EMU_DCI */ 660 #define _EMU_RSTCAUSE_DCI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 661 #define EMU_RSTCAUSE_DCI_DEFAULT (_EMU_RSTCAUSE_DCI_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 662 #define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ 663 #define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ 664 #define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ 665 #define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 666 #define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 667 668 /* Bit fields for EMU DGIF */ 669 #define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ 670 #define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ 671 #define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ 672 #define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ 673 #define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ 674 #define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ 675 #define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ 676 #define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ 677 #define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ 678 #define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ 679 #define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ 680 #define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ 681 #define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ 682 #define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ 683 #define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ 684 #define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ 685 #define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ 686 #define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ 687 #define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ 688 #define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ 689 #define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ 690 #define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ 691 692 /* Bit fields for EMU DGIEN */ 693 #define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ 694 #define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ 695 #define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ 696 #define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ 697 #define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ 698 #define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ 699 #define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ 700 #define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ 701 #define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ 702 #define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ 703 #define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ 704 #define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ 705 #define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ 706 #define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ 707 #define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ 708 #define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ 709 #define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ 710 #define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ 711 #define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ 712 #define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ 713 #define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ 714 #define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ 715 716 /* Bit fields for EMU EFPIF */ 717 #define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ 718 #define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ 719 #define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ 720 #define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ 721 #define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ 722 #define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ 723 #define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ 724 725 /* Bit fields for EMU EFPIEN */ 726 #define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ 727 #define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ 728 #define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ 729 #define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ 730 #define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ 731 #define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ 732 #define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ 733 734 /** @} End of group EFR32BG22_EMU_BitFields */ 735 /** @} End of group EFR32BG22_EMU */ 736 /** @} End of group Parts */ 737 738 #endif /* EFR32BG22_EMU_H */ 739
