1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG22 AMUXCP register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG22_AMUXCP_H 31 #define EFR32BG22_AMUXCP_H 32 #define AMUXCP_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG22_AMUXCP AMUXCP 40 * @{ 41 * @brief EFR32BG22 AMUXCP Register Declaration. 42 *****************************************************************************/ 43 44 /** AMUXCP Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IPVERSION */ 47 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 48 __IOM uint32_t CTRL; /**< Control */ 49 __IM uint32_t STATUS; /**< Status */ 50 __IOM uint32_t TEST; /**< Test */ 51 __IOM uint32_t TRIM; /**< Trim */ 52 uint32_t RESERVED1[1018U]; /**< Reserved for future use */ 53 __IM uint32_t IPVERSION_SET; /**< IPVERSION */ 54 uint32_t RESERVED2[1U]; /**< Reserved for future use */ 55 __IOM uint32_t CTRL_SET; /**< Control */ 56 __IM uint32_t STATUS_SET; /**< Status */ 57 __IOM uint32_t TEST_SET; /**< Test */ 58 __IOM uint32_t TRIM_SET; /**< Trim */ 59 uint32_t RESERVED3[1018U]; /**< Reserved for future use */ 60 __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ 61 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 62 __IOM uint32_t CTRL_CLR; /**< Control */ 63 __IM uint32_t STATUS_CLR; /**< Status */ 64 __IOM uint32_t TEST_CLR; /**< Test */ 65 __IOM uint32_t TRIM_CLR; /**< Trim */ 66 uint32_t RESERVED5[1018U]; /**< Reserved for future use */ 67 __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ 68 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 69 __IOM uint32_t CTRL_TGL; /**< Control */ 70 __IM uint32_t STATUS_TGL; /**< Status */ 71 __IOM uint32_t TEST_TGL; /**< Test */ 72 __IOM uint32_t TRIM_TGL; /**< Trim */ 73 } AMUXCP_TypeDef; 74 /** @} End of group EFR32BG22_AMUXCP */ 75 76 /**************************************************************************//** 77 * @addtogroup EFR32BG22_AMUXCP 78 * @{ 79 * @defgroup EFR32BG22_AMUXCP_BitFields AMUXCP Bit Fields 80 * @{ 81 *****************************************************************************/ 82 83 /* Bit fields for AMUXCP IPVERSION */ 84 #define _AMUXCP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for AMUXCP_IPVERSION */ 85 #define _AMUXCP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for AMUXCP_IPVERSION */ 86 #define _AMUXCP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for AMUXCP_IPVERSION */ 87 #define _AMUXCP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for AMUXCP_IPVERSION */ 88 #define _AMUXCP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_IPVERSION */ 89 #define AMUXCP_IPVERSION_IPVERSION_DEFAULT (_AMUXCP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_IPVERSION */ 90 91 /* Bit fields for AMUXCP CTRL */ 92 #define _AMUXCP_CTRL_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_CTRL */ 93 #define _AMUXCP_CTRL_MASK 0x00000033UL /**< Mask for AMUXCP_CTRL */ 94 #define AMUXCP_CTRL_FORCEHP (0x1UL << 0) /**< Force High Power */ 95 #define _AMUXCP_CTRL_FORCEHP_SHIFT 0 /**< Shift value for AMUXCP_FORCEHP */ 96 #define _AMUXCP_CTRL_FORCEHP_MASK 0x1UL /**< Bit mask for AMUXCP_FORCEHP */ 97 #define _AMUXCP_CTRL_FORCEHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */ 98 #define AMUXCP_CTRL_FORCEHP_DEFAULT (_AMUXCP_CTRL_FORCEHP_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_CTRL */ 99 #define AMUXCP_CTRL_FORCELP (0x1UL << 1) /**< Force Low Power */ 100 #define _AMUXCP_CTRL_FORCELP_SHIFT 1 /**< Shift value for AMUXCP_FORCELP */ 101 #define _AMUXCP_CTRL_FORCELP_MASK 0x2UL /**< Bit mask for AMUXCP_FORCELP */ 102 #define _AMUXCP_CTRL_FORCELP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */ 103 #define AMUXCP_CTRL_FORCELP_DEFAULT (_AMUXCP_CTRL_FORCELP_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_CTRL */ 104 #define AMUXCP_CTRL_FORCERUN (0x1UL << 4) /**< Force run */ 105 #define _AMUXCP_CTRL_FORCERUN_SHIFT 4 /**< Shift value for AMUXCP_FORCERUN */ 106 #define _AMUXCP_CTRL_FORCERUN_MASK 0x10UL /**< Bit mask for AMUXCP_FORCERUN */ 107 #define _AMUXCP_CTRL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */ 108 #define AMUXCP_CTRL_FORCERUN_DEFAULT (_AMUXCP_CTRL_FORCERUN_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_CTRL */ 109 #define AMUXCP_CTRL_FORCESTOP (0x1UL << 5) /**< Force stop */ 110 #define _AMUXCP_CTRL_FORCESTOP_SHIFT 5 /**< Shift value for AMUXCP_FORCESTOP */ 111 #define _AMUXCP_CTRL_FORCESTOP_MASK 0x20UL /**< Bit mask for AMUXCP_FORCESTOP */ 112 #define _AMUXCP_CTRL_FORCESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */ 113 #define AMUXCP_CTRL_FORCESTOP_DEFAULT (_AMUXCP_CTRL_FORCESTOP_DEFAULT << 5) /**< Shifted mode DEFAULT for AMUXCP_CTRL */ 114 115 /* Bit fields for AMUXCP STATUS */ 116 #define _AMUXCP_STATUS_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_STATUS */ 117 #define _AMUXCP_STATUS_MASK 0x00000003UL /**< Mask for AMUXCP_STATUS */ 118 #define AMUXCP_STATUS_RUN (0x1UL << 0) /**< running */ 119 #define _AMUXCP_STATUS_RUN_SHIFT 0 /**< Shift value for AMUXCP_RUN */ 120 #define _AMUXCP_STATUS_RUN_MASK 0x1UL /**< Bit mask for AMUXCP_RUN */ 121 #define _AMUXCP_STATUS_RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_STATUS */ 122 #define AMUXCP_STATUS_RUN_DEFAULT (_AMUXCP_STATUS_RUN_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_STATUS */ 123 #define AMUXCP_STATUS_HICAP (0x1UL << 1) /**< high cap */ 124 #define _AMUXCP_STATUS_HICAP_SHIFT 1 /**< Shift value for AMUXCP_HICAP */ 125 #define _AMUXCP_STATUS_HICAP_MASK 0x2UL /**< Bit mask for AMUXCP_HICAP */ 126 #define _AMUXCP_STATUS_HICAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_STATUS */ 127 #define AMUXCP_STATUS_HICAP_DEFAULT (_AMUXCP_STATUS_HICAP_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_STATUS */ 128 129 /* Bit fields for AMUXCP TEST */ 130 #define _AMUXCP_TEST_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_TEST */ 131 #define _AMUXCP_TEST_MASK 0x80003313UL /**< Mask for AMUXCP_TEST */ 132 #define AMUXCP_TEST_SYNCCLK (0x1UL << 0) /**< Sync Clock */ 133 #define _AMUXCP_TEST_SYNCCLK_SHIFT 0 /**< Shift value for AMUXCP_SYNCCLK */ 134 #define _AMUXCP_TEST_SYNCCLK_MASK 0x1UL /**< Bit mask for AMUXCP_SYNCCLK */ 135 #define _AMUXCP_TEST_SYNCCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ 136 #define AMUXCP_TEST_SYNCCLK_DEFAULT (_AMUXCP_TEST_SYNCCLK_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_TEST */ 137 #define AMUXCP_TEST_SYNCMODE (0x1UL << 1) /**< Sync Mode */ 138 #define _AMUXCP_TEST_SYNCMODE_SHIFT 1 /**< Shift value for AMUXCP_SYNCMODE */ 139 #define _AMUXCP_TEST_SYNCMODE_MASK 0x2UL /**< Bit mask for AMUXCP_SYNCMODE */ 140 #define _AMUXCP_TEST_SYNCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ 141 #define AMUXCP_TEST_SYNCMODE_DEFAULT (_AMUXCP_TEST_SYNCMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_TEST */ 142 #define AMUXCP_TEST_FORCEREQUEST (0x1UL << 4) /**< Force Request */ 143 #define _AMUXCP_TEST_FORCEREQUEST_SHIFT 4 /**< Shift value for AMUXCP_FORCEREQUEST */ 144 #define _AMUXCP_TEST_FORCEREQUEST_MASK 0x10UL /**< Bit mask for AMUXCP_FORCEREQUEST */ 145 #define _AMUXCP_TEST_FORCEREQUEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ 146 #define AMUXCP_TEST_FORCEREQUEST_DEFAULT (_AMUXCP_TEST_FORCEREQUEST_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_TEST */ 147 #define AMUXCP_TEST_FORCEHICAP (0x1UL << 8) /**< Force high capacitance driver */ 148 #define _AMUXCP_TEST_FORCEHICAP_SHIFT 8 /**< Shift value for AMUXCP_FORCEHICAP */ 149 #define _AMUXCP_TEST_FORCEHICAP_MASK 0x100UL /**< Bit mask for AMUXCP_FORCEHICAP */ 150 #define _AMUXCP_TEST_FORCEHICAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ 151 #define AMUXCP_TEST_FORCEHICAP_DEFAULT (_AMUXCP_TEST_FORCEHICAP_DEFAULT << 8) /**< Shifted mode DEFAULT for AMUXCP_TEST */ 152 #define AMUXCP_TEST_FORCELOCAP (0x1UL << 9) /**< Force low capacitance driver */ 153 #define _AMUXCP_TEST_FORCELOCAP_SHIFT 9 /**< Shift value for AMUXCP_FORCELOCAP */ 154 #define _AMUXCP_TEST_FORCELOCAP_MASK 0x200UL /**< Bit mask for AMUXCP_FORCELOCAP */ 155 #define _AMUXCP_TEST_FORCELOCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ 156 #define AMUXCP_TEST_FORCELOCAP_DEFAULT (_AMUXCP_TEST_FORCELOCAP_DEFAULT << 9) /**< Shifted mode DEFAULT for AMUXCP_TEST */ 157 #define AMUXCP_TEST_FORCEBOOSTON (0x1UL << 12) /**< Force Boost On */ 158 #define _AMUXCP_TEST_FORCEBOOSTON_SHIFT 12 /**< Shift value for AMUXCP_FORCEBOOSTON */ 159 #define _AMUXCP_TEST_FORCEBOOSTON_MASK 0x1000UL /**< Bit mask for AMUXCP_FORCEBOOSTON */ 160 #define _AMUXCP_TEST_FORCEBOOSTON_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ 161 #define AMUXCP_TEST_FORCEBOOSTON_DEFAULT (_AMUXCP_TEST_FORCEBOOSTON_DEFAULT << 12) /**< Shifted mode DEFAULT for AMUXCP_TEST */ 162 #define AMUXCP_TEST_FORCEBOOSTOFF (0x1UL << 13) /**< Force Boost Off */ 163 #define _AMUXCP_TEST_FORCEBOOSTOFF_SHIFT 13 /**< Shift value for AMUXCP_FORCEBOOSTOFF */ 164 #define _AMUXCP_TEST_FORCEBOOSTOFF_MASK 0x2000UL /**< Bit mask for AMUXCP_FORCEBOOSTOFF */ 165 #define _AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ 166 #define AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT (_AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT << 13) /**< Shifted mode DEFAULT for AMUXCP_TEST */ 167 #define AMUXCP_TEST_STATUSEN (0x1UL << 31) /**< Enable write to status bits */ 168 #define _AMUXCP_TEST_STATUSEN_SHIFT 31 /**< Shift value for AMUXCP_STATUSEN */ 169 #define _AMUXCP_TEST_STATUSEN_MASK 0x80000000UL /**< Bit mask for AMUXCP_STATUSEN */ 170 #define _AMUXCP_TEST_STATUSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ 171 #define AMUXCP_TEST_STATUSEN_DEFAULT (_AMUXCP_TEST_STATUSEN_DEFAULT << 31) /**< Shifted mode DEFAULT for AMUXCP_TEST */ 172 173 /* Bit fields for AMUXCP TRIM */ 174 #define _AMUXCP_TRIM_RESETVALUE 0x77E44AA1UL /**< Default value for AMUXCP_TRIM */ 175 #define _AMUXCP_TRIM_MASK 0x77FFEFFFUL /**< Mask for AMUXCP_TRIM */ 176 #define _AMUXCP_TRIM_WARMUPTIME_SHIFT 0 /**< Shift value for AMUXCP_WARMUPTIME */ 177 #define _AMUXCP_TRIM_WARMUPTIME_MASK 0x3UL /**< Bit mask for AMUXCP_WARMUPTIME */ 178 #define _AMUXCP_TRIM_WARMUPTIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ 179 #define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 0x00000000UL /**< Mode WUCYCLES72 for AMUXCP_TRIM */ 180 #define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 0x00000001UL /**< Mode WUCYCLES96 for AMUXCP_TRIM */ 181 #define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 0x00000002UL /**< Mode WUCYCLES128 for AMUXCP_TRIM */ 182 #define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 0x00000003UL /**< Mode WUCYCLES160 for AMUXCP_TRIM */ 183 #define AMUXCP_TRIM_WARMUPTIME_DEFAULT (_AMUXCP_TRIM_WARMUPTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 184 #define AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 << 0) /**< Shifted mode WUCYCLES72 for AMUXCP_TRIM */ 185 #define AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 << 0) /**< Shifted mode WUCYCLES96 for AMUXCP_TRIM */ 186 #define AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 << 0) /**< Shifted mode WUCYCLES128 for AMUXCP_TRIM */ 187 #define AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 << 0) /**< Shifted mode WUCYCLES160 for AMUXCP_TRIM */ 188 #define AMUXCP_TRIM_FLOATVDDCPLO (0x1UL << 2) /**< Float VDDCP Low Power */ 189 #define _AMUXCP_TRIM_FLOATVDDCPLO_SHIFT 2 /**< Shift value for AMUXCP_FLOATVDDCPLO */ 190 #define _AMUXCP_TRIM_FLOATVDDCPLO_MASK 0x4UL /**< Bit mask for AMUXCP_FLOATVDDCPLO */ 191 #define _AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ 192 #define AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT (_AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT << 2) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 193 #define AMUXCP_TRIM_FLOATVDDCPHI (0x1UL << 3) /**< Float VDDCP High Power */ 194 #define _AMUXCP_TRIM_FLOATVDDCPHI_SHIFT 3 /**< Shift value for AMUXCP_FLOATVDDCPHI */ 195 #define _AMUXCP_TRIM_FLOATVDDCPHI_MASK 0x8UL /**< Bit mask for AMUXCP_FLOATVDDCPHI */ 196 #define _AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ 197 #define AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT (_AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT << 3) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 198 #define AMUXCP_TRIM_BYPASSDIV2LO (0x1UL << 4) /**< Bypass Div2 Low Power */ 199 #define _AMUXCP_TRIM_BYPASSDIV2LO_SHIFT 4 /**< Shift value for AMUXCP_BYPASSDIV2LO */ 200 #define _AMUXCP_TRIM_BYPASSDIV2LO_MASK 0x10UL /**< Bit mask for AMUXCP_BYPASSDIV2LO */ 201 #define _AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ 202 #define AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT (_AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 203 #define AMUXCP_TRIM_BYPASSDIV2HI (0x1UL << 5) /**< Bypass Div2 High Power */ 204 #define _AMUXCP_TRIM_BYPASSDIV2HI_SHIFT 5 /**< Shift value for AMUXCP_BYPASSDIV2HI */ 205 #define _AMUXCP_TRIM_BYPASSDIV2HI_MASK 0x20UL /**< Bit mask for AMUXCP_BYPASSDIV2HI */ 206 #define _AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ 207 #define AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT (_AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT << 5) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 208 #define AMUXCP_TRIM_BUMP0P5XLO (0x1UL << 6) /**< Bump 0.5X Low Power */ 209 #define _AMUXCP_TRIM_BUMP0P5XLO_SHIFT 6 /**< Shift value for AMUXCP_BUMP0P5XLO */ 210 #define _AMUXCP_TRIM_BUMP0P5XLO_MASK 0x40UL /**< Bit mask for AMUXCP_BUMP0P5XLO */ 211 #define _AMUXCP_TRIM_BUMP0P5XLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ 212 #define AMUXCP_TRIM_BUMP0P5XLO_DEFAULT (_AMUXCP_TRIM_BUMP0P5XLO_DEFAULT << 6) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 213 #define AMUXCP_TRIM_BUMP0P5XHI (0x1UL << 7) /**< Bump 0.5X High Power */ 214 #define _AMUXCP_TRIM_BUMP0P5XHI_SHIFT 7 /**< Shift value for AMUXCP_BUMP0P5XHI */ 215 #define _AMUXCP_TRIM_BUMP0P5XHI_MASK 0x80UL /**< Bit mask for AMUXCP_BUMP0P5XHI */ 216 #define _AMUXCP_TRIM_BUMP0P5XHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ 217 #define AMUXCP_TRIM_BUMP0P5XHI_DEFAULT (_AMUXCP_TRIM_BUMP0P5XHI_DEFAULT << 7) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 218 #define AMUXCP_TRIM_BIAS2XLO (0x1UL << 8) /**< Bias 2x Low Power */ 219 #define _AMUXCP_TRIM_BIAS2XLO_SHIFT 8 /**< Shift value for AMUXCP_BIAS2XLO */ 220 #define _AMUXCP_TRIM_BIAS2XLO_MASK 0x100UL /**< Bit mask for AMUXCP_BIAS2XLO */ 221 #define _AMUXCP_TRIM_BIAS2XLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ 222 #define AMUXCP_TRIM_BIAS2XLO_DEFAULT (_AMUXCP_TRIM_BIAS2XLO_DEFAULT << 8) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 223 #define AMUXCP_TRIM_BIAS2XHI (0x1UL << 9) /**< Bias 2x High Power */ 224 #define _AMUXCP_TRIM_BIAS2XHI_SHIFT 9 /**< Shift value for AMUXCP_BIAS2XHI */ 225 #define _AMUXCP_TRIM_BIAS2XHI_MASK 0x200UL /**< Bit mask for AMUXCP_BIAS2XHI */ 226 #define _AMUXCP_TRIM_BIAS2XHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ 227 #define AMUXCP_TRIM_BIAS2XHI_DEFAULT (_AMUXCP_TRIM_BIAS2XHI_DEFAULT << 9) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 228 #define _AMUXCP_TRIM_VOLTAGECTRLLO_SHIFT 10 /**< Shift value for AMUXCP_VOLTAGECTRLLO */ 229 #define _AMUXCP_TRIM_VOLTAGECTRLLO_MASK 0xC00UL /**< Bit mask for AMUXCP_VOLTAGECTRLLO */ 230 #define _AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_TRIM */ 231 #define AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT (_AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT << 10) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 232 #define _AMUXCP_TRIM_VOLTAGECTRLHI_SHIFT 13 /**< Shift value for AMUXCP_VOLTAGECTRLHI */ 233 #define _AMUXCP_TRIM_VOLTAGECTRLHI_MASK 0x6000UL /**< Bit mask for AMUXCP_VOLTAGECTRLHI */ 234 #define _AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_TRIM */ 235 #define AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT (_AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT << 13) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 236 #define _AMUXCP_TRIM_BIASCTRLLO_SHIFT 15 /**< Shift value for AMUXCP_BIASCTRLLO */ 237 #define _AMUXCP_TRIM_BIASCTRLLO_MASK 0x38000UL /**< Bit mask for AMUXCP_BIASCTRLLO */ 238 #define _AMUXCP_TRIM_BIASCTRLLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ 239 #define AMUXCP_TRIM_BIASCTRLLO_DEFAULT (_AMUXCP_TRIM_BIASCTRLLO_DEFAULT << 15) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 240 #define _AMUXCP_TRIM_BIASCTRLLOCONT_SHIFT 18 /**< Shift value for AMUXCP_BIASCTRLLOCONT */ 241 #define _AMUXCP_TRIM_BIASCTRLLOCONT_MASK 0x1C0000UL /**< Bit mask for AMUXCP_BIASCTRLLOCONT */ 242 #define _AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ 243 #define AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT (_AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT << 18) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 244 #define _AMUXCP_TRIM_BIASCTRLHI_SHIFT 21 /**< Shift value for AMUXCP_BIASCTRLHI */ 245 #define _AMUXCP_TRIM_BIASCTRLHI_MASK 0xE00000UL /**< Bit mask for AMUXCP_BIASCTRLHI */ 246 #define _AMUXCP_TRIM_BIASCTRLHI_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */ 247 #define AMUXCP_TRIM_BIASCTRLHI_DEFAULT (_AMUXCP_TRIM_BIASCTRLHI_DEFAULT << 21) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 248 #define _AMUXCP_TRIM_PUMPCAPLO_SHIFT 24 /**< Shift value for AMUXCP_PUMPCAPLO */ 249 #define _AMUXCP_TRIM_PUMPCAPLO_MASK 0x7000000UL /**< Bit mask for AMUXCP_PUMPCAPLO */ 250 #define _AMUXCP_TRIM_PUMPCAPLO_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */ 251 #define AMUXCP_TRIM_PUMPCAPLO_DEFAULT (_AMUXCP_TRIM_PUMPCAPLO_DEFAULT << 24) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 252 #define _AMUXCP_TRIM_PUMPCAPHI_SHIFT 28 /**< Shift value for AMUXCP_PUMPCAPHI */ 253 #define _AMUXCP_TRIM_PUMPCAPHI_MASK 0x70000000UL /**< Bit mask for AMUXCP_PUMPCAPHI */ 254 #define _AMUXCP_TRIM_PUMPCAPHI_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */ 255 #define AMUXCP_TRIM_PUMPCAPHI_DEFAULT (_AMUXCP_TRIM_PUMPCAPHI_DEFAULT << 28) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ 256 257 /** @} End of group EFR32BG22_AMUXCP_BitFields */ 258 /** @} End of group EFR32BG22_AMUXCP */ 259 /** @} End of group Parts */ 260 261 #endif /* EFR32BG22_AMUXCP_H */ 262
