1 /***************************************************************************//** 2 * @file 3 * @brief EFM32WG_USART register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32WG_USART 43 * @{ 44 * @brief EFM32WG_USART Register Declaration 45 ******************************************************************************/ 46 typedef struct { 47 __IOM uint32_t CTRL; /**< Control Register */ 48 __IOM uint32_t FRAME; /**< USART Frame Format Register */ 49 __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ 50 __IOM uint32_t CMD; /**< Command Register */ 51 __IM uint32_t STATUS; /**< USART Status Register */ 52 __IOM uint32_t CLKDIV; /**< Clock Control Register */ 53 __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ 54 __IM uint32_t RXDATA; /**< RX Buffer Data Register */ 55 __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ 56 __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ 57 __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ 58 __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */ 59 __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ 60 __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ 61 __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ 62 __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ 63 __IM uint32_t IF; /**< Interrupt Flag Register */ 64 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 65 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 66 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 67 __IOM uint32_t IRCTRL; /**< IrDA Control Register */ 68 __IOM uint32_t ROUTE; /**< I/O Routing Register */ 69 __IOM uint32_t INPUT; /**< USART Input Register */ 70 __IOM uint32_t I2SCTRL; /**< I2S Control Register */ 71 } USART_TypeDef; /**< USART Register Declaration *//** @} */ 72 73 /***************************************************************************//** 74 * @defgroup EFM32WG_USART_BitFields 75 * @{ 76 ******************************************************************************/ 77 78 /* Bit fields for USART CTRL */ 79 #define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ 80 #define _USART_CTRL_MASK 0xFFFFFF7FUL /**< Mask for USART_CTRL */ 81 #define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ 82 #define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ 83 #define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ 84 #define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 85 #define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ 86 #define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ 87 #define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ 88 #define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ 89 #define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 90 #define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ 91 #define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ 92 #define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ 93 #define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ 94 #define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 95 #define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ 96 #define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ 97 #define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ 98 #define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ 99 #define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 100 #define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ 101 #define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ 102 #define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ 103 #define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ 104 #define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 105 #define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ 106 #define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ 107 #define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ 108 #define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 109 #define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ 110 #define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ 111 #define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ 112 #define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ 113 #define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ 114 #define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ 115 #define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ 116 #define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ 117 #define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ 118 #define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ 119 #define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ 120 #define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ 121 #define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 122 #define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ 123 #define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ 124 #define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ 125 #define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ 126 #define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ 127 #define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ 128 #define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ 129 #define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ 130 #define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 131 #define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ 132 #define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ 133 #define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ 134 #define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ 135 #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ 136 #define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ 137 #define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ 138 #define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ 139 #define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 140 #define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ 141 #define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */ 142 #define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ 143 #define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ 144 #define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 145 #define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ 146 #define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ 147 #define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ 148 #define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ 149 #define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ 150 #define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ 151 #define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ 152 #define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ 153 #define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 154 #define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ 155 #define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ 156 #define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ 157 #define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ 158 #define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ 159 #define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ 160 #define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ 161 #define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ 162 #define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 163 #define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ 164 #define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ 165 #define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ 166 #define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ 167 #define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 168 #define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ 169 #define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ 170 #define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ 171 #define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ 172 #define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 173 #define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ 174 #define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ 175 #define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ 176 #define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ 177 #define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 178 #define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ 179 #define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ 180 #define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ 181 #define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ 182 #define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 183 #define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ 184 #define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ 185 #define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ 186 #define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ 187 #define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 188 #define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ 189 #define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ 190 #define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ 191 #define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ 192 #define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 193 #define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ 194 #define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ 195 #define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ 196 #define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ 197 #define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 198 #define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ 199 #define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ 200 #define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ 201 #define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ 202 #define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 203 #define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ 204 #define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ 205 #define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ 206 #define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ 207 #define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 208 #define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ 209 #define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ 210 #define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ 211 #define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ 212 #define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 213 #define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ 214 #define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ 215 #define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ 216 #define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ 217 #define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 218 #define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ 219 #define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */ 220 #define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ 221 #define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ 222 #define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 223 #define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ 224 #define _USART_CTRL_TXDELAY_SHIFT 26 /**< Shift value for USART_TXDELAY */ 225 #define _USART_CTRL_TXDELAY_MASK 0xC000000UL /**< Bit mask for USART_TXDELAY */ 226 #define _USART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 227 #define _USART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for USART_CTRL */ 228 #define _USART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for USART_CTRL */ 229 #define _USART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for USART_CTRL */ 230 #define _USART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for USART_CTRL */ 231 #define USART_CTRL_TXDELAY_DEFAULT (_USART_CTRL_TXDELAY_DEFAULT << 26) /**< Shifted mode DEFAULT for USART_CTRL */ 232 #define USART_CTRL_TXDELAY_NONE (_USART_CTRL_TXDELAY_NONE << 26) /**< Shifted mode NONE for USART_CTRL */ 233 #define USART_CTRL_TXDELAY_SINGLE (_USART_CTRL_TXDELAY_SINGLE << 26) /**< Shifted mode SINGLE for USART_CTRL */ 234 #define USART_CTRL_TXDELAY_DOUBLE (_USART_CTRL_TXDELAY_DOUBLE << 26) /**< Shifted mode DOUBLE for USART_CTRL */ 235 #define USART_CTRL_TXDELAY_TRIPLE (_USART_CTRL_TXDELAY_TRIPLE << 26) /**< Shifted mode TRIPLE for USART_CTRL */ 236 #define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ 237 #define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ 238 #define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ 239 #define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 240 #define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ 241 #define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ 242 #define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ 243 #define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ 244 #define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 245 #define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ 246 #define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ 247 #define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ 248 #define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ 249 #define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 250 #define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ 251 #define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */ 252 #define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ 253 #define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ 254 #define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 255 #define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ 256 257 /* Bit fields for USART FRAME */ 258 #define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ 259 #define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ 260 #define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ 261 #define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ 262 #define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ 263 #define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ 264 #define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ 265 #define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ 266 #define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ 267 #define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ 268 #define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ 269 #define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ 270 #define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ 271 #define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ 272 #define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ 273 #define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ 274 #define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ 275 #define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ 276 #define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ 277 #define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ 278 #define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ 279 #define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ 280 #define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ 281 #define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ 282 #define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ 283 #define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ 284 #define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ 285 #define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ 286 #define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ 287 #define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ 288 #define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ 289 #define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ 290 #define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ 291 #define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ 292 #define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ 293 #define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ 294 #define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ 295 #define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ 296 #define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ 297 #define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ 298 #define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ 299 #define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ 300 #define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ 301 #define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ 302 #define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ 303 #define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ 304 #define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ 305 #define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ 306 #define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ 307 #define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ 308 #define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ 309 #define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ 310 #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ 311 #define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ 312 313 /* Bit fields for USART TRIGCTRL */ 314 #define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ 315 #define _USART_TRIGCTRL_MASK 0x00000077UL /**< Mask for USART_TRIGCTRL */ 316 #define _USART_TRIGCTRL_TSEL_SHIFT 0 /**< Shift value for USART_TSEL */ 317 #define _USART_TRIGCTRL_TSEL_MASK 0x7UL /**< Bit mask for USART_TSEL */ 318 #define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 319 #define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */ 320 #define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */ 321 #define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */ 322 #define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */ 323 #define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */ 324 #define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */ 325 #define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */ 326 #define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */ 327 #define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 328 #define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */ 329 #define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */ 330 #define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */ 331 #define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */ 332 #define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */ 333 #define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */ 334 #define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */ 335 #define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */ 336 #define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ 337 #define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ 338 #define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ 339 #define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 340 #define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 341 #define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ 342 #define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ 343 #define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ 344 #define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 345 #define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 346 #define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ 347 #define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ 348 #define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ 349 #define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 350 #define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 351 352 /* Bit fields for USART CMD */ 353 #define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ 354 #define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ 355 #define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ 356 #define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ 357 #define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ 358 #define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 359 #define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ 360 #define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ 361 #define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ 362 #define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ 363 #define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 364 #define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ 365 #define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ 366 #define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ 367 #define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ 368 #define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 369 #define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ 370 #define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ 371 #define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ 372 #define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ 373 #define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 374 #define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ 375 #define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */ 376 #define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ 377 #define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ 378 #define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 379 #define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ 380 #define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */ 381 #define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ 382 #define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ 383 #define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 384 #define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ 385 #define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ 386 #define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ 387 #define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ 388 #define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 389 #define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ 390 #define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ 391 #define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ 392 #define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ 393 #define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 394 #define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ 395 #define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ 396 #define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ 397 #define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ 398 #define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 399 #define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ 400 #define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ 401 #define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ 402 #define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ 403 #define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 404 #define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ 405 #define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ 406 #define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ 407 #define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ 408 #define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 409 #define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ 410 #define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ 411 #define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ 412 #define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ 413 #define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 414 #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ 415 416 /* Bit fields for USART STATUS */ 417 #define _USART_STATUS_RESETVALUE 0x00000040UL /**< Default value for USART_STATUS */ 418 #define _USART_STATUS_MASK 0x00001FFFUL /**< Mask for USART_STATUS */ 419 #define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ 420 #define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ 421 #define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ 422 #define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 423 #define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ 424 #define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ 425 #define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ 426 #define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ 427 #define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 428 #define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ 429 #define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */ 430 #define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ 431 #define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ 432 #define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 433 #define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ 434 #define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ 435 #define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ 436 #define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ 437 #define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 438 #define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ 439 #define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ 440 #define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ 441 #define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ 442 #define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 443 #define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ 444 #define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ 445 #define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ 446 #define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ 447 #define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 448 #define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ 449 #define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ 450 #define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ 451 #define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ 452 #define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ 453 #define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ 454 #define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ 455 #define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ 456 #define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ 457 #define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 458 #define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ 459 #define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ 460 #define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ 461 #define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ 462 #define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 463 #define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ 464 #define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ 465 #define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ 466 #define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ 467 #define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 468 #define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ 469 #define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ 470 #define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ 471 #define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ 472 #define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 473 #define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ 474 #define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ 475 #define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ 476 #define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ 477 #define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 478 #define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ 479 #define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ 480 #define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ 481 #define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ 482 #define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 483 #define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ 484 485 /* Bit fields for USART CLKDIV */ 486 #define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ 487 #define _USART_CLKDIV_MASK 0x001FFFC0UL /**< Mask for USART_CLKDIV */ 488 #define _USART_CLKDIV_DIV_SHIFT 6 /**< Shift value for USART_DIV */ 489 #define _USART_CLKDIV_DIV_MASK 0x1FFFC0UL /**< Bit mask for USART_DIV */ 490 #define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ 491 #define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CLKDIV */ 492 493 /* Bit fields for USART RXDATAX */ 494 #define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ 495 #define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ 496 #define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ 497 #define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ 498 #define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ 499 #define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ 500 #define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ 501 #define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ 502 #define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ 503 #define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ 504 #define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ 505 #define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ 506 #define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ 507 #define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ 508 #define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ 509 #define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ 510 511 /* Bit fields for USART RXDATA */ 512 #define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ 513 #define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ 514 #define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ 515 #define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ 516 #define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ 517 #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ 518 519 /* Bit fields for USART RXDOUBLEX */ 520 #define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ 521 #define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ 522 #define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ 523 #define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ 524 #define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ 525 #define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ 526 #define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ 527 #define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ 528 #define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ 529 #define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ 530 #define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ 531 #define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ 532 #define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ 533 #define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ 534 #define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ 535 #define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ 536 #define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ 537 #define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ 538 #define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ 539 #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ 540 #define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ 541 #define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ 542 #define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ 543 #define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ 544 #define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ 545 #define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ 546 #define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ 547 #define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ 548 #define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ 549 #define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ 550 551 /* Bit fields for USART RXDOUBLE */ 552 #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ 553 #define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ 554 #define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ 555 #define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ 556 #define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ 557 #define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ 558 #define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ 559 #define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ 560 #define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ 561 #define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ 562 563 /* Bit fields for USART RXDATAXP */ 564 #define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ 565 #define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ 566 #define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ 567 #define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ 568 #define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ 569 #define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ 570 #define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ 571 #define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ 572 #define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ 573 #define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ 574 #define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ 575 #define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ 576 #define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ 577 #define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ 578 #define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ 579 #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ 580 581 /* Bit fields for USART RXDOUBLEXP */ 582 #define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ 583 #define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ 584 #define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ 585 #define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ 586 #define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ 587 #define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ 588 #define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ 589 #define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ 590 #define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ 591 #define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ 592 #define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ 593 #define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ 594 #define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ 595 #define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ 596 #define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ 597 #define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ 598 #define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ 599 #define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ 600 #define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ 601 #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ 602 #define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ 603 #define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ 604 #define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ 605 #define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ 606 #define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ 607 #define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ 608 #define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ 609 #define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ 610 #define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ 611 #define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ 612 613 /* Bit fields for USART TXDATAX */ 614 #define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ 615 #define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ 616 #define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ 617 #define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ 618 #define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ 619 #define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ 620 #define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ 621 #define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ 622 #define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ 623 #define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ 624 #define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ 625 #define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ 626 #define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ 627 #define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ 628 #define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ 629 #define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ 630 #define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ 631 #define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ 632 #define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ 633 #define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ 634 #define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ 635 #define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ 636 #define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ 637 #define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ 638 #define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ 639 #define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ 640 #define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ 641 #define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ 642 #define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ 643 #define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ 644 #define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ 645 646 /* Bit fields for USART TXDATA */ 647 #define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ 648 #define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ 649 #define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ 650 #define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ 651 #define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ 652 #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ 653 654 /* Bit fields for USART TXDOUBLEX */ 655 #define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ 656 #define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ 657 #define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ 658 #define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ 659 #define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 660 #define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 661 #define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ 662 #define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ 663 #define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ 664 #define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 665 #define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 666 #define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ 667 #define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ 668 #define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ 669 #define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 670 #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 671 #define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ 672 #define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ 673 #define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ 674 #define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 675 #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 676 #define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ 677 #define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ 678 #define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ 679 #define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 680 #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 681 #define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ 682 #define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ 683 #define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ 684 #define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 685 #define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 686 #define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ 687 #define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ 688 #define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 689 #define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 690 #define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ 691 #define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ 692 #define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ 693 #define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 694 #define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 695 #define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ 696 #define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ 697 #define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ 698 #define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 699 #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 700 #define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ 701 #define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ 702 #define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ 703 #define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 704 #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 705 #define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ 706 #define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ 707 #define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ 708 #define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 709 #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 710 #define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ 711 #define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ 712 #define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ 713 #define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 714 #define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 715 716 /* Bit fields for USART TXDOUBLE */ 717 #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ 718 #define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ 719 #define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ 720 #define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ 721 #define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ 722 #define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ 723 #define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ 724 #define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ 725 #define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ 726 #define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ 727 728 /* Bit fields for USART IF */ 729 #define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ 730 #define _USART_IF_MASK 0x00001FFFUL /**< Mask for USART_IF */ 731 #define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ 732 #define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ 733 #define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ 734 #define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 735 #define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ 736 #define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ 737 #define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ 738 #define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ 739 #define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ 740 #define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ 741 #define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ 742 #define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ 743 #define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ 744 #define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 745 #define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ 746 #define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ 747 #define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ 748 #define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ 749 #define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 750 #define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ 751 #define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ 752 #define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ 753 #define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ 754 #define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 755 #define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ 756 #define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ 757 #define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ 758 #define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ 759 #define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 760 #define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ 761 #define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ 762 #define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ 763 #define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ 764 #define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 765 #define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ 766 #define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ 767 #define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ 768 #define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ 769 #define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 770 #define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ 771 #define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ 772 #define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ 773 #define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ 774 #define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 775 #define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ 776 #define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ 777 #define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ 778 #define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ 779 #define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 780 #define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ 781 #define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */ 782 #define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ 783 #define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ 784 #define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 785 #define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ 786 #define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */ 787 #define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ 788 #define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ 789 #define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 790 #define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ 791 #define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ 792 #define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ 793 #define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ 794 #define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 795 #define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ 796 797 /* Bit fields for USART IFS */ 798 #define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */ 799 #define _USART_IFS_MASK 0x00001FF9UL /**< Mask for USART_IFS */ 800 #define USART_IFS_TXC (0x1UL << 0) /**< Set TX Complete Interrupt Flag */ 801 #define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ 802 #define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ 803 #define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 804 #define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */ 805 #define USART_IFS_RXFULL (0x1UL << 3) /**< Set RX Buffer Full Interrupt Flag */ 806 #define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ 807 #define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ 808 #define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 809 #define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */ 810 #define USART_IFS_RXOF (0x1UL << 4) /**< Set RX Overflow Interrupt Flag */ 811 #define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ 812 #define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ 813 #define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 814 #define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */ 815 #define USART_IFS_RXUF (0x1UL << 5) /**< Set RX Underflow Interrupt Flag */ 816 #define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ 817 #define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ 818 #define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 819 #define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */ 820 #define USART_IFS_TXOF (0x1UL << 6) /**< Set TX Overflow Interrupt Flag */ 821 #define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ 822 #define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ 823 #define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 824 #define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */ 825 #define USART_IFS_TXUF (0x1UL << 7) /**< Set TX Underflow Interrupt Flag */ 826 #define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ 827 #define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ 828 #define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 829 #define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */ 830 #define USART_IFS_PERR (0x1UL << 8) /**< Set Parity Error Interrupt Flag */ 831 #define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ 832 #define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ 833 #define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 834 #define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */ 835 #define USART_IFS_FERR (0x1UL << 9) /**< Set Framing Error Interrupt Flag */ 836 #define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ 837 #define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ 838 #define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 839 #define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */ 840 #define USART_IFS_MPAF (0x1UL << 10) /**< Set Multi-Processor Address Frame Interrupt Flag */ 841 #define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ 842 #define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ 843 #define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 844 #define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */ 845 #define USART_IFS_SSM (0x1UL << 11) /**< Set Slave-Select in Master mode Interrupt Flag */ 846 #define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ 847 #define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ 848 #define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 849 #define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */ 850 #define USART_IFS_CCF (0x1UL << 12) /**< Set Collision Check Fail Interrupt Flag */ 851 #define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ 852 #define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ 853 #define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 854 #define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */ 855 856 /* Bit fields for USART IFC */ 857 #define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */ 858 #define _USART_IFC_MASK 0x00001FF9UL /**< Mask for USART_IFC */ 859 #define USART_IFC_TXC (0x1UL << 0) /**< Clear TX Complete Interrupt Flag */ 860 #define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ 861 #define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ 862 #define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 863 #define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */ 864 #define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RX Buffer Full Interrupt Flag */ 865 #define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ 866 #define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ 867 #define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 868 #define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */ 869 #define USART_IFC_RXOF (0x1UL << 4) /**< Clear RX Overflow Interrupt Flag */ 870 #define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ 871 #define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ 872 #define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 873 #define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */ 874 #define USART_IFC_RXUF (0x1UL << 5) /**< Clear RX Underflow Interrupt Flag */ 875 #define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ 876 #define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ 877 #define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 878 #define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */ 879 #define USART_IFC_TXOF (0x1UL << 6) /**< Clear TX Overflow Interrupt Flag */ 880 #define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ 881 #define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ 882 #define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 883 #define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */ 884 #define USART_IFC_TXUF (0x1UL << 7) /**< Clear TX Underflow Interrupt Flag */ 885 #define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ 886 #define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ 887 #define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 888 #define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */ 889 #define USART_IFC_PERR (0x1UL << 8) /**< Clear Parity Error Interrupt Flag */ 890 #define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ 891 #define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ 892 #define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 893 #define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */ 894 #define USART_IFC_FERR (0x1UL << 9) /**< Clear Framing Error Interrupt Flag */ 895 #define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ 896 #define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ 897 #define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 898 #define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */ 899 #define USART_IFC_MPAF (0x1UL << 10) /**< Clear Multi-Processor Address Frame Interrupt Flag */ 900 #define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ 901 #define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ 902 #define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 903 #define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */ 904 #define USART_IFC_SSM (0x1UL << 11) /**< Clear Slave-Select In Master Mode Interrupt Flag */ 905 #define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ 906 #define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ 907 #define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 908 #define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */ 909 #define USART_IFC_CCF (0x1UL << 12) /**< Clear Collision Check Fail Interrupt Flag */ 910 #define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ 911 #define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ 912 #define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 913 #define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */ 914 915 /* Bit fields for USART IEN */ 916 #define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ 917 #define _USART_IEN_MASK 0x00001FFFUL /**< Mask for USART_IEN */ 918 #define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */ 919 #define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ 920 #define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ 921 #define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 922 #define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ 923 #define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */ 924 #define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ 925 #define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ 926 #define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 927 #define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ 928 #define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */ 929 #define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ 930 #define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ 931 #define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 932 #define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ 933 #define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */ 934 #define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ 935 #define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ 936 #define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 937 #define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ 938 #define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */ 939 #define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ 940 #define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ 941 #define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 942 #define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ 943 #define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */ 944 #define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ 945 #define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ 946 #define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 947 #define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ 948 #define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */ 949 #define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ 950 #define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ 951 #define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 952 #define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ 953 #define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */ 954 #define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ 955 #define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ 956 #define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 957 #define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ 958 #define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */ 959 #define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ 960 #define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ 961 #define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 962 #define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ 963 #define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */ 964 #define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ 965 #define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ 966 #define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 967 #define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ 968 #define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Enable */ 969 #define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ 970 #define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ 971 #define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 972 #define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ 973 #define USART_IEN_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Enable */ 974 #define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ 975 #define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ 976 #define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 977 #define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ 978 #define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */ 979 #define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ 980 #define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ 981 #define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 982 #define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ 983 984 /* Bit fields for USART IRCTRL */ 985 #define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ 986 #define _USART_IRCTRL_MASK 0x000000FFUL /**< Mask for USART_IRCTRL */ 987 #define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ 988 #define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ 989 #define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ 990 #define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ 991 #define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ 992 #define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ 993 #define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ 994 #define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ 995 #define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ 996 #define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ 997 #define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ 998 #define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ 999 #define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ 1000 #define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ 1001 #define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ 1002 #define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ 1003 #define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ 1004 #define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ 1005 #define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ 1006 #define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ 1007 #define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ 1008 #define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ 1009 #define _USART_IRCTRL_IRPRSSEL_SHIFT 4 /**< Shift value for USART_IRPRSSEL */ 1010 #define _USART_IRCTRL_IRPRSSEL_MASK 0x70UL /**< Bit mask for USART_IRPRSSEL */ 1011 #define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ 1012 #define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */ 1013 #define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */ 1014 #define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */ 1015 #define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */ 1016 #define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */ 1017 #define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */ 1018 #define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */ 1019 #define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */ 1020 #define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IRCTRL */ 1021 #define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for USART_IRCTRL */ 1022 #define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for USART_IRCTRL */ 1023 #define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for USART_IRCTRL */ 1024 #define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for USART_IRCTRL */ 1025 #define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for USART_IRCTRL */ 1026 #define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for USART_IRCTRL */ 1027 #define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for USART_IRCTRL */ 1028 #define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for USART_IRCTRL */ 1029 #define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */ 1030 #define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ 1031 #define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ 1032 #define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ 1033 #define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */ 1034 1035 /* Bit fields for USART ROUTE */ 1036 #define _USART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTE */ 1037 #define _USART_ROUTE_MASK 0x0000070FUL /**< Mask for USART_ROUTE */ 1038 #define USART_ROUTE_RXPEN (0x1UL << 0) /**< RX Pin Enable */ 1039 #define _USART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ 1040 #define _USART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ 1041 #define _USART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ 1042 #define USART_ROUTE_RXPEN_DEFAULT (_USART_ROUTE_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTE */ 1043 #define USART_ROUTE_TXPEN (0x1UL << 1) /**< TX Pin Enable */ 1044 #define _USART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ 1045 #define _USART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ 1046 #define _USART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ 1047 #define USART_ROUTE_TXPEN_DEFAULT (_USART_ROUTE_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTE */ 1048 #define USART_ROUTE_CSPEN (0x1UL << 2) /**< CS Pin Enable */ 1049 #define _USART_ROUTE_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ 1050 #define _USART_ROUTE_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ 1051 #define _USART_ROUTE_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ 1052 #define USART_ROUTE_CSPEN_DEFAULT (_USART_ROUTE_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTE */ 1053 #define USART_ROUTE_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */ 1054 #define _USART_ROUTE_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ 1055 #define _USART_ROUTE_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ 1056 #define _USART_ROUTE_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ 1057 #define USART_ROUTE_CLKPEN_DEFAULT (_USART_ROUTE_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTE */ 1058 #define _USART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for USART_LOCATION */ 1059 #define _USART_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for USART_LOCATION */ 1060 #define _USART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTE */ 1061 #define _USART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ 1062 #define _USART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTE */ 1063 #define _USART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTE */ 1064 #define _USART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTE */ 1065 #define _USART_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTE */ 1066 #define _USART_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTE */ 1067 #define USART_ROUTE_LOCATION_LOC0 (_USART_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTE */ 1068 #define USART_ROUTE_LOCATION_DEFAULT (_USART_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTE */ 1069 #define USART_ROUTE_LOCATION_LOC1 (_USART_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTE */ 1070 #define USART_ROUTE_LOCATION_LOC2 (_USART_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTE */ 1071 #define USART_ROUTE_LOCATION_LOC3 (_USART_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTE */ 1072 #define USART_ROUTE_LOCATION_LOC4 (_USART_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTE */ 1073 #define USART_ROUTE_LOCATION_LOC5 (_USART_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTE */ 1074 1075 /* Bit fields for USART INPUT */ 1076 #define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */ 1077 #define _USART_INPUT_MASK 0x0000001FUL /**< Mask for USART_INPUT */ 1078 #define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */ 1079 #define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */ 1080 #define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ 1081 #define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ 1082 #define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ 1083 #define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ 1084 #define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ 1085 #define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ 1086 #define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ 1087 #define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ 1088 #define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ 1089 #define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ 1090 #define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ 1091 #define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ 1092 #define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ 1093 #define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */ 1094 #define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */ 1095 #define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */ 1096 #define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */ 1097 #define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */ 1098 #define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */ 1099 #define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */ 1100 #define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */ 1101 #define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */ 1102 #define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */ 1103 #define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */ 1104 #define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */ 1105 #define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */ 1106 #define USART_INPUT_RXPRS (0x1UL << 4) /**< PRS RX Enable */ 1107 #define _USART_INPUT_RXPRS_SHIFT 4 /**< Shift value for USART_RXPRS */ 1108 #define _USART_INPUT_RXPRS_MASK 0x10UL /**< Bit mask for USART_RXPRS */ 1109 #define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ 1110 #define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_INPUT */ 1111 1112 /* Bit fields for USART I2SCTRL */ 1113 #define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ 1114 #define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ 1115 #define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ 1116 #define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ 1117 #define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ 1118 #define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ 1119 #define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ 1120 #define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ 1121 #define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ 1122 #define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ 1123 #define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ 1124 #define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ 1125 #define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ 1126 #define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ 1127 #define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ 1128 #define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ 1129 #define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ 1130 #define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ 1131 #define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ 1132 #define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ 1133 #define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ 1134 #define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ 1135 #define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ 1136 #define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ 1137 #define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ 1138 #define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ 1139 #define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ 1140 #define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ 1141 #define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ 1142 #define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ 1143 #define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ 1144 #define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ 1145 #define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ 1146 #define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ 1147 #define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ 1148 #define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ 1149 #define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ 1150 #define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ 1151 #define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ 1152 #define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ 1153 #define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ 1154 #define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ 1155 #define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ 1156 #define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ 1157 #define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ 1158 #define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ 1159 #define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ 1160 #define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ 1161 #define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ 1162 #define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ 1163 #define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ 1164 1165 /** @} End of group EFM32WG_USART */ 1166 /** @} End of group Parts */ 1167
