1 /***************************************************************************//** 2 * @file 3 * @brief EFM32HG_RTC register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32HG_RTC 43 * @{ 44 * @brief EFM32HG_RTC Register Declaration 45 ******************************************************************************/ 46 typedef struct { 47 __IOM uint32_t CTRL; /**< Control Register */ 48 __IOM uint32_t CNT; /**< Counter Value Register */ 49 __IOM uint32_t COMP0; /**< Compare Value Register 0 */ 50 __IOM uint32_t COMP1; /**< Compare Value Register 1 */ 51 __IM uint32_t IF; /**< Interrupt Flag Register */ 52 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 53 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 54 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 55 56 __IOM uint32_t FREEZE; /**< Freeze Register */ 57 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 58 } RTC_TypeDef; /**< RTC Register Declaration *//** @} */ 59 60 /***************************************************************************//** 61 * @defgroup EFM32HG_RTC_BitFields 62 * @{ 63 ******************************************************************************/ 64 65 /* Bit fields for RTC CTRL */ 66 #define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */ 67 #define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */ 68 #define RTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */ 69 #define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */ 70 #define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */ 71 #define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ 72 #define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CTRL */ 73 #define RTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ 74 #define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */ 75 #define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */ 76 #define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ 77 #define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */ 78 #define RTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */ 79 #define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */ 80 #define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */ 81 #define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ 82 #define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */ 83 #define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */ 84 #define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */ 85 #define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */ 86 #define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for RTC_CTRL */ 87 88 /* Bit fields for RTC CNT */ 89 #define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */ 90 #define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */ 91 #define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */ 92 #define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */ 93 #define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */ 94 #define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */ 95 96 /* Bit fields for RTC COMP0 */ 97 #define _RTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP0 */ 98 #define _RTC_COMP0_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP0 */ 99 #define _RTC_COMP0_COMP0_SHIFT 0 /**< Shift value for RTC_COMP0 */ 100 #define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP0 */ 101 #define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP0 */ 102 #define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */ 103 104 /* Bit fields for RTC COMP1 */ 105 #define _RTC_COMP1_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP1 */ 106 #define _RTC_COMP1_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP1 */ 107 #define _RTC_COMP1_COMP1_SHIFT 0 /**< Shift value for RTC_COMP1 */ 108 #define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP1 */ 109 #define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP1 */ 110 #define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */ 111 112 /* Bit fields for RTC IF */ 113 #define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */ 114 #define _RTC_IF_MASK 0x00000007UL /**< Mask for RTC_IF */ 115 #define RTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ 116 #define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */ 117 #define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 118 #define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ 119 #define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IF */ 120 #define RTC_IF_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Flag */ 121 #define _RTC_IF_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ 122 #define _RTC_IF_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ 123 #define _RTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ 124 #define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */ 125 #define RTC_IF_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Flag */ 126 #define _RTC_IF_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ 127 #define _RTC_IF_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ 128 #define _RTC_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ 129 #define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IF */ 130 131 /* Bit fields for RTC IFS */ 132 #define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */ 133 #define _RTC_IFS_MASK 0x00000007UL /**< Mask for RTC_IFS */ 134 #define RTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */ 135 #define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */ 136 #define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 137 #define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ 138 #define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFS */ 139 #define RTC_IFS_COMP0 (0x1UL << 1) /**< Set Compare match 0 Interrupt Flag */ 140 #define _RTC_IFS_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ 141 #define _RTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ 142 #define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ 143 #define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */ 144 #define RTC_IFS_COMP1 (0x1UL << 2) /**< Set Compare match 1 Interrupt Flag */ 145 #define _RTC_IFS_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ 146 #define _RTC_IFS_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ 147 #define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ 148 #define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFS */ 149 150 /* Bit fields for RTC IFC */ 151 #define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */ 152 #define _RTC_IFC_MASK 0x00000007UL /**< Mask for RTC_IFC */ 153 #define RTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */ 154 #define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */ 155 #define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 156 #define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ 157 #define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFC */ 158 #define RTC_IFC_COMP0 (0x1UL << 1) /**< Clear Compare match 0 Interrupt Flag */ 159 #define _RTC_IFC_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ 160 #define _RTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ 161 #define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ 162 #define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */ 163 #define RTC_IFC_COMP1 (0x1UL << 2) /**< Clear Compare match 1 Interrupt Flag */ 164 #define _RTC_IFC_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ 165 #define _RTC_IFC_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ 166 #define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ 167 #define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFC */ 168 169 /* Bit fields for RTC IEN */ 170 #define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */ 171 #define _RTC_IEN_MASK 0x00000007UL /**< Mask for RTC_IEN */ 172 #define RTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ 173 #define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */ 174 #define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 175 #define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ 176 #define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IEN */ 177 #define RTC_IEN_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Enable */ 178 #define _RTC_IEN_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ 179 #define _RTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ 180 #define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ 181 #define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */ 182 #define RTC_IEN_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Enable */ 183 #define _RTC_IEN_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ 184 #define _RTC_IEN_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ 185 #define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ 186 #define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IEN */ 187 188 /* Bit fields for RTC FREEZE */ 189 #define _RTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for RTC_FREEZE */ 190 #define _RTC_FREEZE_MASK 0x00000001UL /**< Mask for RTC_FREEZE */ 191 #define RTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ 192 #define _RTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for RTC_REGFREEZE */ 193 #define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for RTC_REGFREEZE */ 194 #define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_FREEZE */ 195 #define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for RTC_FREEZE */ 196 #define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for RTC_FREEZE */ 197 #define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */ 198 #define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for RTC_FREEZE */ 199 #define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for RTC_FREEZE */ 200 201 /* Bit fields for RTC SYNCBUSY */ 202 #define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTC_SYNCBUSY */ 203 #define _RTC_SYNCBUSY_MASK 0x00000007UL /**< Mask for RTC_SYNCBUSY */ 204 #define RTC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ 205 #define _RTC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for RTC_CTRL */ 206 #define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for RTC_CTRL */ 207 #define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ 208 #define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ 209 #define RTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< COMP0 Register Busy */ 210 #define _RTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ 211 #define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ 212 #define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ 213 #define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ 214 #define RTC_SYNCBUSY_COMP1 (0x1UL << 2) /**< COMP1 Register Busy */ 215 #define _RTC_SYNCBUSY_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ 216 #define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ 217 #define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ 218 #define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ 219 220 /** @} End of group EFM32HG_RTC */ 221 /** @} End of group Parts */ 222
