1 /***************************************************************************//** 2 * @file 3 * @brief EFM32HG_EMU register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32HG_EMU 43 * @{ 44 * @brief EFM32HG_EMU Register Declaration 45 ******************************************************************************/ 46 typedef struct { 47 __IOM uint32_t CTRL; /**< Control Register */ 48 49 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 50 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 51 52 uint32_t RESERVED1[6U]; /**< Reserved for future use **/ 53 __IOM uint32_t AUXCTRL; /**< Auxiliary Control Register */ 54 } EMU_TypeDef; /**< EMU Register Declaration *//** @} */ 55 56 /***************************************************************************//** 57 * @defgroup EFM32HG_EMU_BitFields 58 * @{ 59 ******************************************************************************/ 60 61 /* Bit fields for EMU CTRL */ 62 #define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ 63 #define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */ 64 #define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */ 65 #define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */ 66 #define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */ 67 #define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 68 #define _EMU_CTRL_EMVREG_REDUCED 0x00000000UL /**< Mode REDUCED for EMU_CTRL */ 69 #define _EMU_CTRL_EMVREG_FULL 0x00000001UL /**< Mode FULL for EMU_CTRL */ 70 #define EMU_CTRL_EMVREG_DEFAULT (_EMU_CTRL_EMVREG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ 71 #define EMU_CTRL_EMVREG_REDUCED (_EMU_CTRL_EMVREG_REDUCED << 0) /**< Shifted mode REDUCED for EMU_CTRL */ 72 #define EMU_CTRL_EMVREG_FULL (_EMU_CTRL_EMVREG_FULL << 0) /**< Shifted mode FULL for EMU_CTRL */ 73 #define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ 74 #define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ 75 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ 76 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 77 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ 78 #define _EMU_CTRL_EM4CTRL_SHIFT 2 /**< Shift value for EMU_EM4CTRL */ 79 #define _EMU_CTRL_EM4CTRL_MASK 0xCUL /**< Bit mask for EMU_EM4CTRL */ 80 #define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 81 #define EMU_CTRL_EM4CTRL_DEFAULT (_EMU_CTRL_EM4CTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ 82 83 /* Bit fields for EMU LOCK */ 84 #define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ 85 #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ 86 #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ 87 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ 88 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ 89 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ 90 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ 91 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ 92 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ 93 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ 94 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ 95 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ 96 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ 97 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ 98 99 /* Bit fields for EMU AUXCTRL */ 100 #define _EMU_AUXCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_AUXCTRL */ 101 #define _EMU_AUXCTRL_MASK 0x00000001UL /**< Mask for EMU_AUXCTRL */ 102 #define EMU_AUXCTRL_HRCCLR (0x1UL << 0) /**< Hard Reset Cause Clear */ 103 #define _EMU_AUXCTRL_HRCCLR_SHIFT 0 /**< Shift value for EMU_HRCCLR */ 104 #define _EMU_AUXCTRL_HRCCLR_MASK 0x1UL /**< Bit mask for EMU_HRCCLR */ 105 #define _EMU_AUXCTRL_HRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_AUXCTRL */ 106 #define EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */ 107 108 /** @} End of group EFM32HG_EMU */ 109 /** @} End of group Parts */ 110
