1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG12B_USB register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG12B_USB USB 43 * @{ 44 * @brief EFM32GG12B_USB Register Declaration 45 ******************************************************************************/ 46 /** USB Register Declaration */ 47 typedef struct { 48 __IOM uint32_t CTRL; /**< System Control Register */ 49 __IM uint32_t STATUS; /**< System Status Register */ 50 __IM uint32_t IF; /**< Interrupt Flag Register */ 51 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 52 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 53 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 54 __IOM uint32_t ROUTE; /**< I/O Routing Register */ 55 56 uint32_t RESERVED0[4U]; /**< Reserved for future use **/ 57 __IOM uint32_t CDCONF; /**< Charger Detect Configuration Register */ 58 __IOM uint32_t CMD; /**< Command Register */ 59 __IOM uint32_t DATTRIM1; /**< Data TRIM 1 Values for USB DP and DM */ 60 61 uint32_t RESERVED1[1U]; /**< Reserved for future use **/ 62 __IOM uint32_t LEMCTRL; /**< USB LEM Control Register */ 63 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ 64 65 uint32_t RESERVED2[227311U]; /**< Reserved for future use **/ 66 __IOM uint32_t GOTGCTL; /**< OTG Control and Status Register */ 67 __IOM uint32_t GOTGINT; /**< OTG Interrupt Register */ 68 __IOM uint32_t GAHBCFG; /**< AHB Configuration Register */ 69 __IOM uint32_t GUSBCFG; /**< USB Configuration Register */ 70 __IOM uint32_t GRSTCTL; /**< Reset Register */ 71 __IOM uint32_t GINTSTS; /**< Interrupt Register */ 72 __IOM uint32_t GINTMSK; /**< Interrupt Mask Register */ 73 __IM uint32_t GRXSTSR; /**< Receive Status Debug Read Register */ 74 __IM uint32_t GRXSTSP; /**< Receive Status Read /Pop Register */ 75 __IOM uint32_t GRXFSIZ; /**< Receive FIFO Size Register */ 76 __IOM uint32_t GNPTXFSIZ; /**< Non-periodic Transmit FIFO Size Register */ 77 __IM uint32_t GNPTXSTS; /**< Non-periodic Transmit FIFO/Queue Status Register */ 78 uint32_t RESERVED3[4U]; /**< Reserved for future use **/ 79 __IM uint32_t GSNPSID; /**< Synopsys ID Register */ 80 81 uint32_t RESERVED4[6U]; /**< Reserved for future use **/ 82 __IOM uint32_t GDFIFOCFG; /**< Global DFIFO Configuration Register */ 83 84 uint32_t RESERVED5[40U]; /**< Reserved for future use **/ 85 __IOM uint32_t HPTXFSIZ; /**< Host Periodic Transmit FIFO Size Register */ 86 __IOM uint32_t DIEPTXF1; /**< Device IN Endpoint Transmit FIFO Size Register 1 */ 87 __IOM uint32_t DIEPTXF2; /**< Device IN Endpoint Transmit FIFO Size Register 2 */ 88 __IOM uint32_t DIEPTXF3; /**< Device IN Endpoint Transmit FIFO Size Register 3 */ 89 __IOM uint32_t DIEPTXF4; /**< Device IN Endpoint Transmit FIFO Size Register 4 */ 90 __IOM uint32_t DIEPTXF5; /**< Device IN Endpoint Transmit FIFO Size Register 5 */ 91 __IOM uint32_t DIEPTXF6; /**< Device IN Endpoint Transmit FIFO Size Register 6 */ 92 93 uint32_t RESERVED6[185U]; /**< Reserved for future use **/ 94 __IOM uint32_t HCFG; /**< Host Configuration Register */ 95 __IOM uint32_t HFIR; /**< Host Frame Interval Register */ 96 __IM uint32_t HFNUM; /**< Host Frame Number/Frame Time Remaining Register */ 97 uint32_t RESERVED7[1U]; /**< Reserved for future use **/ 98 __IM uint32_t HPTXSTS; /**< Host Periodic Transmit FIFO/Queue Status Register */ 99 __IM uint32_t HAINT; /**< Host All Channels Interrupt Register */ 100 __IOM uint32_t HAINTMSK; /**< Host All Channels Interrupt Mask Register */ 101 uint32_t RESERVED8[9U]; /**< Reserved for future use **/ 102 __IOM uint32_t HPRT; /**< Host Port Control and Status Register */ 103 104 uint32_t RESERVED9[47U]; /**< Reserved registers */ 105 USB_HC_TypeDef HC[14U]; /**< Host Channel Registers */ 106 107 uint32_t RESERVED10[80U]; /**< Reserved for future use **/ 108 __IOM uint32_t DCFG; /**< Device Configuration Register */ 109 __IOM uint32_t DCTL; /**< Device Control Register */ 110 __IM uint32_t DSTS; /**< Device Status Register */ 111 uint32_t RESERVED11[1U]; /**< Reserved for future use **/ 112 __IOM uint32_t DIEPMSK; /**< Device IN Endpoint Common Interrupt Mask Register */ 113 __IOM uint32_t DOEPMSK; /**< Device OUT Endpoint Common Interrupt Mask Register */ 114 __IM uint32_t DAINT; /**< Device All Endpoints Interrupt Register */ 115 __IOM uint32_t DAINTMSK; /**< Device All Endpoints Interrupt Mask Register */ 116 uint32_t RESERVED12[2U]; /**< Reserved for future use **/ 117 __IOM uint32_t DVBUSDIS; /**< Device VBUS Discharge Time Register */ 118 __IOM uint32_t DVBUSPULSE; /**< Device VBUS Pulsing Time Register */ 119 __IOM uint32_t DTHRCTL; /**< Device Threshold Control Register */ 120 __IOM uint32_t DIEPEMPMSK; /**< Device IN Endpoint FIFO Empty Interrupt Mask Register */ 121 122 uint32_t RESERVED13[50U]; /**< Reserved for future use **/ 123 __IOM uint32_t DIEP0CTL; /**< Device Control IN Endpoint 0 Control Register */ 124 uint32_t RESERVED14[1U]; /**< Reserved for future use **/ 125 __IOM uint32_t DIEP0INT; /**< Device IN Endpoint 0 Interrupt Register */ 126 uint32_t RESERVED15[1U]; /**< Reserved for future use **/ 127 __IOM uint32_t DIEP0TSIZ; /**< Device IN Endpoint 0 Transfer Size Register */ 128 __IOM uint32_t DIEP0DMAADDR; /**< Device IN Endpoint 0 DMA Address Register */ 129 __IM uint32_t DIEP0TXFSTS; /**< Device IN Endpoint Transmit FIFO Status Register 0 */ 130 131 uint32_t RESERVED16[1U]; /**< Reserved registers */ 132 USB_DIEP_TypeDef DIEP[6U]; /**< Device IN Endpoint n Registers */ 133 134 uint32_t RESERVED17[72U]; /**< Reserved for future use **/ 135 __IOM uint32_t DOEP0CTL; /**< Device Control OUT Endpoint 0 Control Register */ 136 uint32_t RESERVED18[1U]; /**< Reserved for future use **/ 137 __IOM uint32_t DOEP0INT; /**< Device OUT Endpoint 0 Interrupt Register */ 138 uint32_t RESERVED19[1U]; /**< Reserved for future use **/ 139 __IOM uint32_t DOEP0TSIZ; /**< Device OUT Endpoint 0 Transfer Size Register */ 140 __IOM uint32_t DOEP0DMAADDR; /**< Device OUT Endpoint 0 DMA Address Register */ 141 142 uint32_t RESERVED20[2U]; /**< Reserved registers */ 143 USB_DOEP_TypeDef DOEP[6U]; /**< Device OUT Endpoint n Registers */ 144 145 uint32_t RESERVED21[136U]; /**< Reserved for future use **/ 146 __IOM uint32_t PCGCCTL; /**< Power and Clock Gating Control Register */ 147 148 uint32_t RESERVED22[127U]; /**< Reserved registers */ 149 __IOM uint32_t FIFO0D[512U]; /**< Device EP 0/Host Channel 0 FIFO */ 150 151 uint32_t RESERVED23[512U]; /**< Reserved registers */ 152 __IOM uint32_t FIFO1D[512U]; /**< Device EP 1/Host Channel 1 FIFO */ 153 154 uint32_t RESERVED24[512U]; /**< Reserved registers */ 155 __IOM uint32_t FIFO2D[512U]; /**< Device EP 2/Host Channel 2 FIFO */ 156 157 uint32_t RESERVED25[512U]; /**< Reserved registers */ 158 __IOM uint32_t FIFO3D[512U]; /**< Device EP 3/Host Channel 3 FIFO */ 159 160 uint32_t RESERVED26[512U]; /**< Reserved registers */ 161 __IOM uint32_t FIFO4D[512U]; /**< Device EP 4/Host Channel 4 FIFO */ 162 163 uint32_t RESERVED27[512U]; /**< Reserved registers */ 164 __IOM uint32_t FIFO5D[512U]; /**< Device EP 5/Host Channel 5 FIFO */ 165 166 uint32_t RESERVED28[512U]; /**< Reserved registers */ 167 __IOM uint32_t FIFO6D[512U]; /**< Device EP 6/Host Channel 6 FIFO */ 168 169 uint32_t RESERVED29[512U]; /**< Reserved registers */ 170 __IOM uint32_t FIFO7D[512U]; /**< Host Channel 7 FIFO */ 171 172 uint32_t RESERVED30[512U]; /**< Reserved registers */ 173 __IOM uint32_t FIFO8D[512U]; /**< Host Channel 8 FIFO */ 174 175 uint32_t RESERVED31[512U]; /**< Reserved registers */ 176 __IOM uint32_t FIFO9D[512U]; /**< Host Channel 9 FIFO */ 177 178 uint32_t RESERVED32[512U]; /**< Reserved registers */ 179 __IOM uint32_t FIFO10D[512U]; /**< Host Channel 10 FIFO */ 180 181 uint32_t RESERVED33[512U]; /**< Reserved registers */ 182 __IOM uint32_t FIFO11D[512U]; /**< Host Channel 11 FIFO */ 183 184 uint32_t RESERVED34[512U]; /**< Reserved registers */ 185 __IOM uint32_t FIFO12D[512U]; /**< Host Channel 12 FIFO */ 186 187 uint32_t RESERVED35[512U]; /**< Reserved registers */ 188 __IOM uint32_t FIFO13D[512U]; /**< Host Channel 13 FIFO */ 189 190 uint32_t RESERVED36[17920U]; /**< Reserved registers */ 191 __IOM uint32_t FIFORAM[512U]; /**< Direct Access to Data FIFO RAM for Debugging (2 KB) */ 192 } USB_TypeDef; /** @} */ 193 194 /***************************************************************************//** 195 * @addtogroup EFM32GG12B_USB 196 * @{ 197 * @defgroup EFM32GG12B_USB_BitFields USB Bit Fields 198 * @{ 199 ******************************************************************************/ 200 201 /* Bit fields for USB CTRL */ 202 #define _USB_CTRL_RESETVALUE 0x00000020UL /**< Default value for USB_CTRL */ 203 #define _USB_CTRL_MASK 0xFE0012B9UL /**< Mask for USB_CTRL */ 204 #define USB_CTRL_VBUSENAP (0x1UL << 0) /**< VBUSEN Active Polarity */ 205 #define _USB_CTRL_VBUSENAP_SHIFT 0 /**< Shift value for USB_VBUSENAP */ 206 #define _USB_CTRL_VBUSENAP_MASK 0x1UL /**< Bit mask for USB_VBUSENAP */ 207 #define _USB_CTRL_VBUSENAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ 208 #define _USB_CTRL_VBUSENAP_HIGH 0x00000000UL /**< Mode HIGH for USB_CTRL */ 209 #define _USB_CTRL_VBUSENAP_LOW 0x00000001UL /**< Mode LOW for USB_CTRL */ 210 #define USB_CTRL_VBUSENAP_DEFAULT (_USB_CTRL_VBUSENAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_CTRL */ 211 #define USB_CTRL_VBUSENAP_HIGH (_USB_CTRL_VBUSENAP_HIGH << 0) /**< Shifted mode HIGH for USB_CTRL */ 212 #define USB_CTRL_VBUSENAP_LOW (_USB_CTRL_VBUSENAP_LOW << 0) /**< Shifted mode LOW for USB_CTRL */ 213 #define USB_CTRL_SELFPOWERED (0x1UL << 3) /**< PHY Power */ 214 #define _USB_CTRL_SELFPOWERED_SHIFT 3 /**< Shift value for USB_SELFPOWERED */ 215 #define _USB_CTRL_SELFPOWERED_MASK 0x8UL /**< Bit mask for USB_SELFPOWERED */ 216 #define _USB_CTRL_SELFPOWERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ 217 #define _USB_CTRL_SELFPOWERED_LOW 0x00000000UL /**< Mode LOW for USB_CTRL */ 218 #define _USB_CTRL_SELFPOWERED_HIGH 0x00000001UL /**< Mode HIGH for USB_CTRL */ 219 #define USB_CTRL_SELFPOWERED_DEFAULT (_USB_CTRL_SELFPOWERED_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_CTRL */ 220 #define USB_CTRL_SELFPOWERED_LOW (_USB_CTRL_SELFPOWERED_LOW << 3) /**< Shifted mode LOW for USB_CTRL */ 221 #define USB_CTRL_SELFPOWERED_HIGH (_USB_CTRL_SELFPOWERED_HIGH << 3) /**< Shifted mode HIGH for USB_CTRL */ 222 #define _USB_CTRL_LEMOSCCTRL_SHIFT 4 /**< Shift value for USB_LEMOSCCTRL */ 223 #define _USB_CTRL_LEMOSCCTRL_MASK 0x30UL /**< Bit mask for USB_LEMOSCCTRL */ 224 #define _USB_CTRL_LEMOSCCTRL_NONE 0x00000000UL /**< Mode NONE for USB_CTRL */ 225 #define _USB_CTRL_LEMOSCCTRL_GATE 0x00000001UL /**< Mode GATE for USB_CTRL */ 226 #define _USB_CTRL_LEMOSCCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for USB_CTRL */ 227 #define USB_CTRL_LEMOSCCTRL_NONE (_USB_CTRL_LEMOSCCTRL_NONE << 4) /**< Shifted mode NONE for USB_CTRL */ 228 #define USB_CTRL_LEMOSCCTRL_GATE (_USB_CTRL_LEMOSCCTRL_GATE << 4) /**< Shifted mode GATE for USB_CTRL */ 229 #define USB_CTRL_LEMOSCCTRL_DEFAULT (_USB_CTRL_LEMOSCCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_CTRL */ 230 #define USB_CTRL_LEMPHYCTRL (0x1UL << 7) /**< Low Energy Mode USB PHY Control */ 231 #define _USB_CTRL_LEMPHYCTRL_SHIFT 7 /**< Shift value for USB_LEMPHYCTRL */ 232 #define _USB_CTRL_LEMPHYCTRL_MASK 0x80UL /**< Bit mask for USB_LEMPHYCTRL */ 233 #define _USB_CTRL_LEMPHYCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ 234 #define _USB_CTRL_LEMPHYCTRL_NONE 0x00000000UL /**< Mode NONE for USB_CTRL */ 235 #define _USB_CTRL_LEMPHYCTRL_LEM 0x00000001UL /**< Mode LEM for USB_CTRL */ 236 #define USB_CTRL_LEMPHYCTRL_DEFAULT (_USB_CTRL_LEMPHYCTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_CTRL */ 237 #define USB_CTRL_LEMPHYCTRL_NONE (_USB_CTRL_LEMPHYCTRL_NONE << 7) /**< Shifted mode NONE for USB_CTRL */ 238 #define USB_CTRL_LEMPHYCTRL_LEM (_USB_CTRL_LEMPHYCTRL_LEM << 7) /**< Shifted mode LEM for USB_CTRL */ 239 #define USB_CTRL_LEMIDLEEN (0x1UL << 9) /**< Low Energy Mode on Bus Idle Enable */ 240 #define _USB_CTRL_LEMIDLEEN_SHIFT 9 /**< Shift value for USB_LEMIDLEEN */ 241 #define _USB_CTRL_LEMIDLEEN_MASK 0x200UL /**< Bit mask for USB_LEMIDLEEN */ 242 #define _USB_CTRL_LEMIDLEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ 243 #define USB_CTRL_LEMIDLEEN_DEFAULT (_USB_CTRL_LEMIDLEEN_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_CTRL */ 244 #define USB_CTRL_IDCDEN (0x1UL << 12) /**< ID Pull-up Enable */ 245 #define _USB_CTRL_IDCDEN_SHIFT 12 /**< Shift value for USB_IDCDEN */ 246 #define _USB_CTRL_IDCDEN_MASK 0x1000UL /**< Bit mask for USB_IDCDEN */ 247 #define _USB_CTRL_IDCDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ 248 #define _USB_CTRL_IDCDEN_DISABLED 0x00000000UL /**< Mode DISABLED for USB_CTRL */ 249 #define _USB_CTRL_IDCDEN_ENABLED 0x00000001UL /**< Mode ENABLED for USB_CTRL */ 250 #define USB_CTRL_IDCDEN_DEFAULT (_USB_CTRL_IDCDEN_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_CTRL */ 251 #define USB_CTRL_IDCDEN_DISABLED (_USB_CTRL_IDCDEN_DISABLED << 12) /**< Shifted mode DISABLED for USB_CTRL */ 252 #define USB_CTRL_IDCDEN_ENABLED (_USB_CTRL_IDCDEN_ENABLED << 12) /**< Shifted mode ENABLED for USB_CTRL */ 253 #define USB_CTRL_OTGCLKCDIS (0x1UL << 25) /**< OTG CLKC Disable */ 254 #define _USB_CTRL_OTGCLKCDIS_SHIFT 25 /**< Shift value for USB_OTGCLKCDIS */ 255 #define _USB_CTRL_OTGCLKCDIS_MASK 0x2000000UL /**< Bit mask for USB_OTGCLKCDIS */ 256 #define _USB_CTRL_OTGCLKCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ 257 #define _USB_CTRL_OTGCLKCDIS_ENABLED 0x00000000UL /**< Mode ENABLED for USB_CTRL */ 258 #define _USB_CTRL_OTGCLKCDIS_DISABLED 0x00000001UL /**< Mode DISABLED for USB_CTRL */ 259 #define USB_CTRL_OTGCLKCDIS_DEFAULT (_USB_CTRL_OTGCLKCDIS_DEFAULT << 25) /**< Shifted mode DEFAULT for USB_CTRL */ 260 #define USB_CTRL_OTGCLKCDIS_ENABLED (_USB_CTRL_OTGCLKCDIS_ENABLED << 25) /**< Shifted mode ENABLED for USB_CTRL */ 261 #define USB_CTRL_OTGCLKCDIS_DISABLED (_USB_CTRL_OTGCLKCDIS_DISABLED << 25) /**< Shifted mode DISABLED for USB_CTRL */ 262 #define USB_CTRL_OTGIDINDIS (0x1UL << 26) /**< OTG ID Input Disable */ 263 #define _USB_CTRL_OTGIDINDIS_SHIFT 26 /**< Shift value for USB_OTGIDINDIS */ 264 #define _USB_CTRL_OTGIDINDIS_MASK 0x4000000UL /**< Bit mask for USB_OTGIDINDIS */ 265 #define _USB_CTRL_OTGIDINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ 266 #define _USB_CTRL_OTGIDINDIS_ENABLED 0x00000000UL /**< Mode ENABLED for USB_CTRL */ 267 #define _USB_CTRL_OTGIDINDIS_DISABLED 0x00000001UL /**< Mode DISABLED for USB_CTRL */ 268 #define USB_CTRL_OTGIDINDIS_DEFAULT (_USB_CTRL_OTGIDINDIS_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_CTRL */ 269 #define USB_CTRL_OTGIDINDIS_ENABLED (_USB_CTRL_OTGIDINDIS_ENABLED << 26) /**< Shifted mode ENABLED for USB_CTRL */ 270 #define USB_CTRL_OTGIDINDIS_DISABLED (_USB_CTRL_OTGIDINDIS_DISABLED << 26) /**< Shifted mode DISABLED for USB_CTRL */ 271 #define USB_CTRL_OTGPHYCTRLDIS (0x1UL << 27) /**< OTG Control Signals to PHY Disable */ 272 #define _USB_CTRL_OTGPHYCTRLDIS_SHIFT 27 /**< Shift value for USB_OTGPHYCTRLDIS */ 273 #define _USB_CTRL_OTGPHYCTRLDIS_MASK 0x8000000UL /**< Bit mask for USB_OTGPHYCTRLDIS */ 274 #define _USB_CTRL_OTGPHYCTRLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ 275 #define _USB_CTRL_OTGPHYCTRLDIS_ENABLED 0x00000000UL /**< Mode ENABLED for USB_CTRL */ 276 #define _USB_CTRL_OTGPHYCTRLDIS_DISABLED 0x00000001UL /**< Mode DISABLED for USB_CTRL */ 277 #define USB_CTRL_OTGPHYCTRLDIS_DEFAULT (_USB_CTRL_OTGPHYCTRLDIS_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_CTRL */ 278 #define USB_CTRL_OTGPHYCTRLDIS_ENABLED (_USB_CTRL_OTGPHYCTRLDIS_ENABLED << 27) /**< Shifted mode ENABLED for USB_CTRL */ 279 #define USB_CTRL_OTGPHYCTRLDIS_DISABLED (_USB_CTRL_OTGPHYCTRLDIS_DISABLED << 27) /**< Shifted mode DISABLED for USB_CTRL */ 280 #define _USB_CTRL_DCDEN_SHIFT 28 /**< Shift value for USB_DCDEN */ 281 #define _USB_CTRL_DCDEN_MASK 0x30000000UL /**< Bit mask for USB_DCDEN */ 282 #define _USB_CTRL_DCDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ 283 #define _USB_CTRL_DCDEN_DISABLED 0x00000000UL /**< Mode DISABLED for USB_CTRL */ 284 #define _USB_CTRL_DCDEN_TIMEOUT 0x00000002UL /**< Mode TIMEOUT for USB_CTRL */ 285 #define _USB_CTRL_DCDEN_ENABLED 0x00000003UL /**< Mode ENABLED for USB_CTRL */ 286 #define USB_CTRL_DCDEN_DEFAULT (_USB_CTRL_DCDEN_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_CTRL */ 287 #define USB_CTRL_DCDEN_DISABLED (_USB_CTRL_DCDEN_DISABLED << 28) /**< Shifted mode DISABLED for USB_CTRL */ 288 #define USB_CTRL_DCDEN_TIMEOUT (_USB_CTRL_DCDEN_TIMEOUT << 28) /**< Shifted mode TIMEOUT for USB_CTRL */ 289 #define USB_CTRL_DCDEN_ENABLED (_USB_CTRL_DCDEN_ENABLED << 28) /**< Shifted mode ENABLED for USB_CTRL */ 290 #define USB_CTRL_PDEN (0x1UL << 30) /**< Primary Detection Enable */ 291 #define _USB_CTRL_PDEN_SHIFT 30 /**< Shift value for USB_PDEN */ 292 #define _USB_CTRL_PDEN_MASK 0x40000000UL /**< Bit mask for USB_PDEN */ 293 #define _USB_CTRL_PDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ 294 #define _USB_CTRL_PDEN_DISABLED 0x00000000UL /**< Mode DISABLED for USB_CTRL */ 295 #define _USB_CTRL_PDEN_ENABLED 0x00000001UL /**< Mode ENABLED for USB_CTRL */ 296 #define USB_CTRL_PDEN_DEFAULT (_USB_CTRL_PDEN_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_CTRL */ 297 #define USB_CTRL_PDEN_DISABLED (_USB_CTRL_PDEN_DISABLED << 30) /**< Shifted mode DISABLED for USB_CTRL */ 298 #define USB_CTRL_PDEN_ENABLED (_USB_CTRL_PDEN_ENABLED << 30) /**< Shifted mode ENABLED for USB_CTRL */ 299 #define USB_CTRL_SDEN (0x1UL << 31) /**< Secondary Detection Enable */ 300 #define _USB_CTRL_SDEN_SHIFT 31 /**< Shift value for USB_SDEN */ 301 #define _USB_CTRL_SDEN_MASK 0x80000000UL /**< Bit mask for USB_SDEN */ 302 #define _USB_CTRL_SDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ 303 #define _USB_CTRL_SDEN_DISABLED 0x00000000UL /**< Mode DISABLED for USB_CTRL */ 304 #define _USB_CTRL_SDEN_ENABLED 0x00000001UL /**< Mode ENABLED for USB_CTRL */ 305 #define USB_CTRL_SDEN_DEFAULT (_USB_CTRL_SDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_CTRL */ 306 #define USB_CTRL_SDEN_DISABLED (_USB_CTRL_SDEN_DISABLED << 31) /**< Shifted mode DISABLED for USB_CTRL */ 307 #define USB_CTRL_SDEN_ENABLED (_USB_CTRL_SDEN_ENABLED << 31) /**< Shifted mode ENABLED for USB_CTRL */ 308 309 /* Bit fields for USB STATUS */ 310 #define _USB_STATUS_RESETVALUE 0x00000000UL /**< Default value for USB_STATUS */ 311 #define _USB_STATUS_MASK 0x0000BF05UL /**< Mask for USB_STATUS */ 312 #define USB_STATUS_VBUSDETH (0x1UL << 0) /**< VBUS Detect High */ 313 #define _USB_STATUS_VBUSDETH_SHIFT 0 /**< Shift value for USB_VBUSDETH */ 314 #define _USB_STATUS_VBUSDETH_MASK 0x1UL /**< Bit mask for USB_VBUSDETH */ 315 #define _USB_STATUS_VBUSDETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ 316 #define USB_STATUS_VBUSDETH_DEFAULT (_USB_STATUS_VBUSDETH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_STATUS */ 317 #define USB_STATUS_LEMACTIVE (0x1UL << 2) /**< Low Energy Mode Active */ 318 #define _USB_STATUS_LEMACTIVE_SHIFT 2 /**< Shift value for USB_LEMACTIVE */ 319 #define _USB_STATUS_LEMACTIVE_MASK 0x4UL /**< Bit mask for USB_LEMACTIVE */ 320 #define _USB_STATUS_LEMACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ 321 #define USB_STATUS_LEMACTIVE_DEFAULT (_USB_STATUS_LEMACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_STATUS */ 322 #define USB_STATUS_DCDTO (0x1UL << 8) /**< Data Contact Detection Timeout */ 323 #define _USB_STATUS_DCDTO_SHIFT 8 /**< Shift value for USB_DCDTO */ 324 #define _USB_STATUS_DCDTO_MASK 0x100UL /**< Bit mask for USB_DCDTO */ 325 #define _USB_STATUS_DCDTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ 326 #define _USB_STATUS_DCDTO_NOTIME 0x00000000UL /**< Mode NOTIME for USB_STATUS */ 327 #define _USB_STATUS_DCDTO_TIMEOUT 0x00000001UL /**< Mode TIMEOUT for USB_STATUS */ 328 #define USB_STATUS_DCDTO_DEFAULT (_USB_STATUS_DCDTO_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_STATUS */ 329 #define USB_STATUS_DCDTO_NOTIME (_USB_STATUS_DCDTO_NOTIME << 8) /**< Shifted mode NOTIME for USB_STATUS */ 330 #define USB_STATUS_DCDTO_TIMEOUT (_USB_STATUS_DCDTO_TIMEOUT << 8) /**< Shifted mode TIMEOUT for USB_STATUS */ 331 #define USB_STATUS_SDP (0x1UL << 9) /**< Standard Downstream Port Detected */ 332 #define _USB_STATUS_SDP_SHIFT 9 /**< Shift value for USB_SDP */ 333 #define _USB_STATUS_SDP_MASK 0x200UL /**< Bit mask for USB_SDP */ 334 #define _USB_STATUS_SDP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ 335 #define USB_STATUS_SDP_DEFAULT (_USB_STATUS_SDP_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_STATUS */ 336 #define USB_STATUS_CDP (0x1UL << 10) /**< Charging Downstream Port Detected */ 337 #define _USB_STATUS_CDP_SHIFT 10 /**< Shift value for USB_CDP */ 338 #define _USB_STATUS_CDP_MASK 0x400UL /**< Bit mask for USB_CDP */ 339 #define _USB_STATUS_CDP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ 340 #define USB_STATUS_CDP_DEFAULT (_USB_STATUS_CDP_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_STATUS */ 341 #define USB_STATUS_DCP (0x1UL << 11) /**< Dedicated Charging Port Detected */ 342 #define _USB_STATUS_DCP_SHIFT 11 /**< Shift value for USB_DCP */ 343 #define _USB_STATUS_DCP_MASK 0x800UL /**< Bit mask for USB_DCP */ 344 #define _USB_STATUS_DCP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ 345 #define USB_STATUS_DCP_DEFAULT (_USB_STATUS_DCP_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_STATUS */ 346 #define USB_STATUS_ACAFS (0x1UL << 12) /**< ACA Full Speed TypeB Device */ 347 #define _USB_STATUS_ACAFS_SHIFT 12 /**< Shift value for USB_ACAFS */ 348 #define _USB_STATUS_ACAFS_MASK 0x1000UL /**< Bit mask for USB_ACAFS */ 349 #define _USB_STATUS_ACAFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ 350 #define USB_STATUS_ACAFS_DEFAULT (_USB_STATUS_ACAFS_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_STATUS */ 351 #define USB_STATUS_ACALS (0x1UL << 13) /**< ACA Low Speed TypeB Device */ 352 #define _USB_STATUS_ACALS_SHIFT 13 /**< Shift value for USB_ACALS */ 353 #define _USB_STATUS_ACALS_MASK 0x2000UL /**< Bit mask for USB_ACALS */ 354 #define _USB_STATUS_ACALS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ 355 #define USB_STATUS_ACALS_DEFAULT (_USB_STATUS_ACALS_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_STATUS */ 356 #define USB_STATUS_USBCDBUSY (0x1UL << 15) /**< USB Charger Detect Busy */ 357 #define _USB_STATUS_USBCDBUSY_SHIFT 15 /**< Shift value for USB_USBCDBUSY */ 358 #define _USB_STATUS_USBCDBUSY_MASK 0x8000UL /**< Bit mask for USB_USBCDBUSY */ 359 #define _USB_STATUS_USBCDBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ 360 #define USB_STATUS_USBCDBUSY_DEFAULT (_USB_STATUS_USBCDBUSY_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_STATUS */ 361 362 /* Bit fields for USB IF */ 363 #define _USB_IF_RESETVALUE 0x00000000UL /**< Default value for USB_IF */ 364 #define _USB_IF_MASK 0x00000F03UL /**< Mask for USB_IF */ 365 #define USB_IF_VBUSDETH (0x1UL << 0) /**< VBUS Detect High Interrupt Flag */ 366 #define _USB_IF_VBUSDETH_SHIFT 0 /**< Shift value for USB_VBUSDETH */ 367 #define _USB_IF_VBUSDETH_MASK 0x1UL /**< Bit mask for USB_VBUSDETH */ 368 #define _USB_IF_VBUSDETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IF */ 369 #define USB_IF_VBUSDETH_DEFAULT (_USB_IF_VBUSDETH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IF */ 370 #define USB_IF_VBUSDETL (0x1UL << 1) /**< VBUS Detect Low Interrupt Flag */ 371 #define _USB_IF_VBUSDETL_SHIFT 1 /**< Shift value for USB_VBUSDETL */ 372 #define _USB_IF_VBUSDETL_MASK 0x2UL /**< Bit mask for USB_VBUSDETL */ 373 #define _USB_IF_VBUSDETL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IF */ 374 #define USB_IF_VBUSDETL_DEFAULT (_USB_IF_VBUSDETL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IF */ 375 #define USB_IF_ERR (0x1UL << 8) /**< Detection Error Interrupt Flag */ 376 #define _USB_IF_ERR_SHIFT 8 /**< Shift value for USB_ERR */ 377 #define _USB_IF_ERR_MASK 0x100UL /**< Bit mask for USB_ERR */ 378 #define _USB_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IF */ 379 #define USB_IF_ERR_DEFAULT (_USB_IF_ERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_IF */ 380 #define USB_IF_DCD (0x1UL << 9) /**< Data Contact Detection Complete Interrupt Flag */ 381 #define _USB_IF_DCD_SHIFT 9 /**< Shift value for USB_DCD */ 382 #define _USB_IF_DCD_MASK 0x200UL /**< Bit mask for USB_DCD */ 383 #define _USB_IF_DCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IF */ 384 #define USB_IF_DCD_DEFAULT (_USB_IF_DCD_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_IF */ 385 #define USB_IF_PD (0x1UL << 10) /**< Primary Detection Complete Interrupt Flag */ 386 #define _USB_IF_PD_SHIFT 10 /**< Shift value for USB_PD */ 387 #define _USB_IF_PD_MASK 0x400UL /**< Bit mask for USB_PD */ 388 #define _USB_IF_PD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IF */ 389 #define USB_IF_PD_DEFAULT (_USB_IF_PD_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_IF */ 390 #define USB_IF_SD (0x1UL << 11) /**< Secondary Detection Complete Interrupt Flag */ 391 #define _USB_IF_SD_SHIFT 11 /**< Shift value for USB_SD */ 392 #define _USB_IF_SD_MASK 0x800UL /**< Bit mask for USB_SD */ 393 #define _USB_IF_SD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IF */ 394 #define USB_IF_SD_DEFAULT (_USB_IF_SD_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_IF */ 395 396 /* Bit fields for USB IFS */ 397 #define _USB_IFS_RESETVALUE 0x00000000UL /**< Default value for USB_IFS */ 398 #define _USB_IFS_MASK 0x00000F03UL /**< Mask for USB_IFS */ 399 #define USB_IFS_VBUSDETH (0x1UL << 0) /**< Set VBUSDETH Interrupt Flag */ 400 #define _USB_IFS_VBUSDETH_SHIFT 0 /**< Shift value for USB_VBUSDETH */ 401 #define _USB_IFS_VBUSDETH_MASK 0x1UL /**< Bit mask for USB_VBUSDETH */ 402 #define _USB_IFS_VBUSDETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ 403 #define USB_IFS_VBUSDETH_DEFAULT (_USB_IFS_VBUSDETH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IFS */ 404 #define USB_IFS_VBUSDETL (0x1UL << 1) /**< Set VBUSDETL Interrupt Flag */ 405 #define _USB_IFS_VBUSDETL_SHIFT 1 /**< Shift value for USB_VBUSDETL */ 406 #define _USB_IFS_VBUSDETL_MASK 0x2UL /**< Bit mask for USB_VBUSDETL */ 407 #define _USB_IFS_VBUSDETL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ 408 #define USB_IFS_VBUSDETL_DEFAULT (_USB_IFS_VBUSDETL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IFS */ 409 #define USB_IFS_ERR (0x1UL << 8) /**< Set ERR Interrupt Flag */ 410 #define _USB_IFS_ERR_SHIFT 8 /**< Shift value for USB_ERR */ 411 #define _USB_IFS_ERR_MASK 0x100UL /**< Bit mask for USB_ERR */ 412 #define _USB_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ 413 #define USB_IFS_ERR_DEFAULT (_USB_IFS_ERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_IFS */ 414 #define USB_IFS_DCD (0x1UL << 9) /**< Set DCD Interrupt Flag */ 415 #define _USB_IFS_DCD_SHIFT 9 /**< Shift value for USB_DCD */ 416 #define _USB_IFS_DCD_MASK 0x200UL /**< Bit mask for USB_DCD */ 417 #define _USB_IFS_DCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ 418 #define USB_IFS_DCD_DEFAULT (_USB_IFS_DCD_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_IFS */ 419 #define USB_IFS_PD (0x1UL << 10) /**< Set PD Interrupt Flag */ 420 #define _USB_IFS_PD_SHIFT 10 /**< Shift value for USB_PD */ 421 #define _USB_IFS_PD_MASK 0x400UL /**< Bit mask for USB_PD */ 422 #define _USB_IFS_PD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ 423 #define USB_IFS_PD_DEFAULT (_USB_IFS_PD_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_IFS */ 424 #define USB_IFS_SD (0x1UL << 11) /**< Set SD Interrupt Flag */ 425 #define _USB_IFS_SD_SHIFT 11 /**< Shift value for USB_SD */ 426 #define _USB_IFS_SD_MASK 0x800UL /**< Bit mask for USB_SD */ 427 #define _USB_IFS_SD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ 428 #define USB_IFS_SD_DEFAULT (_USB_IFS_SD_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_IFS */ 429 430 /* Bit fields for USB IFC */ 431 #define _USB_IFC_RESETVALUE 0x00000000UL /**< Default value for USB_IFC */ 432 #define _USB_IFC_MASK 0x00000F03UL /**< Mask for USB_IFC */ 433 #define USB_IFC_VBUSDETH (0x1UL << 0) /**< Clear VBUSDETH Interrupt Flag */ 434 #define _USB_IFC_VBUSDETH_SHIFT 0 /**< Shift value for USB_VBUSDETH */ 435 #define _USB_IFC_VBUSDETH_MASK 0x1UL /**< Bit mask for USB_VBUSDETH */ 436 #define _USB_IFC_VBUSDETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ 437 #define USB_IFC_VBUSDETH_DEFAULT (_USB_IFC_VBUSDETH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IFC */ 438 #define USB_IFC_VBUSDETL (0x1UL << 1) /**< Clear VBUSDETL Interrupt Flag */ 439 #define _USB_IFC_VBUSDETL_SHIFT 1 /**< Shift value for USB_VBUSDETL */ 440 #define _USB_IFC_VBUSDETL_MASK 0x2UL /**< Bit mask for USB_VBUSDETL */ 441 #define _USB_IFC_VBUSDETL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ 442 #define USB_IFC_VBUSDETL_DEFAULT (_USB_IFC_VBUSDETL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IFC */ 443 #define USB_IFC_ERR (0x1UL << 8) /**< Clear ERR Interrupt Flag */ 444 #define _USB_IFC_ERR_SHIFT 8 /**< Shift value for USB_ERR */ 445 #define _USB_IFC_ERR_MASK 0x100UL /**< Bit mask for USB_ERR */ 446 #define _USB_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ 447 #define USB_IFC_ERR_DEFAULT (_USB_IFC_ERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_IFC */ 448 #define USB_IFC_DCD (0x1UL << 9) /**< Clear DCD Interrupt Flag */ 449 #define _USB_IFC_DCD_SHIFT 9 /**< Shift value for USB_DCD */ 450 #define _USB_IFC_DCD_MASK 0x200UL /**< Bit mask for USB_DCD */ 451 #define _USB_IFC_DCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ 452 #define USB_IFC_DCD_DEFAULT (_USB_IFC_DCD_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_IFC */ 453 #define USB_IFC_PD (0x1UL << 10) /**< Clear PD Interrupt Flag */ 454 #define _USB_IFC_PD_SHIFT 10 /**< Shift value for USB_PD */ 455 #define _USB_IFC_PD_MASK 0x400UL /**< Bit mask for USB_PD */ 456 #define _USB_IFC_PD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ 457 #define USB_IFC_PD_DEFAULT (_USB_IFC_PD_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_IFC */ 458 #define USB_IFC_SD (0x1UL << 11) /**< Clear SD Interrupt Flag */ 459 #define _USB_IFC_SD_SHIFT 11 /**< Shift value for USB_SD */ 460 #define _USB_IFC_SD_MASK 0x800UL /**< Bit mask for USB_SD */ 461 #define _USB_IFC_SD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ 462 #define USB_IFC_SD_DEFAULT (_USB_IFC_SD_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_IFC */ 463 464 /* Bit fields for USB IEN */ 465 #define _USB_IEN_RESETVALUE 0x00000000UL /**< Default value for USB_IEN */ 466 #define _USB_IEN_MASK 0x00000F03UL /**< Mask for USB_IEN */ 467 #define USB_IEN_VBUSDETH (0x1UL << 0) /**< VBUSDETH Interrupt Enable */ 468 #define _USB_IEN_VBUSDETH_SHIFT 0 /**< Shift value for USB_VBUSDETH */ 469 #define _USB_IEN_VBUSDETH_MASK 0x1UL /**< Bit mask for USB_VBUSDETH */ 470 #define _USB_IEN_VBUSDETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ 471 #define USB_IEN_VBUSDETH_DEFAULT (_USB_IEN_VBUSDETH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IEN */ 472 #define USB_IEN_VBUSDETL (0x1UL << 1) /**< VBUSDETL Interrupt Enable */ 473 #define _USB_IEN_VBUSDETL_SHIFT 1 /**< Shift value for USB_VBUSDETL */ 474 #define _USB_IEN_VBUSDETL_MASK 0x2UL /**< Bit mask for USB_VBUSDETL */ 475 #define _USB_IEN_VBUSDETL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ 476 #define USB_IEN_VBUSDETL_DEFAULT (_USB_IEN_VBUSDETL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IEN */ 477 #define USB_IEN_ERR (0x1UL << 8) /**< ERR Interrupt Enable */ 478 #define _USB_IEN_ERR_SHIFT 8 /**< Shift value for USB_ERR */ 479 #define _USB_IEN_ERR_MASK 0x100UL /**< Bit mask for USB_ERR */ 480 #define _USB_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ 481 #define USB_IEN_ERR_DEFAULT (_USB_IEN_ERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_IEN */ 482 #define USB_IEN_DCD (0x1UL << 9) /**< DCD Interrupt Enable */ 483 #define _USB_IEN_DCD_SHIFT 9 /**< Shift value for USB_DCD */ 484 #define _USB_IEN_DCD_MASK 0x200UL /**< Bit mask for USB_DCD */ 485 #define _USB_IEN_DCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ 486 #define USB_IEN_DCD_DEFAULT (_USB_IEN_DCD_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_IEN */ 487 #define USB_IEN_PD (0x1UL << 10) /**< PD Interrupt Enable */ 488 #define _USB_IEN_PD_SHIFT 10 /**< Shift value for USB_PD */ 489 #define _USB_IEN_PD_MASK 0x400UL /**< Bit mask for USB_PD */ 490 #define _USB_IEN_PD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ 491 #define USB_IEN_PD_DEFAULT (_USB_IEN_PD_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_IEN */ 492 #define USB_IEN_SD (0x1UL << 11) /**< SD Interrupt Enable */ 493 #define _USB_IEN_SD_SHIFT 11 /**< Shift value for USB_SD */ 494 #define _USB_IEN_SD_MASK 0x800UL /**< Bit mask for USB_SD */ 495 #define _USB_IEN_SD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ 496 #define USB_IEN_SD_DEFAULT (_USB_IEN_SD_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_IEN */ 497 498 /* Bit fields for USB ROUTE */ 499 #define _USB_ROUTE_RESETVALUE 0x00000000UL /**< Default value for USB_ROUTE */ 500 #define _USB_ROUTE_MASK 0x00000003UL /**< Mask for USB_ROUTE */ 501 #define USB_ROUTE_PHYPEN (0x1UL << 0) /**< USB PHY Pin Enable */ 502 #define _USB_ROUTE_PHYPEN_SHIFT 0 /**< Shift value for USB_PHYPEN */ 503 #define _USB_ROUTE_PHYPEN_MASK 0x1UL /**< Bit mask for USB_PHYPEN */ 504 #define _USB_ROUTE_PHYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTE */ 505 #define USB_ROUTE_PHYPEN_DEFAULT (_USB_ROUTE_PHYPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_ROUTE */ 506 #define USB_ROUTE_VBUSENPEN (0x1UL << 1) /**< VBUSEN Pin Enable */ 507 #define _USB_ROUTE_VBUSENPEN_SHIFT 1 /**< Shift value for USB_VBUSENPEN */ 508 #define _USB_ROUTE_VBUSENPEN_MASK 0x2UL /**< Bit mask for USB_VBUSENPEN */ 509 #define _USB_ROUTE_VBUSENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTE */ 510 #define USB_ROUTE_VBUSENPEN_DEFAULT (_USB_ROUTE_VBUSENPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_ROUTE */ 511 512 /* Bit fields for USB CDCONF */ 513 #define _USB_CDCONF_RESETVALUE 0x00000000UL /**< Default value for USB_CDCONF */ 514 #define _USB_CDCONF_MASK 0x000003FFUL /**< Mask for USB_CDCONF */ 515 #define _USB_CDCONF_DCDTOCONF_SHIFT 0 /**< Shift value for USB_DCDTOCONF */ 516 #define _USB_CDCONF_DCDTOCONF_MASK 0x3FFUL /**< Bit mask for USB_DCDTOCONF */ 517 #define _USB_CDCONF_DCDTOCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CDCONF */ 518 #define USB_CDCONF_DCDTOCONF_DEFAULT (_USB_CDCONF_DCDTOCONF_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_CDCONF */ 519 520 /* Bit fields for USB CMD */ 521 #define _USB_CMD_RESETVALUE 0x00000000UL /**< Default value for USB_CMD */ 522 #define _USB_CMD_MASK 0x00000003UL /**< Mask for USB_CMD */ 523 #define USB_CMD_STARTCD (0x1UL << 0) /**< Start Charger Detection Enabled */ 524 #define _USB_CMD_STARTCD_SHIFT 0 /**< Shift value for USB_STARTCD */ 525 #define _USB_CMD_STARTCD_MASK 0x1UL /**< Bit mask for USB_STARTCD */ 526 #define _USB_CMD_STARTCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CMD */ 527 #define USB_CMD_STARTCD_DEFAULT (_USB_CMD_STARTCD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_CMD */ 528 #define USB_CMD_STOPCD (0x1UL << 1) /**< Start Charger Detection in Progress */ 529 #define _USB_CMD_STOPCD_SHIFT 1 /**< Shift value for USB_STOPCD */ 530 #define _USB_CMD_STOPCD_MASK 0x2UL /**< Bit mask for USB_STOPCD */ 531 #define _USB_CMD_STOPCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CMD */ 532 #define USB_CMD_STOPCD_DEFAULT (_USB_CMD_STOPCD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_CMD */ 533 534 /* Bit fields for USB DATTRIM1 */ 535 #define _USB_DATTRIM1_RESETVALUE 0x00000024UL /**< Default value for USB_DATTRIM1 */ 536 #define _USB_DATTRIM1_MASK 0x000FFFBFUL /**< Mask for USB_DATTRIM1 */ 537 #define _USB_DATTRIM1_ROUT_SHIFT 0 /**< Shift value for USB_ROUT */ 538 #define _USB_DATTRIM1_ROUT_MASK 0x3FUL /**< Bit mask for USB_ROUT */ 539 #define _USB_DATTRIM1_ROUT_DEFAULT 0x00000024UL /**< Mode DEFAULT for USB_DATTRIM1 */ 540 #define USB_DATTRIM1_ROUT_DEFAULT (_USB_DATTRIM1_ROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ 541 #define USB_DATTRIM1_ENDLYPULLUP (0x1UL << 7) /**< Enables Delay of Pull in TX Mode for Both FS and LS */ 542 #define _USB_DATTRIM1_ENDLYPULLUP_SHIFT 7 /**< Shift value for USB_ENDLYPULLUP */ 543 #define _USB_DATTRIM1_ENDLYPULLUP_MASK 0x80UL /**< Bit mask for USB_ENDLYPULLUP */ 544 #define _USB_DATTRIM1_ENDLYPULLUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ 545 #define USB_DATTRIM1_ENDLYPULLUP_DEFAULT (_USB_DATTRIM1_ENDLYPULLUP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ 546 #define _USB_DATTRIM1_DLYPULLUPFS_SHIFT 8 /**< Shift value for USB_DLYPULLUPFS */ 547 #define _USB_DATTRIM1_DLYPULLUPFS_MASK 0x300UL /**< Bit mask for USB_DLYPULLUPFS */ 548 #define _USB_DATTRIM1_DLYPULLUPFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ 549 #define USB_DATTRIM1_DLYPULLUPFS_DEFAULT (_USB_DATTRIM1_DLYPULLUPFS_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ 550 #define _USB_DATTRIM1_VCRSFS_SHIFT 10 /**< Shift value for USB_VCRSFS */ 551 #define _USB_DATTRIM1_VCRSFS_MASK 0xC00UL /**< Bit mask for USB_VCRSFS */ 552 #define _USB_DATTRIM1_VCRSFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ 553 #define USB_DATTRIM1_VCRSFS_DEFAULT (_USB_DATTRIM1_VCRSFS_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ 554 #define _USB_DATTRIM1_TFDMFS_SHIFT 12 /**< Shift value for USB_TFDMFS */ 555 #define _USB_DATTRIM1_TFDMFS_MASK 0x3000UL /**< Bit mask for USB_TFDMFS */ 556 #define _USB_DATTRIM1_TFDMFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ 557 #define USB_DATTRIM1_TFDMFS_DEFAULT (_USB_DATTRIM1_TFDMFS_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ 558 #define _USB_DATTRIM1_TRDMFS_SHIFT 14 /**< Shift value for USB_TRDMFS */ 559 #define _USB_DATTRIM1_TRDMFS_MASK 0xC000UL /**< Bit mask for USB_TRDMFS */ 560 #define _USB_DATTRIM1_TRDMFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ 561 #define USB_DATTRIM1_TRDMFS_DEFAULT (_USB_DATTRIM1_TRDMFS_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ 562 #define _USB_DATTRIM1_TFDPFS_SHIFT 16 /**< Shift value for USB_TFDPFS */ 563 #define _USB_DATTRIM1_TFDPFS_MASK 0x30000UL /**< Bit mask for USB_TFDPFS */ 564 #define _USB_DATTRIM1_TFDPFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ 565 #define USB_DATTRIM1_TFDPFS_DEFAULT (_USB_DATTRIM1_TFDPFS_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ 566 #define _USB_DATTRIM1_TRDPFS_SHIFT 18 /**< Shift value for USB_TRDPFS */ 567 #define _USB_DATTRIM1_TRDPFS_MASK 0xC0000UL /**< Bit mask for USB_TRDPFS */ 568 #define _USB_DATTRIM1_TRDPFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ 569 #define USB_DATTRIM1_TRDPFS_DEFAULT (_USB_DATTRIM1_TRDPFS_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ 570 571 /* Bit fields for USB LEMCTRL */ 572 #define _USB_LEMCTRL_RESETVALUE 0x00000067UL /**< Default value for USB_LEMCTRL */ 573 #define _USB_LEMCTRL_MASK 0x000003FFUL /**< Mask for USB_LEMCTRL */ 574 #define _USB_LEMCTRL_TIMEBASE_SHIFT 0 /**< Shift value for USB_TIMEBASE */ 575 #define _USB_LEMCTRL_TIMEBASE_MASK 0x3FFUL /**< Bit mask for USB_TIMEBASE */ 576 #define _USB_LEMCTRL_TIMEBASE_DEFAULT 0x00000067UL /**< Mode DEFAULT for USB_LEMCTRL */ 577 #define USB_LEMCTRL_TIMEBASE_DEFAULT (_USB_LEMCTRL_TIMEBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_LEMCTRL */ 578 579 /* Bit fields for USB ROUTELOC0 */ 580 #define _USB_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USB_ROUTELOC0 */ 581 #define _USB_ROUTELOC0_MASK 0x00000003UL /**< Mask for USB_ROUTELOC0 */ 582 #define _USB_ROUTELOC0_VBUSENPENLOC_SHIFT 0 /**< Shift value for USB_VBUSENPENLOC */ 583 #define _USB_ROUTELOC0_VBUSENPENLOC_MASK 0x3UL /**< Bit mask for USB_VBUSENPENLOC */ 584 #define _USB_ROUTELOC0_VBUSENPENLOC_LOC0 0x00000000UL /**< Mode LOC0 for USB_ROUTELOC0 */ 585 #define _USB_ROUTELOC0_VBUSENPENLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTELOC0 */ 586 #define _USB_ROUTELOC0_VBUSENPENLOC_LOC1 0x00000001UL /**< Mode LOC1 for USB_ROUTELOC0 */ 587 #define _USB_ROUTELOC0_VBUSENPENLOC_LOC2 0x00000002UL /**< Mode LOC2 for USB_ROUTELOC0 */ 588 #define USB_ROUTELOC0_VBUSENPENLOC_LOC0 (_USB_ROUTELOC0_VBUSENPENLOC_LOC0 << 0) /**< Shifted mode LOC0 for USB_ROUTELOC0 */ 589 #define USB_ROUTELOC0_VBUSENPENLOC_DEFAULT (_USB_ROUTELOC0_VBUSENPENLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_ROUTELOC0 */ 590 #define USB_ROUTELOC0_VBUSENPENLOC_LOC1 (_USB_ROUTELOC0_VBUSENPENLOC_LOC1 << 0) /**< Shifted mode LOC1 for USB_ROUTELOC0 */ 591 #define USB_ROUTELOC0_VBUSENPENLOC_LOC2 (_USB_ROUTELOC0_VBUSENPENLOC_LOC2 << 0) /**< Shifted mode LOC2 for USB_ROUTELOC0 */ 592 593 /* Bit fields for USB GOTGCTL */ 594 #define _USB_GOTGCTL_RESETVALUE 0x00010000UL /**< Default value for USB_GOTGCTL */ 595 #define _USB_GOTGCTL_MASK 0x003F9FFFUL /**< Mask for USB_GOTGCTL */ 596 #define USB_GOTGCTL_SESREQSCS (0x1UL << 0) /**< Session Request Success */ 597 #define _USB_GOTGCTL_SESREQSCS_SHIFT 0 /**< Shift value for USB_SESREQSCS */ 598 #define _USB_GOTGCTL_SESREQSCS_MASK 0x1UL /**< Bit mask for USB_SESREQSCS */ 599 #define _USB_GOTGCTL_SESREQSCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 600 #define USB_GOTGCTL_SESREQSCS_DEFAULT (_USB_GOTGCTL_SESREQSCS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 601 #define USB_GOTGCTL_SESREQ (0x1UL << 1) /**< Session Request */ 602 #define _USB_GOTGCTL_SESREQ_SHIFT 1 /**< Shift value for USB_SESREQ */ 603 #define _USB_GOTGCTL_SESREQ_MASK 0x2UL /**< Bit mask for USB_SESREQ */ 604 #define _USB_GOTGCTL_SESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 605 #define USB_GOTGCTL_SESREQ_DEFAULT (_USB_GOTGCTL_SESREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 606 #define USB_GOTGCTL_VBVALIDOVEN (0x1UL << 2) /**< VBUS Valid Override Enable */ 607 #define _USB_GOTGCTL_VBVALIDOVEN_SHIFT 2 /**< Shift value for USB_VBVALIDOVEN */ 608 #define _USB_GOTGCTL_VBVALIDOVEN_MASK 0x4UL /**< Bit mask for USB_VBVALIDOVEN */ 609 #define _USB_GOTGCTL_VBVALIDOVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 610 #define USB_GOTGCTL_VBVALIDOVEN_DEFAULT (_USB_GOTGCTL_VBVALIDOVEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 611 #define USB_GOTGCTL_VBVALIDOVVAL (0x1UL << 3) /**< VBUS Valid OverrideValue */ 612 #define _USB_GOTGCTL_VBVALIDOVVAL_SHIFT 3 /**< Shift value for USB_VBVALIDOVVAL */ 613 #define _USB_GOTGCTL_VBVALIDOVVAL_MASK 0x8UL /**< Bit mask for USB_VBVALIDOVVAL */ 614 #define _USB_GOTGCTL_VBVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 615 #define USB_GOTGCTL_VBVALIDOVVAL_DEFAULT (_USB_GOTGCTL_VBVALIDOVVAL_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 616 #define USB_GOTGCTL_AVALIDOVEN (0x1UL << 4) /**< A-Peripheral Session Valid Override Enable */ 617 #define _USB_GOTGCTL_AVALIDOVEN_SHIFT 4 /**< Shift value for USB_AVALIDOVEN */ 618 #define _USB_GOTGCTL_AVALIDOVEN_MASK 0x10UL /**< Bit mask for USB_AVALIDOVEN */ 619 #define _USB_GOTGCTL_AVALIDOVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 620 #define USB_GOTGCTL_AVALIDOVEN_DEFAULT (_USB_GOTGCTL_AVALIDOVEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 621 #define USB_GOTGCTL_AVALIDOVVAL (0x1UL << 5) /**< A-Peripheral Session Valid OverrideValue */ 622 #define _USB_GOTGCTL_AVALIDOVVAL_SHIFT 5 /**< Shift value for USB_AVALIDOVVAL */ 623 #define _USB_GOTGCTL_AVALIDOVVAL_MASK 0x20UL /**< Bit mask for USB_AVALIDOVVAL */ 624 #define _USB_GOTGCTL_AVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 625 #define USB_GOTGCTL_AVALIDOVVAL_DEFAULT (_USB_GOTGCTL_AVALIDOVVAL_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 626 #define USB_GOTGCTL_BVALIDOVEN (0x1UL << 6) /**< B-Peripheral Session Valid Override Enable */ 627 #define _USB_GOTGCTL_BVALIDOVEN_SHIFT 6 /**< Shift value for USB_BVALIDOVEN */ 628 #define _USB_GOTGCTL_BVALIDOVEN_MASK 0x40UL /**< Bit mask for USB_BVALIDOVEN */ 629 #define _USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 630 #define USB_GOTGCTL_BVALIDOVEN_DEFAULT (_USB_GOTGCTL_BVALIDOVEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 631 #define USB_GOTGCTL_BVALIDOVVAL (0x1UL << 7) /**< B-Peripheral Session Valid OverrideValue */ 632 #define _USB_GOTGCTL_BVALIDOVVAL_SHIFT 7 /**< Shift value for USB_BVALIDOVVAL */ 633 #define _USB_GOTGCTL_BVALIDOVVAL_MASK 0x80UL /**< Bit mask for USB_BVALIDOVVAL */ 634 #define _USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 635 #define USB_GOTGCTL_BVALIDOVVAL_DEFAULT (_USB_GOTGCTL_BVALIDOVVAL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 636 #define USB_GOTGCTL_HSTNEGSCS (0x1UL << 8) /**< Host Negotiation Success */ 637 #define _USB_GOTGCTL_HSTNEGSCS_SHIFT 8 /**< Shift value for USB_HSTNEGSCS */ 638 #define _USB_GOTGCTL_HSTNEGSCS_MASK 0x100UL /**< Bit mask for USB_HSTNEGSCS */ 639 #define _USB_GOTGCTL_HSTNEGSCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 640 #define USB_GOTGCTL_HSTNEGSCS_DEFAULT (_USB_GOTGCTL_HSTNEGSCS_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 641 #define USB_GOTGCTL_HNPREQ (0x1UL << 9) /**< HNP Request */ 642 #define _USB_GOTGCTL_HNPREQ_SHIFT 9 /**< Shift value for USB_HNPREQ */ 643 #define _USB_GOTGCTL_HNPREQ_MASK 0x200UL /**< Bit mask for USB_HNPREQ */ 644 #define _USB_GOTGCTL_HNPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 645 #define USB_GOTGCTL_HNPREQ_DEFAULT (_USB_GOTGCTL_HNPREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 646 #define USB_GOTGCTL_HSTSETHNPEN (0x1UL << 10) /**< Host Set HNP Enable */ 647 #define _USB_GOTGCTL_HSTSETHNPEN_SHIFT 10 /**< Shift value for USB_HSTSETHNPEN */ 648 #define _USB_GOTGCTL_HSTSETHNPEN_MASK 0x400UL /**< Bit mask for USB_HSTSETHNPEN */ 649 #define _USB_GOTGCTL_HSTSETHNPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 650 #define USB_GOTGCTL_HSTSETHNPEN_DEFAULT (_USB_GOTGCTL_HSTSETHNPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 651 #define USB_GOTGCTL_DEVHNPEN (0x1UL << 11) /**< Device HNP Enabled */ 652 #define _USB_GOTGCTL_DEVHNPEN_SHIFT 11 /**< Shift value for USB_DEVHNPEN */ 653 #define _USB_GOTGCTL_DEVHNPEN_MASK 0x800UL /**< Bit mask for USB_DEVHNPEN */ 654 #define _USB_GOTGCTL_DEVHNPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 655 #define USB_GOTGCTL_DEVHNPEN_DEFAULT (_USB_GOTGCTL_DEVHNPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 656 #define USB_GOTGCTL_EHEN (0x1UL << 12) /**< Embedded Host Enable */ 657 #define _USB_GOTGCTL_EHEN_SHIFT 12 /**< Shift value for USB_EHEN */ 658 #define _USB_GOTGCTL_EHEN_MASK 0x1000UL /**< Bit mask for USB_EHEN */ 659 #define _USB_GOTGCTL_EHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 660 #define USB_GOTGCTL_EHEN_DEFAULT (_USB_GOTGCTL_EHEN_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 661 #define USB_GOTGCTL_DBNCEFLTRBYPASS (0x1UL << 15) /**< Debounce Filter Bypass */ 662 #define _USB_GOTGCTL_DBNCEFLTRBYPASS_SHIFT 15 /**< Shift value for USB_DBNCEFLTRBYPASS */ 663 #define _USB_GOTGCTL_DBNCEFLTRBYPASS_MASK 0x8000UL /**< Bit mask for USB_DBNCEFLTRBYPASS */ 664 #define _USB_GOTGCTL_DBNCEFLTRBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 665 #define USB_GOTGCTL_DBNCEFLTRBYPASS_DEFAULT (_USB_GOTGCTL_DBNCEFLTRBYPASS_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 666 #define USB_GOTGCTL_CONIDSTS (0x1UL << 16) /**< Connector ID Status */ 667 #define _USB_GOTGCTL_CONIDSTS_SHIFT 16 /**< Shift value for USB_CONIDSTS */ 668 #define _USB_GOTGCTL_CONIDSTS_MASK 0x10000UL /**< Bit mask for USB_CONIDSTS */ 669 #define _USB_GOTGCTL_CONIDSTS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GOTGCTL */ 670 #define USB_GOTGCTL_CONIDSTS_DEFAULT (_USB_GOTGCTL_CONIDSTS_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 671 #define USB_GOTGCTL_DBNCTIME (0x1UL << 17) /**< Long/Short Debounce Time */ 672 #define _USB_GOTGCTL_DBNCTIME_SHIFT 17 /**< Shift value for USB_DBNCTIME */ 673 #define _USB_GOTGCTL_DBNCTIME_MASK 0x20000UL /**< Bit mask for USB_DBNCTIME */ 674 #define _USB_GOTGCTL_DBNCTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 675 #define USB_GOTGCTL_DBNCTIME_DEFAULT (_USB_GOTGCTL_DBNCTIME_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 676 #define USB_GOTGCTL_ASESVLD (0x1UL << 18) /**< A-Session Valid */ 677 #define _USB_GOTGCTL_ASESVLD_SHIFT 18 /**< Shift value for USB_ASESVLD */ 678 #define _USB_GOTGCTL_ASESVLD_MASK 0x40000UL /**< Bit mask for USB_ASESVLD */ 679 #define _USB_GOTGCTL_ASESVLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 680 #define USB_GOTGCTL_ASESVLD_DEFAULT (_USB_GOTGCTL_ASESVLD_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 681 #define USB_GOTGCTL_BSESVLD (0x1UL << 19) /**< B-Session Valid */ 682 #define _USB_GOTGCTL_BSESVLD_SHIFT 19 /**< Shift value for USB_BSESVLD */ 683 #define _USB_GOTGCTL_BSESVLD_MASK 0x80000UL /**< Bit mask for USB_BSESVLD */ 684 #define _USB_GOTGCTL_BSESVLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 685 #define USB_GOTGCTL_BSESVLD_DEFAULT (_USB_GOTGCTL_BSESVLD_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 686 #define USB_GOTGCTL_OTGVER (0x1UL << 20) /**< OTG Version */ 687 #define _USB_GOTGCTL_OTGVER_SHIFT 20 /**< Shift value for USB_OTGVER */ 688 #define _USB_GOTGCTL_OTGVER_MASK 0x100000UL /**< Bit mask for USB_OTGVER */ 689 #define _USB_GOTGCTL_OTGVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 690 #define USB_GOTGCTL_OTGVER_DEFAULT (_USB_GOTGCTL_OTGVER_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 691 #define USB_GOTGCTL_CURMOD (0x1UL << 21) /**< Current Mode of Operation */ 692 #define _USB_GOTGCTL_CURMOD_SHIFT 21 /**< Shift value for USB_CURMOD */ 693 #define _USB_GOTGCTL_CURMOD_MASK 0x200000UL /**< Bit mask for USB_CURMOD */ 694 #define _USB_GOTGCTL_CURMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ 695 #define USB_GOTGCTL_CURMOD_DEFAULT (_USB_GOTGCTL_CURMOD_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GOTGCTL */ 696 697 /* Bit fields for USB GOTGINT */ 698 #define _USB_GOTGINT_RESETVALUE 0x00000000UL /**< Default value for USB_GOTGINT */ 699 #define _USB_GOTGINT_MASK 0x000E0304UL /**< Mask for USB_GOTGINT */ 700 #define USB_GOTGINT_SESENDDET (0x1UL << 2) /**< Session End Detected */ 701 #define _USB_GOTGINT_SESENDDET_SHIFT 2 /**< Shift value for USB_SESENDDET */ 702 #define _USB_GOTGINT_SESENDDET_MASK 0x4UL /**< Bit mask for USB_SESENDDET */ 703 #define _USB_GOTGINT_SESENDDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */ 704 #define USB_GOTGINT_SESENDDET_DEFAULT (_USB_GOTGINT_SESENDDET_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GOTGINT */ 705 #define USB_GOTGINT_SESREQSUCSTSCHNG (0x1UL << 8) /**< Session Request Success Status Change */ 706 #define _USB_GOTGINT_SESREQSUCSTSCHNG_SHIFT 8 /**< Shift value for USB_SESREQSUCSTSCHNG */ 707 #define _USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100UL /**< Bit mask for USB_SESREQSUCSTSCHNG */ 708 #define _USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */ 709 #define USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT (_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGINT */ 710 #define USB_GOTGINT_HSTNEGSUCSTSCHNG (0x1UL << 9) /**< Host Negotiation Success Status Change */ 711 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_SHIFT 9 /**< Shift value for USB_HSTNEGSUCSTSCHNG */ 712 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200UL /**< Bit mask for USB_HSTNEGSUCSTSCHNG */ 713 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */ 714 #define USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT (_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGINT */ 715 #define USB_GOTGINT_HSTNEGDET (0x1UL << 17) /**< Host Negotiation Detected */ 716 #define _USB_GOTGINT_HSTNEGDET_SHIFT 17 /**< Shift value for USB_HSTNEGDET */ 717 #define _USB_GOTGINT_HSTNEGDET_MASK 0x20000UL /**< Bit mask for USB_HSTNEGDET */ 718 #define _USB_GOTGINT_HSTNEGDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */ 719 #define USB_GOTGINT_HSTNEGDET_DEFAULT (_USB_GOTGINT_HSTNEGDET_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GOTGINT */ 720 #define USB_GOTGINT_ADEVTOUTCHG (0x1UL << 18) /**< A-Device Timeout Change */ 721 #define _USB_GOTGINT_ADEVTOUTCHG_SHIFT 18 /**< Shift value for USB_ADEVTOUTCHG */ 722 #define _USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000UL /**< Bit mask for USB_ADEVTOUTCHG */ 723 #define _USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */ 724 #define USB_GOTGINT_ADEVTOUTCHG_DEFAULT (_USB_GOTGINT_ADEVTOUTCHG_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GOTGINT */ 725 #define USB_GOTGINT_DBNCEDONE (0x1UL << 19) /**< Debounce Done */ 726 #define _USB_GOTGINT_DBNCEDONE_SHIFT 19 /**< Shift value for USB_DBNCEDONE */ 727 #define _USB_GOTGINT_DBNCEDONE_MASK 0x80000UL /**< Bit mask for USB_DBNCEDONE */ 728 #define _USB_GOTGINT_DBNCEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */ 729 #define USB_GOTGINT_DBNCEDONE_DEFAULT (_USB_GOTGINT_DBNCEDONE_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GOTGINT */ 730 731 /* Bit fields for USB GAHBCFG */ 732 #define _USB_GAHBCFG_RESETVALUE 0x00000000UL /**< Default value for USB_GAHBCFG */ 733 #define _USB_GAHBCFG_MASK 0x00E001BFUL /**< Mask for USB_GAHBCFG */ 734 #define USB_GAHBCFG_GLBLINTRMSK (0x1UL << 0) /**< Global Interrupt Mask */ 735 #define _USB_GAHBCFG_GLBLINTRMSK_SHIFT 0 /**< Shift value for USB_GLBLINTRMSK */ 736 #define _USB_GAHBCFG_GLBLINTRMSK_MASK 0x1UL /**< Bit mask for USB_GLBLINTRMSK */ 737 #define _USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ 738 #define USB_GAHBCFG_GLBLINTRMSK_DEFAULT (_USB_GAHBCFG_GLBLINTRMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GAHBCFG */ 739 #define _USB_GAHBCFG_HBSTLEN_SHIFT 1 /**< Shift value for USB_HBSTLEN */ 740 #define _USB_GAHBCFG_HBSTLEN_MASK 0x1EUL /**< Bit mask for USB_HBSTLEN */ 741 #define _USB_GAHBCFG_HBSTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ 742 #define _USB_GAHBCFG_HBSTLEN_SINGLE 0x00000000UL /**< Mode SINGLE for USB_GAHBCFG */ 743 #define _USB_GAHBCFG_HBSTLEN_INCR 0x00000001UL /**< Mode INCR for USB_GAHBCFG */ 744 #define _USB_GAHBCFG_HBSTLEN_INCR4 0x00000003UL /**< Mode INCR4 for USB_GAHBCFG */ 745 #define _USB_GAHBCFG_HBSTLEN_INCR8 0x00000005UL /**< Mode INCR8 for USB_GAHBCFG */ 746 #define _USB_GAHBCFG_HBSTLEN_INCR16 0x00000007UL /**< Mode INCR16 for USB_GAHBCFG */ 747 #define USB_GAHBCFG_HBSTLEN_DEFAULT (_USB_GAHBCFG_HBSTLEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GAHBCFG */ 748 #define USB_GAHBCFG_HBSTLEN_SINGLE (_USB_GAHBCFG_HBSTLEN_SINGLE << 1) /**< Shifted mode SINGLE for USB_GAHBCFG */ 749 #define USB_GAHBCFG_HBSTLEN_INCR (_USB_GAHBCFG_HBSTLEN_INCR << 1) /**< Shifted mode INCR for USB_GAHBCFG */ 750 #define USB_GAHBCFG_HBSTLEN_INCR4 (_USB_GAHBCFG_HBSTLEN_INCR4 << 1) /**< Shifted mode INCR4 for USB_GAHBCFG */ 751 #define USB_GAHBCFG_HBSTLEN_INCR8 (_USB_GAHBCFG_HBSTLEN_INCR8 << 1) /**< Shifted mode INCR8 for USB_GAHBCFG */ 752 #define USB_GAHBCFG_HBSTLEN_INCR16 (_USB_GAHBCFG_HBSTLEN_INCR16 << 1) /**< Shifted mode INCR16 for USB_GAHBCFG */ 753 #define USB_GAHBCFG_DMAEN (0x1UL << 5) /**< DMA Enable */ 754 #define _USB_GAHBCFG_DMAEN_SHIFT 5 /**< Shift value for USB_DMAEN */ 755 #define _USB_GAHBCFG_DMAEN_MASK 0x20UL /**< Bit mask for USB_DMAEN */ 756 #define _USB_GAHBCFG_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ 757 #define USB_GAHBCFG_DMAEN_DEFAULT (_USB_GAHBCFG_DMAEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GAHBCFG */ 758 #define USB_GAHBCFG_NPTXFEMPLVL (0x1UL << 7) /**< Non-Periodic TxFIFO Empty Level */ 759 #define _USB_GAHBCFG_NPTXFEMPLVL_SHIFT 7 /**< Shift value for USB_NPTXFEMPLVL */ 760 #define _USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80UL /**< Bit mask for USB_NPTXFEMPLVL */ 761 #define _USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ 762 #define _USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY 0x00000000UL /**< Mode HALFEMPTY for USB_GAHBCFG */ 763 #define _USB_GAHBCFG_NPTXFEMPLVL_EMPTY 0x00000001UL /**< Mode EMPTY for USB_GAHBCFG */ 764 #define USB_GAHBCFG_NPTXFEMPLVL_DEFAULT (_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GAHBCFG */ 765 #define USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY (_USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY << 7) /**< Shifted mode HALFEMPTY for USB_GAHBCFG */ 766 #define USB_GAHBCFG_NPTXFEMPLVL_EMPTY (_USB_GAHBCFG_NPTXFEMPLVL_EMPTY << 7) /**< Shifted mode EMPTY for USB_GAHBCFG */ 767 #define USB_GAHBCFG_PTXFEMPLVL (0x1UL << 8) /**< Periodic TxFIFO Empty Level */ 768 #define _USB_GAHBCFG_PTXFEMPLVL_SHIFT 8 /**< Shift value for USB_PTXFEMPLVL */ 769 #define _USB_GAHBCFG_PTXFEMPLVL_MASK 0x100UL /**< Bit mask for USB_PTXFEMPLVL */ 770 #define _USB_GAHBCFG_PTXFEMPLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ 771 #define _USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY 0x00000000UL /**< Mode HALFEMPTY for USB_GAHBCFG */ 772 #define _USB_GAHBCFG_PTXFEMPLVL_EMPTY 0x00000001UL /**< Mode EMPTY for USB_GAHBCFG */ 773 #define USB_GAHBCFG_PTXFEMPLVL_DEFAULT (_USB_GAHBCFG_PTXFEMPLVL_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GAHBCFG */ 774 #define USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY (_USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY << 8) /**< Shifted mode HALFEMPTY for USB_GAHBCFG */ 775 #define USB_GAHBCFG_PTXFEMPLVL_EMPTY (_USB_GAHBCFG_PTXFEMPLVL_EMPTY << 8) /**< Shifted mode EMPTY for USB_GAHBCFG */ 776 #define USB_GAHBCFG_REMMEMSUPP (0x1UL << 21) /**< Remote Memory Support */ 777 #define _USB_GAHBCFG_REMMEMSUPP_SHIFT 21 /**< Shift value for USB_REMMEMSUPP */ 778 #define _USB_GAHBCFG_REMMEMSUPP_MASK 0x200000UL /**< Bit mask for USB_REMMEMSUPP */ 779 #define _USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ 780 #define USB_GAHBCFG_REMMEMSUPP_DEFAULT (_USB_GAHBCFG_REMMEMSUPP_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GAHBCFG */ 781 #define USB_GAHBCFG_NOTIALLDMAWRIT (0x1UL << 22) /**< Notify All Dma Write Transactions */ 782 #define _USB_GAHBCFG_NOTIALLDMAWRIT_SHIFT 22 /**< Shift value for USB_NOTIALLDMAWRIT */ 783 #define _USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000UL /**< Bit mask for USB_NOTIALLDMAWRIT */ 784 #define _USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ 785 #define USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT (_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GAHBCFG */ 786 #define USB_GAHBCFG_AHBSINGLE (0x1UL << 23) /**< AHB Single Support */ 787 #define _USB_GAHBCFG_AHBSINGLE_SHIFT 23 /**< Shift value for USB_AHBSINGLE */ 788 #define _USB_GAHBCFG_AHBSINGLE_MASK 0x800000UL /**< Bit mask for USB_AHBSINGLE */ 789 #define _USB_GAHBCFG_AHBSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ 790 #define USB_GAHBCFG_AHBSINGLE_DEFAULT (_USB_GAHBCFG_AHBSINGLE_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GAHBCFG */ 791 792 /* Bit fields for USB GUSBCFG */ 793 #define _USB_GUSBCFG_RESETVALUE 0x00001400UL /**< Default value for USB_GUSBCFG */ 794 #define _USB_GUSBCFG_MASK 0xF0403F27UL /**< Mask for USB_GUSBCFG */ 795 #define _USB_GUSBCFG_TOUTCAL_SHIFT 0 /**< Shift value for USB_TOUTCAL */ 796 #define _USB_GUSBCFG_TOUTCAL_MASK 0x7UL /**< Bit mask for USB_TOUTCAL */ 797 #define _USB_GUSBCFG_TOUTCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ 798 #define USB_GUSBCFG_TOUTCAL_DEFAULT (_USB_GUSBCFG_TOUTCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GUSBCFG */ 799 #define USB_GUSBCFG_FSINTF (0x1UL << 5) /**< Full-Speed Serial Interface Select */ 800 #define _USB_GUSBCFG_FSINTF_SHIFT 5 /**< Shift value for USB_FSINTF */ 801 #define _USB_GUSBCFG_FSINTF_MASK 0x20UL /**< Bit mask for USB_FSINTF */ 802 #define _USB_GUSBCFG_FSINTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ 803 #define USB_GUSBCFG_FSINTF_DEFAULT (_USB_GUSBCFG_FSINTF_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GUSBCFG */ 804 #define USB_GUSBCFG_SRPCAP (0x1UL << 8) /**< SRP-Capable */ 805 #define _USB_GUSBCFG_SRPCAP_SHIFT 8 /**< Shift value for USB_SRPCAP */ 806 #define _USB_GUSBCFG_SRPCAP_MASK 0x100UL /**< Bit mask for USB_SRPCAP */ 807 #define _USB_GUSBCFG_SRPCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ 808 #define USB_GUSBCFG_SRPCAP_DEFAULT (_USB_GUSBCFG_SRPCAP_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GUSBCFG */ 809 #define USB_GUSBCFG_HNPCAP (0x1UL << 9) /**< HNP-Capable */ 810 #define _USB_GUSBCFG_HNPCAP_SHIFT 9 /**< Shift value for USB_HNPCAP */ 811 #define _USB_GUSBCFG_HNPCAP_MASK 0x200UL /**< Bit mask for USB_HNPCAP */ 812 #define _USB_GUSBCFG_HNPCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ 813 #define USB_GUSBCFG_HNPCAP_DEFAULT (_USB_GUSBCFG_HNPCAP_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GUSBCFG */ 814 #define _USB_GUSBCFG_USBTRDTIM_SHIFT 10 /**< Shift value for USB_USBTRDTIM */ 815 #define _USB_GUSBCFG_USBTRDTIM_MASK 0x3C00UL /**< Bit mask for USB_USBTRDTIM */ 816 #define _USB_GUSBCFG_USBTRDTIM_DEFAULT 0x00000005UL /**< Mode DEFAULT for USB_GUSBCFG */ 817 #define USB_GUSBCFG_USBTRDTIM_DEFAULT (_USB_GUSBCFG_USBTRDTIM_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GUSBCFG */ 818 #define USB_GUSBCFG_TERMSELDLPULSE (0x1UL << 22) /**< TermSel DLine Pulsing Selection */ 819 #define _USB_GUSBCFG_TERMSELDLPULSE_SHIFT 22 /**< Shift value for USB_TERMSELDLPULSE */ 820 #define _USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000UL /**< Bit mask for USB_TERMSELDLPULSE */ 821 #define _USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ 822 #define _USB_GUSBCFG_TERMSELDLPULSE_TXVALID 0x00000000UL /**< Mode TXVALID for USB_GUSBCFG */ 823 #define _USB_GUSBCFG_TERMSELDLPULSE_TERMSEL 0x00000001UL /**< Mode TERMSEL for USB_GUSBCFG */ 824 #define USB_GUSBCFG_TERMSELDLPULSE_DEFAULT (_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GUSBCFG */ 825 #define USB_GUSBCFG_TERMSELDLPULSE_TXVALID (_USB_GUSBCFG_TERMSELDLPULSE_TXVALID << 22) /**< Shifted mode TXVALID for USB_GUSBCFG */ 826 #define USB_GUSBCFG_TERMSELDLPULSE_TERMSEL (_USB_GUSBCFG_TERMSELDLPULSE_TERMSEL << 22) /**< Shifted mode TERMSEL for USB_GUSBCFG */ 827 #define USB_GUSBCFG_TXENDDELAY (0x1UL << 28) /**< Tx End Delay */ 828 #define _USB_GUSBCFG_TXENDDELAY_SHIFT 28 /**< Shift value for USB_TXENDDELAY */ 829 #define _USB_GUSBCFG_TXENDDELAY_MASK 0x10000000UL /**< Bit mask for USB_TXENDDELAY */ 830 #define _USB_GUSBCFG_TXENDDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ 831 #define USB_GUSBCFG_TXENDDELAY_DEFAULT (_USB_GUSBCFG_TXENDDELAY_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GUSBCFG */ 832 #define USB_GUSBCFG_FORCEHSTMODE (0x1UL << 29) /**< Force Host Mode */ 833 #define _USB_GUSBCFG_FORCEHSTMODE_SHIFT 29 /**< Shift value for USB_FORCEHSTMODE */ 834 #define _USB_GUSBCFG_FORCEHSTMODE_MASK 0x20000000UL /**< Bit mask for USB_FORCEHSTMODE */ 835 #define _USB_GUSBCFG_FORCEHSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ 836 #define USB_GUSBCFG_FORCEHSTMODE_DEFAULT (_USB_GUSBCFG_FORCEHSTMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GUSBCFG */ 837 #define USB_GUSBCFG_FORCEDEVMODE (0x1UL << 30) /**< Force Device Mode */ 838 #define _USB_GUSBCFG_FORCEDEVMODE_SHIFT 30 /**< Shift value for USB_FORCEDEVMODE */ 839 #define _USB_GUSBCFG_FORCEDEVMODE_MASK 0x40000000UL /**< Bit mask for USB_FORCEDEVMODE */ 840 #define _USB_GUSBCFG_FORCEDEVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ 841 #define USB_GUSBCFG_FORCEDEVMODE_DEFAULT (_USB_GUSBCFG_FORCEDEVMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GUSBCFG */ 842 #define USB_GUSBCFG_CORRUPTTXPKT (0x1UL << 31) /**< Corrupt Tx packet (host and device) */ 843 #define _USB_GUSBCFG_CORRUPTTXPKT_SHIFT 31 /**< Shift value for USB_CORRUPTTXPKT */ 844 #define _USB_GUSBCFG_CORRUPTTXPKT_MASK 0x80000000UL /**< Bit mask for USB_CORRUPTTXPKT */ 845 #define _USB_GUSBCFG_CORRUPTTXPKT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ 846 #define USB_GUSBCFG_CORRUPTTXPKT_DEFAULT (_USB_GUSBCFG_CORRUPTTXPKT_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GUSBCFG */ 847 848 /* Bit fields for USB GRSTCTL */ 849 #define _USB_GRSTCTL_RESETVALUE 0x80000000UL /**< Default value for USB_GRSTCTL */ 850 #define _USB_GRSTCTL_MASK 0xC00007F7UL /**< Mask for USB_GRSTCTL */ 851 #define USB_GRSTCTL_CSFTRST (0x1UL << 0) /**< Core Soft Reset (host and device) */ 852 #define _USB_GRSTCTL_CSFTRST_SHIFT 0 /**< Shift value for USB_CSFTRST */ 853 #define _USB_GRSTCTL_CSFTRST_MASK 0x1UL /**< Bit mask for USB_CSFTRST */ 854 #define _USB_GRSTCTL_CSFTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ 855 #define USB_GRSTCTL_CSFTRST_DEFAULT (_USB_GRSTCTL_CSFTRST_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRSTCTL */ 856 #define USB_GRSTCTL_PIUFSSFTRST (0x1UL << 1) /**< PIU FS Dedicated Controller Soft Reset */ 857 #define _USB_GRSTCTL_PIUFSSFTRST_SHIFT 1 /**< Shift value for USB_PIUFSSFTRST */ 858 #define _USB_GRSTCTL_PIUFSSFTRST_MASK 0x2UL /**< Bit mask for USB_PIUFSSFTRST */ 859 #define _USB_GRSTCTL_PIUFSSFTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ 860 #define USB_GRSTCTL_PIUFSSFTRST_DEFAULT (_USB_GRSTCTL_PIUFSSFTRST_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GRSTCTL */ 861 #define USB_GRSTCTL_FRMCNTRRST (0x1UL << 2) /**< Host Frame Counter Reset */ 862 #define _USB_GRSTCTL_FRMCNTRRST_SHIFT 2 /**< Shift value for USB_FRMCNTRRST */ 863 #define _USB_GRSTCTL_FRMCNTRRST_MASK 0x4UL /**< Bit mask for USB_FRMCNTRRST */ 864 #define _USB_GRSTCTL_FRMCNTRRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ 865 #define USB_GRSTCTL_FRMCNTRRST_DEFAULT (_USB_GRSTCTL_FRMCNTRRST_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GRSTCTL */ 866 #define USB_GRSTCTL_RXFFLSH (0x1UL << 4) /**< RxFIFO Flush */ 867 #define _USB_GRSTCTL_RXFFLSH_SHIFT 4 /**< Shift value for USB_RXFFLSH */ 868 #define _USB_GRSTCTL_RXFFLSH_MASK 0x10UL /**< Bit mask for USB_RXFFLSH */ 869 #define _USB_GRSTCTL_RXFFLSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ 870 #define USB_GRSTCTL_RXFFLSH_DEFAULT (_USB_GRSTCTL_RXFFLSH_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRSTCTL */ 871 #define USB_GRSTCTL_TXFFLSH (0x1UL << 5) /**< TxFIFO Flush */ 872 #define _USB_GRSTCTL_TXFFLSH_SHIFT 5 /**< Shift value for USB_TXFFLSH */ 873 #define _USB_GRSTCTL_TXFFLSH_MASK 0x20UL /**< Bit mask for USB_TXFFLSH */ 874 #define _USB_GRSTCTL_TXFFLSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ 875 #define USB_GRSTCTL_TXFFLSH_DEFAULT (_USB_GRSTCTL_TXFFLSH_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GRSTCTL */ 876 #define _USB_GRSTCTL_TXFNUM_SHIFT 6 /**< Shift value for USB_TXFNUM */ 877 #define _USB_GRSTCTL_TXFNUM_MASK 0x7C0UL /**< Bit mask for USB_TXFNUM */ 878 #define _USB_GRSTCTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ 879 #define _USB_GRSTCTL_TXFNUM_F0 0x00000000UL /**< Mode F0 for USB_GRSTCTL */ 880 #define _USB_GRSTCTL_TXFNUM_F1 0x00000001UL /**< Mode F1 for USB_GRSTCTL */ 881 #define _USB_GRSTCTL_TXFNUM_F2 0x00000002UL /**< Mode F2 for USB_GRSTCTL */ 882 #define _USB_GRSTCTL_TXFNUM_F3 0x00000003UL /**< Mode F3 for USB_GRSTCTL */ 883 #define _USB_GRSTCTL_TXFNUM_F4 0x00000004UL /**< Mode F4 for USB_GRSTCTL */ 884 #define _USB_GRSTCTL_TXFNUM_F5 0x00000005UL /**< Mode F5 for USB_GRSTCTL */ 885 #define _USB_GRSTCTL_TXFNUM_F6 0x00000006UL /**< Mode F6 for USB_GRSTCTL */ 886 #define _USB_GRSTCTL_TXFNUM_FALL 0x00000010UL /**< Mode FALL for USB_GRSTCTL */ 887 #define USB_GRSTCTL_TXFNUM_DEFAULT (_USB_GRSTCTL_TXFNUM_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GRSTCTL */ 888 #define USB_GRSTCTL_TXFNUM_F0 (_USB_GRSTCTL_TXFNUM_F0 << 6) /**< Shifted mode F0 for USB_GRSTCTL */ 889 #define USB_GRSTCTL_TXFNUM_F1 (_USB_GRSTCTL_TXFNUM_F1 << 6) /**< Shifted mode F1 for USB_GRSTCTL */ 890 #define USB_GRSTCTL_TXFNUM_F2 (_USB_GRSTCTL_TXFNUM_F2 << 6) /**< Shifted mode F2 for USB_GRSTCTL */ 891 #define USB_GRSTCTL_TXFNUM_F3 (_USB_GRSTCTL_TXFNUM_F3 << 6) /**< Shifted mode F3 for USB_GRSTCTL */ 892 #define USB_GRSTCTL_TXFNUM_F4 (_USB_GRSTCTL_TXFNUM_F4 << 6) /**< Shifted mode F4 for USB_GRSTCTL */ 893 #define USB_GRSTCTL_TXFNUM_F5 (_USB_GRSTCTL_TXFNUM_F5 << 6) /**< Shifted mode F5 for USB_GRSTCTL */ 894 #define USB_GRSTCTL_TXFNUM_F6 (_USB_GRSTCTL_TXFNUM_F6 << 6) /**< Shifted mode F6 for USB_GRSTCTL */ 895 #define USB_GRSTCTL_TXFNUM_FALL (_USB_GRSTCTL_TXFNUM_FALL << 6) /**< Shifted mode FALL for USB_GRSTCTL */ 896 #define USB_GRSTCTL_DMAREQ (0x1UL << 30) /**< DMA Request Signal */ 897 #define _USB_GRSTCTL_DMAREQ_SHIFT 30 /**< Shift value for USB_DMAREQ */ 898 #define _USB_GRSTCTL_DMAREQ_MASK 0x40000000UL /**< Bit mask for USB_DMAREQ */ 899 #define _USB_GRSTCTL_DMAREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ 900 #define USB_GRSTCTL_DMAREQ_DEFAULT (_USB_GRSTCTL_DMAREQ_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GRSTCTL */ 901 #define USB_GRSTCTL_AHBIDLE (0x1UL << 31) /**< AHB Master Idle */ 902 #define _USB_GRSTCTL_AHBIDLE_SHIFT 31 /**< Shift value for USB_AHBIDLE */ 903 #define _USB_GRSTCTL_AHBIDLE_MASK 0x80000000UL /**< Bit mask for USB_AHBIDLE */ 904 #define _USB_GRSTCTL_AHBIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GRSTCTL */ 905 #define USB_GRSTCTL_AHBIDLE_DEFAULT (_USB_GRSTCTL_AHBIDLE_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GRSTCTL */ 906 907 /* Bit fields for USB GINTSTS */ 908 #define _USB_GINTSTS_RESETVALUE 0x14000020UL /**< Default value for USB_GINTSTS */ 909 #define _USB_GINTSTS_MASK 0xF7FEFCFFUL /**< Mask for USB_GINTSTS */ 910 #define USB_GINTSTS_CURMOD (0x1UL << 0) /**< Current Mode of Operation (host and device) */ 911 #define _USB_GINTSTS_CURMOD_SHIFT 0 /**< Shift value for USB_CURMOD */ 912 #define _USB_GINTSTS_CURMOD_MASK 0x1UL /**< Bit mask for USB_CURMOD */ 913 #define _USB_GINTSTS_CURMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 914 #define _USB_GINTSTS_CURMOD_DEVICE 0x00000000UL /**< Mode DEVICE for USB_GINTSTS */ 915 #define _USB_GINTSTS_CURMOD_HOST 0x00000001UL /**< Mode HOST for USB_GINTSTS */ 916 #define USB_GINTSTS_CURMOD_DEFAULT (_USB_GINTSTS_CURMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GINTSTS */ 917 #define USB_GINTSTS_CURMOD_DEVICE (_USB_GINTSTS_CURMOD_DEVICE << 0) /**< Shifted mode DEVICE for USB_GINTSTS */ 918 #define USB_GINTSTS_CURMOD_HOST (_USB_GINTSTS_CURMOD_HOST << 0) /**< Shifted mode HOST for USB_GINTSTS */ 919 #define USB_GINTSTS_MODEMIS (0x1UL << 1) /**< Mode Mismatch Interrupt (host and device) */ 920 #define _USB_GINTSTS_MODEMIS_SHIFT 1 /**< Shift value for USB_MODEMIS */ 921 #define _USB_GINTSTS_MODEMIS_MASK 0x2UL /**< Bit mask for USB_MODEMIS */ 922 #define _USB_GINTSTS_MODEMIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 923 #define USB_GINTSTS_MODEMIS_DEFAULT (_USB_GINTSTS_MODEMIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GINTSTS */ 924 #define USB_GINTSTS_OTGINT (0x1UL << 2) /**< OTG Interrupt (host and device) */ 925 #define _USB_GINTSTS_OTGINT_SHIFT 2 /**< Shift value for USB_OTGINT */ 926 #define _USB_GINTSTS_OTGINT_MASK 0x4UL /**< Bit mask for USB_OTGINT */ 927 #define _USB_GINTSTS_OTGINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 928 #define USB_GINTSTS_OTGINT_DEFAULT (_USB_GINTSTS_OTGINT_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GINTSTS */ 929 #define USB_GINTSTS_SOF (0x1UL << 3) /**< Start of Frame (host and device) */ 930 #define _USB_GINTSTS_SOF_SHIFT 3 /**< Shift value for USB_SOF */ 931 #define _USB_GINTSTS_SOF_MASK 0x8UL /**< Bit mask for USB_SOF */ 932 #define _USB_GINTSTS_SOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 933 #define USB_GINTSTS_SOF_DEFAULT (_USB_GINTSTS_SOF_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GINTSTS */ 934 #define USB_GINTSTS_RXFLVL (0x1UL << 4) /**< RxFIFO Non-Empty (host and device) */ 935 #define _USB_GINTSTS_RXFLVL_SHIFT 4 /**< Shift value for USB_RXFLVL */ 936 #define _USB_GINTSTS_RXFLVL_MASK 0x10UL /**< Bit mask for USB_RXFLVL */ 937 #define _USB_GINTSTS_RXFLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 938 #define USB_GINTSTS_RXFLVL_DEFAULT (_USB_GINTSTS_RXFLVL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GINTSTS */ 939 #define USB_GINTSTS_NPTXFEMP (0x1UL << 5) /**< Non-Periodic TxFIFO Empty (host only) */ 940 #define _USB_GINTSTS_NPTXFEMP_SHIFT 5 /**< Shift value for USB_NPTXFEMP */ 941 #define _USB_GINTSTS_NPTXFEMP_MASK 0x20UL /**< Bit mask for USB_NPTXFEMP */ 942 #define _USB_GINTSTS_NPTXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */ 943 #define USB_GINTSTS_NPTXFEMP_DEFAULT (_USB_GINTSTS_NPTXFEMP_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GINTSTS */ 944 #define USB_GINTSTS_GINNAKEFF (0x1UL << 6) /**< Global IN Non-periodic NAK Effective (device only) */ 945 #define _USB_GINTSTS_GINNAKEFF_SHIFT 6 /**< Shift value for USB_GINNAKEFF */ 946 #define _USB_GINTSTS_GINNAKEFF_MASK 0x40UL /**< Bit mask for USB_GINNAKEFF */ 947 #define _USB_GINTSTS_GINNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 948 #define USB_GINTSTS_GINNAKEFF_DEFAULT (_USB_GINTSTS_GINNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GINTSTS */ 949 #define USB_GINTSTS_GOUTNAKEFF (0x1UL << 7) /**< Global OUT NAK Effective (device only) */ 950 #define _USB_GINTSTS_GOUTNAKEFF_SHIFT 7 /**< Shift value for USB_GOUTNAKEFF */ 951 #define _USB_GINTSTS_GOUTNAKEFF_MASK 0x80UL /**< Bit mask for USB_GOUTNAKEFF */ 952 #define _USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 953 #define USB_GINTSTS_GOUTNAKEFF_DEFAULT (_USB_GINTSTS_GOUTNAKEFF_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GINTSTS */ 954 #define USB_GINTSTS_ERLYSUSP (0x1UL << 10) /**< Early Suspend (device only) */ 955 #define _USB_GINTSTS_ERLYSUSP_SHIFT 10 /**< Shift value for USB_ERLYSUSP */ 956 #define _USB_GINTSTS_ERLYSUSP_MASK 0x400UL /**< Bit mask for USB_ERLYSUSP */ 957 #define _USB_GINTSTS_ERLYSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 958 #define USB_GINTSTS_ERLYSUSP_DEFAULT (_USB_GINTSTS_ERLYSUSP_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GINTSTS */ 959 #define USB_GINTSTS_USBSUSP (0x1UL << 11) /**< USB Suspend (device only) */ 960 #define _USB_GINTSTS_USBSUSP_SHIFT 11 /**< Shift value for USB_USBSUSP */ 961 #define _USB_GINTSTS_USBSUSP_MASK 0x800UL /**< Bit mask for USB_USBSUSP */ 962 #define _USB_GINTSTS_USBSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 963 #define USB_GINTSTS_USBSUSP_DEFAULT (_USB_GINTSTS_USBSUSP_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GINTSTS */ 964 #define USB_GINTSTS_USBRST (0x1UL << 12) /**< USB Reset (device only) */ 965 #define _USB_GINTSTS_USBRST_SHIFT 12 /**< Shift value for USB_USBRST */ 966 #define _USB_GINTSTS_USBRST_MASK 0x1000UL /**< Bit mask for USB_USBRST */ 967 #define _USB_GINTSTS_USBRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 968 #define USB_GINTSTS_USBRST_DEFAULT (_USB_GINTSTS_USBRST_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GINTSTS */ 969 #define USB_GINTSTS_ENUMDONE (0x1UL << 13) /**< Enumeration Done (device only) */ 970 #define _USB_GINTSTS_ENUMDONE_SHIFT 13 /**< Shift value for USB_ENUMDONE */ 971 #define _USB_GINTSTS_ENUMDONE_MASK 0x2000UL /**< Bit mask for USB_ENUMDONE */ 972 #define _USB_GINTSTS_ENUMDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 973 #define USB_GINTSTS_ENUMDONE_DEFAULT (_USB_GINTSTS_ENUMDONE_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_GINTSTS */ 974 #define USB_GINTSTS_ISOOUTDROP (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt (device only) */ 975 #define _USB_GINTSTS_ISOOUTDROP_SHIFT 14 /**< Shift value for USB_ISOOUTDROP */ 976 #define _USB_GINTSTS_ISOOUTDROP_MASK 0x4000UL /**< Bit mask for USB_ISOOUTDROP */ 977 #define _USB_GINTSTS_ISOOUTDROP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 978 #define USB_GINTSTS_ISOOUTDROP_DEFAULT (_USB_GINTSTS_ISOOUTDROP_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_GINTSTS */ 979 #define USB_GINTSTS_EOPF (0x1UL << 15) /**< End of Periodic Frame Interrupt */ 980 #define _USB_GINTSTS_EOPF_SHIFT 15 /**< Shift value for USB_EOPF */ 981 #define _USB_GINTSTS_EOPF_MASK 0x8000UL /**< Bit mask for USB_EOPF */ 982 #define _USB_GINTSTS_EOPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 983 #define USB_GINTSTS_EOPF_DEFAULT (_USB_GINTSTS_EOPF_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GINTSTS */ 984 #define USB_GINTSTS_EPMIS (0x1UL << 17) /**< Endpoint Mismatch Interrupt (device only) */ 985 #define _USB_GINTSTS_EPMIS_SHIFT 17 /**< Shift value for USB_EPMIS */ 986 #define _USB_GINTSTS_EPMIS_MASK 0x20000UL /**< Bit mask for USB_EPMIS */ 987 #define _USB_GINTSTS_EPMIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 988 #define USB_GINTSTS_EPMIS_DEFAULT (_USB_GINTSTS_EPMIS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GINTSTS */ 989 #define USB_GINTSTS_IEPINT (0x1UL << 18) /**< IN Endpoints Interrupt (device only) */ 990 #define _USB_GINTSTS_IEPINT_SHIFT 18 /**< Shift value for USB_IEPINT */ 991 #define _USB_GINTSTS_IEPINT_MASK 0x40000UL /**< Bit mask for USB_IEPINT */ 992 #define _USB_GINTSTS_IEPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 993 #define USB_GINTSTS_IEPINT_DEFAULT (_USB_GINTSTS_IEPINT_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GINTSTS */ 994 #define USB_GINTSTS_OEPINT (0x1UL << 19) /**< OUT Endpoints Interrupt (device only) */ 995 #define _USB_GINTSTS_OEPINT_SHIFT 19 /**< Shift value for USB_OEPINT */ 996 #define _USB_GINTSTS_OEPINT_MASK 0x80000UL /**< Bit mask for USB_OEPINT */ 997 #define _USB_GINTSTS_OEPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 998 #define USB_GINTSTS_OEPINT_DEFAULT (_USB_GINTSTS_OEPINT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GINTSTS */ 999 #define USB_GINTSTS_INCOMPISOIN (0x1UL << 20) /**< Incomplete Isochronous IN Transfer (device only) */ 1000 #define _USB_GINTSTS_INCOMPISOIN_SHIFT 20 /**< Shift value for USB_INCOMPISOIN */ 1001 #define _USB_GINTSTS_INCOMPISOIN_MASK 0x100000UL /**< Bit mask for USB_INCOMPISOIN */ 1002 #define _USB_GINTSTS_INCOMPISOIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 1003 #define USB_GINTSTS_INCOMPISOIN_DEFAULT (_USB_GINTSTS_INCOMPISOIN_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GINTSTS */ 1004 #define USB_GINTSTS_INCOMPLP (0x1UL << 21) /**< Incomplete Periodic Transfer (device only) */ 1005 #define _USB_GINTSTS_INCOMPLP_SHIFT 21 /**< Shift value for USB_INCOMPLP */ 1006 #define _USB_GINTSTS_INCOMPLP_MASK 0x200000UL /**< Bit mask for USB_INCOMPLP */ 1007 #define _USB_GINTSTS_INCOMPLP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 1008 #define USB_GINTSTS_INCOMPLP_DEFAULT (_USB_GINTSTS_INCOMPLP_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GINTSTS */ 1009 #define USB_GINTSTS_FETSUSP (0x1UL << 22) /**< Data Fetch Suspended (device only) */ 1010 #define _USB_GINTSTS_FETSUSP_SHIFT 22 /**< Shift value for USB_FETSUSP */ 1011 #define _USB_GINTSTS_FETSUSP_MASK 0x400000UL /**< Bit mask for USB_FETSUSP */ 1012 #define _USB_GINTSTS_FETSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 1013 #define USB_GINTSTS_FETSUSP_DEFAULT (_USB_GINTSTS_FETSUSP_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GINTSTS */ 1014 #define USB_GINTSTS_RESETDET (0x1UL << 23) /**< Reset detected Interrupt (device only) */ 1015 #define _USB_GINTSTS_RESETDET_SHIFT 23 /**< Shift value for USB_RESETDET */ 1016 #define _USB_GINTSTS_RESETDET_MASK 0x800000UL /**< Bit mask for USB_RESETDET */ 1017 #define _USB_GINTSTS_RESETDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 1018 #define USB_GINTSTS_RESETDET_DEFAULT (_USB_GINTSTS_RESETDET_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GINTSTS */ 1019 #define USB_GINTSTS_PRTINT (0x1UL << 24) /**< Host Port Interrupt (host only) */ 1020 #define _USB_GINTSTS_PRTINT_SHIFT 24 /**< Shift value for USB_PRTINT */ 1021 #define _USB_GINTSTS_PRTINT_MASK 0x1000000UL /**< Bit mask for USB_PRTINT */ 1022 #define _USB_GINTSTS_PRTINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 1023 #define USB_GINTSTS_PRTINT_DEFAULT (_USB_GINTSTS_PRTINT_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GINTSTS */ 1024 #define USB_GINTSTS_HCHINT (0x1UL << 25) /**< Host Channels Interrupt (host only) */ 1025 #define _USB_GINTSTS_HCHINT_SHIFT 25 /**< Shift value for USB_HCHINT */ 1026 #define _USB_GINTSTS_HCHINT_MASK 0x2000000UL /**< Bit mask for USB_HCHINT */ 1027 #define _USB_GINTSTS_HCHINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 1028 #define USB_GINTSTS_HCHINT_DEFAULT (_USB_GINTSTS_HCHINT_DEFAULT << 25) /**< Shifted mode DEFAULT for USB_GINTSTS */ 1029 #define USB_GINTSTS_PTXFEMP (0x1UL << 26) /**< Periodic TxFIFO Empty (host only) */ 1030 #define _USB_GINTSTS_PTXFEMP_SHIFT 26 /**< Shift value for USB_PTXFEMP */ 1031 #define _USB_GINTSTS_PTXFEMP_MASK 0x4000000UL /**< Bit mask for USB_PTXFEMP */ 1032 #define _USB_GINTSTS_PTXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */ 1033 #define USB_GINTSTS_PTXFEMP_DEFAULT (_USB_GINTSTS_PTXFEMP_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_GINTSTS */ 1034 #define USB_GINTSTS_CONIDSTSCHNG (0x1UL << 28) /**< Connector ID Status Change (host and device) */ 1035 #define _USB_GINTSTS_CONIDSTSCHNG_SHIFT 28 /**< Shift value for USB_CONIDSTSCHNG */ 1036 #define _USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000UL /**< Bit mask for USB_CONIDSTSCHNG */ 1037 #define _USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */ 1038 #define USB_GINTSTS_CONIDSTSCHNG_DEFAULT (_USB_GINTSTS_CONIDSTSCHNG_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTSTS */ 1039 #define USB_GINTSTS_DISCONNINT (0x1UL << 29) /**< Disconnect Detected Interrupt (host only) */ 1040 #define _USB_GINTSTS_DISCONNINT_SHIFT 29 /**< Shift value for USB_DISCONNINT */ 1041 #define _USB_GINTSTS_DISCONNINT_MASK 0x20000000UL /**< Bit mask for USB_DISCONNINT */ 1042 #define _USB_GINTSTS_DISCONNINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 1043 #define USB_GINTSTS_DISCONNINT_DEFAULT (_USB_GINTSTS_DISCONNINT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GINTSTS */ 1044 #define USB_GINTSTS_SESSREQINT (0x1UL << 30) /**< Session Request/New Session Detected Interrupt (host and device) */ 1045 #define _USB_GINTSTS_SESSREQINT_SHIFT 30 /**< Shift value for USB_SESSREQINT */ 1046 #define _USB_GINTSTS_SESSREQINT_MASK 0x40000000UL /**< Bit mask for USB_SESSREQINT */ 1047 #define _USB_GINTSTS_SESSREQINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 1048 #define USB_GINTSTS_SESSREQINT_DEFAULT (_USB_GINTSTS_SESSREQINT_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GINTSTS */ 1049 #define USB_GINTSTS_WKUPINT (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt (host and device) */ 1050 #define _USB_GINTSTS_WKUPINT_SHIFT 31 /**< Shift value for USB_WKUPINT */ 1051 #define _USB_GINTSTS_WKUPINT_MASK 0x80000000UL /**< Bit mask for USB_WKUPINT */ 1052 #define _USB_GINTSTS_WKUPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ 1053 #define USB_GINTSTS_WKUPINT_DEFAULT (_USB_GINTSTS_WKUPINT_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GINTSTS */ 1054 1055 /* Bit fields for USB GINTMSK */ 1056 #define _USB_GINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_GINTMSK */ 1057 #define _USB_GINTMSK_MASK 0xF7FEFCFEUL /**< Mask for USB_GINTMSK */ 1058 #define USB_GINTMSK_MODEMISMSK (0x1UL << 1) /**< Mode Mismatch Interrupt Mask (host and device) */ 1059 #define _USB_GINTMSK_MODEMISMSK_SHIFT 1 /**< Shift value for USB_MODEMISMSK */ 1060 #define _USB_GINTMSK_MODEMISMSK_MASK 0x2UL /**< Bit mask for USB_MODEMISMSK */ 1061 #define _USB_GINTMSK_MODEMISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1062 #define USB_GINTMSK_MODEMISMSK_DEFAULT (_USB_GINTMSK_MODEMISMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1063 #define USB_GINTMSK_OTGINTMSK (0x1UL << 2) /**< OTG Interrupt Mask (host and device) */ 1064 #define _USB_GINTMSK_OTGINTMSK_SHIFT 2 /**< Shift value for USB_OTGINTMSK */ 1065 #define _USB_GINTMSK_OTGINTMSK_MASK 0x4UL /**< Bit mask for USB_OTGINTMSK */ 1066 #define _USB_GINTMSK_OTGINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1067 #define USB_GINTMSK_OTGINTMSK_DEFAULT (_USB_GINTMSK_OTGINTMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1068 #define USB_GINTMSK_SOFMSK (0x1UL << 3) /**< Start of Frame Mask (host and device) */ 1069 #define _USB_GINTMSK_SOFMSK_SHIFT 3 /**< Shift value for USB_SOFMSK */ 1070 #define _USB_GINTMSK_SOFMSK_MASK 0x8UL /**< Bit mask for USB_SOFMSK */ 1071 #define _USB_GINTMSK_SOFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1072 #define USB_GINTMSK_SOFMSK_DEFAULT (_USB_GINTMSK_SOFMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1073 #define USB_GINTMSK_RXFLVLMSK (0x1UL << 4) /**< Receive FIFO Non-Empty Mask (host and device) */ 1074 #define _USB_GINTMSK_RXFLVLMSK_SHIFT 4 /**< Shift value for USB_RXFLVLMSK */ 1075 #define _USB_GINTMSK_RXFLVLMSK_MASK 0x10UL /**< Bit mask for USB_RXFLVLMSK */ 1076 #define _USB_GINTMSK_RXFLVLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1077 #define USB_GINTMSK_RXFLVLMSK_DEFAULT (_USB_GINTMSK_RXFLVLMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1078 #define USB_GINTMSK_NPTXFEMPMSK (0x1UL << 5) /**< Non-Periodic TxFIFO Empty Mask (host only) */ 1079 #define _USB_GINTMSK_NPTXFEMPMSK_SHIFT 5 /**< Shift value for USB_NPTXFEMPMSK */ 1080 #define _USB_GINTMSK_NPTXFEMPMSK_MASK 0x20UL /**< Bit mask for USB_NPTXFEMPMSK */ 1081 #define _USB_GINTMSK_NPTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1082 #define USB_GINTMSK_NPTXFEMPMSK_DEFAULT (_USB_GINTMSK_NPTXFEMPMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1083 #define USB_GINTMSK_GINNAKEFFMSK (0x1UL << 6) /**< Global Non-periodic IN NAK Effective Mask (device only) */ 1084 #define _USB_GINTMSK_GINNAKEFFMSK_SHIFT 6 /**< Shift value for USB_GINNAKEFFMSK */ 1085 #define _USB_GINTMSK_GINNAKEFFMSK_MASK 0x40UL /**< Bit mask for USB_GINNAKEFFMSK */ 1086 #define _USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1087 #define USB_GINTMSK_GINNAKEFFMSK_DEFAULT (_USB_GINTMSK_GINNAKEFFMSK_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1088 #define USB_GINTMSK_GOUTNAKEFFMSK (0x1UL << 7) /**< Global OUT NAK Effective Mask (device only) */ 1089 #define _USB_GINTMSK_GOUTNAKEFFMSK_SHIFT 7 /**< Shift value for USB_GOUTNAKEFFMSK */ 1090 #define _USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80UL /**< Bit mask for USB_GOUTNAKEFFMSK */ 1091 #define _USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1092 #define USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT (_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1093 #define USB_GINTMSK_ERLYSUSPMSK (0x1UL << 10) /**< Early Suspend Mask (device only) */ 1094 #define _USB_GINTMSK_ERLYSUSPMSK_SHIFT 10 /**< Shift value for USB_ERLYSUSPMSK */ 1095 #define _USB_GINTMSK_ERLYSUSPMSK_MASK 0x400UL /**< Bit mask for USB_ERLYSUSPMSK */ 1096 #define _USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1097 #define USB_GINTMSK_ERLYSUSPMSK_DEFAULT (_USB_GINTMSK_ERLYSUSPMSK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1098 #define USB_GINTMSK_USBSUSPMSK (0x1UL << 11) /**< USB Suspend Mask (device only) */ 1099 #define _USB_GINTMSK_USBSUSPMSK_SHIFT 11 /**< Shift value for USB_USBSUSPMSK */ 1100 #define _USB_GINTMSK_USBSUSPMSK_MASK 0x800UL /**< Bit mask for USB_USBSUSPMSK */ 1101 #define _USB_GINTMSK_USBSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1102 #define USB_GINTMSK_USBSUSPMSK_DEFAULT (_USB_GINTMSK_USBSUSPMSK_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1103 #define USB_GINTMSK_USBRSTMSK (0x1UL << 12) /**< USB Reset Mask (device only) */ 1104 #define _USB_GINTMSK_USBRSTMSK_SHIFT 12 /**< Shift value for USB_USBRSTMSK */ 1105 #define _USB_GINTMSK_USBRSTMSK_MASK 0x1000UL /**< Bit mask for USB_USBRSTMSK */ 1106 #define _USB_GINTMSK_USBRSTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1107 #define USB_GINTMSK_USBRSTMSK_DEFAULT (_USB_GINTMSK_USBRSTMSK_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1108 #define USB_GINTMSK_ENUMDONEMSK (0x1UL << 13) /**< Enumeration Done Mask (device only) */ 1109 #define _USB_GINTMSK_ENUMDONEMSK_SHIFT 13 /**< Shift value for USB_ENUMDONEMSK */ 1110 #define _USB_GINTMSK_ENUMDONEMSK_MASK 0x2000UL /**< Bit mask for USB_ENUMDONEMSK */ 1111 #define _USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1112 #define USB_GINTMSK_ENUMDONEMSK_DEFAULT (_USB_GINTMSK_ENUMDONEMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1113 #define USB_GINTMSK_ISOOUTDROPMSK (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt Mask (device only) */ 1114 #define _USB_GINTMSK_ISOOUTDROPMSK_SHIFT 14 /**< Shift value for USB_ISOOUTDROPMSK */ 1115 #define _USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000UL /**< Bit mask for USB_ISOOUTDROPMSK */ 1116 #define _USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1117 #define USB_GINTMSK_ISOOUTDROPMSK_DEFAULT (_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1118 #define USB_GINTMSK_EOPFMSK (0x1UL << 15) /**< End of Periodic Frame Interrupt Mask (device only) */ 1119 #define _USB_GINTMSK_EOPFMSK_SHIFT 15 /**< Shift value for USB_EOPFMSK */ 1120 #define _USB_GINTMSK_EOPFMSK_MASK 0x8000UL /**< Bit mask for USB_EOPFMSK */ 1121 #define _USB_GINTMSK_EOPFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1122 #define USB_GINTMSK_EOPFMSK_DEFAULT (_USB_GINTMSK_EOPFMSK_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1123 #define USB_GINTMSK_EPMISMSK (0x1UL << 17) /**< Endpoint Mismatch Interrupt Mask (device only) */ 1124 #define _USB_GINTMSK_EPMISMSK_SHIFT 17 /**< Shift value for USB_EPMISMSK */ 1125 #define _USB_GINTMSK_EPMISMSK_MASK 0x20000UL /**< Bit mask for USB_EPMISMSK */ 1126 #define _USB_GINTMSK_EPMISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1127 #define USB_GINTMSK_EPMISMSK_DEFAULT (_USB_GINTMSK_EPMISMSK_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1128 #define USB_GINTMSK_IEPINTMSK (0x1UL << 18) /**< IN Endpoints Interrupt Mask (device only) */ 1129 #define _USB_GINTMSK_IEPINTMSK_SHIFT 18 /**< Shift value for USB_IEPINTMSK */ 1130 #define _USB_GINTMSK_IEPINTMSK_MASK 0x40000UL /**< Bit mask for USB_IEPINTMSK */ 1131 #define _USB_GINTMSK_IEPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1132 #define USB_GINTMSK_IEPINTMSK_DEFAULT (_USB_GINTMSK_IEPINTMSK_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1133 #define USB_GINTMSK_OEPINTMSK (0x1UL << 19) /**< OUT Endpoints Interrupt Mask (device only) */ 1134 #define _USB_GINTMSK_OEPINTMSK_SHIFT 19 /**< Shift value for USB_OEPINTMSK */ 1135 #define _USB_GINTMSK_OEPINTMSK_MASK 0x80000UL /**< Bit mask for USB_OEPINTMSK */ 1136 #define _USB_GINTMSK_OEPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1137 #define USB_GINTMSK_OEPINTMSK_DEFAULT (_USB_GINTMSK_OEPINTMSK_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1138 #define USB_GINTMSK_INCOMPISOINMSK (0x1UL << 20) /**< Incomplete Isochronous IN Transfer Mask (device only) */ 1139 #define _USB_GINTMSK_INCOMPISOINMSK_SHIFT 20 /**< Shift value for USB_INCOMPISOINMSK */ 1140 #define _USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000UL /**< Bit mask for USB_INCOMPISOINMSK */ 1141 #define _USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1142 #define USB_GINTMSK_INCOMPISOINMSK_DEFAULT (_USB_GINTMSK_INCOMPISOINMSK_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1143 #define USB_GINTMSK_INCOMPLPMSK (0x1UL << 21) /**< Incomplete Periodic Transfer Mask (host only) */ 1144 #define _USB_GINTMSK_INCOMPLPMSK_SHIFT 21 /**< Shift value for USB_INCOMPLPMSK */ 1145 #define _USB_GINTMSK_INCOMPLPMSK_MASK 0x200000UL /**< Bit mask for USB_INCOMPLPMSK */ 1146 #define _USB_GINTMSK_INCOMPLPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1147 #define USB_GINTMSK_INCOMPLPMSK_DEFAULT (_USB_GINTMSK_INCOMPLPMSK_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1148 #define USB_GINTMSK_FETSUSPMSK (0x1UL << 22) /**< Data Fetch Suspended Mask (device only) */ 1149 #define _USB_GINTMSK_FETSUSPMSK_SHIFT 22 /**< Shift value for USB_FETSUSPMSK */ 1150 #define _USB_GINTMSK_FETSUSPMSK_MASK 0x400000UL /**< Bit mask for USB_FETSUSPMSK */ 1151 #define _USB_GINTMSK_FETSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1152 #define USB_GINTMSK_FETSUSPMSK_DEFAULT (_USB_GINTMSK_FETSUSPMSK_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1153 #define USB_GINTMSK_RESETDETMSK (0x1UL << 23) /**< Reset detected Interrupt Mask (device only) */ 1154 #define _USB_GINTMSK_RESETDETMSK_SHIFT 23 /**< Shift value for USB_RESETDETMSK */ 1155 #define _USB_GINTMSK_RESETDETMSK_MASK 0x800000UL /**< Bit mask for USB_RESETDETMSK */ 1156 #define _USB_GINTMSK_RESETDETMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1157 #define USB_GINTMSK_RESETDETMSK_DEFAULT (_USB_GINTMSK_RESETDETMSK_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1158 #define USB_GINTMSK_PRTINTMSK (0x1UL << 24) /**< Host Port Interrupt Mask (host only) */ 1159 #define _USB_GINTMSK_PRTINTMSK_SHIFT 24 /**< Shift value for USB_PRTINTMSK */ 1160 #define _USB_GINTMSK_PRTINTMSK_MASK 0x1000000UL /**< Bit mask for USB_PRTINTMSK */ 1161 #define _USB_GINTMSK_PRTINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1162 #define USB_GINTMSK_PRTINTMSK_DEFAULT (_USB_GINTMSK_PRTINTMSK_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1163 #define USB_GINTMSK_HCHINTMSK (0x1UL << 25) /**< Host Channels Interrupt Mask (host only) */ 1164 #define _USB_GINTMSK_HCHINTMSK_SHIFT 25 /**< Shift value for USB_HCHINTMSK */ 1165 #define _USB_GINTMSK_HCHINTMSK_MASK 0x2000000UL /**< Bit mask for USB_HCHINTMSK */ 1166 #define _USB_GINTMSK_HCHINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1167 #define USB_GINTMSK_HCHINTMSK_DEFAULT (_USB_GINTMSK_HCHINTMSK_DEFAULT << 25) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1168 #define USB_GINTMSK_PTXFEMPMSK (0x1UL << 26) /**< Periodic TxFIFO Empty Mask (host only) */ 1169 #define _USB_GINTMSK_PTXFEMPMSK_SHIFT 26 /**< Shift value for USB_PTXFEMPMSK */ 1170 #define _USB_GINTMSK_PTXFEMPMSK_MASK 0x4000000UL /**< Bit mask for USB_PTXFEMPMSK */ 1171 #define _USB_GINTMSK_PTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1172 #define USB_GINTMSK_PTXFEMPMSK_DEFAULT (_USB_GINTMSK_PTXFEMPMSK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1173 #define USB_GINTMSK_CONIDSTSCHNGMSK (0x1UL << 28) /**< Connector ID Status Change Mask (host and device) */ 1174 #define _USB_GINTMSK_CONIDSTSCHNGMSK_SHIFT 28 /**< Shift value for USB_CONIDSTSCHNGMSK */ 1175 #define _USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000UL /**< Bit mask for USB_CONIDSTSCHNGMSK */ 1176 #define _USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1177 #define USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT (_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1178 #define USB_GINTMSK_DISCONNINTMSK (0x1UL << 29) /**< Disconnect Detected Interrupt Mask (host and device) */ 1179 #define _USB_GINTMSK_DISCONNINTMSK_SHIFT 29 /**< Shift value for USB_DISCONNINTMSK */ 1180 #define _USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000UL /**< Bit mask for USB_DISCONNINTMSK */ 1181 #define _USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1182 #define USB_GINTMSK_DISCONNINTMSK_DEFAULT (_USB_GINTMSK_DISCONNINTMSK_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1183 #define USB_GINTMSK_SESSREQINTMSK (0x1UL << 30) /**< Session Request/New Session Detected Interrupt Mask (host and device) */ 1184 #define _USB_GINTMSK_SESSREQINTMSK_SHIFT 30 /**< Shift value for USB_SESSREQINTMSK */ 1185 #define _USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000UL /**< Bit mask for USB_SESSREQINTMSK */ 1186 #define _USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1187 #define USB_GINTMSK_SESSREQINTMSK_DEFAULT (_USB_GINTMSK_SESSREQINTMSK_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1188 #define USB_GINTMSK_WKUPINTMSK (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt Mask (host and device) */ 1189 #define _USB_GINTMSK_WKUPINTMSK_SHIFT 31 /**< Shift value for USB_WKUPINTMSK */ 1190 #define _USB_GINTMSK_WKUPINTMSK_MASK 0x80000000UL /**< Bit mask for USB_WKUPINTMSK */ 1191 #define _USB_GINTMSK_WKUPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ 1192 #define USB_GINTMSK_WKUPINTMSK_DEFAULT (_USB_GINTMSK_WKUPINTMSK_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GINTMSK */ 1193 1194 /* Bit fields for USB GRXSTSR */ 1195 #define _USB_GRXSTSR_RESETVALUE 0x00000000UL /**< Default value for USB_GRXSTSR */ 1196 #define _USB_GRXSTSR_MASK 0x01FFFFFFUL /**< Mask for USB_GRXSTSR */ 1197 #define _USB_GRXSTSR_CHNUM_SHIFT 0 /**< Shift value for USB_CHNUM */ 1198 #define _USB_GRXSTSR_CHNUM_MASK 0xFUL /**< Bit mask for USB_CHNUM */ 1199 #define _USB_GRXSTSR_CHNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ 1200 #define USB_GRXSTSR_CHNUM_DEFAULT (_USB_GRXSTSR_CHNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXSTSR */ 1201 #define _USB_GRXSTSR_BCNT_SHIFT 4 /**< Shift value for USB_BCNT */ 1202 #define _USB_GRXSTSR_BCNT_MASK 0x7FF0UL /**< Bit mask for USB_BCNT */ 1203 #define _USB_GRXSTSR_BCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ 1204 #define USB_GRXSTSR_BCNT_DEFAULT (_USB_GRXSTSR_BCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRXSTSR */ 1205 #define _USB_GRXSTSR_DPID_SHIFT 15 /**< Shift value for USB_DPID */ 1206 #define _USB_GRXSTSR_DPID_MASK 0x18000UL /**< Bit mask for USB_DPID */ 1207 #define _USB_GRXSTSR_DPID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ 1208 #define _USB_GRXSTSR_DPID_DATA0 0x00000000UL /**< Mode DATA0 for USB_GRXSTSR */ 1209 #define _USB_GRXSTSR_DPID_DATA1 0x00000001UL /**< Mode DATA1 for USB_GRXSTSR */ 1210 #define _USB_GRXSTSR_DPID_DATA2 0x00000002UL /**< Mode DATA2 for USB_GRXSTSR */ 1211 #define _USB_GRXSTSR_DPID_MDATA 0x00000003UL /**< Mode MDATA for USB_GRXSTSR */ 1212 #define USB_GRXSTSR_DPID_DEFAULT (_USB_GRXSTSR_DPID_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GRXSTSR */ 1213 #define USB_GRXSTSR_DPID_DATA0 (_USB_GRXSTSR_DPID_DATA0 << 15) /**< Shifted mode DATA0 for USB_GRXSTSR */ 1214 #define USB_GRXSTSR_DPID_DATA1 (_USB_GRXSTSR_DPID_DATA1 << 15) /**< Shifted mode DATA1 for USB_GRXSTSR */ 1215 #define USB_GRXSTSR_DPID_DATA2 (_USB_GRXSTSR_DPID_DATA2 << 15) /**< Shifted mode DATA2 for USB_GRXSTSR */ 1216 #define USB_GRXSTSR_DPID_MDATA (_USB_GRXSTSR_DPID_MDATA << 15) /**< Shifted mode MDATA for USB_GRXSTSR */ 1217 #define _USB_GRXSTSR_PKTSTS_SHIFT 17 /**< Shift value for USB_PKTSTS */ 1218 #define _USB_GRXSTSR_PKTSTS_MASK 0x1E0000UL /**< Bit mask for USB_PKTSTS */ 1219 #define _USB_GRXSTSR_PKTSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ 1220 #define _USB_GRXSTSR_PKTSTS_GOUTNAK 0x00000001UL /**< Mode GOUTNAK for USB_GRXSTSR */ 1221 #define _USB_GRXSTSR_PKTSTS_PKTRCV 0x00000002UL /**< Mode PKTRCV for USB_GRXSTSR */ 1222 #define _USB_GRXSTSR_PKTSTS_XFERCOMPL 0x00000003UL /**< Mode XFERCOMPL for USB_GRXSTSR */ 1223 #define _USB_GRXSTSR_PKTSTS_SETUPCOMPL 0x00000004UL /**< Mode SETUPCOMPL for USB_GRXSTSR */ 1224 #define _USB_GRXSTSR_PKTSTS_TGLERR 0x00000005UL /**< Mode TGLERR for USB_GRXSTSR */ 1225 #define _USB_GRXSTSR_PKTSTS_SETUPRCV 0x00000006UL /**< Mode SETUPRCV for USB_GRXSTSR */ 1226 #define _USB_GRXSTSR_PKTSTS_CHLT 0x00000007UL /**< Mode CHLT for USB_GRXSTSR */ 1227 #define USB_GRXSTSR_PKTSTS_DEFAULT (_USB_GRXSTSR_PKTSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GRXSTSR */ 1228 #define USB_GRXSTSR_PKTSTS_GOUTNAK (_USB_GRXSTSR_PKTSTS_GOUTNAK << 17) /**< Shifted mode GOUTNAK for USB_GRXSTSR */ 1229 #define USB_GRXSTSR_PKTSTS_PKTRCV (_USB_GRXSTSR_PKTSTS_PKTRCV << 17) /**< Shifted mode PKTRCV for USB_GRXSTSR */ 1230 #define USB_GRXSTSR_PKTSTS_XFERCOMPL (_USB_GRXSTSR_PKTSTS_XFERCOMPL << 17) /**< Shifted mode XFERCOMPL for USB_GRXSTSR */ 1231 #define USB_GRXSTSR_PKTSTS_SETUPCOMPL (_USB_GRXSTSR_PKTSTS_SETUPCOMPL << 17) /**< Shifted mode SETUPCOMPL for USB_GRXSTSR */ 1232 #define USB_GRXSTSR_PKTSTS_TGLERR (_USB_GRXSTSR_PKTSTS_TGLERR << 17) /**< Shifted mode TGLERR for USB_GRXSTSR */ 1233 #define USB_GRXSTSR_PKTSTS_SETUPRCV (_USB_GRXSTSR_PKTSTS_SETUPRCV << 17) /**< Shifted mode SETUPRCV for USB_GRXSTSR */ 1234 #define USB_GRXSTSR_PKTSTS_CHLT (_USB_GRXSTSR_PKTSTS_CHLT << 17) /**< Shifted mode CHLT for USB_GRXSTSR */ 1235 #define _USB_GRXSTSR_FN_SHIFT 21 /**< Shift value for USB_FN */ 1236 #define _USB_GRXSTSR_FN_MASK 0x1E00000UL /**< Bit mask for USB_FN */ 1237 #define _USB_GRXSTSR_FN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ 1238 #define USB_GRXSTSR_FN_DEFAULT (_USB_GRXSTSR_FN_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GRXSTSR */ 1239 1240 /* Bit fields for USB GRXSTSP */ 1241 #define _USB_GRXSTSP_RESETVALUE 0x00000000UL /**< Default value for USB_GRXSTSP */ 1242 #define _USB_GRXSTSP_MASK 0x01FFFFFFUL /**< Mask for USB_GRXSTSP */ 1243 #define _USB_GRXSTSP_CHNUM_SHIFT 0 /**< Shift value for USB_CHNUM */ 1244 #define _USB_GRXSTSP_CHNUM_MASK 0xFUL /**< Bit mask for USB_CHNUM */ 1245 #define _USB_GRXSTSP_CHNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ 1246 #define USB_GRXSTSP_CHNUM_DEFAULT (_USB_GRXSTSP_CHNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXSTSP */ 1247 #define _USB_GRXSTSP_BCNT_SHIFT 4 /**< Shift value for USB_BCNT */ 1248 #define _USB_GRXSTSP_BCNT_MASK 0x7FF0UL /**< Bit mask for USB_BCNT */ 1249 #define _USB_GRXSTSP_BCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ 1250 #define USB_GRXSTSP_BCNT_DEFAULT (_USB_GRXSTSP_BCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRXSTSP */ 1251 #define _USB_GRXSTSP_DPID_SHIFT 15 /**< Shift value for USB_DPID */ 1252 #define _USB_GRXSTSP_DPID_MASK 0x18000UL /**< Bit mask for USB_DPID */ 1253 #define _USB_GRXSTSP_DPID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ 1254 #define _USB_GRXSTSP_DPID_DATA0 0x00000000UL /**< Mode DATA0 for USB_GRXSTSP */ 1255 #define _USB_GRXSTSP_DPID_DATA1 0x00000001UL /**< Mode DATA1 for USB_GRXSTSP */ 1256 #define _USB_GRXSTSP_DPID_DATA2 0x00000002UL /**< Mode DATA2 for USB_GRXSTSP */ 1257 #define _USB_GRXSTSP_DPID_MDATA 0x00000003UL /**< Mode MDATA for USB_GRXSTSP */ 1258 #define USB_GRXSTSP_DPID_DEFAULT (_USB_GRXSTSP_DPID_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GRXSTSP */ 1259 #define USB_GRXSTSP_DPID_DATA0 (_USB_GRXSTSP_DPID_DATA0 << 15) /**< Shifted mode DATA0 for USB_GRXSTSP */ 1260 #define USB_GRXSTSP_DPID_DATA1 (_USB_GRXSTSP_DPID_DATA1 << 15) /**< Shifted mode DATA1 for USB_GRXSTSP */ 1261 #define USB_GRXSTSP_DPID_DATA2 (_USB_GRXSTSP_DPID_DATA2 << 15) /**< Shifted mode DATA2 for USB_GRXSTSP */ 1262 #define USB_GRXSTSP_DPID_MDATA (_USB_GRXSTSP_DPID_MDATA << 15) /**< Shifted mode MDATA for USB_GRXSTSP */ 1263 #define _USB_GRXSTSP_PKTSTS_SHIFT 17 /**< Shift value for USB_PKTSTS */ 1264 #define _USB_GRXSTSP_PKTSTS_MASK 0x1E0000UL /**< Bit mask for USB_PKTSTS */ 1265 #define _USB_GRXSTSP_PKTSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ 1266 #define _USB_GRXSTSP_PKTSTS_GOUTNAK 0x00000001UL /**< Mode GOUTNAK for USB_GRXSTSP */ 1267 #define _USB_GRXSTSP_PKTSTS_PKTRCV 0x00000002UL /**< Mode PKTRCV for USB_GRXSTSP */ 1268 #define _USB_GRXSTSP_PKTSTS_XFERCOMPL 0x00000003UL /**< Mode XFERCOMPL for USB_GRXSTSP */ 1269 #define _USB_GRXSTSP_PKTSTS_SETUPCOMPL 0x00000004UL /**< Mode SETUPCOMPL for USB_GRXSTSP */ 1270 #define _USB_GRXSTSP_PKTSTS_TGLERR 0x00000005UL /**< Mode TGLERR for USB_GRXSTSP */ 1271 #define _USB_GRXSTSP_PKTSTS_SETUPRCV 0x00000006UL /**< Mode SETUPRCV for USB_GRXSTSP */ 1272 #define _USB_GRXSTSP_PKTSTS_CHLT 0x00000007UL /**< Mode CHLT for USB_GRXSTSP */ 1273 #define USB_GRXSTSP_PKTSTS_DEFAULT (_USB_GRXSTSP_PKTSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GRXSTSP */ 1274 #define USB_GRXSTSP_PKTSTS_GOUTNAK (_USB_GRXSTSP_PKTSTS_GOUTNAK << 17) /**< Shifted mode GOUTNAK for USB_GRXSTSP */ 1275 #define USB_GRXSTSP_PKTSTS_PKTRCV (_USB_GRXSTSP_PKTSTS_PKTRCV << 17) /**< Shifted mode PKTRCV for USB_GRXSTSP */ 1276 #define USB_GRXSTSP_PKTSTS_XFERCOMPL (_USB_GRXSTSP_PKTSTS_XFERCOMPL << 17) /**< Shifted mode XFERCOMPL for USB_GRXSTSP */ 1277 #define USB_GRXSTSP_PKTSTS_SETUPCOMPL (_USB_GRXSTSP_PKTSTS_SETUPCOMPL << 17) /**< Shifted mode SETUPCOMPL for USB_GRXSTSP */ 1278 #define USB_GRXSTSP_PKTSTS_TGLERR (_USB_GRXSTSP_PKTSTS_TGLERR << 17) /**< Shifted mode TGLERR for USB_GRXSTSP */ 1279 #define USB_GRXSTSP_PKTSTS_SETUPRCV (_USB_GRXSTSP_PKTSTS_SETUPRCV << 17) /**< Shifted mode SETUPRCV for USB_GRXSTSP */ 1280 #define USB_GRXSTSP_PKTSTS_CHLT (_USB_GRXSTSP_PKTSTS_CHLT << 17) /**< Shifted mode CHLT for USB_GRXSTSP */ 1281 #define _USB_GRXSTSP_FN_SHIFT 21 /**< Shift value for USB_FN */ 1282 #define _USB_GRXSTSP_FN_MASK 0x1E00000UL /**< Bit mask for USB_FN */ 1283 #define _USB_GRXSTSP_FN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ 1284 #define USB_GRXSTSP_FN_DEFAULT (_USB_GRXSTSP_FN_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GRXSTSP */ 1285 1286 /* Bit fields for USB GRXFSIZ */ 1287 #define _USB_GRXFSIZ_RESETVALUE 0x00000200UL /**< Default value for USB_GRXFSIZ */ 1288 #define _USB_GRXFSIZ_MASK 0x000003FFUL /**< Mask for USB_GRXFSIZ */ 1289 #define _USB_GRXFSIZ_RXFDEP_SHIFT 0 /**< Shift value for USB_RXFDEP */ 1290 #define _USB_GRXFSIZ_RXFDEP_MASK 0x3FFUL /**< Bit mask for USB_RXFDEP */ 1291 #define _USB_GRXFSIZ_RXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GRXFSIZ */ 1292 #define USB_GRXFSIZ_RXFDEP_DEFAULT (_USB_GRXFSIZ_RXFDEP_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXFSIZ */ 1293 1294 /* Bit fields for USB GNPTXFSIZ */ 1295 #define _USB_GNPTXFSIZ_RESETVALUE 0x02000200UL /**< Default value for USB_GNPTXFSIZ */ 1296 #define _USB_GNPTXFSIZ_MASK 0xFFFFFFFFUL /**< Mask for USB_GNPTXFSIZ */ 1297 #define _USB_GNPTXFSIZ_NPTXFSTADDR_SHIFT 0 /**< Shift value for USB_NPTXFSTADDR */ 1298 #define _USB_GNPTXFSIZ_NPTXFSTADDR_MASK 0xFFFFUL /**< Bit mask for USB_NPTXFSTADDR */ 1299 #define _USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXFSIZ */ 1300 #define USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT (_USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GNPTXFSIZ */ 1301 #define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_SHIFT 16 /**< Shift value for USB_NPTXFINEPTXF0DEP */ 1302 #define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_MASK 0xFFFF0000UL /**< Bit mask for USB_NPTXFINEPTXF0DEP */ 1303 #define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXFSIZ */ 1304 #define USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT (_USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GNPTXFSIZ */ 1305 1306 /* Bit fields for USB GNPTXSTS */ 1307 #define _USB_GNPTXSTS_RESETVALUE 0x00080200UL /**< Default value for USB_GNPTXSTS */ 1308 #define _USB_GNPTXSTS_MASK 0x7FFFFFFFUL /**< Mask for USB_GNPTXSTS */ 1309 #define _USB_GNPTXSTS_NPTXFSPCAVAIL_SHIFT 0 /**< Shift value for USB_NPTXFSPCAVAIL */ 1310 #define _USB_GNPTXSTS_NPTXFSPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_NPTXFSPCAVAIL */ 1311 #define _USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXSTS */ 1312 #define USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT (_USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GNPTXSTS */ 1313 #define _USB_GNPTXSTS_NPTXQSPCAVAIL_SHIFT 16 /**< Shift value for USB_NPTXQSPCAVAIL */ 1314 #define _USB_GNPTXSTS_NPTXQSPCAVAIL_MASK 0xFF0000UL /**< Bit mask for USB_NPTXQSPCAVAIL */ 1315 #define _USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT 0x00000008UL /**< Mode DEFAULT for USB_GNPTXSTS */ 1316 #define USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT (_USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GNPTXSTS */ 1317 #define _USB_GNPTXSTS_NPTXQTOP_SHIFT 24 /**< Shift value for USB_NPTXQTOP */ 1318 #define _USB_GNPTXSTS_NPTXQTOP_MASK 0x7F000000UL /**< Bit mask for USB_NPTXQTOP */ 1319 #define _USB_GNPTXSTS_NPTXQTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GNPTXSTS */ 1320 #define USB_GNPTXSTS_NPTXQTOP_DEFAULT (_USB_GNPTXSTS_NPTXQTOP_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GNPTXSTS */ 1321 1322 /* Bit fields for USB GSNPSID */ 1323 #define _USB_GSNPSID_RESETVALUE 0x4F54330AUL /**< Default value for USB_GSNPSID */ 1324 #define _USB_GSNPSID_MASK 0xFFFFFFFFUL /**< Mask for USB_GSNPSID */ 1325 #define _USB_GSNPSID_SYNOPSYSID_SHIFT 0 /**< Shift value for USB_SYNOPSYSID */ 1326 #define _USB_GSNPSID_SYNOPSYSID_MASK 0xFFFFFFFFUL /**< Bit mask for USB_SYNOPSYSID */ 1327 #define _USB_GSNPSID_SYNOPSYSID_DEFAULT 0x4F54330AUL /**< Mode DEFAULT for USB_GSNPSID */ 1328 #define USB_GSNPSID_SYNOPSYSID_DEFAULT (_USB_GSNPSID_SYNOPSYSID_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GSNPSID */ 1329 1330 /* Bit fields for USB GDFIFOCFG */ 1331 #define _USB_GDFIFOCFG_RESETVALUE 0x01F20200UL /**< Default value for USB_GDFIFOCFG */ 1332 #define _USB_GDFIFOCFG_MASK 0xFFFFFFFFUL /**< Mask for USB_GDFIFOCFG */ 1333 #define _USB_GDFIFOCFG_GDFIFOCFG_SHIFT 0 /**< Shift value for USB_GDFIFOCFG */ 1334 #define _USB_GDFIFOCFG_GDFIFOCFG_MASK 0xFFFFUL /**< Bit mask for USB_GDFIFOCFG */ 1335 #define _USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GDFIFOCFG */ 1336 #define USB_GDFIFOCFG_GDFIFOCFG_DEFAULT (_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GDFIFOCFG */ 1337 #define _USB_GDFIFOCFG_EPINFOBASEADDR_SHIFT 16 /**< Shift value for USB_EPINFOBASEADDR */ 1338 #define _USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xFFFF0000UL /**< Bit mask for USB_EPINFOBASEADDR */ 1339 #define _USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x000001F2UL /**< Mode DEFAULT for USB_GDFIFOCFG */ 1340 #define USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT (_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GDFIFOCFG */ 1341 1342 /* Bit fields for USB HPTXFSIZ */ 1343 #define _USB_HPTXFSIZ_RESETVALUE 0x02000400UL /**< Default value for USB_HPTXFSIZ */ 1344 #define _USB_HPTXFSIZ_MASK 0x03FF07FFUL /**< Mask for USB_HPTXFSIZ */ 1345 #define _USB_HPTXFSIZ_PTXFSTADDR_SHIFT 0 /**< Shift value for USB_PTXFSTADDR */ 1346 #define _USB_HPTXFSIZ_PTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_PTXFSTADDR */ 1347 #define _USB_HPTXFSIZ_PTXFSTADDR_DEFAULT 0x00000400UL /**< Mode DEFAULT for USB_HPTXFSIZ */ 1348 #define USB_HPTXFSIZ_PTXFSTADDR_DEFAULT (_USB_HPTXFSIZ_PTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HPTXFSIZ */ 1349 #define _USB_HPTXFSIZ_PTXFSIZE_SHIFT 16 /**< Shift value for USB_PTXFSIZE */ 1350 #define _USB_HPTXFSIZ_PTXFSIZE_MASK 0x3FF0000UL /**< Bit mask for USB_PTXFSIZE */ 1351 #define _USB_HPTXFSIZ_PTXFSIZE_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_HPTXFSIZ */ 1352 #define USB_HPTXFSIZ_PTXFSIZE_DEFAULT (_USB_HPTXFSIZ_PTXFSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HPTXFSIZ */ 1353 1354 /* Bit fields for USB DIEPTXF1 */ 1355 #define _USB_DIEPTXF1_RESETVALUE 0x02000400UL /**< Default value for USB_DIEPTXF1 */ 1356 #define _USB_DIEPTXF1_MASK 0x03FF07FFUL /**< Mask for USB_DIEPTXF1 */ 1357 #define _USB_DIEPTXF1_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ 1358 #define _USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_INEPNTXFSTADDR */ 1359 #define _USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x00000400UL /**< Mode DEFAULT for USB_DIEPTXF1 */ 1360 #define USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF1 */ 1361 #define _USB_DIEPTXF1_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ 1362 #define _USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ 1363 #define _USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF1 */ 1364 #define USB_DIEPTXF1_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF1 */ 1365 1366 /* Bit fields for USB DIEPTXF2 */ 1367 #define _USB_DIEPTXF2_RESETVALUE 0x02000600UL /**< Default value for USB_DIEPTXF2 */ 1368 #define _USB_DIEPTXF2_MASK 0x03FF07FFUL /**< Mask for USB_DIEPTXF2 */ 1369 #define _USB_DIEPTXF2_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ 1370 #define _USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_INEPNTXFSTADDR */ 1371 #define _USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x00000600UL /**< Mode DEFAULT for USB_DIEPTXF2 */ 1372 #define USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF2 */ 1373 #define _USB_DIEPTXF2_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ 1374 #define _USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ 1375 #define _USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF2 */ 1376 #define USB_DIEPTXF2_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF2 */ 1377 1378 /* Bit fields for USB DIEPTXF3 */ 1379 #define _USB_DIEPTXF3_RESETVALUE 0x02000800UL /**< Default value for USB_DIEPTXF3 */ 1380 #define _USB_DIEPTXF3_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF3 */ 1381 #define _USB_DIEPTXF3_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ 1382 #define _USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */ 1383 #define _USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x00000800UL /**< Mode DEFAULT for USB_DIEPTXF3 */ 1384 #define USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF3 */ 1385 #define _USB_DIEPTXF3_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ 1386 #define _USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ 1387 #define _USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF3 */ 1388 #define USB_DIEPTXF3_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF3 */ 1389 1390 /* Bit fields for USB DIEPTXF4 */ 1391 #define _USB_DIEPTXF4_RESETVALUE 0x02000A00UL /**< Default value for USB_DIEPTXF4 */ 1392 #define _USB_DIEPTXF4_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF4 */ 1393 #define _USB_DIEPTXF4_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ 1394 #define _USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */ 1395 #define _USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x00000A00UL /**< Mode DEFAULT for USB_DIEPTXF4 */ 1396 #define USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF4 */ 1397 #define _USB_DIEPTXF4_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ 1398 #define _USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ 1399 #define _USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF4 */ 1400 #define USB_DIEPTXF4_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF4 */ 1401 1402 /* Bit fields for USB DIEPTXF5 */ 1403 #define _USB_DIEPTXF5_RESETVALUE 0x02000C00UL /**< Default value for USB_DIEPTXF5 */ 1404 #define _USB_DIEPTXF5_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF5 */ 1405 #define _USB_DIEPTXF5_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ 1406 #define _USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */ 1407 #define _USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x00000C00UL /**< Mode DEFAULT for USB_DIEPTXF5 */ 1408 #define USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF5 */ 1409 #define _USB_DIEPTXF5_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ 1410 #define _USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ 1411 #define _USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF5 */ 1412 #define USB_DIEPTXF5_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF5 */ 1413 1414 /* Bit fields for USB DIEPTXF6 */ 1415 #define _USB_DIEPTXF6_RESETVALUE 0x02000E00UL /**< Default value for USB_DIEPTXF6 */ 1416 #define _USB_DIEPTXF6_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF6 */ 1417 #define _USB_DIEPTXF6_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ 1418 #define _USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */ 1419 #define _USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x00000E00UL /**< Mode DEFAULT for USB_DIEPTXF6 */ 1420 #define USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF6 */ 1421 #define _USB_DIEPTXF6_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ 1422 #define _USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ 1423 #define _USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF6 */ 1424 #define USB_DIEPTXF6_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF6 */ 1425 1426 /* Bit fields for USB HCFG */ 1427 #define _USB_HCFG_RESETVALUE 0x00000200UL /**< Default value for USB_HCFG */ 1428 #define _USB_HCFG_MASK 0x8000FF87UL /**< Mask for USB_HCFG */ 1429 #define _USB_HCFG_FSLSPCLKSEL_SHIFT 0 /**< Shift value for USB_FSLSPCLKSEL */ 1430 #define _USB_HCFG_FSLSPCLKSEL_MASK 0x3UL /**< Bit mask for USB_FSLSPCLKSEL */ 1431 #define _USB_HCFG_FSLSPCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */ 1432 #define _USB_HCFG_FSLSPCLKSEL_DIV1 0x00000001UL /**< Mode DIV1 for USB_HCFG */ 1433 #define _USB_HCFG_FSLSPCLKSEL_DIV8 0x00000002UL /**< Mode DIV8 for USB_HCFG */ 1434 #define USB_HCFG_FSLSPCLKSEL_DEFAULT (_USB_HCFG_FSLSPCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HCFG */ 1435 #define USB_HCFG_FSLSPCLKSEL_DIV1 (_USB_HCFG_FSLSPCLKSEL_DIV1 << 0) /**< Shifted mode DIV1 for USB_HCFG */ 1436 #define USB_HCFG_FSLSPCLKSEL_DIV8 (_USB_HCFG_FSLSPCLKSEL_DIV8 << 0) /**< Shifted mode DIV8 for USB_HCFG */ 1437 #define USB_HCFG_FSLSSUPP (0x1UL << 2) /**< FS- and LS-Only Support */ 1438 #define _USB_HCFG_FSLSSUPP_SHIFT 2 /**< Shift value for USB_FSLSSUPP */ 1439 #define _USB_HCFG_FSLSSUPP_MASK 0x4UL /**< Bit mask for USB_FSLSSUPP */ 1440 #define _USB_HCFG_FSLSSUPP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */ 1441 #define _USB_HCFG_FSLSSUPP_HSFSLS 0x00000000UL /**< Mode HSFSLS for USB_HCFG */ 1442 #define _USB_HCFG_FSLSSUPP_FSLS 0x00000001UL /**< Mode FSLS for USB_HCFG */ 1443 #define USB_HCFG_FSLSSUPP_DEFAULT (_USB_HCFG_FSLSSUPP_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HCFG */ 1444 #define USB_HCFG_FSLSSUPP_HSFSLS (_USB_HCFG_FSLSSUPP_HSFSLS << 2) /**< Shifted mode HSFSLS for USB_HCFG */ 1445 #define USB_HCFG_FSLSSUPP_FSLS (_USB_HCFG_FSLSSUPP_FSLS << 2) /**< Shifted mode FSLS for USB_HCFG */ 1446 #define USB_HCFG_ENA32KHZS (0x1UL << 7) /**< Enable 32 kHz Suspend Mode */ 1447 #define _USB_HCFG_ENA32KHZS_SHIFT 7 /**< Shift value for USB_ENA32KHZS */ 1448 #define _USB_HCFG_ENA32KHZS_MASK 0x80UL /**< Bit mask for USB_ENA32KHZS */ 1449 #define _USB_HCFG_ENA32KHZS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */ 1450 #define USB_HCFG_ENA32KHZS_DEFAULT (_USB_HCFG_ENA32KHZS_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HCFG */ 1451 #define _USB_HCFG_RESVALID_SHIFT 8 /**< Shift value for USB_RESVALID */ 1452 #define _USB_HCFG_RESVALID_MASK 0xFF00UL /**< Bit mask for USB_RESVALID */ 1453 #define _USB_HCFG_RESVALID_DEFAULT 0x00000002UL /**< Mode DEFAULT for USB_HCFG */ 1454 #define USB_HCFG_RESVALID_DEFAULT (_USB_HCFG_RESVALID_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HCFG */ 1455 #define USB_HCFG_MODECHTIMEN (0x1UL << 31) /**< Mode Change Time */ 1456 #define _USB_HCFG_MODECHTIMEN_SHIFT 31 /**< Shift value for USB_MODECHTIMEN */ 1457 #define _USB_HCFG_MODECHTIMEN_MASK 0x80000000UL /**< Bit mask for USB_MODECHTIMEN */ 1458 #define _USB_HCFG_MODECHTIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */ 1459 #define USB_HCFG_MODECHTIMEN_DEFAULT (_USB_HCFG_MODECHTIMEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_HCFG */ 1460 1461 /* Bit fields for USB HFIR */ 1462 #define _USB_HFIR_RESETVALUE 0x0000EA60UL /**< Default value for USB_HFIR */ 1463 #define _USB_HFIR_MASK 0x0001FFFFUL /**< Mask for USB_HFIR */ 1464 #define _USB_HFIR_FRINT_SHIFT 0 /**< Shift value for USB_FRINT */ 1465 #define _USB_HFIR_FRINT_MASK 0xFFFFUL /**< Bit mask for USB_FRINT */ 1466 #define _USB_HFIR_FRINT_DEFAULT 0x0000EA60UL /**< Mode DEFAULT for USB_HFIR */ 1467 #define USB_HFIR_FRINT_DEFAULT (_USB_HFIR_FRINT_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HFIR */ 1468 #define USB_HFIR_HFIRRLDCTRL (0x1UL << 16) /**< Reload Control */ 1469 #define _USB_HFIR_HFIRRLDCTRL_SHIFT 16 /**< Shift value for USB_HFIRRLDCTRL */ 1470 #define _USB_HFIR_HFIRRLDCTRL_MASK 0x10000UL /**< Bit mask for USB_HFIRRLDCTRL */ 1471 #define _USB_HFIR_HFIRRLDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HFIR */ 1472 #define _USB_HFIR_HFIRRLDCTRL_STATIC 0x00000000UL /**< Mode STATIC for USB_HFIR */ 1473 #define _USB_HFIR_HFIRRLDCTRL_DYNAMIC 0x00000001UL /**< Mode DYNAMIC for USB_HFIR */ 1474 #define USB_HFIR_HFIRRLDCTRL_DEFAULT (_USB_HFIR_HFIRRLDCTRL_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HFIR */ 1475 #define USB_HFIR_HFIRRLDCTRL_STATIC (_USB_HFIR_HFIRRLDCTRL_STATIC << 16) /**< Shifted mode STATIC for USB_HFIR */ 1476 #define USB_HFIR_HFIRRLDCTRL_DYNAMIC (_USB_HFIR_HFIRRLDCTRL_DYNAMIC << 16) /**< Shifted mode DYNAMIC for USB_HFIR */ 1477 1478 /* Bit fields for USB HFNUM */ 1479 #define _USB_HFNUM_RESETVALUE 0x00003FFFUL /**< Default value for USB_HFNUM */ 1480 #define _USB_HFNUM_MASK 0xFFFFFFFFUL /**< Mask for USB_HFNUM */ 1481 #define _USB_HFNUM_FRNUM_SHIFT 0 /**< Shift value for USB_FRNUM */ 1482 #define _USB_HFNUM_FRNUM_MASK 0xFFFFUL /**< Bit mask for USB_FRNUM */ 1483 #define _USB_HFNUM_FRNUM_DEFAULT 0x00003FFFUL /**< Mode DEFAULT for USB_HFNUM */ 1484 #define USB_HFNUM_FRNUM_DEFAULT (_USB_HFNUM_FRNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HFNUM */ 1485 #define _USB_HFNUM_FRREM_SHIFT 16 /**< Shift value for USB_FRREM */ 1486 #define _USB_HFNUM_FRREM_MASK 0xFFFF0000UL /**< Bit mask for USB_FRREM */ 1487 #define _USB_HFNUM_FRREM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HFNUM */ 1488 #define USB_HFNUM_FRREM_DEFAULT (_USB_HFNUM_FRREM_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HFNUM */ 1489 1490 /* Bit fields for USB HPTXSTS */ 1491 #define _USB_HPTXSTS_RESETVALUE 0x00080200UL /**< Default value for USB_HPTXSTS */ 1492 #define _USB_HPTXSTS_MASK 0xFFFFFFFFUL /**< Mask for USB_HPTXSTS */ 1493 #define _USB_HPTXSTS_PTXFSPCAVAIL_SHIFT 0 /**< Shift value for USB_PTXFSPCAVAIL */ 1494 #define _USB_HPTXSTS_PTXFSPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_PTXFSPCAVAIL */ 1495 #define _USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_HPTXSTS */ 1496 #define USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT (_USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HPTXSTS */ 1497 #define _USB_HPTXSTS_PTXQSPCAVAIL_SHIFT 16 /**< Shift value for USB_PTXQSPCAVAIL */ 1498 #define _USB_HPTXSTS_PTXQSPCAVAIL_MASK 0xFF0000UL /**< Bit mask for USB_PTXQSPCAVAIL */ 1499 #define _USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT 0x00000008UL /**< Mode DEFAULT for USB_HPTXSTS */ 1500 #define USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT (_USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HPTXSTS */ 1501 #define _USB_HPTXSTS_PTXQTOP_SHIFT 24 /**< Shift value for USB_PTXQTOP */ 1502 #define _USB_HPTXSTS_PTXQTOP_MASK 0xFF000000UL /**< Bit mask for USB_PTXQTOP */ 1503 #define _USB_HPTXSTS_PTXQTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPTXSTS */ 1504 #define USB_HPTXSTS_PTXQTOP_DEFAULT (_USB_HPTXSTS_PTXQTOP_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_HPTXSTS */ 1505 1506 /* Bit fields for USB HAINT */ 1507 #define _USB_HAINT_RESETVALUE 0x00000000UL /**< Default value for USB_HAINT */ 1508 #define _USB_HAINT_MASK 0x00003FFFUL /**< Mask for USB_HAINT */ 1509 #define _USB_HAINT_HAINT_SHIFT 0 /**< Shift value for USB_HAINT */ 1510 #define _USB_HAINT_HAINT_MASK 0x3FFFUL /**< Bit mask for USB_HAINT */ 1511 #define _USB_HAINT_HAINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HAINT */ 1512 #define USB_HAINT_HAINT_DEFAULT (_USB_HAINT_HAINT_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HAINT */ 1513 1514 /* Bit fields for USB HAINTMSK */ 1515 #define _USB_HAINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_HAINTMSK */ 1516 #define _USB_HAINTMSK_MASK 0x00003FFFUL /**< Mask for USB_HAINTMSK */ 1517 #define _USB_HAINTMSK_HAINTMSK_SHIFT 0 /**< Shift value for USB_HAINTMSK */ 1518 #define _USB_HAINTMSK_HAINTMSK_MASK 0x3FFFUL /**< Bit mask for USB_HAINTMSK */ 1519 #define _USB_HAINTMSK_HAINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HAINTMSK */ 1520 #define USB_HAINTMSK_HAINTMSK_DEFAULT (_USB_HAINTMSK_HAINTMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HAINTMSK */ 1521 1522 /* Bit fields for USB HPRT */ 1523 #define _USB_HPRT_RESETVALUE 0x00000000UL /**< Default value for USB_HPRT */ 1524 #define _USB_HPRT_MASK 0x0007FDFFUL /**< Mask for USB_HPRT */ 1525 #define USB_HPRT_PRTCONNSTS (0x1UL << 0) /**< Port Connect Status */ 1526 #define _USB_HPRT_PRTCONNSTS_SHIFT 0 /**< Shift value for USB_PRTCONNSTS */ 1527 #define _USB_HPRT_PRTCONNSTS_MASK 0x1UL /**< Bit mask for USB_PRTCONNSTS */ 1528 #define _USB_HPRT_PRTCONNSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1529 #define USB_HPRT_PRTCONNSTS_DEFAULT (_USB_HPRT_PRTCONNSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HPRT */ 1530 #define USB_HPRT_PRTCONNDET (0x1UL << 1) /**< Port Connect Detected */ 1531 #define _USB_HPRT_PRTCONNDET_SHIFT 1 /**< Shift value for USB_PRTCONNDET */ 1532 #define _USB_HPRT_PRTCONNDET_MASK 0x2UL /**< Bit mask for USB_PRTCONNDET */ 1533 #define _USB_HPRT_PRTCONNDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1534 #define USB_HPRT_PRTCONNDET_DEFAULT (_USB_HPRT_PRTCONNDET_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_HPRT */ 1535 #define USB_HPRT_PRTENA (0x1UL << 2) /**< Port Enable */ 1536 #define _USB_HPRT_PRTENA_SHIFT 2 /**< Shift value for USB_PRTENA */ 1537 #define _USB_HPRT_PRTENA_MASK 0x4UL /**< Bit mask for USB_PRTENA */ 1538 #define _USB_HPRT_PRTENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1539 #define USB_HPRT_PRTENA_DEFAULT (_USB_HPRT_PRTENA_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HPRT */ 1540 #define USB_HPRT_PRTENCHNG (0x1UL << 3) /**< Port Enable/Disable Change */ 1541 #define _USB_HPRT_PRTENCHNG_SHIFT 3 /**< Shift value for USB_PRTENCHNG */ 1542 #define _USB_HPRT_PRTENCHNG_MASK 0x8UL /**< Bit mask for USB_PRTENCHNG */ 1543 #define _USB_HPRT_PRTENCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1544 #define USB_HPRT_PRTENCHNG_DEFAULT (_USB_HPRT_PRTENCHNG_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_HPRT */ 1545 #define USB_HPRT_PRTOVRCURRACT (0x1UL << 4) /**< Port Overcurrent Active */ 1546 #define _USB_HPRT_PRTOVRCURRACT_SHIFT 4 /**< Shift value for USB_PRTOVRCURRACT */ 1547 #define _USB_HPRT_PRTOVRCURRACT_MASK 0x10UL /**< Bit mask for USB_PRTOVRCURRACT */ 1548 #define _USB_HPRT_PRTOVRCURRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1549 #define USB_HPRT_PRTOVRCURRACT_DEFAULT (_USB_HPRT_PRTOVRCURRACT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_HPRT */ 1550 #define USB_HPRT_PRTOVRCURRCHNG (0x1UL << 5) /**< Port Overcurrent Change */ 1551 #define _USB_HPRT_PRTOVRCURRCHNG_SHIFT 5 /**< Shift value for USB_PRTOVRCURRCHNG */ 1552 #define _USB_HPRT_PRTOVRCURRCHNG_MASK 0x20UL /**< Bit mask for USB_PRTOVRCURRCHNG */ 1553 #define _USB_HPRT_PRTOVRCURRCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1554 #define USB_HPRT_PRTOVRCURRCHNG_DEFAULT (_USB_HPRT_PRTOVRCURRCHNG_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_HPRT */ 1555 #define USB_HPRT_PRTRES (0x1UL << 6) /**< Port Resume */ 1556 #define _USB_HPRT_PRTRES_SHIFT 6 /**< Shift value for USB_PRTRES */ 1557 #define _USB_HPRT_PRTRES_MASK 0x40UL /**< Bit mask for USB_PRTRES */ 1558 #define _USB_HPRT_PRTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1559 #define USB_HPRT_PRTRES_DEFAULT (_USB_HPRT_PRTRES_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_HPRT */ 1560 #define USB_HPRT_PRTSUSP (0x1UL << 7) /**< Port Suspend */ 1561 #define _USB_HPRT_PRTSUSP_SHIFT 7 /**< Shift value for USB_PRTSUSP */ 1562 #define _USB_HPRT_PRTSUSP_MASK 0x80UL /**< Bit mask for USB_PRTSUSP */ 1563 #define _USB_HPRT_PRTSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1564 #define USB_HPRT_PRTSUSP_DEFAULT (_USB_HPRT_PRTSUSP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HPRT */ 1565 #define USB_HPRT_PRTRST (0x1UL << 8) /**< Port Reset */ 1566 #define _USB_HPRT_PRTRST_SHIFT 8 /**< Shift value for USB_PRTRST */ 1567 #define _USB_HPRT_PRTRST_MASK 0x100UL /**< Bit mask for USB_PRTRST */ 1568 #define _USB_HPRT_PRTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1569 #define USB_HPRT_PRTRST_DEFAULT (_USB_HPRT_PRTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HPRT */ 1570 #define _USB_HPRT_PRTLNSTS_SHIFT 10 /**< Shift value for USB_PRTLNSTS */ 1571 #define _USB_HPRT_PRTLNSTS_MASK 0xC00UL /**< Bit mask for USB_PRTLNSTS */ 1572 #define _USB_HPRT_PRTLNSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1573 #define USB_HPRT_PRTLNSTS_DEFAULT (_USB_HPRT_PRTLNSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_HPRT */ 1574 #define USB_HPRT_PRTPWR (0x1UL << 12) /**< Port Power */ 1575 #define _USB_HPRT_PRTPWR_SHIFT 12 /**< Shift value for USB_PRTPWR */ 1576 #define _USB_HPRT_PRTPWR_MASK 0x1000UL /**< Bit mask for USB_PRTPWR */ 1577 #define _USB_HPRT_PRTPWR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1578 #define _USB_HPRT_PRTPWR_OFF 0x00000000UL /**< Mode OFF for USB_HPRT */ 1579 #define _USB_HPRT_PRTPWR_ON 0x00000001UL /**< Mode ON for USB_HPRT */ 1580 #define USB_HPRT_PRTPWR_DEFAULT (_USB_HPRT_PRTPWR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_HPRT */ 1581 #define USB_HPRT_PRTPWR_OFF (_USB_HPRT_PRTPWR_OFF << 12) /**< Shifted mode OFF for USB_HPRT */ 1582 #define USB_HPRT_PRTPWR_ON (_USB_HPRT_PRTPWR_ON << 12) /**< Shifted mode ON for USB_HPRT */ 1583 #define _USB_HPRT_PRTTSTCTL_SHIFT 13 /**< Shift value for USB_PRTTSTCTL */ 1584 #define _USB_HPRT_PRTTSTCTL_MASK 0x1E000UL /**< Bit mask for USB_PRTTSTCTL */ 1585 #define _USB_HPRT_PRTTSTCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1586 #define _USB_HPRT_PRTTSTCTL_DISABLE 0x00000000UL /**< Mode DISABLE for USB_HPRT */ 1587 #define _USB_HPRT_PRTTSTCTL_J 0x00000001UL /**< Mode J for USB_HPRT */ 1588 #define _USB_HPRT_PRTTSTCTL_K 0x00000002UL /**< Mode K for USB_HPRT */ 1589 #define _USB_HPRT_PRTTSTCTL_SE0NAK 0x00000003UL /**< Mode SE0NAK for USB_HPRT */ 1590 #define _USB_HPRT_PRTTSTCTL_PACKET 0x00000004UL /**< Mode PACKET for USB_HPRT */ 1591 #define _USB_HPRT_PRTTSTCTL_FORCE 0x00000005UL /**< Mode FORCE for USB_HPRT */ 1592 #define USB_HPRT_PRTTSTCTL_DEFAULT (_USB_HPRT_PRTTSTCTL_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_HPRT */ 1593 #define USB_HPRT_PRTTSTCTL_DISABLE (_USB_HPRT_PRTTSTCTL_DISABLE << 13) /**< Shifted mode DISABLE for USB_HPRT */ 1594 #define USB_HPRT_PRTTSTCTL_J (_USB_HPRT_PRTTSTCTL_J << 13) /**< Shifted mode J for USB_HPRT */ 1595 #define USB_HPRT_PRTTSTCTL_K (_USB_HPRT_PRTTSTCTL_K << 13) /**< Shifted mode K for USB_HPRT */ 1596 #define USB_HPRT_PRTTSTCTL_SE0NAK (_USB_HPRT_PRTTSTCTL_SE0NAK << 13) /**< Shifted mode SE0NAK for USB_HPRT */ 1597 #define USB_HPRT_PRTTSTCTL_PACKET (_USB_HPRT_PRTTSTCTL_PACKET << 13) /**< Shifted mode PACKET for USB_HPRT */ 1598 #define USB_HPRT_PRTTSTCTL_FORCE (_USB_HPRT_PRTTSTCTL_FORCE << 13) /**< Shifted mode FORCE for USB_HPRT */ 1599 #define _USB_HPRT_PRTSPD_SHIFT 17 /**< Shift value for USB_PRTSPD */ 1600 #define _USB_HPRT_PRTSPD_MASK 0x60000UL /**< Bit mask for USB_PRTSPD */ 1601 #define _USB_HPRT_PRTSPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ 1602 #define _USB_HPRT_PRTSPD_FS 0x00000001UL /**< Mode FS for USB_HPRT */ 1603 #define _USB_HPRT_PRTSPD_LS 0x00000002UL /**< Mode LS for USB_HPRT */ 1604 #define USB_HPRT_PRTSPD_DEFAULT (_USB_HPRT_PRTSPD_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_HPRT */ 1605 #define USB_HPRT_PRTSPD_FS (_USB_HPRT_PRTSPD_FS << 17) /**< Shifted mode FS for USB_HPRT */ 1606 #define USB_HPRT_PRTSPD_LS (_USB_HPRT_PRTSPD_LS << 17) /**< Shifted mode LS for USB_HPRT */ 1607 1608 /* Bit fields for USB HC_CHAR */ 1609 #define _USB_HC_CHAR_RESETVALUE 0x00000000UL /**< Default value for USB_HC_CHAR */ 1610 #define _USB_HC_CHAR_MASK 0xFFFEFFFFUL /**< Mask for USB_HC_CHAR */ 1611 #define _USB_HC_CHAR_MPS_SHIFT 0 /**< Shift value for USB_MPS */ 1612 #define _USB_HC_CHAR_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */ 1613 #define _USB_HC_CHAR_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ 1614 #define USB_HC_CHAR_MPS_DEFAULT (_USB_HC_CHAR_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_CHAR */ 1615 #define _USB_HC_CHAR_EPNUM_SHIFT 11 /**< Shift value for USB_EPNUM */ 1616 #define _USB_HC_CHAR_EPNUM_MASK 0x7800UL /**< Bit mask for USB_EPNUM */ 1617 #define _USB_HC_CHAR_EPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ 1618 #define USB_HC_CHAR_EPNUM_DEFAULT (_USB_HC_CHAR_EPNUM_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_HC_CHAR */ 1619 #define USB_HC_CHAR_EPDIR (0x1UL << 15) /**< Endpoint Direction */ 1620 #define _USB_HC_CHAR_EPDIR_SHIFT 15 /**< Shift value for USB_EPDIR */ 1621 #define _USB_HC_CHAR_EPDIR_MASK 0x8000UL /**< Bit mask for USB_EPDIR */ 1622 #define _USB_HC_CHAR_EPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ 1623 #define _USB_HC_CHAR_EPDIR_OUT 0x00000000UL /**< Mode OUT for USB_HC_CHAR */ 1624 #define _USB_HC_CHAR_EPDIR_IN 0x00000001UL /**< Mode IN for USB_HC_CHAR */ 1625 #define USB_HC_CHAR_EPDIR_DEFAULT (_USB_HC_CHAR_EPDIR_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_HC_CHAR */ 1626 #define USB_HC_CHAR_EPDIR_OUT (_USB_HC_CHAR_EPDIR_OUT << 15) /**< Shifted mode OUT for USB_HC_CHAR */ 1627 #define USB_HC_CHAR_EPDIR_IN (_USB_HC_CHAR_EPDIR_IN << 15) /**< Shifted mode IN for USB_HC_CHAR */ 1628 #define USB_HC_CHAR_LSPDDEV (0x1UL << 17) /**< Low-Speed Device */ 1629 #define _USB_HC_CHAR_LSPDDEV_SHIFT 17 /**< Shift value for USB_LSPDDEV */ 1630 #define _USB_HC_CHAR_LSPDDEV_MASK 0x20000UL /**< Bit mask for USB_LSPDDEV */ 1631 #define _USB_HC_CHAR_LSPDDEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ 1632 #define USB_HC_CHAR_LSPDDEV_DEFAULT (_USB_HC_CHAR_LSPDDEV_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_HC_CHAR */ 1633 #define _USB_HC_CHAR_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ 1634 #define _USB_HC_CHAR_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ 1635 #define _USB_HC_CHAR_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ 1636 #define _USB_HC_CHAR_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_HC_CHAR */ 1637 #define _USB_HC_CHAR_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_HC_CHAR */ 1638 #define _USB_HC_CHAR_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_HC_CHAR */ 1639 #define _USB_HC_CHAR_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_HC_CHAR */ 1640 #define USB_HC_CHAR_EPTYPE_DEFAULT (_USB_HC_CHAR_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_HC_CHAR */ 1641 #define USB_HC_CHAR_EPTYPE_CONTROL (_USB_HC_CHAR_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_HC_CHAR */ 1642 #define USB_HC_CHAR_EPTYPE_ISO (_USB_HC_CHAR_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_HC_CHAR */ 1643 #define USB_HC_CHAR_EPTYPE_BULK (_USB_HC_CHAR_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_HC_CHAR */ 1644 #define USB_HC_CHAR_EPTYPE_INT (_USB_HC_CHAR_EPTYPE_INT << 18) /**< Shifted mode INT for USB_HC_CHAR */ 1645 #define _USB_HC_CHAR_MC_SHIFT 20 /**< Shift value for USB_MC */ 1646 #define _USB_HC_CHAR_MC_MASK 0x300000UL /**< Bit mask for USB_MC */ 1647 #define _USB_HC_CHAR_MC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ 1648 #define USB_HC_CHAR_MC_DEFAULT (_USB_HC_CHAR_MC_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_HC_CHAR */ 1649 #define _USB_HC_CHAR_DEVADDR_SHIFT 22 /**< Shift value for USB_DEVADDR */ 1650 #define _USB_HC_CHAR_DEVADDR_MASK 0x1FC00000UL /**< Bit mask for USB_DEVADDR */ 1651 #define _USB_HC_CHAR_DEVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ 1652 #define USB_HC_CHAR_DEVADDR_DEFAULT (_USB_HC_CHAR_DEVADDR_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_HC_CHAR */ 1653 #define USB_HC_CHAR_ODDFRM (0x1UL << 29) /**< Odd Frame */ 1654 #define _USB_HC_CHAR_ODDFRM_SHIFT 29 /**< Shift value for USB_ODDFRM */ 1655 #define _USB_HC_CHAR_ODDFRM_MASK 0x20000000UL /**< Bit mask for USB_ODDFRM */ 1656 #define _USB_HC_CHAR_ODDFRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ 1657 #define USB_HC_CHAR_ODDFRM_DEFAULT (_USB_HC_CHAR_ODDFRM_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_HC_CHAR */ 1658 #define USB_HC_CHAR_CHDIS (0x1UL << 30) /**< Channel Disable */ 1659 #define _USB_HC_CHAR_CHDIS_SHIFT 30 /**< Shift value for USB_CHDIS */ 1660 #define _USB_HC_CHAR_CHDIS_MASK 0x40000000UL /**< Bit mask for USB_CHDIS */ 1661 #define _USB_HC_CHAR_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ 1662 #define USB_HC_CHAR_CHDIS_DEFAULT (_USB_HC_CHAR_CHDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_HC_CHAR */ 1663 #define USB_HC_CHAR_CHENA (0x1UL << 31) /**< Channel Enable */ 1664 #define _USB_HC_CHAR_CHENA_SHIFT 31 /**< Shift value for USB_CHENA */ 1665 #define _USB_HC_CHAR_CHENA_MASK 0x80000000UL /**< Bit mask for USB_CHENA */ 1666 #define _USB_HC_CHAR_CHENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ 1667 #define USB_HC_CHAR_CHENA_DEFAULT (_USB_HC_CHAR_CHENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_HC_CHAR */ 1668 1669 /* Bit fields for USB HC_SPLT */ 1670 #define _USB_HC_SPLT_RESETVALUE 0x00000000UL /**< Default value for USB_HC_SPLT */ 1671 #define _USB_HC_SPLT_MASK 0x8001FFFFUL /**< Mask for USB_HC_SPLT */ 1672 #define _USB_HC_SPLT_PRTADDR_SHIFT 0 /**< Shift value for USB_PRTADDR */ 1673 #define _USB_HC_SPLT_PRTADDR_MASK 0x7FUL /**< Bit mask for USB_PRTADDR */ 1674 #define _USB_HC_SPLT_PRTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_SPLT */ 1675 #define USB_HC_SPLT_PRTADDR_DEFAULT (_USB_HC_SPLT_PRTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_SPLT */ 1676 #define _USB_HC_SPLT_HUBADDR_SHIFT 7 /**< Shift value for USB_HUBADDR */ 1677 #define _USB_HC_SPLT_HUBADDR_MASK 0x3F80UL /**< Bit mask for USB_HUBADDR */ 1678 #define _USB_HC_SPLT_HUBADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_SPLT */ 1679 #define USB_HC_SPLT_HUBADDR_DEFAULT (_USB_HC_SPLT_HUBADDR_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HC_SPLT */ 1680 #define _USB_HC_SPLT_XACTPOS_SHIFT 14 /**< Shift value for USB_XACTPOS */ 1681 #define _USB_HC_SPLT_XACTPOS_MASK 0xC000UL /**< Bit mask for USB_XACTPOS */ 1682 #define _USB_HC_SPLT_XACTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_SPLT */ 1683 #define USB_HC_SPLT_XACTPOS_DEFAULT (_USB_HC_SPLT_XACTPOS_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_HC_SPLT */ 1684 #define USB_HC_SPLT_COMPSPLT (0x1UL << 16) /**< Do Complete Split */ 1685 #define _USB_HC_SPLT_COMPSPLT_SHIFT 16 /**< Shift value for USB_COMPSPLT */ 1686 #define _USB_HC_SPLT_COMPSPLT_MASK 0x10000UL /**< Bit mask for USB_COMPSPLT */ 1687 #define _USB_HC_SPLT_COMPSPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_SPLT */ 1688 #define USB_HC_SPLT_COMPSPLT_DEFAULT (_USB_HC_SPLT_COMPSPLT_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HC_SPLT */ 1689 #define USB_HC_SPLT_SPLTENA (0x1UL << 31) /**< Split Enable */ 1690 #define _USB_HC_SPLT_SPLTENA_SHIFT 31 /**< Shift value for USB_SPLTENA */ 1691 #define _USB_HC_SPLT_SPLTENA_MASK 0x80000000UL /**< Bit mask for USB_SPLTENA */ 1692 #define _USB_HC_SPLT_SPLTENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_SPLT */ 1693 #define USB_HC_SPLT_SPLTENA_DEFAULT (_USB_HC_SPLT_SPLTENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_HC_SPLT */ 1694 1695 /* Bit fields for USB HC_INT */ 1696 #define _USB_HC_INT_RESETVALUE 0x00000000UL /**< Default value for USB_HC_INT */ 1697 #define _USB_HC_INT_MASK 0x000007BFUL /**< Mask for USB_HC_INT */ 1698 #define USB_HC_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed */ 1699 #define _USB_HC_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ 1700 #define _USB_HC_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ 1701 #define _USB_HC_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ 1702 #define USB_HC_INT_XFERCOMPL_DEFAULT (_USB_HC_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_INT */ 1703 #define USB_HC_INT_CHHLTD (0x1UL << 1) /**< Channel Halted */ 1704 #define _USB_HC_INT_CHHLTD_SHIFT 1 /**< Shift value for USB_CHHLTD */ 1705 #define _USB_HC_INT_CHHLTD_MASK 0x2UL /**< Bit mask for USB_CHHLTD */ 1706 #define _USB_HC_INT_CHHLTD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ 1707 #define USB_HC_INT_CHHLTD_DEFAULT (_USB_HC_INT_CHHLTD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_HC_INT */ 1708 #define USB_HC_INT_AHBERR (0x1UL << 2) /**< AHB Error */ 1709 #define _USB_HC_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ 1710 #define _USB_HC_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ 1711 #define _USB_HC_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ 1712 #define USB_HC_INT_AHBERR_DEFAULT (_USB_HC_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HC_INT */ 1713 #define USB_HC_INT_STALL (0x1UL << 3) /**< STALL Response Received Interrupt */ 1714 #define _USB_HC_INT_STALL_SHIFT 3 /**< Shift value for USB_STALL */ 1715 #define _USB_HC_INT_STALL_MASK 0x8UL /**< Bit mask for USB_STALL */ 1716 #define _USB_HC_INT_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ 1717 #define USB_HC_INT_STALL_DEFAULT (_USB_HC_INT_STALL_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_HC_INT */ 1718 #define USB_HC_INT_NAK (0x1UL << 4) /**< NAK Response Received Interrupt */ 1719 #define _USB_HC_INT_NAK_SHIFT 4 /**< Shift value for USB_NAK */ 1720 #define _USB_HC_INT_NAK_MASK 0x10UL /**< Bit mask for USB_NAK */ 1721 #define _USB_HC_INT_NAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ 1722 #define USB_HC_INT_NAK_DEFAULT (_USB_HC_INT_NAK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_HC_INT */ 1723 #define USB_HC_INT_ACK (0x1UL << 5) /**< ACK Response Received/Transmitted Interrupt */ 1724 #define _USB_HC_INT_ACK_SHIFT 5 /**< Shift value for USB_ACK */ 1725 #define _USB_HC_INT_ACK_MASK 0x20UL /**< Bit mask for USB_ACK */ 1726 #define _USB_HC_INT_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ 1727 #define USB_HC_INT_ACK_DEFAULT (_USB_HC_INT_ACK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_HC_INT */ 1728 #define USB_HC_INT_XACTERR (0x1UL << 7) /**< Transaction Error */ 1729 #define _USB_HC_INT_XACTERR_SHIFT 7 /**< Shift value for USB_XACTERR */ 1730 #define _USB_HC_INT_XACTERR_MASK 0x80UL /**< Bit mask for USB_XACTERR */ 1731 #define _USB_HC_INT_XACTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ 1732 #define USB_HC_INT_XACTERR_DEFAULT (_USB_HC_INT_XACTERR_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HC_INT */ 1733 #define USB_HC_INT_BBLERR (0x1UL << 8) /**< Babble Error */ 1734 #define _USB_HC_INT_BBLERR_SHIFT 8 /**< Shift value for USB_BBLERR */ 1735 #define _USB_HC_INT_BBLERR_MASK 0x100UL /**< Bit mask for USB_BBLERR */ 1736 #define _USB_HC_INT_BBLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ 1737 #define USB_HC_INT_BBLERR_DEFAULT (_USB_HC_INT_BBLERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HC_INT */ 1738 #define USB_HC_INT_FRMOVRUN (0x1UL << 9) /**< Frame Overrun */ 1739 #define _USB_HC_INT_FRMOVRUN_SHIFT 9 /**< Shift value for USB_FRMOVRUN */ 1740 #define _USB_HC_INT_FRMOVRUN_MASK 0x200UL /**< Bit mask for USB_FRMOVRUN */ 1741 #define _USB_HC_INT_FRMOVRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ 1742 #define USB_HC_INT_FRMOVRUN_DEFAULT (_USB_HC_INT_FRMOVRUN_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_HC_INT */ 1743 #define USB_HC_INT_DATATGLERR (0x1UL << 10) /**< Data Toggle Error */ 1744 #define _USB_HC_INT_DATATGLERR_SHIFT 10 /**< Shift value for USB_DATATGLERR */ 1745 #define _USB_HC_INT_DATATGLERR_MASK 0x400UL /**< Bit mask for USB_DATATGLERR */ 1746 #define _USB_HC_INT_DATATGLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ 1747 #define USB_HC_INT_DATATGLERR_DEFAULT (_USB_HC_INT_DATATGLERR_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_HC_INT */ 1748 1749 /* Bit fields for USB HC_INTMSK */ 1750 #define _USB_HC_INTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_HC_INTMSK */ 1751 #define _USB_HC_INTMSK_MASK 0x000007BFUL /**< Mask for USB_HC_INTMSK */ 1752 #define USB_HC_INTMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Mask */ 1753 #define _USB_HC_INTMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */ 1754 #define _USB_HC_INTMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */ 1755 #define _USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ 1756 #define USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT (_USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ 1757 #define USB_HC_INTMSK_CHHLTDMSK (0x1UL << 1) /**< Channel Halted Mask */ 1758 #define _USB_HC_INTMSK_CHHLTDMSK_SHIFT 1 /**< Shift value for USB_CHHLTDMSK */ 1759 #define _USB_HC_INTMSK_CHHLTDMSK_MASK 0x2UL /**< Bit mask for USB_CHHLTDMSK */ 1760 #define _USB_HC_INTMSK_CHHLTDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ 1761 #define USB_HC_INTMSK_CHHLTDMSK_DEFAULT (_USB_HC_INTMSK_CHHLTDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ 1762 #define USB_HC_INTMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error Mask */ 1763 #define _USB_HC_INTMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */ 1764 #define _USB_HC_INTMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */ 1765 #define _USB_HC_INTMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ 1766 #define USB_HC_INTMSK_AHBERRMSK_DEFAULT (_USB_HC_INTMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ 1767 #define USB_HC_INTMSK_STALLMSK (0x1UL << 3) /**< STALL Response Received Interrupt Mask */ 1768 #define _USB_HC_INTMSK_STALLMSK_SHIFT 3 /**< Shift value for USB_STALLMSK */ 1769 #define _USB_HC_INTMSK_STALLMSK_MASK 0x8UL /**< Bit mask for USB_STALLMSK */ 1770 #define _USB_HC_INTMSK_STALLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ 1771 #define USB_HC_INTMSK_STALLMSK_DEFAULT (_USB_HC_INTMSK_STALLMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ 1772 #define USB_HC_INTMSK_NAKMSK (0x1UL << 4) /**< NAK Response Received Interrupt Mask */ 1773 #define _USB_HC_INTMSK_NAKMSK_SHIFT 4 /**< Shift value for USB_NAKMSK */ 1774 #define _USB_HC_INTMSK_NAKMSK_MASK 0x10UL /**< Bit mask for USB_NAKMSK */ 1775 #define _USB_HC_INTMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ 1776 #define USB_HC_INTMSK_NAKMSK_DEFAULT (_USB_HC_INTMSK_NAKMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ 1777 #define USB_HC_INTMSK_ACKMSK (0x1UL << 5) /**< ACK Response Received/Transmitted Interrupt Mask */ 1778 #define _USB_HC_INTMSK_ACKMSK_SHIFT 5 /**< Shift value for USB_ACKMSK */ 1779 #define _USB_HC_INTMSK_ACKMSK_MASK 0x20UL /**< Bit mask for USB_ACKMSK */ 1780 #define _USB_HC_INTMSK_ACKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ 1781 #define USB_HC_INTMSK_ACKMSK_DEFAULT (_USB_HC_INTMSK_ACKMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ 1782 #define USB_HC_INTMSK_XACTERRMSK (0x1UL << 7) /**< Transaction Error Mask */ 1783 #define _USB_HC_INTMSK_XACTERRMSK_SHIFT 7 /**< Shift value for USB_XACTERRMSK */ 1784 #define _USB_HC_INTMSK_XACTERRMSK_MASK 0x80UL /**< Bit mask for USB_XACTERRMSK */ 1785 #define _USB_HC_INTMSK_XACTERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ 1786 #define USB_HC_INTMSK_XACTERRMSK_DEFAULT (_USB_HC_INTMSK_XACTERRMSK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ 1787 #define USB_HC_INTMSK_BBLERRMSK (0x1UL << 8) /**< Babble Error Mask */ 1788 #define _USB_HC_INTMSK_BBLERRMSK_SHIFT 8 /**< Shift value for USB_BBLERRMSK */ 1789 #define _USB_HC_INTMSK_BBLERRMSK_MASK 0x100UL /**< Bit mask for USB_BBLERRMSK */ 1790 #define _USB_HC_INTMSK_BBLERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ 1791 #define USB_HC_INTMSK_BBLERRMSK_DEFAULT (_USB_HC_INTMSK_BBLERRMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ 1792 #define USB_HC_INTMSK_FRMOVRUNMSK (0x1UL << 9) /**< Frame Overrun Mask */ 1793 #define _USB_HC_INTMSK_FRMOVRUNMSK_SHIFT 9 /**< Shift value for USB_FRMOVRUNMSK */ 1794 #define _USB_HC_INTMSK_FRMOVRUNMSK_MASK 0x200UL /**< Bit mask for USB_FRMOVRUNMSK */ 1795 #define _USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ 1796 #define USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT (_USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ 1797 #define USB_HC_INTMSK_DATATGLERRMSK (0x1UL << 10) /**< Data Toggle Error Mask */ 1798 #define _USB_HC_INTMSK_DATATGLERRMSK_SHIFT 10 /**< Shift value for USB_DATATGLERRMSK */ 1799 #define _USB_HC_INTMSK_DATATGLERRMSK_MASK 0x400UL /**< Bit mask for USB_DATATGLERRMSK */ 1800 #define _USB_HC_INTMSK_DATATGLERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ 1801 #define USB_HC_INTMSK_DATATGLERRMSK_DEFAULT (_USB_HC_INTMSK_DATATGLERRMSK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ 1802 1803 /* Bit fields for USB HC_TSIZ */ 1804 #define _USB_HC_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_HC_TSIZ */ 1805 #define _USB_HC_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_HC_TSIZ */ 1806 #define _USB_HC_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ 1807 #define _USB_HC_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */ 1808 #define _USB_HC_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_TSIZ */ 1809 #define USB_HC_TSIZ_XFERSIZE_DEFAULT (_USB_HC_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_TSIZ */ 1810 #define _USB_HC_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ 1811 #define _USB_HC_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */ 1812 #define _USB_HC_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_TSIZ */ 1813 #define USB_HC_TSIZ_PKTCNT_DEFAULT (_USB_HC_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_HC_TSIZ */ 1814 #define _USB_HC_TSIZ_PID_SHIFT 29 /**< Shift value for USB_PID */ 1815 #define _USB_HC_TSIZ_PID_MASK 0x60000000UL /**< Bit mask for USB_PID */ 1816 #define _USB_HC_TSIZ_PID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_TSIZ */ 1817 #define _USB_HC_TSIZ_PID_DATA0 0x00000000UL /**< Mode DATA0 for USB_HC_TSIZ */ 1818 #define _USB_HC_TSIZ_PID_DATA2 0x00000001UL /**< Mode DATA2 for USB_HC_TSIZ */ 1819 #define _USB_HC_TSIZ_PID_DATA1 0x00000002UL /**< Mode DATA1 for USB_HC_TSIZ */ 1820 #define _USB_HC_TSIZ_PID_MDATA 0x00000003UL /**< Mode MDATA for USB_HC_TSIZ */ 1821 #define USB_HC_TSIZ_PID_DEFAULT (_USB_HC_TSIZ_PID_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_HC_TSIZ */ 1822 #define USB_HC_TSIZ_PID_DATA0 (_USB_HC_TSIZ_PID_DATA0 << 29) /**< Shifted mode DATA0 for USB_HC_TSIZ */ 1823 #define USB_HC_TSIZ_PID_DATA2 (_USB_HC_TSIZ_PID_DATA2 << 29) /**< Shifted mode DATA2 for USB_HC_TSIZ */ 1824 #define USB_HC_TSIZ_PID_DATA1 (_USB_HC_TSIZ_PID_DATA1 << 29) /**< Shifted mode DATA1 for USB_HC_TSIZ */ 1825 #define USB_HC_TSIZ_PID_MDATA (_USB_HC_TSIZ_PID_MDATA << 29) /**< Shifted mode MDATA for USB_HC_TSIZ */ 1826 1827 /* Bit fields for USB HC_DMAADDR */ 1828 #define _USB_HC_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_HC_DMAADDR */ 1829 #define _USB_HC_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_HC_DMAADDR */ 1830 #define _USB_HC_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */ 1831 #define _USB_HC_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */ 1832 #define _USB_HC_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_DMAADDR */ 1833 #define USB_HC_DMAADDR_DMAADDR_DEFAULT (_USB_HC_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_DMAADDR */ 1834 1835 /* Bit fields for USB DCFG */ 1836 #define _USB_DCFG_RESETVALUE 0x08000000UL /**< Default value for USB_DCFG */ 1837 #define _USB_DCFG_MASK 0xFC00FFFFUL /**< Mask for USB_DCFG */ 1838 #define _USB_DCFG_DEVSPD_SHIFT 0 /**< Shift value for USB_DEVSPD */ 1839 #define _USB_DCFG_DEVSPD_MASK 0x3UL /**< Bit mask for USB_DEVSPD */ 1840 #define _USB_DCFG_DEVSPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ 1841 #define _USB_DCFG_DEVSPD_LS 0x00000002UL /**< Mode LS for USB_DCFG */ 1842 #define _USB_DCFG_DEVSPD_FS 0x00000003UL /**< Mode FS for USB_DCFG */ 1843 #define USB_DCFG_DEVSPD_DEFAULT (_USB_DCFG_DEVSPD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DCFG */ 1844 #define USB_DCFG_DEVSPD_LS (_USB_DCFG_DEVSPD_LS << 0) /**< Shifted mode LS for USB_DCFG */ 1845 #define USB_DCFG_DEVSPD_FS (_USB_DCFG_DEVSPD_FS << 0) /**< Shifted mode FS for USB_DCFG */ 1846 #define USB_DCFG_NZSTSOUTHSHK (0x1UL << 2) /**< Non-Zero-Length Status OUT Handshake */ 1847 #define _USB_DCFG_NZSTSOUTHSHK_SHIFT 2 /**< Shift value for USB_NZSTSOUTHSHK */ 1848 #define _USB_DCFG_NZSTSOUTHSHK_MASK 0x4UL /**< Bit mask for USB_NZSTSOUTHSHK */ 1849 #define _USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ 1850 #define USB_DCFG_NZSTSOUTHSHK_DEFAULT (_USB_DCFG_NZSTSOUTHSHK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DCFG */ 1851 #define USB_DCFG_ENA32KHZSUSP (0x1UL << 3) /**< Enable 32 kHz Suspend Mode */ 1852 #define _USB_DCFG_ENA32KHZSUSP_SHIFT 3 /**< Shift value for USB_ENA32KHZSUSP */ 1853 #define _USB_DCFG_ENA32KHZSUSP_MASK 0x8UL /**< Bit mask for USB_ENA32KHZSUSP */ 1854 #define _USB_DCFG_ENA32KHZSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ 1855 #define USB_DCFG_ENA32KHZSUSP_DEFAULT (_USB_DCFG_ENA32KHZSUSP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DCFG */ 1856 #define _USB_DCFG_DEVADDR_SHIFT 4 /**< Shift value for USB_DEVADDR */ 1857 #define _USB_DCFG_DEVADDR_MASK 0x7F0UL /**< Bit mask for USB_DEVADDR */ 1858 #define _USB_DCFG_DEVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ 1859 #define USB_DCFG_DEVADDR_DEFAULT (_USB_DCFG_DEVADDR_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DCFG */ 1860 #define _USB_DCFG_PERFRINT_SHIFT 11 /**< Shift value for USB_PERFRINT */ 1861 #define _USB_DCFG_PERFRINT_MASK 0x1800UL /**< Bit mask for USB_PERFRINT */ 1862 #define _USB_DCFG_PERFRINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ 1863 #define _USB_DCFG_PERFRINT_80PCNT 0x00000000UL /**< Mode 80PCNT for USB_DCFG */ 1864 #define _USB_DCFG_PERFRINT_85PCNT 0x00000001UL /**< Mode 85PCNT for USB_DCFG */ 1865 #define _USB_DCFG_PERFRINT_90PCNT 0x00000002UL /**< Mode 90PCNT for USB_DCFG */ 1866 #define _USB_DCFG_PERFRINT_95PCNT 0x00000003UL /**< Mode 95PCNT for USB_DCFG */ 1867 #define USB_DCFG_PERFRINT_DEFAULT (_USB_DCFG_PERFRINT_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DCFG */ 1868 #define USB_DCFG_PERFRINT_80PCNT (_USB_DCFG_PERFRINT_80PCNT << 11) /**< Shifted mode 80PCNT for USB_DCFG */ 1869 #define USB_DCFG_PERFRINT_85PCNT (_USB_DCFG_PERFRINT_85PCNT << 11) /**< Shifted mode 85PCNT for USB_DCFG */ 1870 #define USB_DCFG_PERFRINT_90PCNT (_USB_DCFG_PERFRINT_90PCNT << 11) /**< Shifted mode 90PCNT for USB_DCFG */ 1871 #define USB_DCFG_PERFRINT_95PCNT (_USB_DCFG_PERFRINT_95PCNT << 11) /**< Shifted mode 95PCNT for USB_DCFG */ 1872 #define USB_DCFG_ENDEVOUTNAK (0x1UL << 13) /**< Enable Device OUT NAK */ 1873 #define _USB_DCFG_ENDEVOUTNAK_SHIFT 13 /**< Shift value for USB_ENDEVOUTNAK */ 1874 #define _USB_DCFG_ENDEVOUTNAK_MASK 0x2000UL /**< Bit mask for USB_ENDEVOUTNAK */ 1875 #define _USB_DCFG_ENDEVOUTNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ 1876 #define USB_DCFG_ENDEVOUTNAK_DEFAULT (_USB_DCFG_ENDEVOUTNAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DCFG */ 1877 #define USB_DCFG_XCVRDLY (0x1UL << 14) /**< */ 1878 #define _USB_DCFG_XCVRDLY_SHIFT 14 /**< Shift value for USB_XCVRDLY */ 1879 #define _USB_DCFG_XCVRDLY_MASK 0x4000UL /**< Bit mask for USB_XCVRDLY */ 1880 #define _USB_DCFG_XCVRDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ 1881 #define USB_DCFG_XCVRDLY_DEFAULT (_USB_DCFG_XCVRDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_DCFG */ 1882 #define USB_DCFG_ERRATICINTMSK (0x1UL << 15) /**< */ 1883 #define _USB_DCFG_ERRATICINTMSK_SHIFT 15 /**< Shift value for USB_ERRATICINTMSK */ 1884 #define _USB_DCFG_ERRATICINTMSK_MASK 0x8000UL /**< Bit mask for USB_ERRATICINTMSK */ 1885 #define _USB_DCFG_ERRATICINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ 1886 #define USB_DCFG_ERRATICINTMSK_DEFAULT (_USB_DCFG_ERRATICINTMSK_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DCFG */ 1887 #define _USB_DCFG_RESVALID_SHIFT 26 /**< Shift value for USB_RESVALID */ 1888 #define _USB_DCFG_RESVALID_MASK 0xFC000000UL /**< Bit mask for USB_RESVALID */ 1889 #define _USB_DCFG_RESVALID_DEFAULT 0x00000002UL /**< Mode DEFAULT for USB_DCFG */ 1890 #define USB_DCFG_RESVALID_DEFAULT (_USB_DCFG_RESVALID_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DCFG */ 1891 1892 /* Bit fields for USB DCTL */ 1893 #define _USB_DCTL_RESETVALUE 0x00000002UL /**< Default value for USB_DCTL */ 1894 #define _USB_DCTL_MASK 0x00018FFFUL /**< Mask for USB_DCTL */ 1895 #define USB_DCTL_RMTWKUPSIG (0x1UL << 0) /**< Remote Wakeup Signaling */ 1896 #define _USB_DCTL_RMTWKUPSIG_SHIFT 0 /**< Shift value for USB_RMTWKUPSIG */ 1897 #define _USB_DCTL_RMTWKUPSIG_MASK 0x1UL /**< Bit mask for USB_RMTWKUPSIG */ 1898 #define _USB_DCTL_RMTWKUPSIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ 1899 #define USB_DCTL_RMTWKUPSIG_DEFAULT (_USB_DCTL_RMTWKUPSIG_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DCTL */ 1900 #define USB_DCTL_SFTDISCON (0x1UL << 1) /**< Soft Disconnect */ 1901 #define _USB_DCTL_SFTDISCON_SHIFT 1 /**< Shift value for USB_SFTDISCON */ 1902 #define _USB_DCTL_SFTDISCON_MASK 0x2UL /**< Bit mask for USB_SFTDISCON */ 1903 #define _USB_DCTL_SFTDISCON_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DCTL */ 1904 #define USB_DCTL_SFTDISCON_DEFAULT (_USB_DCTL_SFTDISCON_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DCTL */ 1905 #define USB_DCTL_GNPINNAKSTS (0x1UL << 2) /**< Global Non-periodic IN NAK Status */ 1906 #define _USB_DCTL_GNPINNAKSTS_SHIFT 2 /**< Shift value for USB_GNPINNAKSTS */ 1907 #define _USB_DCTL_GNPINNAKSTS_MASK 0x4UL /**< Bit mask for USB_GNPINNAKSTS */ 1908 #define _USB_DCTL_GNPINNAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ 1909 #define USB_DCTL_GNPINNAKSTS_DEFAULT (_USB_DCTL_GNPINNAKSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DCTL */ 1910 #define USB_DCTL_GOUTNAKSTS (0x1UL << 3) /**< Global OUT NAK Status */ 1911 #define _USB_DCTL_GOUTNAKSTS_SHIFT 3 /**< Shift value for USB_GOUTNAKSTS */ 1912 #define _USB_DCTL_GOUTNAKSTS_MASK 0x8UL /**< Bit mask for USB_GOUTNAKSTS */ 1913 #define _USB_DCTL_GOUTNAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ 1914 #define USB_DCTL_GOUTNAKSTS_DEFAULT (_USB_DCTL_GOUTNAKSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DCTL */ 1915 #define _USB_DCTL_TSTCTL_SHIFT 4 /**< Shift value for USB_TSTCTL */ 1916 #define _USB_DCTL_TSTCTL_MASK 0x70UL /**< Bit mask for USB_TSTCTL */ 1917 #define _USB_DCTL_TSTCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ 1918 #define _USB_DCTL_TSTCTL_DISABLE 0x00000000UL /**< Mode DISABLE for USB_DCTL */ 1919 #define _USB_DCTL_TSTCTL_J 0x00000001UL /**< Mode J for USB_DCTL */ 1920 #define _USB_DCTL_TSTCTL_K 0x00000002UL /**< Mode K for USB_DCTL */ 1921 #define _USB_DCTL_TSTCTL_SE0NAK 0x00000003UL /**< Mode SE0NAK for USB_DCTL */ 1922 #define _USB_DCTL_TSTCTL_PACKET 0x00000004UL /**< Mode PACKET for USB_DCTL */ 1923 #define _USB_DCTL_TSTCTL_FORCE 0x00000005UL /**< Mode FORCE for USB_DCTL */ 1924 #define USB_DCTL_TSTCTL_DEFAULT (_USB_DCTL_TSTCTL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DCTL */ 1925 #define USB_DCTL_TSTCTL_DISABLE (_USB_DCTL_TSTCTL_DISABLE << 4) /**< Shifted mode DISABLE for USB_DCTL */ 1926 #define USB_DCTL_TSTCTL_J (_USB_DCTL_TSTCTL_J << 4) /**< Shifted mode J for USB_DCTL */ 1927 #define USB_DCTL_TSTCTL_K (_USB_DCTL_TSTCTL_K << 4) /**< Shifted mode K for USB_DCTL */ 1928 #define USB_DCTL_TSTCTL_SE0NAK (_USB_DCTL_TSTCTL_SE0NAK << 4) /**< Shifted mode SE0NAK for USB_DCTL */ 1929 #define USB_DCTL_TSTCTL_PACKET (_USB_DCTL_TSTCTL_PACKET << 4) /**< Shifted mode PACKET for USB_DCTL */ 1930 #define USB_DCTL_TSTCTL_FORCE (_USB_DCTL_TSTCTL_FORCE << 4) /**< Shifted mode FORCE for USB_DCTL */ 1931 #define USB_DCTL_SGNPINNAK (0x1UL << 7) /**< Set Global Non-periodic IN NAK */ 1932 #define _USB_DCTL_SGNPINNAK_SHIFT 7 /**< Shift value for USB_SGNPINNAK */ 1933 #define _USB_DCTL_SGNPINNAK_MASK 0x80UL /**< Bit mask for USB_SGNPINNAK */ 1934 #define _USB_DCTL_SGNPINNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ 1935 #define USB_DCTL_SGNPINNAK_DEFAULT (_USB_DCTL_SGNPINNAK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DCTL */ 1936 #define USB_DCTL_CGNPINNAK (0x1UL << 8) /**< Clear Global Non-periodic IN NAK */ 1937 #define _USB_DCTL_CGNPINNAK_SHIFT 8 /**< Shift value for USB_CGNPINNAK */ 1938 #define _USB_DCTL_CGNPINNAK_MASK 0x100UL /**< Bit mask for USB_CGNPINNAK */ 1939 #define _USB_DCTL_CGNPINNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ 1940 #define USB_DCTL_CGNPINNAK_DEFAULT (_USB_DCTL_CGNPINNAK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DCTL */ 1941 #define USB_DCTL_SGOUTNAK (0x1UL << 9) /**< Set Global OUT NAK */ 1942 #define _USB_DCTL_SGOUTNAK_SHIFT 9 /**< Shift value for USB_SGOUTNAK */ 1943 #define _USB_DCTL_SGOUTNAK_MASK 0x200UL /**< Bit mask for USB_SGOUTNAK */ 1944 #define _USB_DCTL_SGOUTNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ 1945 #define USB_DCTL_SGOUTNAK_DEFAULT (_USB_DCTL_SGOUTNAK_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_DCTL */ 1946 #define USB_DCTL_CGOUTNAK (0x1UL << 10) /**< Clear Global OUT NAK */ 1947 #define _USB_DCTL_CGOUTNAK_SHIFT 10 /**< Shift value for USB_CGOUTNAK */ 1948 #define _USB_DCTL_CGOUTNAK_MASK 0x400UL /**< Bit mask for USB_CGOUTNAK */ 1949 #define _USB_DCTL_CGOUTNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ 1950 #define USB_DCTL_CGOUTNAK_DEFAULT (_USB_DCTL_CGOUTNAK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_DCTL */ 1951 #define USB_DCTL_PWRONPRGDONE (0x1UL << 11) /**< Power-On Programming Done */ 1952 #define _USB_DCTL_PWRONPRGDONE_SHIFT 11 /**< Shift value for USB_PWRONPRGDONE */ 1953 #define _USB_DCTL_PWRONPRGDONE_MASK 0x800UL /**< Bit mask for USB_PWRONPRGDONE */ 1954 #define _USB_DCTL_PWRONPRGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ 1955 #define USB_DCTL_PWRONPRGDONE_DEFAULT (_USB_DCTL_PWRONPRGDONE_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DCTL */ 1956 #define USB_DCTL_IGNRFRMNUM (0x1UL << 15) /**< Ignore Frame number For Isochronous End points */ 1957 #define _USB_DCTL_IGNRFRMNUM_SHIFT 15 /**< Shift value for USB_IGNRFRMNUM */ 1958 #define _USB_DCTL_IGNRFRMNUM_MASK 0x8000UL /**< Bit mask for USB_IGNRFRMNUM */ 1959 #define _USB_DCTL_IGNRFRMNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ 1960 #define USB_DCTL_IGNRFRMNUM_DEFAULT (_USB_DCTL_IGNRFRMNUM_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DCTL */ 1961 #define USB_DCTL_NAKONBBLE (0x1UL << 16) /**< NAK on Babble Error */ 1962 #define _USB_DCTL_NAKONBBLE_SHIFT 16 /**< Shift value for USB_NAKONBBLE */ 1963 #define _USB_DCTL_NAKONBBLE_MASK 0x10000UL /**< Bit mask for USB_NAKONBBLE */ 1964 #define _USB_DCTL_NAKONBBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ 1965 #define USB_DCTL_NAKONBBLE_DEFAULT (_USB_DCTL_NAKONBBLE_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DCTL */ 1966 1967 /* Bit fields for USB DSTS */ 1968 #define _USB_DSTS_RESETVALUE 0x00000002UL /**< Default value for USB_DSTS */ 1969 #define _USB_DSTS_MASK 0x00FFFF0FUL /**< Mask for USB_DSTS */ 1970 #define USB_DSTS_SUSPSTS (0x1UL << 0) /**< Suspend Status */ 1971 #define _USB_DSTS_SUSPSTS_SHIFT 0 /**< Shift value for USB_SUSPSTS */ 1972 #define _USB_DSTS_SUSPSTS_MASK 0x1UL /**< Bit mask for USB_SUSPSTS */ 1973 #define _USB_DSTS_SUSPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */ 1974 #define USB_DSTS_SUSPSTS_DEFAULT (_USB_DSTS_SUSPSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DSTS */ 1975 #define _USB_DSTS_ENUMSPD_SHIFT 1 /**< Shift value for USB_ENUMSPD */ 1976 #define _USB_DSTS_ENUMSPD_MASK 0x6UL /**< Bit mask for USB_ENUMSPD */ 1977 #define _USB_DSTS_ENUMSPD_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DSTS */ 1978 #define _USB_DSTS_ENUMSPD_LS 0x00000002UL /**< Mode LS for USB_DSTS */ 1979 #define _USB_DSTS_ENUMSPD_FS 0x00000003UL /**< Mode FS for USB_DSTS */ 1980 #define USB_DSTS_ENUMSPD_DEFAULT (_USB_DSTS_ENUMSPD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DSTS */ 1981 #define USB_DSTS_ENUMSPD_LS (_USB_DSTS_ENUMSPD_LS << 1) /**< Shifted mode LS for USB_DSTS */ 1982 #define USB_DSTS_ENUMSPD_FS (_USB_DSTS_ENUMSPD_FS << 1) /**< Shifted mode FS for USB_DSTS */ 1983 #define USB_DSTS_ERRTICERR (0x1UL << 3) /**< Erratic Error */ 1984 #define _USB_DSTS_ERRTICERR_SHIFT 3 /**< Shift value for USB_ERRTICERR */ 1985 #define _USB_DSTS_ERRTICERR_MASK 0x8UL /**< Bit mask for USB_ERRTICERR */ 1986 #define _USB_DSTS_ERRTICERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */ 1987 #define USB_DSTS_ERRTICERR_DEFAULT (_USB_DSTS_ERRTICERR_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DSTS */ 1988 #define _USB_DSTS_SOFFN_SHIFT 8 /**< Shift value for USB_SOFFN */ 1989 #define _USB_DSTS_SOFFN_MASK 0x3FFF00UL /**< Bit mask for USB_SOFFN */ 1990 #define _USB_DSTS_SOFFN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */ 1991 #define USB_DSTS_SOFFN_DEFAULT (_USB_DSTS_SOFFN_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DSTS */ 1992 #define _USB_DSTS_DEVLNSTS_SHIFT 22 /**< Shift value for USB_DEVLNSTS */ 1993 #define _USB_DSTS_DEVLNSTS_MASK 0xC00000UL /**< Bit mask for USB_DEVLNSTS */ 1994 #define _USB_DSTS_DEVLNSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */ 1995 #define USB_DSTS_DEVLNSTS_DEFAULT (_USB_DSTS_DEVLNSTS_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DSTS */ 1996 1997 /* Bit fields for USB DIEPMSK */ 1998 #define _USB_DIEPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DIEPMSK */ 1999 #define _USB_DIEPMSK_MASK 0x0000217FUL /**< Mask for USB_DIEPMSK */ 2000 #define USB_DIEPMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Interrupt Mask */ 2001 #define _USB_DIEPMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */ 2002 #define _USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */ 2003 #define _USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ 2004 #define USB_DIEPMSK_XFERCOMPLMSK_DEFAULT (_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPMSK */ 2005 #define USB_DIEPMSK_EPDISBLDMSK (0x1UL << 1) /**< Endpoint Disabled Interrupt Mask */ 2006 #define _USB_DIEPMSK_EPDISBLDMSK_SHIFT 1 /**< Shift value for USB_EPDISBLDMSK */ 2007 #define _USB_DIEPMSK_EPDISBLDMSK_MASK 0x2UL /**< Bit mask for USB_EPDISBLDMSK */ 2008 #define _USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ 2009 #define USB_DIEPMSK_EPDISBLDMSK_DEFAULT (_USB_DIEPMSK_EPDISBLDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEPMSK */ 2010 #define USB_DIEPMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error Mask */ 2011 #define _USB_DIEPMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */ 2012 #define _USB_DIEPMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */ 2013 #define _USB_DIEPMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ 2014 #define USB_DIEPMSK_AHBERRMSK_DEFAULT (_USB_DIEPMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEPMSK */ 2015 #define USB_DIEPMSK_TIMEOUTMSK (0x1UL << 3) /**< Timeout Condition Mask */ 2016 #define _USB_DIEPMSK_TIMEOUTMSK_SHIFT 3 /**< Shift value for USB_TIMEOUTMSK */ 2017 #define _USB_DIEPMSK_TIMEOUTMSK_MASK 0x8UL /**< Bit mask for USB_TIMEOUTMSK */ 2018 #define _USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ 2019 #define USB_DIEPMSK_TIMEOUTMSK_DEFAULT (_USB_DIEPMSK_TIMEOUTMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEPMSK */ 2020 #define USB_DIEPMSK_INTKNTXFEMPMSK (0x1UL << 4) /**< IN Token Received When TxFIFO Empty Mask */ 2021 #define _USB_DIEPMSK_INTKNTXFEMPMSK_SHIFT 4 /**< Shift value for USB_INTKNTXFEMPMSK */ 2022 #define _USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMPMSK */ 2023 #define _USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ 2024 #define USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT (_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEPMSK */ 2025 #define USB_DIEPMSK_INTKNEPMISMSK (0x1UL << 5) /**< IN Token received with EP Mismatch Mask */ 2026 #define _USB_DIEPMSK_INTKNEPMISMSK_SHIFT 5 /**< Shift value for USB_INTKNEPMISMSK */ 2027 #define _USB_DIEPMSK_INTKNEPMISMSK_MASK 0x20UL /**< Bit mask for USB_INTKNEPMISMSK */ 2028 #define _USB_DIEPMSK_INTKNEPMISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ 2029 #define USB_DIEPMSK_INTKNEPMISMSK_DEFAULT (_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DIEPMSK */ 2030 #define USB_DIEPMSK_INEPNAKEFFMSK (0x1UL << 6) /**< IN Endpoint NAK Effective Mask */ 2031 #define _USB_DIEPMSK_INEPNAKEFFMSK_SHIFT 6 /**< Shift value for USB_INEPNAKEFFMSK */ 2032 #define _USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFFMSK */ 2033 #define _USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ 2034 #define USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT (_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEPMSK */ 2035 #define USB_DIEPMSK_TXFIFOUNDRNMSK (0x1UL << 8) /**< Fifo Underrun Mask */ 2036 #define _USB_DIEPMSK_TXFIFOUNDRNMSK_SHIFT 8 /**< Shift value for USB_TXFIFOUNDRNMSK */ 2037 #define _USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100UL /**< Bit mask for USB_TXFIFOUNDRNMSK */ 2038 #define _USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ 2039 #define USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT (_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DIEPMSK */ 2040 #define USB_DIEPMSK_NAKMSK (0x1UL << 13) /**< NAK interrupt Mask */ 2041 #define _USB_DIEPMSK_NAKMSK_SHIFT 13 /**< Shift value for USB_NAKMSK */ 2042 #define _USB_DIEPMSK_NAKMSK_MASK 0x2000UL /**< Bit mask for USB_NAKMSK */ 2043 #define _USB_DIEPMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ 2044 #define USB_DIEPMSK_NAKMSK_DEFAULT (_USB_DIEPMSK_NAKMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEPMSK */ 2045 2046 /* Bit fields for USB DOEPMSK */ 2047 #define _USB_DOEPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DOEPMSK */ 2048 #define _USB_DOEPMSK_MASK 0x0000317FUL /**< Mask for USB_DOEPMSK */ 2049 #define USB_DOEPMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Interrupt Mask */ 2050 #define _USB_DOEPMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */ 2051 #define _USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */ 2052 #define _USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ 2053 #define USB_DOEPMSK_XFERCOMPLMSK_DEFAULT (_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEPMSK */ 2054 #define USB_DOEPMSK_EPDISBLDMSK (0x1UL << 1) /**< Endpoint Disabled Interrupt Mask */ 2055 #define _USB_DOEPMSK_EPDISBLDMSK_SHIFT 1 /**< Shift value for USB_EPDISBLDMSK */ 2056 #define _USB_DOEPMSK_EPDISBLDMSK_MASK 0x2UL /**< Bit mask for USB_EPDISBLDMSK */ 2057 #define _USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ 2058 #define USB_DOEPMSK_EPDISBLDMSK_DEFAULT (_USB_DOEPMSK_EPDISBLDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEPMSK */ 2059 #define USB_DOEPMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error */ 2060 #define _USB_DOEPMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */ 2061 #define _USB_DOEPMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */ 2062 #define _USB_DOEPMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ 2063 #define USB_DOEPMSK_AHBERRMSK_DEFAULT (_USB_DOEPMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEPMSK */ 2064 #define USB_DOEPMSK_SETUPMSK (0x1UL << 3) /**< SETUP Phase Done Mask */ 2065 #define _USB_DOEPMSK_SETUPMSK_SHIFT 3 /**< Shift value for USB_SETUPMSK */ 2066 #define _USB_DOEPMSK_SETUPMSK_MASK 0x8UL /**< Bit mask for USB_SETUPMSK */ 2067 #define _USB_DOEPMSK_SETUPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ 2068 #define USB_DOEPMSK_SETUPMSK_DEFAULT (_USB_DOEPMSK_SETUPMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEPMSK */ 2069 #define USB_DOEPMSK_OUTTKNEPDISMSK (0x1UL << 4) /**< OUT Token Received when Endpoint Disabled Mask */ 2070 #define _USB_DOEPMSK_OUTTKNEPDISMSK_SHIFT 4 /**< Shift value for USB_OUTTKNEPDISMSK */ 2071 #define _USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDISMSK */ 2072 #define _USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ 2073 #define USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT (_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEPMSK */ 2074 #define USB_DOEPMSK_STSPHSERCVDMSK (0x1UL << 5) /**< Status Phase Received Mask */ 2075 #define _USB_DOEPMSK_STSPHSERCVDMSK_SHIFT 5 /**< Shift value for USB_STSPHSERCVDMSK */ 2076 #define _USB_DOEPMSK_STSPHSERCVDMSK_MASK 0x20UL /**< Bit mask for USB_STSPHSERCVDMSK */ 2077 #define _USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ 2078 #define USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT (_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DOEPMSK */ 2079 #define USB_DOEPMSK_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received Mask */ 2080 #define _USB_DOEPMSK_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */ 2081 #define _USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */ 2082 #define _USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ 2083 #define USB_DOEPMSK_BACK2BACKSETUP_DEFAULT (_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEPMSK */ 2084 #define USB_DOEPMSK_OUTPKTERRMSK (0x1UL << 8) /**< OUT Packet Error Mask */ 2085 #define _USB_DOEPMSK_OUTPKTERRMSK_SHIFT 8 /**< Shift value for USB_OUTPKTERRMSK */ 2086 #define _USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100UL /**< Bit mask for USB_OUTPKTERRMSK */ 2087 #define _USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ 2088 #define USB_DOEPMSK_OUTPKTERRMSK_DEFAULT (_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DOEPMSK */ 2089 #define USB_DOEPMSK_BBLEERRMSK (0x1UL << 12) /**< Babble Error interrupt Mask */ 2090 #define _USB_DOEPMSK_BBLEERRMSK_SHIFT 12 /**< Shift value for USB_BBLEERRMSK */ 2091 #define _USB_DOEPMSK_BBLEERRMSK_MASK 0x1000UL /**< Bit mask for USB_BBLEERRMSK */ 2092 #define _USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ 2093 #define USB_DOEPMSK_BBLEERRMSK_DEFAULT (_USB_DOEPMSK_BBLEERRMSK_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEPMSK */ 2094 #define USB_DOEPMSK_NAKMSK (0x1UL << 13) /**< NAK interrupt Mask */ 2095 #define _USB_DOEPMSK_NAKMSK_SHIFT 13 /**< Shift value for USB_NAKMSK */ 2096 #define _USB_DOEPMSK_NAKMSK_MASK 0x2000UL /**< Bit mask for USB_NAKMSK */ 2097 #define _USB_DOEPMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ 2098 #define USB_DOEPMSK_NAKMSK_DEFAULT (_USB_DOEPMSK_NAKMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEPMSK */ 2099 2100 /* Bit fields for USB DAINT */ 2101 #define _USB_DAINT_RESETVALUE 0x00000000UL /**< Default value for USB_DAINT */ 2102 #define _USB_DAINT_MASK 0x007F007FUL /**< Mask for USB_DAINT */ 2103 #define USB_DAINT_INEPINT0 (0x1UL << 0) /**< IN Endpoint 0 Interrupt Bit */ 2104 #define _USB_DAINT_INEPINT0_SHIFT 0 /**< Shift value for USB_INEPINT0 */ 2105 #define _USB_DAINT_INEPINT0_MASK 0x1UL /**< Bit mask for USB_INEPINT0 */ 2106 #define _USB_DAINT_INEPINT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2107 #define USB_DAINT_INEPINT0_DEFAULT (_USB_DAINT_INEPINT0_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DAINT */ 2108 #define USB_DAINT_INEPINT1 (0x1UL << 1) /**< IN Endpoint 1 Interrupt Bit */ 2109 #define _USB_DAINT_INEPINT1_SHIFT 1 /**< Shift value for USB_INEPINT1 */ 2110 #define _USB_DAINT_INEPINT1_MASK 0x2UL /**< Bit mask for USB_INEPINT1 */ 2111 #define _USB_DAINT_INEPINT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2112 #define USB_DAINT_INEPINT1_DEFAULT (_USB_DAINT_INEPINT1_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DAINT */ 2113 #define USB_DAINT_INEPINT2 (0x1UL << 2) /**< IN Endpoint 2 Interrupt Bit */ 2114 #define _USB_DAINT_INEPINT2_SHIFT 2 /**< Shift value for USB_INEPINT2 */ 2115 #define _USB_DAINT_INEPINT2_MASK 0x4UL /**< Bit mask for USB_INEPINT2 */ 2116 #define _USB_DAINT_INEPINT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2117 #define USB_DAINT_INEPINT2_DEFAULT (_USB_DAINT_INEPINT2_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DAINT */ 2118 #define USB_DAINT_INEPINT3 (0x1UL << 3) /**< IN Endpoint 3 Interrupt Bit */ 2119 #define _USB_DAINT_INEPINT3_SHIFT 3 /**< Shift value for USB_INEPINT3 */ 2120 #define _USB_DAINT_INEPINT3_MASK 0x8UL /**< Bit mask for USB_INEPINT3 */ 2121 #define _USB_DAINT_INEPINT3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2122 #define USB_DAINT_INEPINT3_DEFAULT (_USB_DAINT_INEPINT3_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DAINT */ 2123 #define USB_DAINT_INEPINT4 (0x1UL << 4) /**< IN Endpoint 4 Interrupt Bit */ 2124 #define _USB_DAINT_INEPINT4_SHIFT 4 /**< Shift value for USB_INEPINT4 */ 2125 #define _USB_DAINT_INEPINT4_MASK 0x10UL /**< Bit mask for USB_INEPINT4 */ 2126 #define _USB_DAINT_INEPINT4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2127 #define USB_DAINT_INEPINT4_DEFAULT (_USB_DAINT_INEPINT4_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DAINT */ 2128 #define USB_DAINT_INEPINT5 (0x1UL << 5) /**< IN Endpoint 5 Interrupt Bit */ 2129 #define _USB_DAINT_INEPINT5_SHIFT 5 /**< Shift value for USB_INEPINT5 */ 2130 #define _USB_DAINT_INEPINT5_MASK 0x20UL /**< Bit mask for USB_INEPINT5 */ 2131 #define _USB_DAINT_INEPINT5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2132 #define USB_DAINT_INEPINT5_DEFAULT (_USB_DAINT_INEPINT5_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DAINT */ 2133 #define USB_DAINT_INEPINT6 (0x1UL << 6) /**< IN Endpoint 6 Interrupt Bit */ 2134 #define _USB_DAINT_INEPINT6_SHIFT 6 /**< Shift value for USB_INEPINT6 */ 2135 #define _USB_DAINT_INEPINT6_MASK 0x40UL /**< Bit mask for USB_INEPINT6 */ 2136 #define _USB_DAINT_INEPINT6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2137 #define USB_DAINT_INEPINT6_DEFAULT (_USB_DAINT_INEPINT6_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DAINT */ 2138 #define USB_DAINT_OUTEPINT0 (0x1UL << 16) /**< OUT Endpoint 0 Interrupt Bit */ 2139 #define _USB_DAINT_OUTEPINT0_SHIFT 16 /**< Shift value for USB_OUTEPINT0 */ 2140 #define _USB_DAINT_OUTEPINT0_MASK 0x10000UL /**< Bit mask for USB_OUTEPINT0 */ 2141 #define _USB_DAINT_OUTEPINT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2142 #define USB_DAINT_OUTEPINT0_DEFAULT (_USB_DAINT_OUTEPINT0_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DAINT */ 2143 #define USB_DAINT_OUTEPINT1 (0x1UL << 17) /**< OUT Endpoint 1 Interrupt Bit */ 2144 #define _USB_DAINT_OUTEPINT1_SHIFT 17 /**< Shift value for USB_OUTEPINT1 */ 2145 #define _USB_DAINT_OUTEPINT1_MASK 0x20000UL /**< Bit mask for USB_OUTEPINT1 */ 2146 #define _USB_DAINT_OUTEPINT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2147 #define USB_DAINT_OUTEPINT1_DEFAULT (_USB_DAINT_OUTEPINT1_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DAINT */ 2148 #define USB_DAINT_OUTEPINT2 (0x1UL << 18) /**< OUT Endpoint 2 Interrupt Bit */ 2149 #define _USB_DAINT_OUTEPINT2_SHIFT 18 /**< Shift value for USB_OUTEPINT2 */ 2150 #define _USB_DAINT_OUTEPINT2_MASK 0x40000UL /**< Bit mask for USB_OUTEPINT2 */ 2151 #define _USB_DAINT_OUTEPINT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2152 #define USB_DAINT_OUTEPINT2_DEFAULT (_USB_DAINT_OUTEPINT2_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DAINT */ 2153 #define USB_DAINT_OUTEPINT3 (0x1UL << 19) /**< OUT Endpoint 3 Interrupt Bit */ 2154 #define _USB_DAINT_OUTEPINT3_SHIFT 19 /**< Shift value for USB_OUTEPINT3 */ 2155 #define _USB_DAINT_OUTEPINT3_MASK 0x80000UL /**< Bit mask for USB_OUTEPINT3 */ 2156 #define _USB_DAINT_OUTEPINT3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2157 #define USB_DAINT_OUTEPINT3_DEFAULT (_USB_DAINT_OUTEPINT3_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DAINT */ 2158 #define USB_DAINT_OUTEPINT4 (0x1UL << 20) /**< OUT Endpoint 4 Interrupt Bit */ 2159 #define _USB_DAINT_OUTEPINT4_SHIFT 20 /**< Shift value for USB_OUTEPINT4 */ 2160 #define _USB_DAINT_OUTEPINT4_MASK 0x100000UL /**< Bit mask for USB_OUTEPINT4 */ 2161 #define _USB_DAINT_OUTEPINT4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2162 #define USB_DAINT_OUTEPINT4_DEFAULT (_USB_DAINT_OUTEPINT4_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DAINT */ 2163 #define USB_DAINT_OUTEPINT5 (0x1UL << 21) /**< OUT Endpoint 5 Interrupt Bit */ 2164 #define _USB_DAINT_OUTEPINT5_SHIFT 21 /**< Shift value for USB_OUTEPINT5 */ 2165 #define _USB_DAINT_OUTEPINT5_MASK 0x200000UL /**< Bit mask for USB_OUTEPINT5 */ 2166 #define _USB_DAINT_OUTEPINT5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2167 #define USB_DAINT_OUTEPINT5_DEFAULT (_USB_DAINT_OUTEPINT5_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DAINT */ 2168 #define USB_DAINT_OUTEPINT6 (0x1UL << 22) /**< OUT Endpoint 6 Interrupt Bit */ 2169 #define _USB_DAINT_OUTEPINT6_SHIFT 22 /**< Shift value for USB_OUTEPINT6 */ 2170 #define _USB_DAINT_OUTEPINT6_MASK 0x400000UL /**< Bit mask for USB_OUTEPINT6 */ 2171 #define _USB_DAINT_OUTEPINT6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ 2172 #define USB_DAINT_OUTEPINT6_DEFAULT (_USB_DAINT_OUTEPINT6_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DAINT */ 2173 2174 /* Bit fields for USB DAINTMSK */ 2175 #define _USB_DAINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DAINTMSK */ 2176 #define _USB_DAINTMSK_MASK 0x007F007FUL /**< Mask for USB_DAINTMSK */ 2177 #define USB_DAINTMSK_INEPMSK0 (0x1UL << 0) /**< IN Endpoint 0 Interrupt mask Bit */ 2178 #define _USB_DAINTMSK_INEPMSK0_SHIFT 0 /**< Shift value for USB_INEPMSK0 */ 2179 #define _USB_DAINTMSK_INEPMSK0_MASK 0x1UL /**< Bit mask for USB_INEPMSK0 */ 2180 #define _USB_DAINTMSK_INEPMSK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2181 #define USB_DAINTMSK_INEPMSK0_DEFAULT (_USB_DAINTMSK_INEPMSK0_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2182 #define USB_DAINTMSK_INEPMSK1 (0x1UL << 1) /**< IN Endpoint 1 Interrupt mask Bit */ 2183 #define _USB_DAINTMSK_INEPMSK1_SHIFT 1 /**< Shift value for USB_INEPMSK1 */ 2184 #define _USB_DAINTMSK_INEPMSK1_MASK 0x2UL /**< Bit mask for USB_INEPMSK1 */ 2185 #define _USB_DAINTMSK_INEPMSK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2186 #define USB_DAINTMSK_INEPMSK1_DEFAULT (_USB_DAINTMSK_INEPMSK1_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2187 #define USB_DAINTMSK_INEPMSK2 (0x1UL << 2) /**< IN Endpoint 2 Interrupt mask Bit */ 2188 #define _USB_DAINTMSK_INEPMSK2_SHIFT 2 /**< Shift value for USB_INEPMSK2 */ 2189 #define _USB_DAINTMSK_INEPMSK2_MASK 0x4UL /**< Bit mask for USB_INEPMSK2 */ 2190 #define _USB_DAINTMSK_INEPMSK2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2191 #define USB_DAINTMSK_INEPMSK2_DEFAULT (_USB_DAINTMSK_INEPMSK2_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2192 #define USB_DAINTMSK_INEPMSK3 (0x1UL << 3) /**< IN Endpoint 3 Interrupt mask Bit */ 2193 #define _USB_DAINTMSK_INEPMSK3_SHIFT 3 /**< Shift value for USB_INEPMSK3 */ 2194 #define _USB_DAINTMSK_INEPMSK3_MASK 0x8UL /**< Bit mask for USB_INEPMSK3 */ 2195 #define _USB_DAINTMSK_INEPMSK3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2196 #define USB_DAINTMSK_INEPMSK3_DEFAULT (_USB_DAINTMSK_INEPMSK3_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2197 #define USB_DAINTMSK_INEPMSK4 (0x1UL << 4) /**< IN Endpoint 4 Interrupt mask Bit */ 2198 #define _USB_DAINTMSK_INEPMSK4_SHIFT 4 /**< Shift value for USB_INEPMSK4 */ 2199 #define _USB_DAINTMSK_INEPMSK4_MASK 0x10UL /**< Bit mask for USB_INEPMSK4 */ 2200 #define _USB_DAINTMSK_INEPMSK4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2201 #define USB_DAINTMSK_INEPMSK4_DEFAULT (_USB_DAINTMSK_INEPMSK4_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2202 #define USB_DAINTMSK_INEPMSK5 (0x1UL << 5) /**< IN Endpoint 5 Interrupt mask Bit */ 2203 #define _USB_DAINTMSK_INEPMSK5_SHIFT 5 /**< Shift value for USB_INEPMSK5 */ 2204 #define _USB_DAINTMSK_INEPMSK5_MASK 0x20UL /**< Bit mask for USB_INEPMSK5 */ 2205 #define _USB_DAINTMSK_INEPMSK5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2206 #define USB_DAINTMSK_INEPMSK5_DEFAULT (_USB_DAINTMSK_INEPMSK5_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2207 #define USB_DAINTMSK_INEPMSK6 (0x1UL << 6) /**< IN Endpoint 6 Interrupt mask Bit */ 2208 #define _USB_DAINTMSK_INEPMSK6_SHIFT 6 /**< Shift value for USB_INEPMSK6 */ 2209 #define _USB_DAINTMSK_INEPMSK6_MASK 0x40UL /**< Bit mask for USB_INEPMSK6 */ 2210 #define _USB_DAINTMSK_INEPMSK6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2211 #define USB_DAINTMSK_INEPMSK6_DEFAULT (_USB_DAINTMSK_INEPMSK6_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2212 #define USB_DAINTMSK_OUTEPMSK0 (0x1UL << 16) /**< OUT Endpoint 0 Interrupt mask Bit */ 2213 #define _USB_DAINTMSK_OUTEPMSK0_SHIFT 16 /**< Shift value for USB_OUTEPMSK0 */ 2214 #define _USB_DAINTMSK_OUTEPMSK0_MASK 0x10000UL /**< Bit mask for USB_OUTEPMSK0 */ 2215 #define _USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2216 #define USB_DAINTMSK_OUTEPMSK0_DEFAULT (_USB_DAINTMSK_OUTEPMSK0_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2217 #define USB_DAINTMSK_OUTEPMSK1 (0x1UL << 17) /**< OUT Endpoint 1 Interrupt mask Bit */ 2218 #define _USB_DAINTMSK_OUTEPMSK1_SHIFT 17 /**< Shift value for USB_OUTEPMSK1 */ 2219 #define _USB_DAINTMSK_OUTEPMSK1_MASK 0x20000UL /**< Bit mask for USB_OUTEPMSK1 */ 2220 #define _USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2221 #define USB_DAINTMSK_OUTEPMSK1_DEFAULT (_USB_DAINTMSK_OUTEPMSK1_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2222 #define USB_DAINTMSK_OUTEPMSK2 (0x1UL << 18) /**< OUT Endpoint 2 Interrupt mask Bit */ 2223 #define _USB_DAINTMSK_OUTEPMSK2_SHIFT 18 /**< Shift value for USB_OUTEPMSK2 */ 2224 #define _USB_DAINTMSK_OUTEPMSK2_MASK 0x40000UL /**< Bit mask for USB_OUTEPMSK2 */ 2225 #define _USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2226 #define USB_DAINTMSK_OUTEPMSK2_DEFAULT (_USB_DAINTMSK_OUTEPMSK2_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2227 #define USB_DAINTMSK_OUTEPMSK3 (0x1UL << 19) /**< OUT Endpoint 3 Interrupt mask Bit */ 2228 #define _USB_DAINTMSK_OUTEPMSK3_SHIFT 19 /**< Shift value for USB_OUTEPMSK3 */ 2229 #define _USB_DAINTMSK_OUTEPMSK3_MASK 0x80000UL /**< Bit mask for USB_OUTEPMSK3 */ 2230 #define _USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2231 #define USB_DAINTMSK_OUTEPMSK3_DEFAULT (_USB_DAINTMSK_OUTEPMSK3_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2232 #define USB_DAINTMSK_OUTEPMSK4 (0x1UL << 20) /**< OUT Endpoint 4 Interrupt mask Bit */ 2233 #define _USB_DAINTMSK_OUTEPMSK4_SHIFT 20 /**< Shift value for USB_OUTEPMSK4 */ 2234 #define _USB_DAINTMSK_OUTEPMSK4_MASK 0x100000UL /**< Bit mask for USB_OUTEPMSK4 */ 2235 #define _USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2236 #define USB_DAINTMSK_OUTEPMSK4_DEFAULT (_USB_DAINTMSK_OUTEPMSK4_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2237 #define USB_DAINTMSK_OUTEPMSK5 (0x1UL << 21) /**< OUT Endpoint 5 Interrupt mask Bit */ 2238 #define _USB_DAINTMSK_OUTEPMSK5_SHIFT 21 /**< Shift value for USB_OUTEPMSK5 */ 2239 #define _USB_DAINTMSK_OUTEPMSK5_MASK 0x200000UL /**< Bit mask for USB_OUTEPMSK5 */ 2240 #define _USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2241 #define USB_DAINTMSK_OUTEPMSK5_DEFAULT (_USB_DAINTMSK_OUTEPMSK5_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2242 #define USB_DAINTMSK_OUTEPMSK6 (0x1UL << 22) /**< OUT Endpoint 6 Interrupt mask Bit */ 2243 #define _USB_DAINTMSK_OUTEPMSK6_SHIFT 22 /**< Shift value for USB_OUTEPMSK6 */ 2244 #define _USB_DAINTMSK_OUTEPMSK6_MASK 0x400000UL /**< Bit mask for USB_OUTEPMSK6 */ 2245 #define _USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ 2246 #define USB_DAINTMSK_OUTEPMSK6_DEFAULT (_USB_DAINTMSK_OUTEPMSK6_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DAINTMSK */ 2247 2248 /* Bit fields for USB DVBUSDIS */ 2249 #define _USB_DVBUSDIS_RESETVALUE 0x000017D7UL /**< Default value for USB_DVBUSDIS */ 2250 #define _USB_DVBUSDIS_MASK 0x0000FFFFUL /**< Mask for USB_DVBUSDIS */ 2251 #define _USB_DVBUSDIS_DVBUSDIS_SHIFT 0 /**< Shift value for USB_DVBUSDIS */ 2252 #define _USB_DVBUSDIS_DVBUSDIS_MASK 0xFFFFUL /**< Bit mask for USB_DVBUSDIS */ 2253 #define _USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x000017D7UL /**< Mode DEFAULT for USB_DVBUSDIS */ 2254 #define USB_DVBUSDIS_DVBUSDIS_DEFAULT (_USB_DVBUSDIS_DVBUSDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DVBUSDIS */ 2255 2256 /* Bit fields for USB DVBUSPULSE */ 2257 #define _USB_DVBUSPULSE_RESETVALUE 0x000005B8UL /**< Default value for USB_DVBUSPULSE */ 2258 #define _USB_DVBUSPULSE_MASK 0x00000FFFUL /**< Mask for USB_DVBUSPULSE */ 2259 #define _USB_DVBUSPULSE_DVBUSPULSE_SHIFT 0 /**< Shift value for USB_DVBUSPULSE */ 2260 #define _USB_DVBUSPULSE_DVBUSPULSE_MASK 0xFFFUL /**< Bit mask for USB_DVBUSPULSE */ 2261 #define _USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x000005B8UL /**< Mode DEFAULT for USB_DVBUSPULSE */ 2262 #define USB_DVBUSPULSE_DVBUSPULSE_DEFAULT (_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DVBUSPULSE */ 2263 2264 /* Bit fields for USB DTHRCTL */ 2265 #define _USB_DTHRCTL_RESETVALUE 0x08100020UL /**< Default value for USB_DTHRCTL */ 2266 #define _USB_DTHRCTL_MASK 0x0BFF1FFFUL /**< Mask for USB_DTHRCTL */ 2267 #define USB_DTHRCTL_NONISOTHREN (0x1UL << 0) /**< Non-ISO IN Endpoints Threshold Enable */ 2268 #define _USB_DTHRCTL_NONISOTHREN_SHIFT 0 /**< Shift value for USB_NONISOTHREN */ 2269 #define _USB_DTHRCTL_NONISOTHREN_MASK 0x1UL /**< Bit mask for USB_NONISOTHREN */ 2270 #define _USB_DTHRCTL_NONISOTHREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DTHRCTL */ 2271 #define USB_DTHRCTL_NONISOTHREN_DEFAULT (_USB_DTHRCTL_NONISOTHREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DTHRCTL */ 2272 #define USB_DTHRCTL_ISOTHREN (0x1UL << 1) /**< ISO IN Endpoints Threshold Enable */ 2273 #define _USB_DTHRCTL_ISOTHREN_SHIFT 1 /**< Shift value for USB_ISOTHREN */ 2274 #define _USB_DTHRCTL_ISOTHREN_MASK 0x2UL /**< Bit mask for USB_ISOTHREN */ 2275 #define _USB_DTHRCTL_ISOTHREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DTHRCTL */ 2276 #define USB_DTHRCTL_ISOTHREN_DEFAULT (_USB_DTHRCTL_ISOTHREN_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DTHRCTL */ 2277 #define _USB_DTHRCTL_TXTHRLEN_SHIFT 2 /**< Shift value for USB_TXTHRLEN */ 2278 #define _USB_DTHRCTL_TXTHRLEN_MASK 0x7FCUL /**< Bit mask for USB_TXTHRLEN */ 2279 #define _USB_DTHRCTL_TXTHRLEN_DEFAULT 0x00000008UL /**< Mode DEFAULT for USB_DTHRCTL */ 2280 #define USB_DTHRCTL_TXTHRLEN_DEFAULT (_USB_DTHRCTL_TXTHRLEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DTHRCTL */ 2281 #define _USB_DTHRCTL_AHBTHRRATIO_SHIFT 11 /**< Shift value for USB_AHBTHRRATIO */ 2282 #define _USB_DTHRCTL_AHBTHRRATIO_MASK 0x1800UL /**< Bit mask for USB_AHBTHRRATIO */ 2283 #define _USB_DTHRCTL_AHBTHRRATIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DTHRCTL */ 2284 #define _USB_DTHRCTL_AHBTHRRATIO_DIV1 0x00000000UL /**< Mode DIV1 for USB_DTHRCTL */ 2285 #define _USB_DTHRCTL_AHBTHRRATIO_DIV2 0x00000001UL /**< Mode DIV2 for USB_DTHRCTL */ 2286 #define _USB_DTHRCTL_AHBTHRRATIO_DIV4 0x00000002UL /**< Mode DIV4 for USB_DTHRCTL */ 2287 #define _USB_DTHRCTL_AHBTHRRATIO_DIV8 0x00000003UL /**< Mode DIV8 for USB_DTHRCTL */ 2288 #define USB_DTHRCTL_AHBTHRRATIO_DEFAULT (_USB_DTHRCTL_AHBTHRRATIO_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DTHRCTL */ 2289 #define USB_DTHRCTL_AHBTHRRATIO_DIV1 (_USB_DTHRCTL_AHBTHRRATIO_DIV1 << 11) /**< Shifted mode DIV1 for USB_DTHRCTL */ 2290 #define USB_DTHRCTL_AHBTHRRATIO_DIV2 (_USB_DTHRCTL_AHBTHRRATIO_DIV2 << 11) /**< Shifted mode DIV2 for USB_DTHRCTL */ 2291 #define USB_DTHRCTL_AHBTHRRATIO_DIV4 (_USB_DTHRCTL_AHBTHRRATIO_DIV4 << 11) /**< Shifted mode DIV4 for USB_DTHRCTL */ 2292 #define USB_DTHRCTL_AHBTHRRATIO_DIV8 (_USB_DTHRCTL_AHBTHRRATIO_DIV8 << 11) /**< Shifted mode DIV8 for USB_DTHRCTL */ 2293 #define USB_DTHRCTL_RXTHREN (0x1UL << 16) /**< Receive Threshold Enable */ 2294 #define _USB_DTHRCTL_RXTHREN_SHIFT 16 /**< Shift value for USB_RXTHREN */ 2295 #define _USB_DTHRCTL_RXTHREN_MASK 0x10000UL /**< Bit mask for USB_RXTHREN */ 2296 #define _USB_DTHRCTL_RXTHREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DTHRCTL */ 2297 #define USB_DTHRCTL_RXTHREN_DEFAULT (_USB_DTHRCTL_RXTHREN_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DTHRCTL */ 2298 #define _USB_DTHRCTL_RXTHRLEN_SHIFT 17 /**< Shift value for USB_RXTHRLEN */ 2299 #define _USB_DTHRCTL_RXTHRLEN_MASK 0x3FE0000UL /**< Bit mask for USB_RXTHRLEN */ 2300 #define _USB_DTHRCTL_RXTHRLEN_DEFAULT 0x00000008UL /**< Mode DEFAULT for USB_DTHRCTL */ 2301 #define USB_DTHRCTL_RXTHRLEN_DEFAULT (_USB_DTHRCTL_RXTHRLEN_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DTHRCTL */ 2302 #define USB_DTHRCTL_ARBPRKEN (0x1UL << 27) /**< Arbiter Parking Enable */ 2303 #define _USB_DTHRCTL_ARBPRKEN_SHIFT 27 /**< Shift value for USB_ARBPRKEN */ 2304 #define _USB_DTHRCTL_ARBPRKEN_MASK 0x8000000UL /**< Bit mask for USB_ARBPRKEN */ 2305 #define _USB_DTHRCTL_ARBPRKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DTHRCTL */ 2306 #define USB_DTHRCTL_ARBPRKEN_DEFAULT (_USB_DTHRCTL_ARBPRKEN_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DTHRCTL */ 2307 2308 /* Bit fields for USB DIEPEMPMSK */ 2309 #define _USB_DIEPEMPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DIEPEMPMSK */ 2310 #define _USB_DIEPEMPMSK_MASK 0x0000FFFFUL /**< Mask for USB_DIEPEMPMSK */ 2311 #define _USB_DIEPEMPMSK_INEPTXFEMPMSK_SHIFT 0 /**< Shift value for USB_INEPTXFEMPMSK */ 2312 #define _USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK 0xFFFFUL /**< Bit mask for USB_INEPTXFEMPMSK */ 2313 #define _USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPEMPMSK */ 2314 #define USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT (_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPEMPMSK */ 2315 2316 /* Bit fields for USB DIEP0CTL */ 2317 #define _USB_DIEP0CTL_RESETVALUE 0x00008000UL /**< Default value for USB_DIEP0CTL */ 2318 #define _USB_DIEP0CTL_MASK 0xCFEE8003UL /**< Mask for USB_DIEP0CTL */ 2319 #define _USB_DIEP0CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */ 2320 #define _USB_DIEP0CTL_MPS_MASK 0x3UL /**< Bit mask for USB_MPS */ 2321 #define _USB_DIEP0CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ 2322 #define _USB_DIEP0CTL_MPS_64B 0x00000000UL /**< Mode 64B for USB_DIEP0CTL */ 2323 #define _USB_DIEP0CTL_MPS_32B 0x00000001UL /**< Mode 32B for USB_DIEP0CTL */ 2324 #define _USB_DIEP0CTL_MPS_16B 0x00000002UL /**< Mode 16B for USB_DIEP0CTL */ 2325 #define _USB_DIEP0CTL_MPS_8B 0x00000003UL /**< Mode 8B for USB_DIEP0CTL */ 2326 #define USB_DIEP0CTL_MPS_DEFAULT (_USB_DIEP0CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ 2327 #define USB_DIEP0CTL_MPS_64B (_USB_DIEP0CTL_MPS_64B << 0) /**< Shifted mode 64B for USB_DIEP0CTL */ 2328 #define USB_DIEP0CTL_MPS_32B (_USB_DIEP0CTL_MPS_32B << 0) /**< Shifted mode 32B for USB_DIEP0CTL */ 2329 #define USB_DIEP0CTL_MPS_16B (_USB_DIEP0CTL_MPS_16B << 0) /**< Shifted mode 16B for USB_DIEP0CTL */ 2330 #define USB_DIEP0CTL_MPS_8B (_USB_DIEP0CTL_MPS_8B << 0) /**< Shifted mode 8B for USB_DIEP0CTL */ 2331 #define USB_DIEP0CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */ 2332 #define _USB_DIEP0CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */ 2333 #define _USB_DIEP0CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */ 2334 #define _USB_DIEP0CTL_USBACTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP0CTL */ 2335 #define USB_DIEP0CTL_USBACTEP_DEFAULT (_USB_DIEP0CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ 2336 #define USB_DIEP0CTL_NAKSTS (0x1UL << 17) /**< NAK Status */ 2337 #define _USB_DIEP0CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */ 2338 #define _USB_DIEP0CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */ 2339 #define _USB_DIEP0CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ 2340 #define USB_DIEP0CTL_NAKSTS_DEFAULT (_USB_DIEP0CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ 2341 #define _USB_DIEP0CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ 2342 #define _USB_DIEP0CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ 2343 #define _USB_DIEP0CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ 2344 #define USB_DIEP0CTL_EPTYPE_DEFAULT (_USB_DIEP0CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ 2345 #define USB_DIEP0CTL_STALL (0x1UL << 21) /**< Handshake */ 2346 #define _USB_DIEP0CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */ 2347 #define _USB_DIEP0CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */ 2348 #define _USB_DIEP0CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ 2349 #define USB_DIEP0CTL_STALL_DEFAULT (_USB_DIEP0CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ 2350 #define _USB_DIEP0CTL_TXFNUM_SHIFT 22 /**< Shift value for USB_TXFNUM */ 2351 #define _USB_DIEP0CTL_TXFNUM_MASK 0x3C00000UL /**< Bit mask for USB_TXFNUM */ 2352 #define _USB_DIEP0CTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ 2353 #define USB_DIEP0CTL_TXFNUM_DEFAULT (_USB_DIEP0CTL_TXFNUM_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ 2354 #define USB_DIEP0CTL_CNAK (0x1UL << 26) /**< Clear NAK */ 2355 #define _USB_DIEP0CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */ 2356 #define _USB_DIEP0CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */ 2357 #define _USB_DIEP0CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ 2358 #define USB_DIEP0CTL_CNAK_DEFAULT (_USB_DIEP0CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ 2359 #define USB_DIEP0CTL_SNAK (0x1UL << 27) /**< Set NAK */ 2360 #define _USB_DIEP0CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */ 2361 #define _USB_DIEP0CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */ 2362 #define _USB_DIEP0CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ 2363 #define USB_DIEP0CTL_SNAK_DEFAULT (_USB_DIEP0CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ 2364 #define USB_DIEP0CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */ 2365 #define _USB_DIEP0CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */ 2366 #define _USB_DIEP0CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */ 2367 #define _USB_DIEP0CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ 2368 #define USB_DIEP0CTL_EPDIS_DEFAULT (_USB_DIEP0CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ 2369 #define USB_DIEP0CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */ 2370 #define _USB_DIEP0CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */ 2371 #define _USB_DIEP0CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */ 2372 #define _USB_DIEP0CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ 2373 #define USB_DIEP0CTL_EPENA_DEFAULT (_USB_DIEP0CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ 2374 2375 /* Bit fields for USB DIEP0INT */ 2376 #define _USB_DIEP0INT_RESETVALUE 0x00000080UL /**< Default value for USB_DIEP0INT */ 2377 #define _USB_DIEP0INT_MASK 0x000039FFUL /**< Mask for USB_DIEP0INT */ 2378 #define USB_DIEP0INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */ 2379 #define _USB_DIEP0INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ 2380 #define _USB_DIEP0INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ 2381 #define _USB_DIEP0INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ 2382 #define USB_DIEP0INT_XFERCOMPL_DEFAULT (_USB_DIEP0INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0INT */ 2383 #define USB_DIEP0INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */ 2384 #define _USB_DIEP0INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */ 2385 #define _USB_DIEP0INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */ 2386 #define _USB_DIEP0INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ 2387 #define USB_DIEP0INT_EPDISBLD_DEFAULT (_USB_DIEP0INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEP0INT */ 2388 #define USB_DIEP0INT_AHBERR (0x1UL << 2) /**< AHB Error */ 2389 #define _USB_DIEP0INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ 2390 #define _USB_DIEP0INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ 2391 #define _USB_DIEP0INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ 2392 #define USB_DIEP0INT_AHBERR_DEFAULT (_USB_DIEP0INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEP0INT */ 2393 #define USB_DIEP0INT_TIMEOUT (0x1UL << 3) /**< Timeout Condition */ 2394 #define _USB_DIEP0INT_TIMEOUT_SHIFT 3 /**< Shift value for USB_TIMEOUT */ 2395 #define _USB_DIEP0INT_TIMEOUT_MASK 0x8UL /**< Bit mask for USB_TIMEOUT */ 2396 #define _USB_DIEP0INT_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ 2397 #define USB_DIEP0INT_TIMEOUT_DEFAULT (_USB_DIEP0INT_TIMEOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEP0INT */ 2398 #define USB_DIEP0INT_INTKNTXFEMP (0x1UL << 4) /**< IN Token Received When TxFIFO is Empty */ 2399 #define _USB_DIEP0INT_INTKNTXFEMP_SHIFT 4 /**< Shift value for USB_INTKNTXFEMP */ 2400 #define _USB_DIEP0INT_INTKNTXFEMP_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMP */ 2401 #define _USB_DIEP0INT_INTKNTXFEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ 2402 #define USB_DIEP0INT_INTKNTXFEMP_DEFAULT (_USB_DIEP0INT_INTKNTXFEMP_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEP0INT */ 2403 #define USB_DIEP0INT_INTKNEPMIS (0x1UL << 5) /**< IN Token Received with EP Mismatch */ 2404 #define _USB_DIEP0INT_INTKNEPMIS_SHIFT 5 /**< Shift value for USB_INTKNEPMIS */ 2405 #define _USB_DIEP0INT_INTKNEPMIS_MASK 0x20UL /**< Bit mask for USB_INTKNEPMIS */ 2406 #define _USB_DIEP0INT_INTKNEPMIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ 2407 #define USB_DIEP0INT_INTKNEPMIS_DEFAULT (_USB_DIEP0INT_INTKNEPMIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DIEP0INT */ 2408 #define USB_DIEP0INT_INEPNAKEFF (0x1UL << 6) /**< IN Endpoint NAK Effective */ 2409 #define _USB_DIEP0INT_INEPNAKEFF_SHIFT 6 /**< Shift value for USB_INEPNAKEFF */ 2410 #define _USB_DIEP0INT_INEPNAKEFF_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFF */ 2411 #define _USB_DIEP0INT_INEPNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ 2412 #define USB_DIEP0INT_INEPNAKEFF_DEFAULT (_USB_DIEP0INT_INEPNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEP0INT */ 2413 #define USB_DIEP0INT_TXFEMP (0x1UL << 7) /**< Transmit FIFO Empty */ 2414 #define _USB_DIEP0INT_TXFEMP_SHIFT 7 /**< Shift value for USB_TXFEMP */ 2415 #define _USB_DIEP0INT_TXFEMP_MASK 0x80UL /**< Bit mask for USB_TXFEMP */ 2416 #define _USB_DIEP0INT_TXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP0INT */ 2417 #define USB_DIEP0INT_TXFEMP_DEFAULT (_USB_DIEP0INT_TXFEMP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DIEP0INT */ 2418 #define USB_DIEP0INT_TXFIFOUNDRN (0x1UL << 8) /**< Fifo Underrun */ 2419 #define _USB_DIEP0INT_TXFIFOUNDRN_SHIFT 8 /**< Shift value for USB_TXFIFOUNDRN */ 2420 #define _USB_DIEP0INT_TXFIFOUNDRN_MASK 0x100UL /**< Bit mask for USB_TXFIFOUNDRN */ 2421 #define _USB_DIEP0INT_TXFIFOUNDRN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ 2422 #define USB_DIEP0INT_TXFIFOUNDRN_DEFAULT (_USB_DIEP0INT_TXFIFOUNDRN_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DIEP0INT */ 2423 #define USB_DIEP0INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */ 2424 #define _USB_DIEP0INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */ 2425 #define _USB_DIEP0INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */ 2426 #define _USB_DIEP0INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ 2427 #define USB_DIEP0INT_PKTDRPSTS_DEFAULT (_USB_DIEP0INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DIEP0INT */ 2428 #define USB_DIEP0INT_BBLEERR (0x1UL << 12) /**< Babble Interrupt */ 2429 #define _USB_DIEP0INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */ 2430 #define _USB_DIEP0INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */ 2431 #define _USB_DIEP0INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ 2432 #define USB_DIEP0INT_BBLEERR_DEFAULT (_USB_DIEP0INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DIEP0INT */ 2433 #define USB_DIEP0INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */ 2434 #define _USB_DIEP0INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */ 2435 #define _USB_DIEP0INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */ 2436 #define _USB_DIEP0INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ 2437 #define USB_DIEP0INT_NAKINTRPT_DEFAULT (_USB_DIEP0INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEP0INT */ 2438 2439 /* Bit fields for USB DIEP0TSIZ */ 2440 #define _USB_DIEP0TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP0TSIZ */ 2441 #define _USB_DIEP0TSIZ_MASK 0x0018007FUL /**< Mask for USB_DIEP0TSIZ */ 2442 #define _USB_DIEP0TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ 2443 #define _USB_DIEP0TSIZ_XFERSIZE_MASK 0x7FUL /**< Bit mask for USB_XFERSIZE */ 2444 #define _USB_DIEP0TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0TSIZ */ 2445 #define USB_DIEP0TSIZ_XFERSIZE_DEFAULT (_USB_DIEP0TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0TSIZ */ 2446 #define _USB_DIEP0TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ 2447 #define _USB_DIEP0TSIZ_PKTCNT_MASK 0x180000UL /**< Bit mask for USB_PKTCNT */ 2448 #define _USB_DIEP0TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0TSIZ */ 2449 #define USB_DIEP0TSIZ_PKTCNT_DEFAULT (_USB_DIEP0TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DIEP0TSIZ */ 2450 2451 /* Bit fields for USB DIEP0DMAADDR */ 2452 #define _USB_DIEP0DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP0DMAADDR */ 2453 #define _USB_DIEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DIEP0DMAADDR */ 2454 #define _USB_DIEP0DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */ 2455 #define _USB_DIEP0DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */ 2456 #define _USB_DIEP0DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0DMAADDR */ 2457 #define USB_DIEP0DMAADDR_DMAADDR_DEFAULT (_USB_DIEP0DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0DMAADDR */ 2458 2459 /* Bit fields for USB DIEP0TXFSTS */ 2460 #define _USB_DIEP0TXFSTS_RESETVALUE 0x00000200UL /**< Default value for USB_DIEP0TXFSTS */ 2461 #define _USB_DIEP0TXFSTS_MASK 0x0000FFFFUL /**< Mask for USB_DIEP0TXFSTS */ 2462 #define _USB_DIEP0TXFSTS_SPCAVAIL_SHIFT 0 /**< Shift value for USB_SPCAVAIL */ 2463 #define _USB_DIEP0TXFSTS_SPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_SPCAVAIL */ 2464 #define _USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEP0TXFSTS */ 2465 #define USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT (_USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0TXFSTS */ 2466 2467 /* Bit fields for USB DIEP_CTL */ 2468 #define _USB_DIEP_CTL_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_CTL */ 2469 #define _USB_DIEP_CTL_MASK 0xFFEF87FFUL /**< Mask for USB_DIEP_CTL */ 2470 #define _USB_DIEP_CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */ 2471 #define _USB_DIEP_CTL_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */ 2472 #define _USB_DIEP_CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2473 #define USB_DIEP_CTL_MPS_DEFAULT (_USB_DIEP_CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2474 #define USB_DIEP_CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */ 2475 #define _USB_DIEP_CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */ 2476 #define _USB_DIEP_CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */ 2477 #define _USB_DIEP_CTL_USBACTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2478 #define USB_DIEP_CTL_USBACTEP_DEFAULT (_USB_DIEP_CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2479 #define USB_DIEP_CTL_DPIDEOF (0x1UL << 16) /**< Endpoint Data PID / Even or Odd Frame */ 2480 #define _USB_DIEP_CTL_DPIDEOF_SHIFT 16 /**< Shift value for USB_DPIDEOF */ 2481 #define _USB_DIEP_CTL_DPIDEOF_MASK 0x10000UL /**< Bit mask for USB_DPIDEOF */ 2482 #define _USB_DIEP_CTL_DPIDEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2483 #define _USB_DIEP_CTL_DPIDEOF_DATA0EVEN 0x00000000UL /**< Mode DATA0EVEN for USB_DIEP_CTL */ 2484 #define _USB_DIEP_CTL_DPIDEOF_DATA1ODD 0x00000001UL /**< Mode DATA1ODD for USB_DIEP_CTL */ 2485 #define USB_DIEP_CTL_DPIDEOF_DEFAULT (_USB_DIEP_CTL_DPIDEOF_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2486 #define USB_DIEP_CTL_DPIDEOF_DATA0EVEN (_USB_DIEP_CTL_DPIDEOF_DATA0EVEN << 16) /**< Shifted mode DATA0EVEN for USB_DIEP_CTL */ 2487 #define USB_DIEP_CTL_DPIDEOF_DATA1ODD (_USB_DIEP_CTL_DPIDEOF_DATA1ODD << 16) /**< Shifted mode DATA1ODD for USB_DIEP_CTL */ 2488 #define USB_DIEP_CTL_NAKSTS (0x1UL << 17) /**< NAK Status */ 2489 #define _USB_DIEP_CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */ 2490 #define _USB_DIEP_CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */ 2491 #define _USB_DIEP_CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2492 #define USB_DIEP_CTL_NAKSTS_DEFAULT (_USB_DIEP_CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2493 #define _USB_DIEP_CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ 2494 #define _USB_DIEP_CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ 2495 #define _USB_DIEP_CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2496 #define _USB_DIEP_CTL_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_DIEP_CTL */ 2497 #define _USB_DIEP_CTL_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_DIEP_CTL */ 2498 #define _USB_DIEP_CTL_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_DIEP_CTL */ 2499 #define _USB_DIEP_CTL_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_DIEP_CTL */ 2500 #define USB_DIEP_CTL_EPTYPE_DEFAULT (_USB_DIEP_CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2501 #define USB_DIEP_CTL_EPTYPE_CONTROL (_USB_DIEP_CTL_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_DIEP_CTL */ 2502 #define USB_DIEP_CTL_EPTYPE_ISO (_USB_DIEP_CTL_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_DIEP_CTL */ 2503 #define USB_DIEP_CTL_EPTYPE_BULK (_USB_DIEP_CTL_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_DIEP_CTL */ 2504 #define USB_DIEP_CTL_EPTYPE_INT (_USB_DIEP_CTL_EPTYPE_INT << 18) /**< Shifted mode INT for USB_DIEP_CTL */ 2505 #define USB_DIEP_CTL_STALL (0x1UL << 21) /**< Handshake */ 2506 #define _USB_DIEP_CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */ 2507 #define _USB_DIEP_CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */ 2508 #define _USB_DIEP_CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2509 #define USB_DIEP_CTL_STALL_DEFAULT (_USB_DIEP_CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2510 #define _USB_DIEP_CTL_TXFNUM_SHIFT 22 /**< Shift value for USB_TXFNUM */ 2511 #define _USB_DIEP_CTL_TXFNUM_MASK 0x3C00000UL /**< Bit mask for USB_TXFNUM */ 2512 #define _USB_DIEP_CTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2513 #define USB_DIEP_CTL_TXFNUM_DEFAULT (_USB_DIEP_CTL_TXFNUM_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2514 #define USB_DIEP_CTL_CNAK (0x1UL << 26) /**< Clear NAK */ 2515 #define _USB_DIEP_CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */ 2516 #define _USB_DIEP_CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */ 2517 #define _USB_DIEP_CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2518 #define USB_DIEP_CTL_CNAK_DEFAULT (_USB_DIEP_CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2519 #define USB_DIEP_CTL_SNAK (0x1UL << 27) /**< Set NAK */ 2520 #define _USB_DIEP_CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */ 2521 #define _USB_DIEP_CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */ 2522 #define _USB_DIEP_CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2523 #define USB_DIEP_CTL_SNAK_DEFAULT (_USB_DIEP_CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2524 #define USB_DIEP_CTL_SETD0PIDEF (0x1UL << 28) /**< Set DATA0 PID / Even Frame */ 2525 #define _USB_DIEP_CTL_SETD0PIDEF_SHIFT 28 /**< Shift value for USB_SETD0PIDEF */ 2526 #define _USB_DIEP_CTL_SETD0PIDEF_MASK 0x10000000UL /**< Bit mask for USB_SETD0PIDEF */ 2527 #define _USB_DIEP_CTL_SETD0PIDEF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2528 #define USB_DIEP_CTL_SETD0PIDEF_DEFAULT (_USB_DIEP_CTL_SETD0PIDEF_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2529 #define USB_DIEP_CTL_SETD1PIDOF (0x1UL << 29) /**< Set DATA1 PID / Odd Frame */ 2530 #define _USB_DIEP_CTL_SETD1PIDOF_SHIFT 29 /**< Shift value for USB_SETD1PIDOF */ 2531 #define _USB_DIEP_CTL_SETD1PIDOF_MASK 0x20000000UL /**< Bit mask for USB_SETD1PIDOF */ 2532 #define _USB_DIEP_CTL_SETD1PIDOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2533 #define USB_DIEP_CTL_SETD1PIDOF_DEFAULT (_USB_DIEP_CTL_SETD1PIDOF_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2534 #define USB_DIEP_CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */ 2535 #define _USB_DIEP_CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */ 2536 #define _USB_DIEP_CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */ 2537 #define _USB_DIEP_CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2538 #define USB_DIEP_CTL_EPDIS_DEFAULT (_USB_DIEP_CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2539 #define USB_DIEP_CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */ 2540 #define _USB_DIEP_CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */ 2541 #define _USB_DIEP_CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */ 2542 #define _USB_DIEP_CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ 2543 #define USB_DIEP_CTL_EPENA_DEFAULT (_USB_DIEP_CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ 2544 2545 /* Bit fields for USB DIEP_INT */ 2546 #define _USB_DIEP_INT_RESETVALUE 0x00000080UL /**< Default value for USB_DIEP_INT */ 2547 #define _USB_DIEP_INT_MASK 0x000039FFUL /**< Mask for USB_DIEP_INT */ 2548 #define USB_DIEP_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */ 2549 #define _USB_DIEP_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ 2550 #define _USB_DIEP_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ 2551 #define _USB_DIEP_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ 2552 #define USB_DIEP_INT_XFERCOMPL_DEFAULT (_USB_DIEP_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_INT */ 2553 #define USB_DIEP_INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */ 2554 #define _USB_DIEP_INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */ 2555 #define _USB_DIEP_INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */ 2556 #define _USB_DIEP_INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ 2557 #define USB_DIEP_INT_EPDISBLD_DEFAULT (_USB_DIEP_INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEP_INT */ 2558 #define USB_DIEP_INT_AHBERR (0x1UL << 2) /**< AHB Error */ 2559 #define _USB_DIEP_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ 2560 #define _USB_DIEP_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ 2561 #define _USB_DIEP_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ 2562 #define USB_DIEP_INT_AHBERR_DEFAULT (_USB_DIEP_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEP_INT */ 2563 #define USB_DIEP_INT_TIMEOUT (0x1UL << 3) /**< Timeout Condition */ 2564 #define _USB_DIEP_INT_TIMEOUT_SHIFT 3 /**< Shift value for USB_TIMEOUT */ 2565 #define _USB_DIEP_INT_TIMEOUT_MASK 0x8UL /**< Bit mask for USB_TIMEOUT */ 2566 #define _USB_DIEP_INT_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ 2567 #define USB_DIEP_INT_TIMEOUT_DEFAULT (_USB_DIEP_INT_TIMEOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEP_INT */ 2568 #define USB_DIEP_INT_INTKNTXFEMP (0x1UL << 4) /**< IN Token Received When TxFIFO is Empty */ 2569 #define _USB_DIEP_INT_INTKNTXFEMP_SHIFT 4 /**< Shift value for USB_INTKNTXFEMP */ 2570 #define _USB_DIEP_INT_INTKNTXFEMP_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMP */ 2571 #define _USB_DIEP_INT_INTKNTXFEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ 2572 #define USB_DIEP_INT_INTKNTXFEMP_DEFAULT (_USB_DIEP_INT_INTKNTXFEMP_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEP_INT */ 2573 #define USB_DIEP_INT_INTKNEPMIS (0x1UL << 5) /**< IN Token Received with EP Mismatch */ 2574 #define _USB_DIEP_INT_INTKNEPMIS_SHIFT 5 /**< Shift value for USB_INTKNEPMIS */ 2575 #define _USB_DIEP_INT_INTKNEPMIS_MASK 0x20UL /**< Bit mask for USB_INTKNEPMIS */ 2576 #define _USB_DIEP_INT_INTKNEPMIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ 2577 #define USB_DIEP_INT_INTKNEPMIS_DEFAULT (_USB_DIEP_INT_INTKNEPMIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DIEP_INT */ 2578 #define USB_DIEP_INT_INEPNAKEFF (0x1UL << 6) /**< IN Endpoint NAK Effective */ 2579 #define _USB_DIEP_INT_INEPNAKEFF_SHIFT 6 /**< Shift value for USB_INEPNAKEFF */ 2580 #define _USB_DIEP_INT_INEPNAKEFF_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFF */ 2581 #define _USB_DIEP_INT_INEPNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ 2582 #define USB_DIEP_INT_INEPNAKEFF_DEFAULT (_USB_DIEP_INT_INEPNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEP_INT */ 2583 #define USB_DIEP_INT_TXFEMP (0x1UL << 7) /**< Transmit FIFO Empty */ 2584 #define _USB_DIEP_INT_TXFEMP_SHIFT 7 /**< Shift value for USB_TXFEMP */ 2585 #define _USB_DIEP_INT_TXFEMP_MASK 0x80UL /**< Bit mask for USB_TXFEMP */ 2586 #define _USB_DIEP_INT_TXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP_INT */ 2587 #define USB_DIEP_INT_TXFEMP_DEFAULT (_USB_DIEP_INT_TXFEMP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DIEP_INT */ 2588 #define USB_DIEP_INT_TXFIFOUNDRN (0x1UL << 8) /**< Fifo Underrun */ 2589 #define _USB_DIEP_INT_TXFIFOUNDRN_SHIFT 8 /**< Shift value for USB_TXFIFOUNDRN */ 2590 #define _USB_DIEP_INT_TXFIFOUNDRN_MASK 0x100UL /**< Bit mask for USB_TXFIFOUNDRN */ 2591 #define _USB_DIEP_INT_TXFIFOUNDRN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ 2592 #define USB_DIEP_INT_TXFIFOUNDRN_DEFAULT (_USB_DIEP_INT_TXFIFOUNDRN_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DIEP_INT */ 2593 #define USB_DIEP_INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */ 2594 #define _USB_DIEP_INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */ 2595 #define _USB_DIEP_INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */ 2596 #define _USB_DIEP_INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ 2597 #define USB_DIEP_INT_PKTDRPSTS_DEFAULT (_USB_DIEP_INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DIEP_INT */ 2598 #define USB_DIEP_INT_BBLEERR (0x1UL << 12) /**< Babble Interrupt */ 2599 #define _USB_DIEP_INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */ 2600 #define _USB_DIEP_INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */ 2601 #define _USB_DIEP_INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ 2602 #define USB_DIEP_INT_BBLEERR_DEFAULT (_USB_DIEP_INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DIEP_INT */ 2603 #define USB_DIEP_INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */ 2604 #define _USB_DIEP_INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */ 2605 #define _USB_DIEP_INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */ 2606 #define _USB_DIEP_INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ 2607 #define USB_DIEP_INT_NAKINTRPT_DEFAULT (_USB_DIEP_INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEP_INT */ 2608 2609 /* Bit fields for USB DIEP_TSIZ */ 2610 #define _USB_DIEP_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_TSIZ */ 2611 #define _USB_DIEP_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_DIEP_TSIZ */ 2612 #define _USB_DIEP_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ 2613 #define _USB_DIEP_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */ 2614 #define _USB_DIEP_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */ 2615 #define USB_DIEP_TSIZ_XFERSIZE_DEFAULT (_USB_DIEP_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */ 2616 #define _USB_DIEP_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ 2617 #define _USB_DIEP_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */ 2618 #define _USB_DIEP_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */ 2619 #define USB_DIEP_TSIZ_PKTCNT_DEFAULT (_USB_DIEP_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */ 2620 #define _USB_DIEP_TSIZ_MC_SHIFT 29 /**< Shift value for USB_MC */ 2621 #define _USB_DIEP_TSIZ_MC_MASK 0x60000000UL /**< Bit mask for USB_MC */ 2622 #define _USB_DIEP_TSIZ_MC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */ 2623 #define USB_DIEP_TSIZ_MC_DEFAULT (_USB_DIEP_TSIZ_MC_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */ 2624 2625 /* Bit fields for USB DIEP_DMAADDR */ 2626 #define _USB_DIEP_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_DMAADDR */ 2627 #define _USB_DIEP_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DIEP_DMAADDR */ 2628 #define _USB_DIEP_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */ 2629 #define _USB_DIEP_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */ 2630 #define _USB_DIEP_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_DMAADDR */ 2631 #define USB_DIEP_DMAADDR_DMAADDR_DEFAULT (_USB_DIEP_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_DMAADDR */ 2632 2633 /* Bit fields for USB DIEP_DTXFSTS */ 2634 #define _USB_DIEP_DTXFSTS_RESETVALUE 0x00000200UL /**< Default value for USB_DIEP_DTXFSTS */ 2635 #define _USB_DIEP_DTXFSTS_MASK 0x0000FFFFUL /**< Mask for USB_DIEP_DTXFSTS */ 2636 #define _USB_DIEP_DTXFSTS_SPCAVAIL_SHIFT 0 /**< Shift value for USB_SPCAVAIL */ 2637 #define _USB_DIEP_DTXFSTS_SPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_SPCAVAIL */ 2638 #define _USB_DIEP_DTXFSTS_SPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEP_DTXFSTS */ 2639 #define USB_DIEP_DTXFSTS_SPCAVAIL_DEFAULT (_USB_DIEP_DTXFSTS_SPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_DTXFSTS */ 2640 2641 /* Bit fields for USB DOEP0CTL */ 2642 #define _USB_DOEP0CTL_RESETVALUE 0x00008000UL /**< Default value for USB_DOEP0CTL */ 2643 #define _USB_DOEP0CTL_MASK 0xCC3E8003UL /**< Mask for USB_DOEP0CTL */ 2644 #define _USB_DOEP0CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */ 2645 #define _USB_DOEP0CTL_MPS_MASK 0x3UL /**< Bit mask for USB_MPS */ 2646 #define _USB_DOEP0CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ 2647 #define _USB_DOEP0CTL_MPS_64B 0x00000000UL /**< Mode 64B for USB_DOEP0CTL */ 2648 #define _USB_DOEP0CTL_MPS_32B 0x00000001UL /**< Mode 32B for USB_DOEP0CTL */ 2649 #define _USB_DOEP0CTL_MPS_16B 0x00000002UL /**< Mode 16B for USB_DOEP0CTL */ 2650 #define _USB_DOEP0CTL_MPS_8B 0x00000003UL /**< Mode 8B for USB_DOEP0CTL */ 2651 #define USB_DOEP0CTL_MPS_DEFAULT (_USB_DOEP0CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ 2652 #define USB_DOEP0CTL_MPS_64B (_USB_DOEP0CTL_MPS_64B << 0) /**< Shifted mode 64B for USB_DOEP0CTL */ 2653 #define USB_DOEP0CTL_MPS_32B (_USB_DOEP0CTL_MPS_32B << 0) /**< Shifted mode 32B for USB_DOEP0CTL */ 2654 #define USB_DOEP0CTL_MPS_16B (_USB_DOEP0CTL_MPS_16B << 0) /**< Shifted mode 16B for USB_DOEP0CTL */ 2655 #define USB_DOEP0CTL_MPS_8B (_USB_DOEP0CTL_MPS_8B << 0) /**< Shifted mode 8B for USB_DOEP0CTL */ 2656 #define USB_DOEP0CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */ 2657 #define _USB_DOEP0CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */ 2658 #define _USB_DOEP0CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */ 2659 #define _USB_DOEP0CTL_USBACTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DOEP0CTL */ 2660 #define USB_DOEP0CTL_USBACTEP_DEFAULT (_USB_DOEP0CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ 2661 #define USB_DOEP0CTL_NAKSTS (0x1UL << 17) /**< NAK Status */ 2662 #define _USB_DOEP0CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */ 2663 #define _USB_DOEP0CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */ 2664 #define _USB_DOEP0CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ 2665 #define USB_DOEP0CTL_NAKSTS_DEFAULT (_USB_DOEP0CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ 2666 #define _USB_DOEP0CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ 2667 #define _USB_DOEP0CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ 2668 #define _USB_DOEP0CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ 2669 #define USB_DOEP0CTL_EPTYPE_DEFAULT (_USB_DOEP0CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ 2670 #define USB_DOEP0CTL_SNP (0x1UL << 20) /**< Snoop Mode */ 2671 #define _USB_DOEP0CTL_SNP_SHIFT 20 /**< Shift value for USB_SNP */ 2672 #define _USB_DOEP0CTL_SNP_MASK 0x100000UL /**< Bit mask for USB_SNP */ 2673 #define _USB_DOEP0CTL_SNP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ 2674 #define USB_DOEP0CTL_SNP_DEFAULT (_USB_DOEP0CTL_SNP_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ 2675 #define USB_DOEP0CTL_STALL (0x1UL << 21) /**< Handshake */ 2676 #define _USB_DOEP0CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */ 2677 #define _USB_DOEP0CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */ 2678 #define _USB_DOEP0CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ 2679 #define USB_DOEP0CTL_STALL_DEFAULT (_USB_DOEP0CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ 2680 #define USB_DOEP0CTL_CNAK (0x1UL << 26) /**< Clear NAK */ 2681 #define _USB_DOEP0CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */ 2682 #define _USB_DOEP0CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */ 2683 #define _USB_DOEP0CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ 2684 #define USB_DOEP0CTL_CNAK_DEFAULT (_USB_DOEP0CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ 2685 #define USB_DOEP0CTL_SNAK (0x1UL << 27) /**< Set NAK */ 2686 #define _USB_DOEP0CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */ 2687 #define _USB_DOEP0CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */ 2688 #define _USB_DOEP0CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ 2689 #define USB_DOEP0CTL_SNAK_DEFAULT (_USB_DOEP0CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ 2690 #define USB_DOEP0CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */ 2691 #define _USB_DOEP0CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */ 2692 #define _USB_DOEP0CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */ 2693 #define _USB_DOEP0CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ 2694 #define USB_DOEP0CTL_EPDIS_DEFAULT (_USB_DOEP0CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ 2695 #define USB_DOEP0CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */ 2696 #define _USB_DOEP0CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */ 2697 #define _USB_DOEP0CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */ 2698 #define _USB_DOEP0CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ 2699 #define USB_DOEP0CTL_EPENA_DEFAULT (_USB_DOEP0CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ 2700 2701 /* Bit fields for USB DOEP0INT */ 2702 #define _USB_DOEP0INT_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0INT */ 2703 #define _USB_DOEP0INT_MASK 0x0000B97FUL /**< Mask for USB_DOEP0INT */ 2704 #define USB_DOEP0INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */ 2705 #define _USB_DOEP0INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ 2706 #define _USB_DOEP0INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ 2707 #define _USB_DOEP0INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ 2708 #define USB_DOEP0INT_XFERCOMPL_DEFAULT (_USB_DOEP0INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0INT */ 2709 #define USB_DOEP0INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */ 2710 #define _USB_DOEP0INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */ 2711 #define _USB_DOEP0INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */ 2712 #define _USB_DOEP0INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ 2713 #define USB_DOEP0INT_EPDISBLD_DEFAULT (_USB_DOEP0INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEP0INT */ 2714 #define USB_DOEP0INT_AHBERR (0x1UL << 2) /**< AHB Error */ 2715 #define _USB_DOEP0INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ 2716 #define _USB_DOEP0INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ 2717 #define _USB_DOEP0INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ 2718 #define USB_DOEP0INT_AHBERR_DEFAULT (_USB_DOEP0INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEP0INT */ 2719 #define USB_DOEP0INT_SETUP (0x1UL << 3) /**< Setup Phase Done */ 2720 #define _USB_DOEP0INT_SETUP_SHIFT 3 /**< Shift value for USB_SETUP */ 2721 #define _USB_DOEP0INT_SETUP_MASK 0x8UL /**< Bit mask for USB_SETUP */ 2722 #define _USB_DOEP0INT_SETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ 2723 #define USB_DOEP0INT_SETUP_DEFAULT (_USB_DOEP0INT_SETUP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEP0INT */ 2724 #define USB_DOEP0INT_OUTTKNEPDIS (0x1UL << 4) /**< OUT Token Received When Endpoint Disabled */ 2725 #define _USB_DOEP0INT_OUTTKNEPDIS_SHIFT 4 /**< Shift value for USB_OUTTKNEPDIS */ 2726 #define _USB_DOEP0INT_OUTTKNEPDIS_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDIS */ 2727 #define _USB_DOEP0INT_OUTTKNEPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ 2728 #define USB_DOEP0INT_OUTTKNEPDIS_DEFAULT (_USB_DOEP0INT_OUTTKNEPDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEP0INT */ 2729 #define USB_DOEP0INT_STSPHSERCVD (0x1UL << 5) /**< Status Phase Received For Control Write */ 2730 #define _USB_DOEP0INT_STSPHSERCVD_SHIFT 5 /**< Shift value for USB_STSPHSERCVD */ 2731 #define _USB_DOEP0INT_STSPHSERCVD_MASK 0x20UL /**< Bit mask for USB_STSPHSERCVD */ 2732 #define _USB_DOEP0INT_STSPHSERCVD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ 2733 #define USB_DOEP0INT_STSPHSERCVD_DEFAULT (_USB_DOEP0INT_STSPHSERCVD_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DOEP0INT */ 2734 #define USB_DOEP0INT_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received */ 2735 #define _USB_DOEP0INT_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */ 2736 #define _USB_DOEP0INT_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */ 2737 #define _USB_DOEP0INT_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ 2738 #define USB_DOEP0INT_BACK2BACKSETUP_DEFAULT (_USB_DOEP0INT_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEP0INT */ 2739 #define USB_DOEP0INT_OUTPKTERR (0x1UL << 8) /**< OUT Packet Error */ 2740 #define _USB_DOEP0INT_OUTPKTERR_SHIFT 8 /**< Shift value for USB_OUTPKTERR */ 2741 #define _USB_DOEP0INT_OUTPKTERR_MASK 0x100UL /**< Bit mask for USB_OUTPKTERR */ 2742 #define _USB_DOEP0INT_OUTPKTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ 2743 #define USB_DOEP0INT_OUTPKTERR_DEFAULT (_USB_DOEP0INT_OUTPKTERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DOEP0INT */ 2744 #define USB_DOEP0INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */ 2745 #define _USB_DOEP0INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */ 2746 #define _USB_DOEP0INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */ 2747 #define _USB_DOEP0INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ 2748 #define USB_DOEP0INT_PKTDRPSTS_DEFAULT (_USB_DOEP0INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DOEP0INT */ 2749 #define USB_DOEP0INT_BBLEERR (0x1UL << 12) /**< NAK Interrupt */ 2750 #define _USB_DOEP0INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */ 2751 #define _USB_DOEP0INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */ 2752 #define _USB_DOEP0INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ 2753 #define USB_DOEP0INT_BBLEERR_DEFAULT (_USB_DOEP0INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEP0INT */ 2754 #define USB_DOEP0INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */ 2755 #define _USB_DOEP0INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */ 2756 #define _USB_DOEP0INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */ 2757 #define _USB_DOEP0INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ 2758 #define USB_DOEP0INT_NAKINTRPT_DEFAULT (_USB_DOEP0INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEP0INT */ 2759 #define USB_DOEP0INT_STUPPKTRCVD (0x1UL << 15) /**< */ 2760 #define _USB_DOEP0INT_STUPPKTRCVD_SHIFT 15 /**< Shift value for USB_STUPPKTRCVD */ 2761 #define _USB_DOEP0INT_STUPPKTRCVD_MASK 0x8000UL /**< Bit mask for USB_STUPPKTRCVD */ 2762 #define _USB_DOEP0INT_STUPPKTRCVD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ 2763 #define USB_DOEP0INT_STUPPKTRCVD_DEFAULT (_USB_DOEP0INT_STUPPKTRCVD_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP0INT */ 2764 2765 /* Bit fields for USB DOEP0TSIZ */ 2766 #define _USB_DOEP0TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0TSIZ */ 2767 #define _USB_DOEP0TSIZ_MASK 0x6008007FUL /**< Mask for USB_DOEP0TSIZ */ 2768 #define _USB_DOEP0TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ 2769 #define _USB_DOEP0TSIZ_XFERSIZE_MASK 0x7FUL /**< Bit mask for USB_XFERSIZE */ 2770 #define _USB_DOEP0TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */ 2771 #define USB_DOEP0TSIZ_XFERSIZE_DEFAULT (_USB_DOEP0TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */ 2772 #define USB_DOEP0TSIZ_PKTCNT (0x1UL << 19) /**< Packet Count */ 2773 #define _USB_DOEP0TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ 2774 #define _USB_DOEP0TSIZ_PKTCNT_MASK 0x80000UL /**< Bit mask for USB_PKTCNT */ 2775 #define _USB_DOEP0TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */ 2776 #define USB_DOEP0TSIZ_PKTCNT_DEFAULT (_USB_DOEP0TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */ 2777 #define _USB_DOEP0TSIZ_SUPCNT_SHIFT 29 /**< Shift value for USB_SUPCNT */ 2778 #define _USB_DOEP0TSIZ_SUPCNT_MASK 0x60000000UL /**< Bit mask for USB_SUPCNT */ 2779 #define _USB_DOEP0TSIZ_SUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */ 2780 #define USB_DOEP0TSIZ_SUPCNT_DEFAULT (_USB_DOEP0TSIZ_SUPCNT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */ 2781 2782 /* Bit fields for USB DOEP0DMAADDR */ 2783 #define _USB_DOEP0DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0DMAADDR */ 2784 #define _USB_DOEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DOEP0DMAADDR */ 2785 #define _USB_DOEP0DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */ 2786 #define _USB_DOEP0DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */ 2787 #define _USB_DOEP0DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0DMAADDR */ 2788 #define USB_DOEP0DMAADDR_DMAADDR_DEFAULT (_USB_DOEP0DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0DMAADDR */ 2789 2790 /* Bit fields for USB DOEP_CTL */ 2791 #define _USB_DOEP_CTL_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_CTL */ 2792 #define _USB_DOEP_CTL_MASK 0xFC3F87FFUL /**< Mask for USB_DOEP_CTL */ 2793 #define _USB_DOEP_CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */ 2794 #define _USB_DOEP_CTL_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */ 2795 #define _USB_DOEP_CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2796 #define USB_DOEP_CTL_MPS_DEFAULT (_USB_DOEP_CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2797 #define USB_DOEP_CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */ 2798 #define _USB_DOEP_CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */ 2799 #define _USB_DOEP_CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */ 2800 #define _USB_DOEP_CTL_USBACTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2801 #define USB_DOEP_CTL_USBACTEP_DEFAULT (_USB_DOEP_CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2802 #define USB_DOEP_CTL_DPIDEOF (0x1UL << 16) /**< Endpoint Data PID / Even-odd Frame */ 2803 #define _USB_DOEP_CTL_DPIDEOF_SHIFT 16 /**< Shift value for USB_DPIDEOF */ 2804 #define _USB_DOEP_CTL_DPIDEOF_MASK 0x10000UL /**< Bit mask for USB_DPIDEOF */ 2805 #define _USB_DOEP_CTL_DPIDEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2806 #define _USB_DOEP_CTL_DPIDEOF_DATA0EVEN 0x00000000UL /**< Mode DATA0EVEN for USB_DOEP_CTL */ 2807 #define _USB_DOEP_CTL_DPIDEOF_DATA1ODD 0x00000001UL /**< Mode DATA1ODD for USB_DOEP_CTL */ 2808 #define USB_DOEP_CTL_DPIDEOF_DEFAULT (_USB_DOEP_CTL_DPIDEOF_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2809 #define USB_DOEP_CTL_DPIDEOF_DATA0EVEN (_USB_DOEP_CTL_DPIDEOF_DATA0EVEN << 16) /**< Shifted mode DATA0EVEN for USB_DOEP_CTL */ 2810 #define USB_DOEP_CTL_DPIDEOF_DATA1ODD (_USB_DOEP_CTL_DPIDEOF_DATA1ODD << 16) /**< Shifted mode DATA1ODD for USB_DOEP_CTL */ 2811 #define USB_DOEP_CTL_NAKSTS (0x1UL << 17) /**< NAK Status */ 2812 #define _USB_DOEP_CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */ 2813 #define _USB_DOEP_CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */ 2814 #define _USB_DOEP_CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2815 #define USB_DOEP_CTL_NAKSTS_DEFAULT (_USB_DOEP_CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2816 #define _USB_DOEP_CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ 2817 #define _USB_DOEP_CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ 2818 #define _USB_DOEP_CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2819 #define _USB_DOEP_CTL_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_DOEP_CTL */ 2820 #define _USB_DOEP_CTL_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_DOEP_CTL */ 2821 #define _USB_DOEP_CTL_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_DOEP_CTL */ 2822 #define _USB_DOEP_CTL_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_DOEP_CTL */ 2823 #define USB_DOEP_CTL_EPTYPE_DEFAULT (_USB_DOEP_CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2824 #define USB_DOEP_CTL_EPTYPE_CONTROL (_USB_DOEP_CTL_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_DOEP_CTL */ 2825 #define USB_DOEP_CTL_EPTYPE_ISO (_USB_DOEP_CTL_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_DOEP_CTL */ 2826 #define USB_DOEP_CTL_EPTYPE_BULK (_USB_DOEP_CTL_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_DOEP_CTL */ 2827 #define USB_DOEP_CTL_EPTYPE_INT (_USB_DOEP_CTL_EPTYPE_INT << 18) /**< Shifted mode INT for USB_DOEP_CTL */ 2828 #define USB_DOEP_CTL_SNP (0x1UL << 20) /**< Snoop Mode */ 2829 #define _USB_DOEP_CTL_SNP_SHIFT 20 /**< Shift value for USB_SNP */ 2830 #define _USB_DOEP_CTL_SNP_MASK 0x100000UL /**< Bit mask for USB_SNP */ 2831 #define _USB_DOEP_CTL_SNP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2832 #define USB_DOEP_CTL_SNP_DEFAULT (_USB_DOEP_CTL_SNP_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2833 #define USB_DOEP_CTL_STALL (0x1UL << 21) /**< STALL Handshake */ 2834 #define _USB_DOEP_CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */ 2835 #define _USB_DOEP_CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */ 2836 #define _USB_DOEP_CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2837 #define USB_DOEP_CTL_STALL_DEFAULT (_USB_DOEP_CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2838 #define USB_DOEP_CTL_CNAK (0x1UL << 26) /**< Clear NAK */ 2839 #define _USB_DOEP_CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */ 2840 #define _USB_DOEP_CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */ 2841 #define _USB_DOEP_CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2842 #define USB_DOEP_CTL_CNAK_DEFAULT (_USB_DOEP_CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2843 #define USB_DOEP_CTL_SNAK (0x1UL << 27) /**< Set NAK */ 2844 #define _USB_DOEP_CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */ 2845 #define _USB_DOEP_CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */ 2846 #define _USB_DOEP_CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2847 #define USB_DOEP_CTL_SNAK_DEFAULT (_USB_DOEP_CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2848 #define USB_DOEP_CTL_SETD0PIDEF (0x1UL << 28) /**< Set DATA0 PID / Even Frame */ 2849 #define _USB_DOEP_CTL_SETD0PIDEF_SHIFT 28 /**< Shift value for USB_SETD0PIDEF */ 2850 #define _USB_DOEP_CTL_SETD0PIDEF_MASK 0x10000000UL /**< Bit mask for USB_SETD0PIDEF */ 2851 #define _USB_DOEP_CTL_SETD0PIDEF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2852 #define USB_DOEP_CTL_SETD0PIDEF_DEFAULT (_USB_DOEP_CTL_SETD0PIDEF_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2853 #define USB_DOEP_CTL_SETD1PIDOF (0x1UL << 29) /**< Set DATA1 PID / Odd Frame */ 2854 #define _USB_DOEP_CTL_SETD1PIDOF_SHIFT 29 /**< Shift value for USB_SETD1PIDOF */ 2855 #define _USB_DOEP_CTL_SETD1PIDOF_MASK 0x20000000UL /**< Bit mask for USB_SETD1PIDOF */ 2856 #define _USB_DOEP_CTL_SETD1PIDOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2857 #define USB_DOEP_CTL_SETD1PIDOF_DEFAULT (_USB_DOEP_CTL_SETD1PIDOF_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2858 #define USB_DOEP_CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */ 2859 #define _USB_DOEP_CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */ 2860 #define _USB_DOEP_CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */ 2861 #define _USB_DOEP_CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2862 #define USB_DOEP_CTL_EPDIS_DEFAULT (_USB_DOEP_CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2863 #define USB_DOEP_CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */ 2864 #define _USB_DOEP_CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */ 2865 #define _USB_DOEP_CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */ 2866 #define _USB_DOEP_CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ 2867 #define USB_DOEP_CTL_EPENA_DEFAULT (_USB_DOEP_CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ 2868 2869 /* Bit fields for USB DOEP_INT */ 2870 #define _USB_DOEP_INT_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_INT */ 2871 #define _USB_DOEP_INT_MASK 0x0000B97FUL /**< Mask for USB_DOEP_INT */ 2872 #define USB_DOEP_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */ 2873 #define _USB_DOEP_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ 2874 #define _USB_DOEP_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ 2875 #define _USB_DOEP_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ 2876 #define USB_DOEP_INT_XFERCOMPL_DEFAULT (_USB_DOEP_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_INT */ 2877 #define USB_DOEP_INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */ 2878 #define _USB_DOEP_INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */ 2879 #define _USB_DOEP_INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */ 2880 #define _USB_DOEP_INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ 2881 #define USB_DOEP_INT_EPDISBLD_DEFAULT (_USB_DOEP_INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEP_INT */ 2882 #define USB_DOEP_INT_AHBERR (0x1UL << 2) /**< AHB Error */ 2883 #define _USB_DOEP_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ 2884 #define _USB_DOEP_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ 2885 #define _USB_DOEP_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ 2886 #define USB_DOEP_INT_AHBERR_DEFAULT (_USB_DOEP_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEP_INT */ 2887 #define USB_DOEP_INT_SETUP (0x1UL << 3) /**< Setup Phase Done */ 2888 #define _USB_DOEP_INT_SETUP_SHIFT 3 /**< Shift value for USB_SETUP */ 2889 #define _USB_DOEP_INT_SETUP_MASK 0x8UL /**< Bit mask for USB_SETUP */ 2890 #define _USB_DOEP_INT_SETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ 2891 #define USB_DOEP_INT_SETUP_DEFAULT (_USB_DOEP_INT_SETUP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEP_INT */ 2892 #define USB_DOEP_INT_OUTTKNEPDIS (0x1UL << 4) /**< OUT Token Received When Endpoint Disabled */ 2893 #define _USB_DOEP_INT_OUTTKNEPDIS_SHIFT 4 /**< Shift value for USB_OUTTKNEPDIS */ 2894 #define _USB_DOEP_INT_OUTTKNEPDIS_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDIS */ 2895 #define _USB_DOEP_INT_OUTTKNEPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ 2896 #define USB_DOEP_INT_OUTTKNEPDIS_DEFAULT (_USB_DOEP_INT_OUTTKNEPDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEP_INT */ 2897 #define USB_DOEP_INT_STSPHSERCVD (0x1UL << 5) /**< Status Phase Received For Control Write */ 2898 #define _USB_DOEP_INT_STSPHSERCVD_SHIFT 5 /**< Shift value for USB_STSPHSERCVD */ 2899 #define _USB_DOEP_INT_STSPHSERCVD_MASK 0x20UL /**< Bit mask for USB_STSPHSERCVD */ 2900 #define _USB_DOEP_INT_STSPHSERCVD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ 2901 #define USB_DOEP_INT_STSPHSERCVD_DEFAULT (_USB_DOEP_INT_STSPHSERCVD_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DOEP_INT */ 2902 #define USB_DOEP_INT_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received */ 2903 #define _USB_DOEP_INT_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */ 2904 #define _USB_DOEP_INT_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */ 2905 #define _USB_DOEP_INT_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ 2906 #define USB_DOEP_INT_BACK2BACKSETUP_DEFAULT (_USB_DOEP_INT_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEP_INT */ 2907 #define USB_DOEP_INT_OUTPKTERR (0x1UL << 8) /**< OUT Packet Error */ 2908 #define _USB_DOEP_INT_OUTPKTERR_SHIFT 8 /**< Shift value for USB_OUTPKTERR */ 2909 #define _USB_DOEP_INT_OUTPKTERR_MASK 0x100UL /**< Bit mask for USB_OUTPKTERR */ 2910 #define _USB_DOEP_INT_OUTPKTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ 2911 #define USB_DOEP_INT_OUTPKTERR_DEFAULT (_USB_DOEP_INT_OUTPKTERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DOEP_INT */ 2912 #define USB_DOEP_INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */ 2913 #define _USB_DOEP_INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */ 2914 #define _USB_DOEP_INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */ 2915 #define _USB_DOEP_INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ 2916 #define USB_DOEP_INT_PKTDRPSTS_DEFAULT (_USB_DOEP_INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DOEP_INT */ 2917 #define USB_DOEP_INT_BBLEERR (0x1UL << 12) /**< Babble Error */ 2918 #define _USB_DOEP_INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */ 2919 #define _USB_DOEP_INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */ 2920 #define _USB_DOEP_INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ 2921 #define USB_DOEP_INT_BBLEERR_DEFAULT (_USB_DOEP_INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEP_INT */ 2922 #define USB_DOEP_INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */ 2923 #define _USB_DOEP_INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */ 2924 #define _USB_DOEP_INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */ 2925 #define _USB_DOEP_INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ 2926 #define USB_DOEP_INT_NAKINTRPT_DEFAULT (_USB_DOEP_INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEP_INT */ 2927 #define USB_DOEP_INT_STUPPKTRCVD (0x1UL << 15) /**< */ 2928 #define _USB_DOEP_INT_STUPPKTRCVD_SHIFT 15 /**< Shift value for USB_STUPPKTRCVD */ 2929 #define _USB_DOEP_INT_STUPPKTRCVD_MASK 0x8000UL /**< Bit mask for USB_STUPPKTRCVD */ 2930 #define _USB_DOEP_INT_STUPPKTRCVD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ 2931 #define USB_DOEP_INT_STUPPKTRCVD_DEFAULT (_USB_DOEP_INT_STUPPKTRCVD_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP_INT */ 2932 2933 /* Bit fields for USB DOEP_TSIZ */ 2934 #define _USB_DOEP_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_TSIZ */ 2935 #define _USB_DOEP_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_DOEP_TSIZ */ 2936 #define _USB_DOEP_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ 2937 #define _USB_DOEP_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */ 2938 #define _USB_DOEP_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */ 2939 #define USB_DOEP_TSIZ_XFERSIZE_DEFAULT (_USB_DOEP_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */ 2940 #define _USB_DOEP_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ 2941 #define _USB_DOEP_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */ 2942 #define _USB_DOEP_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */ 2943 #define USB_DOEP_TSIZ_PKTCNT_DEFAULT (_USB_DOEP_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */ 2944 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_SHIFT 29 /**< Shift value for USB_RXDPIDSUPCNT */ 2945 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_MASK 0x60000000UL /**< Bit mask for USB_RXDPIDSUPCNT */ 2946 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */ 2947 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 0x00000000UL /**< Mode DATA0 for USB_DOEP_TSIZ */ 2948 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 0x00000001UL /**< Mode DATA2 for USB_DOEP_TSIZ */ 2949 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 0x00000002UL /**< Mode DATA1 for USB_DOEP_TSIZ */ 2950 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA 0x00000003UL /**< Mode MDATA for USB_DOEP_TSIZ */ 2951 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */ 2952 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 << 29) /**< Shifted mode DATA0 for USB_DOEP_TSIZ */ 2953 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 << 29) /**< Shifted mode DATA2 for USB_DOEP_TSIZ */ 2954 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 << 29) /**< Shifted mode DATA1 for USB_DOEP_TSIZ */ 2955 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA (_USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA << 29) /**< Shifted mode MDATA for USB_DOEP_TSIZ */ 2956 2957 /* Bit fields for USB DOEP_DMAADDR */ 2958 #define _USB_DOEP_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_DMAADDR */ 2959 #define _USB_DOEP_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DOEP_DMAADDR */ 2960 #define _USB_DOEP_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */ 2961 #define _USB_DOEP_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */ 2962 #define _USB_DOEP_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_DMAADDR */ 2963 #define USB_DOEP_DMAADDR_DMAADDR_DEFAULT (_USB_DOEP_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_DMAADDR */ 2964 2965 /* Bit fields for USB PCGCCTL */ 2966 #define _USB_PCGCCTL_RESETVALUE 0x00000000UL /**< Default value for USB_PCGCCTL */ 2967 #define _USB_PCGCCTL_MASK 0x0000014FUL /**< Mask for USB_PCGCCTL */ 2968 #define USB_PCGCCTL_STOPPCLK (0x1UL << 0) /**< Stop PHY clock */ 2969 #define _USB_PCGCCTL_STOPPCLK_SHIFT 0 /**< Shift value for USB_STOPPCLK */ 2970 #define _USB_PCGCCTL_STOPPCLK_MASK 0x1UL /**< Bit mask for USB_STOPPCLK */ 2971 #define _USB_PCGCCTL_STOPPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ 2972 #define USB_PCGCCTL_STOPPCLK_DEFAULT (_USB_PCGCCTL_STOPPCLK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_PCGCCTL */ 2973 #define USB_PCGCCTL_GATEHCLK (0x1UL << 1) /**< Gate HCLK */ 2974 #define _USB_PCGCCTL_GATEHCLK_SHIFT 1 /**< Shift value for USB_GATEHCLK */ 2975 #define _USB_PCGCCTL_GATEHCLK_MASK 0x2UL /**< Bit mask for USB_GATEHCLK */ 2976 #define _USB_PCGCCTL_GATEHCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ 2977 #define USB_PCGCCTL_GATEHCLK_DEFAULT (_USB_PCGCCTL_GATEHCLK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_PCGCCTL */ 2978 #define USB_PCGCCTL_PWRCLMP (0x1UL << 2) /**< Power Clamp */ 2979 #define _USB_PCGCCTL_PWRCLMP_SHIFT 2 /**< Shift value for USB_PWRCLMP */ 2980 #define _USB_PCGCCTL_PWRCLMP_MASK 0x4UL /**< Bit mask for USB_PWRCLMP */ 2981 #define _USB_PCGCCTL_PWRCLMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ 2982 #define USB_PCGCCTL_PWRCLMP_DEFAULT (_USB_PCGCCTL_PWRCLMP_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_PCGCCTL */ 2983 #define USB_PCGCCTL_RSTPDWNMODULE (0x1UL << 3) /**< Reset Power-Down Modules */ 2984 #define _USB_PCGCCTL_RSTPDWNMODULE_SHIFT 3 /**< Shift value for USB_RSTPDWNMODULE */ 2985 #define _USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8UL /**< Bit mask for USB_RSTPDWNMODULE */ 2986 #define _USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ 2987 #define USB_PCGCCTL_RSTPDWNMODULE_DEFAULT (_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_PCGCCTL */ 2988 #define USB_PCGCCTL_PHYSLEEP (0x1UL << 6) /**< PHY In Sleep */ 2989 #define _USB_PCGCCTL_PHYSLEEP_SHIFT 6 /**< Shift value for USB_PHYSLEEP */ 2990 #define _USB_PCGCCTL_PHYSLEEP_MASK 0x40UL /**< Bit mask for USB_PHYSLEEP */ 2991 #define _USB_PCGCCTL_PHYSLEEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ 2992 #define USB_PCGCCTL_PHYSLEEP_DEFAULT (_USB_PCGCCTL_PHYSLEEP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_PCGCCTL */ 2993 #define USB_PCGCCTL_RESETAFTERSUSP (0x1UL << 8) /**< Reset after suspend */ 2994 #define _USB_PCGCCTL_RESETAFTERSUSP_SHIFT 8 /**< Shift value for USB_RESETAFTERSUSP */ 2995 #define _USB_PCGCCTL_RESETAFTERSUSP_MASK 0x100UL /**< Bit mask for USB_RESETAFTERSUSP */ 2996 #define _USB_PCGCCTL_RESETAFTERSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ 2997 #define USB_PCGCCTL_RESETAFTERSUSP_DEFAULT (_USB_PCGCCTL_RESETAFTERSUSP_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_PCGCCTL */ 2998 2999 /* Bit fields for USB FIFO0D */ 3000 #define _USB_FIFO0D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO0D */ 3001 #define _USB_FIFO0D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO0D */ 3002 #define _USB_FIFO0D_FIFO0D_SHIFT 0 /**< Shift value for USB_FIFO0D */ 3003 #define _USB_FIFO0D_FIFO0D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO0D */ 3004 #define _USB_FIFO0D_FIFO0D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO0D */ 3005 #define USB_FIFO0D_FIFO0D_DEFAULT (_USB_FIFO0D_FIFO0D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO0D */ 3006 3007 /* Bit fields for USB FIFO1D */ 3008 #define _USB_FIFO1D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO1D */ 3009 #define _USB_FIFO1D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO1D */ 3010 #define _USB_FIFO1D_FIFO1D_SHIFT 0 /**< Shift value for USB_FIFO1D */ 3011 #define _USB_FIFO1D_FIFO1D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO1D */ 3012 #define _USB_FIFO1D_FIFO1D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO1D */ 3013 #define USB_FIFO1D_FIFO1D_DEFAULT (_USB_FIFO1D_FIFO1D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO1D */ 3014 3015 /* Bit fields for USB FIFO2D */ 3016 #define _USB_FIFO2D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO2D */ 3017 #define _USB_FIFO2D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO2D */ 3018 #define _USB_FIFO2D_FIFO2D_SHIFT 0 /**< Shift value for USB_FIFO2D */ 3019 #define _USB_FIFO2D_FIFO2D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO2D */ 3020 #define _USB_FIFO2D_FIFO2D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO2D */ 3021 #define USB_FIFO2D_FIFO2D_DEFAULT (_USB_FIFO2D_FIFO2D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO2D */ 3022 3023 /* Bit fields for USB FIFO3D */ 3024 #define _USB_FIFO3D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO3D */ 3025 #define _USB_FIFO3D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO3D */ 3026 #define _USB_FIFO3D_FIFO3D_SHIFT 0 /**< Shift value for USB_FIFO3D */ 3027 #define _USB_FIFO3D_FIFO3D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO3D */ 3028 #define _USB_FIFO3D_FIFO3D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO3D */ 3029 #define USB_FIFO3D_FIFO3D_DEFAULT (_USB_FIFO3D_FIFO3D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO3D */ 3030 3031 /* Bit fields for USB FIFO4D */ 3032 #define _USB_FIFO4D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO4D */ 3033 #define _USB_FIFO4D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO4D */ 3034 #define _USB_FIFO4D_FIFO4D_SHIFT 0 /**< Shift value for USB_FIFO4D */ 3035 #define _USB_FIFO4D_FIFO4D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO4D */ 3036 #define _USB_FIFO4D_FIFO4D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO4D */ 3037 #define USB_FIFO4D_FIFO4D_DEFAULT (_USB_FIFO4D_FIFO4D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO4D */ 3038 3039 /* Bit fields for USB FIFO5D */ 3040 #define _USB_FIFO5D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO5D */ 3041 #define _USB_FIFO5D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO5D */ 3042 #define _USB_FIFO5D_FIFO5D_SHIFT 0 /**< Shift value for USB_FIFO5D */ 3043 #define _USB_FIFO5D_FIFO5D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO5D */ 3044 #define _USB_FIFO5D_FIFO5D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO5D */ 3045 #define USB_FIFO5D_FIFO5D_DEFAULT (_USB_FIFO5D_FIFO5D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO5D */ 3046 3047 /* Bit fields for USB FIFO6D */ 3048 #define _USB_FIFO6D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO6D */ 3049 #define _USB_FIFO6D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO6D */ 3050 #define _USB_FIFO6D_FIFO6D_SHIFT 0 /**< Shift value for USB_FIFO6D */ 3051 #define _USB_FIFO6D_FIFO6D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO6D */ 3052 #define _USB_FIFO6D_FIFO6D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO6D */ 3053 #define USB_FIFO6D_FIFO6D_DEFAULT (_USB_FIFO6D_FIFO6D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO6D */ 3054 3055 /* Bit fields for USB FIFO7D */ 3056 #define _USB_FIFO7D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO7D */ 3057 #define _USB_FIFO7D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO7D */ 3058 #define _USB_FIFO7D_FIFO7D_SHIFT 0 /**< Shift value for USB_FIFO7D */ 3059 #define _USB_FIFO7D_FIFO7D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO7D */ 3060 #define _USB_FIFO7D_FIFO7D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO7D */ 3061 #define USB_FIFO7D_FIFO7D_DEFAULT (_USB_FIFO7D_FIFO7D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO7D */ 3062 3063 /* Bit fields for USB FIFO8D */ 3064 #define _USB_FIFO8D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO8D */ 3065 #define _USB_FIFO8D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO8D */ 3066 #define _USB_FIFO8D_FIFO8D_SHIFT 0 /**< Shift value for USB_FIFO8D */ 3067 #define _USB_FIFO8D_FIFO8D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO8D */ 3068 #define _USB_FIFO8D_FIFO8D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO8D */ 3069 #define USB_FIFO8D_FIFO8D_DEFAULT (_USB_FIFO8D_FIFO8D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO8D */ 3070 3071 /* Bit fields for USB FIFO9D */ 3072 #define _USB_FIFO9D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO9D */ 3073 #define _USB_FIFO9D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO9D */ 3074 #define _USB_FIFO9D_FIFO9D_SHIFT 0 /**< Shift value for USB_FIFO9D */ 3075 #define _USB_FIFO9D_FIFO9D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO9D */ 3076 #define _USB_FIFO9D_FIFO9D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO9D */ 3077 #define USB_FIFO9D_FIFO9D_DEFAULT (_USB_FIFO9D_FIFO9D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO9D */ 3078 3079 /* Bit fields for USB FIFO10D */ 3080 #define _USB_FIFO10D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO10D */ 3081 #define _USB_FIFO10D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO10D */ 3082 #define _USB_FIFO10D_FIFO10D_SHIFT 0 /**< Shift value for USB_FIFO10D */ 3083 #define _USB_FIFO10D_FIFO10D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO10D */ 3084 #define _USB_FIFO10D_FIFO10D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO10D */ 3085 #define USB_FIFO10D_FIFO10D_DEFAULT (_USB_FIFO10D_FIFO10D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO10D */ 3086 3087 /* Bit fields for USB FIFO11D */ 3088 #define _USB_FIFO11D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO11D */ 3089 #define _USB_FIFO11D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO11D */ 3090 #define _USB_FIFO11D_FIFO11D_SHIFT 0 /**< Shift value for USB_FIFO11D */ 3091 #define _USB_FIFO11D_FIFO11D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO11D */ 3092 #define _USB_FIFO11D_FIFO11D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO11D */ 3093 #define USB_FIFO11D_FIFO11D_DEFAULT (_USB_FIFO11D_FIFO11D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO11D */ 3094 3095 /* Bit fields for USB FIFO12D */ 3096 #define _USB_FIFO12D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO12D */ 3097 #define _USB_FIFO12D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO12D */ 3098 #define _USB_FIFO12D_FIFO12D_SHIFT 0 /**< Shift value for USB_FIFO12D */ 3099 #define _USB_FIFO12D_FIFO12D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO12D */ 3100 #define _USB_FIFO12D_FIFO12D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO12D */ 3101 #define USB_FIFO12D_FIFO12D_DEFAULT (_USB_FIFO12D_FIFO12D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO12D */ 3102 3103 /* Bit fields for USB FIFO13D */ 3104 #define _USB_FIFO13D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO13D */ 3105 #define _USB_FIFO13D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO13D */ 3106 #define _USB_FIFO13D_FIFO13D_SHIFT 0 /**< Shift value for USB_FIFO13D */ 3107 #define _USB_FIFO13D_FIFO13D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO13D */ 3108 #define _USB_FIFO13D_FIFO13D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO13D */ 3109 #define USB_FIFO13D_FIFO13D_DEFAULT (_USB_FIFO13D_FIFO13D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO13D */ 3110 3111 /* Bit fields for USB FIFORAM */ 3112 #define _USB_FIFORAM_RESETVALUE 0x00000000UL /**< Default value for USB_FIFORAM */ 3113 #define _USB_FIFORAM_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFORAM */ 3114 #define _USB_FIFORAM_FIFORAM_SHIFT 0 /**< Shift value for USB_FIFORAM */ 3115 #define _USB_FIFORAM_FIFORAM_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFORAM */ 3116 #define _USB_FIFORAM_FIFORAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFORAM */ 3117 #define USB_FIFORAM_FIFORAM_DEFAULT (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */ 3118 3119 /** @} */ 3120 /** @} End of group EFM32GG12B_USB */ 3121 /** @} End of group Parts */ 3122
