1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG12B_UART register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 42 /***************************************************************************//** 43 * @addtogroup EFM32GG12B_UART 44 * @{ 45 * @defgroup EFM32GG12B_UART_BitFields UART Bit Fields 46 * @{ 47 ******************************************************************************/ 48 49 /* Bit fields for UART CTRL */ 50 #define _UART_CTRL_RESETVALUE 0x00000000UL /**< Default value for UART_CTRL */ 51 #define _UART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for UART_CTRL */ 52 #define UART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ 53 #define _UART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ 54 #define _UART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ 55 #define _UART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 56 #define UART_CTRL_SYNC_DEFAULT (_UART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CTRL */ 57 #define UART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ 58 #define _UART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ 59 #define _UART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ 60 #define _UART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 61 #define UART_CTRL_LOOPBK_DEFAULT (_UART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CTRL */ 62 #define UART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ 63 #define _UART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ 64 #define _UART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ 65 #define _UART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 66 #define UART_CTRL_CCEN_DEFAULT (_UART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CTRL */ 67 #define UART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ 68 #define _UART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ 69 #define _UART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ 70 #define _UART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 71 #define UART_CTRL_MPM_DEFAULT (_UART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CTRL */ 72 #define UART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ 73 #define _UART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ 74 #define _UART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ 75 #define _UART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 76 #define UART_CTRL_MPAB_DEFAULT (_UART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_CTRL */ 77 #define _UART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ 78 #define _UART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ 79 #define _UART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 80 #define _UART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for UART_CTRL */ 81 #define _UART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for UART_CTRL */ 82 #define _UART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for UART_CTRL */ 83 #define _UART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for UART_CTRL */ 84 #define UART_CTRL_OVS_DEFAULT (_UART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_CTRL */ 85 #define UART_CTRL_OVS_X16 (_UART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for UART_CTRL */ 86 #define UART_CTRL_OVS_X8 (_UART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for UART_CTRL */ 87 #define UART_CTRL_OVS_X6 (_UART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for UART_CTRL */ 88 #define UART_CTRL_OVS_X4 (_UART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for UART_CTRL */ 89 #define UART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ 90 #define _UART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ 91 #define _UART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ 92 #define _UART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 93 #define _UART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for UART_CTRL */ 94 #define _UART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for UART_CTRL */ 95 #define UART_CTRL_CLKPOL_DEFAULT (_UART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_CTRL */ 96 #define UART_CTRL_CLKPOL_IDLELOW (_UART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for UART_CTRL */ 97 #define UART_CTRL_CLKPOL_IDLEHIGH (_UART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for UART_CTRL */ 98 #define UART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge for Setup/Sample */ 99 #define _UART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ 100 #define _UART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ 101 #define _UART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 102 #define _UART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for UART_CTRL */ 103 #define _UART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for UART_CTRL */ 104 #define UART_CTRL_CLKPHA_DEFAULT (_UART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_CTRL */ 105 #define UART_CTRL_CLKPHA_SAMPLELEADING (_UART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for UART_CTRL */ 106 #define UART_CTRL_CLKPHA_SAMPLETRAILING (_UART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for UART_CTRL */ 107 #define UART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ 108 #define _UART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ 109 #define _UART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ 110 #define _UART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 111 #define UART_CTRL_MSBF_DEFAULT (_UART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_CTRL */ 112 #define UART_CTRL_CSMA (0x1UL << 11) /**< Action on Slave-Select in Master Mode */ 113 #define _UART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ 114 #define _UART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ 115 #define _UART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 116 #define _UART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for UART_CTRL */ 117 #define _UART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for UART_CTRL */ 118 #define UART_CTRL_CSMA_DEFAULT (_UART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_CTRL */ 119 #define UART_CTRL_CSMA_NOACTION (_UART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for UART_CTRL */ 120 #define UART_CTRL_CSMA_GOTOSLAVEMODE (_UART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for UART_CTRL */ 121 #define UART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ 122 #define _UART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ 123 #define _UART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ 124 #define _UART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 125 #define _UART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for UART_CTRL */ 126 #define _UART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for UART_CTRL */ 127 #define UART_CTRL_TXBIL_DEFAULT (_UART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_CTRL */ 128 #define UART_CTRL_TXBIL_EMPTY (_UART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for UART_CTRL */ 129 #define UART_CTRL_TXBIL_HALFFULL (_UART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for UART_CTRL */ 130 #define UART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ 131 #define _UART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ 132 #define _UART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ 133 #define _UART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 134 #define UART_CTRL_RXINV_DEFAULT (_UART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_CTRL */ 135 #define UART_CTRL_TXINV (0x1UL << 14) /**< Transmitter Output Invert */ 136 #define _UART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ 137 #define _UART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ 138 #define _UART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 139 #define UART_CTRL_TXINV_DEFAULT (_UART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_CTRL */ 140 #define UART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ 141 #define _UART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ 142 #define _UART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ 143 #define _UART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 144 #define UART_CTRL_CSINV_DEFAULT (_UART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_CTRL */ 145 #define UART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ 146 #define _UART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ 147 #define _UART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ 148 #define _UART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 149 #define UART_CTRL_AUTOCS_DEFAULT (_UART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_CTRL */ 150 #define UART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ 151 #define _UART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ 152 #define _UART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ 153 #define _UART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 154 #define UART_CTRL_AUTOTRI_DEFAULT (_UART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for UART_CTRL */ 155 #define UART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ 156 #define _UART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ 157 #define _UART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ 158 #define _UART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 159 #define UART_CTRL_SCMODE_DEFAULT (_UART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for UART_CTRL */ 160 #define UART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ 161 #define _UART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ 162 #define _UART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ 163 #define _UART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 164 #define UART_CTRL_SCRETRANS_DEFAULT (_UART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for UART_CTRL */ 165 #define UART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ 166 #define _UART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ 167 #define _UART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ 168 #define _UART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 169 #define UART_CTRL_SKIPPERRF_DEFAULT (_UART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_CTRL */ 170 #define UART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ 171 #define _UART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ 172 #define _UART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ 173 #define _UART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 174 #define UART_CTRL_BIT8DV_DEFAULT (_UART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for UART_CTRL */ 175 #define UART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA on Error */ 176 #define _UART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ 177 #define _UART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ 178 #define _UART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 179 #define UART_CTRL_ERRSDMA_DEFAULT (_UART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for UART_CTRL */ 180 #define UART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX on Error */ 181 #define _UART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ 182 #define _UART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ 183 #define _UART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 184 #define UART_CTRL_ERRSRX_DEFAULT (_UART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for UART_CTRL */ 185 #define UART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX on Error */ 186 #define _UART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ 187 #define _UART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ 188 #define _UART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 189 #define UART_CTRL_ERRSTX_DEFAULT (_UART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_CTRL */ 190 #define UART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */ 191 #define _UART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ 192 #define _UART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ 193 #define _UART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 194 #define UART_CTRL_SSSEARLY_DEFAULT (_UART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for UART_CTRL */ 195 #define UART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap in Double Accesses */ 196 #define _UART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ 197 #define _UART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ 198 #define _UART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 199 #define UART_CTRL_BYTESWAP_DEFAULT (_UART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_CTRL */ 200 #define UART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ 201 #define _UART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ 202 #define _UART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ 203 #define _UART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 204 #define UART_CTRL_AUTOTX_DEFAULT (_UART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for UART_CTRL */ 205 #define UART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ 206 #define _UART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ 207 #define _UART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ 208 #define _UART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 209 #define UART_CTRL_MVDIS_DEFAULT (_UART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_CTRL */ 210 #define UART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */ 211 #define _UART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ 212 #define _UART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ 213 #define _UART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ 214 #define UART_CTRL_SMSDELAY_DEFAULT (_UART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_CTRL */ 215 216 /* Bit fields for UART FRAME */ 217 #define _UART_FRAME_RESETVALUE 0x00001005UL /**< Default value for UART_FRAME */ 218 #define _UART_FRAME_MASK 0x0000330FUL /**< Mask for UART_FRAME */ 219 #define _UART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ 220 #define _UART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ 221 #define _UART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for UART_FRAME */ 222 #define _UART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for UART_FRAME */ 223 #define _UART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for UART_FRAME */ 224 #define _UART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for UART_FRAME */ 225 #define _UART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for UART_FRAME */ 226 #define _UART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for UART_FRAME */ 227 #define _UART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for UART_FRAME */ 228 #define _UART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for UART_FRAME */ 229 #define _UART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for UART_FRAME */ 230 #define _UART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for UART_FRAME */ 231 #define _UART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for UART_FRAME */ 232 #define _UART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for UART_FRAME */ 233 #define _UART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for UART_FRAME */ 234 #define _UART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for UART_FRAME */ 235 #define UART_FRAME_DATABITS_FOUR (_UART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for UART_FRAME */ 236 #define UART_FRAME_DATABITS_FIVE (_UART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for UART_FRAME */ 237 #define UART_FRAME_DATABITS_SIX (_UART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for UART_FRAME */ 238 #define UART_FRAME_DATABITS_SEVEN (_UART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for UART_FRAME */ 239 #define UART_FRAME_DATABITS_DEFAULT (_UART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_FRAME */ 240 #define UART_FRAME_DATABITS_EIGHT (_UART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for UART_FRAME */ 241 #define UART_FRAME_DATABITS_NINE (_UART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for UART_FRAME */ 242 #define UART_FRAME_DATABITS_TEN (_UART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for UART_FRAME */ 243 #define UART_FRAME_DATABITS_ELEVEN (_UART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for UART_FRAME */ 244 #define UART_FRAME_DATABITS_TWELVE (_UART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for UART_FRAME */ 245 #define UART_FRAME_DATABITS_THIRTEEN (_UART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for UART_FRAME */ 246 #define UART_FRAME_DATABITS_FOURTEEN (_UART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for UART_FRAME */ 247 #define UART_FRAME_DATABITS_FIFTEEN (_UART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for UART_FRAME */ 248 #define UART_FRAME_DATABITS_SIXTEEN (_UART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for UART_FRAME */ 249 #define _UART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ 250 #define _UART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ 251 #define _UART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_FRAME */ 252 #define _UART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for UART_FRAME */ 253 #define _UART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for UART_FRAME */ 254 #define _UART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for UART_FRAME */ 255 #define UART_FRAME_PARITY_DEFAULT (_UART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_FRAME */ 256 #define UART_FRAME_PARITY_NONE (_UART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for UART_FRAME */ 257 #define UART_FRAME_PARITY_EVEN (_UART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for UART_FRAME */ 258 #define UART_FRAME_PARITY_ODD (_UART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for UART_FRAME */ 259 #define _UART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ 260 #define _UART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ 261 #define _UART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for UART_FRAME */ 262 #define _UART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_FRAME */ 263 #define _UART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for UART_FRAME */ 264 #define _UART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for UART_FRAME */ 265 #define _UART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for UART_FRAME */ 266 #define UART_FRAME_STOPBITS_HALF (_UART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for UART_FRAME */ 267 #define UART_FRAME_STOPBITS_DEFAULT (_UART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_FRAME */ 268 #define UART_FRAME_STOPBITS_ONE (_UART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for UART_FRAME */ 269 #define UART_FRAME_STOPBITS_ONEANDAHALF (_UART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for UART_FRAME */ 270 #define UART_FRAME_STOPBITS_TWO (_UART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for UART_FRAME */ 271 272 /* Bit fields for UART TRIGCTRL */ 273 #define _UART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_TRIGCTRL */ 274 #define _UART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for UART_TRIGCTRL */ 275 #define UART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ 276 #define _UART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ 277 #define _UART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ 278 #define _UART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ 279 #define UART_TRIGCTRL_RXTEN_DEFAULT (_UART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ 280 #define UART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ 281 #define _UART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ 282 #define _UART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ 283 #define _UART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ 284 #define UART_TRIGCTRL_TXTEN_DEFAULT (_UART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ 285 #define UART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ 286 #define _UART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ 287 #define _UART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ 288 #define _UART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ 289 #define UART_TRIGCTRL_AUTOTXTEN_DEFAULT (_UART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ 290 #define UART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL */ 291 #define _UART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ 292 #define _UART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ 293 #define _UART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ 294 #define UART_TRIGCTRL_TXARX0EN_DEFAULT (_UART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ 295 #define UART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL */ 296 #define _UART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ 297 #define _UART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ 298 #define _UART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ 299 #define UART_TRIGCTRL_TXARX1EN_DEFAULT (_UART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ 300 #define UART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL */ 301 #define _UART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ 302 #define _UART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ 303 #define _UART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ 304 #define UART_TRIGCTRL_TXARX2EN_DEFAULT (_UART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ 305 #define UART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times */ 306 #define _UART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ 307 #define _UART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ 308 #define _UART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ 309 #define UART_TRIGCTRL_RXATX0EN_DEFAULT (_UART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ 310 #define UART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times */ 311 #define _UART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ 312 #define _UART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ 313 #define _UART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ 314 #define UART_TRIGCTRL_RXATX1EN_DEFAULT (_UART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ 315 #define UART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times */ 316 #define _UART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ 317 #define _UART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ 318 #define _UART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ 319 #define UART_TRIGCTRL_RXATX2EN_DEFAULT (_UART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ 320 #define _UART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */ 321 #define _UART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */ 322 #define _UART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ 323 #define _UART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_TRIGCTRL */ 324 #define _UART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_TRIGCTRL */ 325 #define _UART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_TRIGCTRL */ 326 #define _UART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_TRIGCTRL */ 327 #define _UART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_TRIGCTRL */ 328 #define _UART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_TRIGCTRL */ 329 #define _UART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_TRIGCTRL */ 330 #define _UART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_TRIGCTRL */ 331 #define _UART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_TRIGCTRL */ 332 #define _UART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_TRIGCTRL */ 333 #define _UART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_TRIGCTRL */ 334 #define _UART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_TRIGCTRL */ 335 #define _UART_TRIGCTRL_TSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for UART_TRIGCTRL */ 336 #define _UART_TRIGCTRL_TSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for UART_TRIGCTRL */ 337 #define _UART_TRIGCTRL_TSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for UART_TRIGCTRL */ 338 #define _UART_TRIGCTRL_TSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for UART_TRIGCTRL */ 339 #define UART_TRIGCTRL_TSEL_DEFAULT (_UART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ 340 #define UART_TRIGCTRL_TSEL_PRSCH0 (_UART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for UART_TRIGCTRL */ 341 #define UART_TRIGCTRL_TSEL_PRSCH1 (_UART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for UART_TRIGCTRL */ 342 #define UART_TRIGCTRL_TSEL_PRSCH2 (_UART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for UART_TRIGCTRL */ 343 #define UART_TRIGCTRL_TSEL_PRSCH3 (_UART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for UART_TRIGCTRL */ 344 #define UART_TRIGCTRL_TSEL_PRSCH4 (_UART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for UART_TRIGCTRL */ 345 #define UART_TRIGCTRL_TSEL_PRSCH5 (_UART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for UART_TRIGCTRL */ 346 #define UART_TRIGCTRL_TSEL_PRSCH6 (_UART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for UART_TRIGCTRL */ 347 #define UART_TRIGCTRL_TSEL_PRSCH7 (_UART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for UART_TRIGCTRL */ 348 #define UART_TRIGCTRL_TSEL_PRSCH8 (_UART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for UART_TRIGCTRL */ 349 #define UART_TRIGCTRL_TSEL_PRSCH9 (_UART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for UART_TRIGCTRL */ 350 #define UART_TRIGCTRL_TSEL_PRSCH10 (_UART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for UART_TRIGCTRL */ 351 #define UART_TRIGCTRL_TSEL_PRSCH11 (_UART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for UART_TRIGCTRL */ 352 #define UART_TRIGCTRL_TSEL_PRSCH12 (_UART_TRIGCTRL_TSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for UART_TRIGCTRL */ 353 #define UART_TRIGCTRL_TSEL_PRSCH13 (_UART_TRIGCTRL_TSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for UART_TRIGCTRL */ 354 #define UART_TRIGCTRL_TSEL_PRSCH14 (_UART_TRIGCTRL_TSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for UART_TRIGCTRL */ 355 #define UART_TRIGCTRL_TSEL_PRSCH15 (_UART_TRIGCTRL_TSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for UART_TRIGCTRL */ 356 357 /* Bit fields for UART CMD */ 358 #define _UART_CMD_RESETVALUE 0x00000000UL /**< Default value for UART_CMD */ 359 #define _UART_CMD_MASK 0x00000FFFUL /**< Mask for UART_CMD */ 360 #define UART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ 361 #define _UART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ 362 #define _UART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ 363 #define _UART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ 364 #define UART_CMD_RXEN_DEFAULT (_UART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CMD */ 365 #define UART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ 366 #define _UART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ 367 #define _UART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ 368 #define _UART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ 369 #define UART_CMD_RXDIS_DEFAULT (_UART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CMD */ 370 #define UART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ 371 #define _UART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ 372 #define _UART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ 373 #define _UART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ 374 #define UART_CMD_TXEN_DEFAULT (_UART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CMD */ 375 #define UART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ 376 #define _UART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ 377 #define _UART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ 378 #define _UART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ 379 #define UART_CMD_TXDIS_DEFAULT (_UART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CMD */ 380 #define UART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */ 381 #define _UART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ 382 #define _UART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ 383 #define _UART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ 384 #define UART_CMD_MASTEREN_DEFAULT (_UART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_CMD */ 385 #define UART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */ 386 #define _UART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ 387 #define _UART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ 388 #define _UART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ 389 #define UART_CMD_MASTERDIS_DEFAULT (_UART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_CMD */ 390 #define UART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ 391 #define _UART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ 392 #define _UART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ 393 #define _UART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ 394 #define UART_CMD_RXBLOCKEN_DEFAULT (_UART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_CMD */ 395 #define UART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ 396 #define _UART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ 397 #define _UART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ 398 #define _UART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ 399 #define UART_CMD_RXBLOCKDIS_DEFAULT (_UART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_CMD */ 400 #define UART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ 401 #define _UART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ 402 #define _UART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ 403 #define _UART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ 404 #define UART_CMD_TXTRIEN_DEFAULT (_UART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_CMD */ 405 #define UART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ 406 #define _UART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ 407 #define _UART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ 408 #define _UART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ 409 #define UART_CMD_TXTRIDIS_DEFAULT (_UART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_CMD */ 410 #define UART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ 411 #define _UART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ 412 #define _UART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ 413 #define _UART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ 414 #define UART_CMD_CLEARTX_DEFAULT (_UART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_CMD */ 415 #define UART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ 416 #define _UART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ 417 #define _UART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ 418 #define _UART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ 419 #define UART_CMD_CLEARRX_DEFAULT (_UART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_CMD */ 420 421 /* Bit fields for UART STATUS */ 422 #define _UART_STATUS_RESETVALUE 0x00002040UL /**< Default value for UART_STATUS */ 423 #define _UART_STATUS_MASK 0x00037FFFUL /**< Mask for UART_STATUS */ 424 #define UART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ 425 #define _UART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ 426 #define _UART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ 427 #define _UART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 428 #define UART_STATUS_RXENS_DEFAULT (_UART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_STATUS */ 429 #define UART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ 430 #define _UART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ 431 #define _UART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ 432 #define _UART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 433 #define UART_STATUS_TXENS_DEFAULT (_UART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_STATUS */ 434 #define UART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */ 435 #define _UART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ 436 #define _UART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ 437 #define _UART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 438 #define UART_STATUS_MASTER_DEFAULT (_UART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_STATUS */ 439 #define UART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ 440 #define _UART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ 441 #define _UART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ 442 #define _UART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 443 #define UART_STATUS_RXBLOCK_DEFAULT (_UART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_STATUS */ 444 #define UART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ 445 #define _UART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ 446 #define _UART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ 447 #define _UART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 448 #define UART_STATUS_TXTRI_DEFAULT (_UART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_STATUS */ 449 #define UART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ 450 #define _UART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ 451 #define _UART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ 452 #define _UART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 453 #define UART_STATUS_TXC_DEFAULT (_UART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_STATUS */ 454 #define UART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ 455 #define _UART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ 456 #define _UART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ 457 #define _UART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_STATUS */ 458 #define UART_STATUS_TXBL_DEFAULT (_UART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_STATUS */ 459 #define UART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ 460 #define _UART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ 461 #define _UART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ 462 #define _UART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 463 #define UART_STATUS_RXDATAV_DEFAULT (_UART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_STATUS */ 464 #define UART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ 465 #define _UART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ 466 #define _UART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ 467 #define _UART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 468 #define UART_STATUS_RXFULL_DEFAULT (_UART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_STATUS */ 469 #define UART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ 470 #define _UART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ 471 #define _UART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ 472 #define _UART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 473 #define UART_STATUS_TXBDRIGHT_DEFAULT (_UART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_STATUS */ 474 #define UART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ 475 #define _UART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ 476 #define _UART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ 477 #define _UART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 478 #define UART_STATUS_TXBSRIGHT_DEFAULT (_UART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_STATUS */ 479 #define UART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ 480 #define _UART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ 481 #define _UART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ 482 #define _UART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 483 #define UART_STATUS_RXDATAVRIGHT_DEFAULT (_UART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_STATUS */ 484 #define UART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ 485 #define _UART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ 486 #define _UART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ 487 #define _UART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 488 #define UART_STATUS_RXFULLRIGHT_DEFAULT (_UART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_STATUS */ 489 #define UART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ 490 #define _UART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ 491 #define _UART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ 492 #define _UART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_STATUS */ 493 #define UART_STATUS_TXIDLE_DEFAULT (_UART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_STATUS */ 494 #define UART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer Restarted Itself */ 495 #define _UART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ 496 #define _UART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ 497 #define _UART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 498 #define UART_STATUS_TIMERRESTARTED_DEFAULT (_UART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_STATUS */ 499 #define _UART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ 500 #define _UART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ 501 #define _UART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ 502 #define UART_STATUS_TXBUFCNT_DEFAULT (_UART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_STATUS */ 503 504 /* Bit fields for UART CLKDIV */ 505 #define _UART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for UART_CLKDIV */ 506 #define _UART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for UART_CLKDIV */ 507 #define _UART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ 508 #define _UART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ 509 #define _UART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CLKDIV */ 510 #define UART_CLKDIV_DIV_DEFAULT (_UART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CLKDIV */ 511 #define UART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD Detection Enable */ 512 #define _UART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ 513 #define _UART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ 514 #define _UART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CLKDIV */ 515 #define UART_CLKDIV_AUTOBAUDEN_DEFAULT (_UART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_CLKDIV */ 516 517 /* Bit fields for UART RXDATAX */ 518 #define _UART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAX */ 519 #define _UART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAX */ 520 #define _UART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ 521 #define _UART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ 522 #define _UART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */ 523 #define UART_RXDATAX_RXDATA_DEFAULT (_UART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATAX */ 524 #define UART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ 525 #define _UART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ 526 #define _UART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ 527 #define _UART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */ 528 #define UART_RXDATAX_PERR_DEFAULT (_UART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDATAX */ 529 #define UART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ 530 #define _UART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ 531 #define _UART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ 532 #define _UART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */ 533 #define UART_RXDATAX_FERR_DEFAULT (_UART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDATAX */ 534 535 /* Bit fields for UART RXDATA */ 536 #define _UART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATA */ 537 #define _UART_RXDATA_MASK 0x000000FFUL /**< Mask for UART_RXDATA */ 538 #define _UART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ 539 #define _UART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ 540 #define _UART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATA */ 541 #define UART_RXDATA_RXDATA_DEFAULT (_UART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATA */ 542 543 /* Bit fields for UART RXDOUBLEX */ 544 #define _UART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEX */ 545 #define _UART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEX */ 546 #define _UART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ 547 #define _UART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ 548 #define _UART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ 549 #define UART_RXDOUBLEX_RXDATA0_DEFAULT (_UART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ 550 #define UART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ 551 #define _UART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ 552 #define _UART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ 553 #define _UART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ 554 #define UART_RXDOUBLEX_PERR0_DEFAULT (_UART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ 555 #define UART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ 556 #define _UART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ 557 #define _UART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ 558 #define _UART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ 559 #define UART_RXDOUBLEX_FERR0_DEFAULT (_UART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ 560 #define _UART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ 561 #define _UART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ 562 #define _UART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ 563 #define UART_RXDOUBLEX_RXDATA1_DEFAULT (_UART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ 564 #define UART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ 565 #define _UART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ 566 #define _UART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ 567 #define _UART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ 568 #define UART_RXDOUBLEX_PERR1_DEFAULT (_UART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ 569 #define UART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ 570 #define _UART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ 571 #define _UART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ 572 #define _UART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ 573 #define UART_RXDOUBLEX_FERR1_DEFAULT (_UART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ 574 575 /* Bit fields for UART RXDOUBLE */ 576 #define _UART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLE */ 577 #define _UART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_RXDOUBLE */ 578 #define _UART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ 579 #define _UART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ 580 #define _UART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */ 581 #define UART_RXDOUBLE_RXDATA0_DEFAULT (_UART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLE */ 582 #define _UART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ 583 #define _UART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ 584 #define _UART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */ 585 #define UART_RXDOUBLE_RXDATA1_DEFAULT (_UART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_RXDOUBLE */ 586 587 /* Bit fields for UART RXDATAXP */ 588 #define _UART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAXP */ 589 #define _UART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAXP */ 590 #define _UART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ 591 #define _UART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ 592 #define _UART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */ 593 #define UART_RXDATAXP_RXDATAP_DEFAULT (_UART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATAXP */ 594 #define UART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ 595 #define _UART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ 596 #define _UART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ 597 #define _UART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */ 598 #define UART_RXDATAXP_PERRP_DEFAULT (_UART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDATAXP */ 599 #define UART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ 600 #define _UART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ 601 #define _UART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ 602 #define _UART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */ 603 #define UART_RXDATAXP_FERRP_DEFAULT (_UART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDATAXP */ 604 605 /* Bit fields for UART RXDOUBLEXP */ 606 #define _UART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEXP */ 607 #define _UART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEXP */ 608 #define _UART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ 609 #define _UART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ 610 #define _UART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ 611 #define UART_RXDOUBLEXP_RXDATAP0_DEFAULT (_UART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ 612 #define UART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ 613 #define _UART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ 614 #define _UART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ 615 #define _UART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ 616 #define UART_RXDOUBLEXP_PERRP0_DEFAULT (_UART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ 617 #define UART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ 618 #define _UART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ 619 #define _UART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ 620 #define _UART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ 621 #define UART_RXDOUBLEXP_FERRP0_DEFAULT (_UART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ 622 #define _UART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ 623 #define _UART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ 624 #define _UART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ 625 #define UART_RXDOUBLEXP_RXDATAP1_DEFAULT (_UART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ 626 #define UART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ 627 #define _UART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ 628 #define _UART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ 629 #define _UART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ 630 #define UART_RXDOUBLEXP_PERRP1_DEFAULT (_UART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ 631 #define UART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ 632 #define _UART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ 633 #define _UART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ 634 #define _UART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ 635 #define UART_RXDOUBLEXP_FERRP1_DEFAULT (_UART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ 636 637 /* Bit fields for UART TXDATAX */ 638 #define _UART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATAX */ 639 #define _UART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for UART_TXDATAX */ 640 #define _UART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ 641 #define _UART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ 642 #define _UART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ 643 #define UART_TXDATAX_TXDATAX_DEFAULT (_UART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDATAX */ 644 #define UART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ 645 #define _UART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ 646 #define _UART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ 647 #define _UART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ 648 #define UART_TXDATAX_UBRXAT_DEFAULT (_UART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TXDATAX */ 649 #define UART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ 650 #define _UART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ 651 #define _UART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ 652 #define _UART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ 653 #define UART_TXDATAX_TXTRIAT_DEFAULT (_UART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TXDATAX */ 654 #define UART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */ 655 #define _UART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ 656 #define _UART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ 657 #define _UART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ 658 #define UART_TXDATAX_TXBREAK_DEFAULT (_UART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_TXDATAX */ 659 #define UART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ 660 #define _UART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ 661 #define _UART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ 662 #define _UART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ 663 #define UART_TXDATAX_TXDISAT_DEFAULT (_UART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_TXDATAX */ 664 #define UART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ 665 #define _UART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ 666 #define _UART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ 667 #define _UART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ 668 #define UART_TXDATAX_RXENAT_DEFAULT (_UART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_TXDATAX */ 669 670 /* Bit fields for UART TXDATA */ 671 #define _UART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATA */ 672 #define _UART_TXDATA_MASK 0x000000FFUL /**< Mask for UART_TXDATA */ 673 #define _UART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ 674 #define _UART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ 675 #define _UART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATA */ 676 #define UART_TXDATA_TXDATA_DEFAULT (_UART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDATA */ 677 678 /* Bit fields for UART TXDOUBLEX */ 679 #define _UART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLEX */ 680 #define _UART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for UART_TXDOUBLEX */ 681 #define _UART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ 682 #define _UART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ 683 #define _UART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ 684 #define UART_TXDOUBLEX_TXDATA0_DEFAULT (_UART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ 685 #define UART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ 686 #define _UART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ 687 #define _UART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ 688 #define _UART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ 689 #define UART_TXDOUBLEX_UBRXAT0_DEFAULT (_UART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ 690 #define UART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ 691 #define _UART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ 692 #define _UART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ 693 #define _UART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ 694 #define UART_TXDOUBLEX_TXTRIAT0_DEFAULT (_UART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ 695 #define UART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data as Break */ 696 #define _UART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ 697 #define _UART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ 698 #define _UART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ 699 #define UART_TXDOUBLEX_TXBREAK0_DEFAULT (_UART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ 700 #define UART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ 701 #define _UART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ 702 #define _UART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ 703 #define _UART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ 704 #define UART_TXDOUBLEX_TXDISAT0_DEFAULT (_UART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ 705 #define UART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ 706 #define _UART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ 707 #define _UART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ 708 #define _UART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ 709 #define UART_TXDOUBLEX_RXENAT0_DEFAULT (_UART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ 710 #define _UART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ 711 #define _UART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ 712 #define _UART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ 713 #define UART_TXDOUBLEX_TXDATA1_DEFAULT (_UART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ 714 #define UART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ 715 #define _UART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ 716 #define _UART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ 717 #define _UART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ 718 #define UART_TXDOUBLEX_UBRXAT1_DEFAULT (_UART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ 719 #define UART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ 720 #define _UART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ 721 #define _UART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ 722 #define _UART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ 723 #define UART_TXDOUBLEX_TXTRIAT1_DEFAULT (_UART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ 724 #define UART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data as Break */ 725 #define _UART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ 726 #define _UART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ 727 #define _UART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ 728 #define UART_TXDOUBLEX_TXBREAK1_DEFAULT (_UART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ 729 #define UART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ 730 #define _UART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ 731 #define _UART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ 732 #define _UART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ 733 #define UART_TXDOUBLEX_TXDISAT1_DEFAULT (_UART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ 734 #define UART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ 735 #define _UART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ 736 #define _UART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ 737 #define _UART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ 738 #define UART_TXDOUBLEX_RXENAT1_DEFAULT (_UART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ 739 740 /* Bit fields for UART TXDOUBLE */ 741 #define _UART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLE */ 742 #define _UART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_TXDOUBLE */ 743 #define _UART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ 744 #define _UART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ 745 #define _UART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */ 746 #define UART_TXDOUBLE_TXDATA0_DEFAULT (_UART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLE */ 747 #define _UART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ 748 #define _UART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ 749 #define _UART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */ 750 #define UART_TXDOUBLE_TXDATA1_DEFAULT (_UART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_TXDOUBLE */ 751 752 /* Bit fields for UART IF */ 753 #define _UART_IF_RESETVALUE 0x00000002UL /**< Default value for UART_IF */ 754 #define _UART_IF_MASK 0x0001FFFFUL /**< Mask for UART_IF */ 755 #define UART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ 756 #define _UART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ 757 #define _UART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ 758 #define _UART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 759 #define UART_IF_TXC_DEFAULT (_UART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IF */ 760 #define UART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ 761 #define _UART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ 762 #define _UART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ 763 #define _UART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_IF */ 764 #define UART_IF_TXBL_DEFAULT (_UART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IF */ 765 #define UART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ 766 #define _UART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ 767 #define _UART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ 768 #define _UART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 769 #define UART_IF_RXDATAV_DEFAULT (_UART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_IF */ 770 #define UART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ 771 #define _UART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ 772 #define _UART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ 773 #define _UART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 774 #define UART_IF_RXFULL_DEFAULT (_UART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IF */ 775 #define UART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ 776 #define _UART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ 777 #define _UART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ 778 #define _UART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 779 #define UART_IF_RXOF_DEFAULT (_UART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IF */ 780 #define UART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ 781 #define _UART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ 782 #define _UART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ 783 #define _UART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 784 #define UART_IF_RXUF_DEFAULT (_UART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IF */ 785 #define UART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ 786 #define _UART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ 787 #define _UART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ 788 #define _UART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 789 #define UART_IF_TXOF_DEFAULT (_UART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IF */ 790 #define UART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ 791 #define _UART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ 792 #define _UART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ 793 #define _UART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 794 #define UART_IF_TXUF_DEFAULT (_UART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IF */ 795 #define UART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ 796 #define _UART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ 797 #define _UART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ 798 #define _UART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 799 #define UART_IF_PERR_DEFAULT (_UART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IF */ 800 #define UART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ 801 #define _UART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ 802 #define _UART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ 803 #define _UART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 804 #define UART_IF_FERR_DEFAULT (_UART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IF */ 805 #define UART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */ 806 #define _UART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ 807 #define _UART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ 808 #define _UART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 809 #define UART_IF_MPAF_DEFAULT (_UART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IF */ 810 #define UART_IF_SSM (0x1UL << 11) /**< Slave-Select in Master Mode Interrupt Flag */ 811 #define _UART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ 812 #define _UART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ 813 #define _UART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 814 #define UART_IF_SSM_DEFAULT (_UART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IF */ 815 #define UART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ 816 #define _UART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ 817 #define _UART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ 818 #define _UART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 819 #define UART_IF_CCF_DEFAULT (_UART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IF */ 820 #define UART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ 821 #define _UART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ 822 #define _UART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ 823 #define _UART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 824 #define UART_IF_TXIDLE_DEFAULT (_UART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_IF */ 825 #define UART_IF_TCMP0 (0x1UL << 14) /**< Timer Comparator 0 Interrupt Flag */ 826 #define _UART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ 827 #define _UART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ 828 #define _UART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 829 #define UART_IF_TCMP0_DEFAULT (_UART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_IF */ 830 #define UART_IF_TCMP1 (0x1UL << 15) /**< Timer Comparator 1 Interrupt Flag */ 831 #define _UART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ 832 #define _UART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ 833 #define _UART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 834 #define UART_IF_TCMP1_DEFAULT (_UART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_IF */ 835 #define UART_IF_TCMP2 (0x1UL << 16) /**< Timer Comparator 2 Interrupt Flag */ 836 #define _UART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ 837 #define _UART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ 838 #define _UART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ 839 #define UART_IF_TCMP2_DEFAULT (_UART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_IF */ 840 841 /* Bit fields for UART IFS */ 842 #define _UART_IFS_RESETVALUE 0x00000000UL /**< Default value for UART_IFS */ 843 #define _UART_IFS_MASK 0x0001FFF9UL /**< Mask for UART_IFS */ 844 #define UART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ 845 #define _UART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ 846 #define _UART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ 847 #define _UART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 848 #define UART_IFS_TXC_DEFAULT (_UART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IFS */ 849 #define UART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */ 850 #define _UART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ 851 #define _UART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ 852 #define _UART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 853 #define UART_IFS_RXFULL_DEFAULT (_UART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IFS */ 854 #define UART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */ 855 #define _UART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ 856 #define _UART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ 857 #define _UART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 858 #define UART_IFS_RXOF_DEFAULT (_UART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IFS */ 859 #define UART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */ 860 #define _UART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ 861 #define _UART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ 862 #define _UART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 863 #define UART_IFS_RXUF_DEFAULT (_UART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IFS */ 864 #define UART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */ 865 #define _UART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ 866 #define _UART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ 867 #define _UART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 868 #define UART_IFS_TXOF_DEFAULT (_UART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IFS */ 869 #define UART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */ 870 #define _UART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ 871 #define _UART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ 872 #define _UART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 873 #define UART_IFS_TXUF_DEFAULT (_UART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IFS */ 874 #define UART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */ 875 #define _UART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ 876 #define _UART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ 877 #define _UART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 878 #define UART_IFS_PERR_DEFAULT (_UART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IFS */ 879 #define UART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */ 880 #define _UART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ 881 #define _UART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ 882 #define _UART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 883 #define UART_IFS_FERR_DEFAULT (_UART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IFS */ 884 #define UART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */ 885 #define _UART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ 886 #define _UART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ 887 #define _UART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 888 #define UART_IFS_MPAF_DEFAULT (_UART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IFS */ 889 #define UART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */ 890 #define _UART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ 891 #define _UART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ 892 #define _UART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 893 #define UART_IFS_SSM_DEFAULT (_UART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IFS */ 894 #define UART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */ 895 #define _UART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ 896 #define _UART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ 897 #define _UART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 898 #define UART_IFS_CCF_DEFAULT (_UART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IFS */ 899 #define UART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */ 900 #define _UART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ 901 #define _UART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ 902 #define _UART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 903 #define UART_IFS_TXIDLE_DEFAULT (_UART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_IFS */ 904 #define UART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */ 905 #define _UART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ 906 #define _UART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ 907 #define _UART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 908 #define UART_IFS_TCMP0_DEFAULT (_UART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_IFS */ 909 #define UART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */ 910 #define _UART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ 911 #define _UART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ 912 #define _UART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 913 #define UART_IFS_TCMP1_DEFAULT (_UART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_IFS */ 914 #define UART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */ 915 #define _UART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ 916 #define _UART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ 917 #define _UART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ 918 #define UART_IFS_TCMP2_DEFAULT (_UART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_IFS */ 919 920 /* Bit fields for UART IFC */ 921 #define _UART_IFC_RESETVALUE 0x00000000UL /**< Default value for UART_IFC */ 922 #define _UART_IFC_MASK 0x0001FFF9UL /**< Mask for UART_IFC */ 923 #define UART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ 924 #define _UART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ 925 #define _UART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ 926 #define _UART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 927 #define UART_IFC_TXC_DEFAULT (_UART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IFC */ 928 #define UART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */ 929 #define _UART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ 930 #define _UART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ 931 #define _UART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 932 #define UART_IFC_RXFULL_DEFAULT (_UART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IFC */ 933 #define UART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */ 934 #define _UART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ 935 #define _UART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ 936 #define _UART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 937 #define UART_IFC_RXOF_DEFAULT (_UART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IFC */ 938 #define UART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */ 939 #define _UART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ 940 #define _UART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ 941 #define _UART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 942 #define UART_IFC_RXUF_DEFAULT (_UART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IFC */ 943 #define UART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */ 944 #define _UART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ 945 #define _UART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ 946 #define _UART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 947 #define UART_IFC_TXOF_DEFAULT (_UART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IFC */ 948 #define UART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */ 949 #define _UART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ 950 #define _UART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ 951 #define _UART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 952 #define UART_IFC_TXUF_DEFAULT (_UART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IFC */ 953 #define UART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */ 954 #define _UART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ 955 #define _UART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ 956 #define _UART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 957 #define UART_IFC_PERR_DEFAULT (_UART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IFC */ 958 #define UART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */ 959 #define _UART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ 960 #define _UART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ 961 #define _UART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 962 #define UART_IFC_FERR_DEFAULT (_UART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IFC */ 963 #define UART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */ 964 #define _UART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ 965 #define _UART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ 966 #define _UART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 967 #define UART_IFC_MPAF_DEFAULT (_UART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IFC */ 968 #define UART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */ 969 #define _UART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ 970 #define _UART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ 971 #define _UART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 972 #define UART_IFC_SSM_DEFAULT (_UART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IFC */ 973 #define UART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */ 974 #define _UART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ 975 #define _UART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ 976 #define _UART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 977 #define UART_IFC_CCF_DEFAULT (_UART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IFC */ 978 #define UART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */ 979 #define _UART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ 980 #define _UART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ 981 #define _UART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 982 #define UART_IFC_TXIDLE_DEFAULT (_UART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_IFC */ 983 #define UART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */ 984 #define _UART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ 985 #define _UART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ 986 #define _UART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 987 #define UART_IFC_TCMP0_DEFAULT (_UART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_IFC */ 988 #define UART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */ 989 #define _UART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ 990 #define _UART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ 991 #define _UART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 992 #define UART_IFC_TCMP1_DEFAULT (_UART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_IFC */ 993 #define UART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */ 994 #define _UART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ 995 #define _UART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ 996 #define _UART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ 997 #define UART_IFC_TCMP2_DEFAULT (_UART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_IFC */ 998 999 /* Bit fields for UART IEN */ 1000 #define _UART_IEN_RESETVALUE 0x00000000UL /**< Default value for UART_IEN */ 1001 #define _UART_IEN_MASK 0x0001FFFFUL /**< Mask for UART_IEN */ 1002 #define UART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ 1003 #define _UART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ 1004 #define _UART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ 1005 #define _UART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1006 #define UART_IEN_TXC_DEFAULT (_UART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IEN */ 1007 #define UART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ 1008 #define _UART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ 1009 #define _UART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ 1010 #define _UART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1011 #define UART_IEN_TXBL_DEFAULT (_UART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IEN */ 1012 #define UART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ 1013 #define _UART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ 1014 #define _UART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ 1015 #define _UART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1016 #define UART_IEN_RXDATAV_DEFAULT (_UART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_IEN */ 1017 #define UART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */ 1018 #define _UART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ 1019 #define _UART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ 1020 #define _UART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1021 #define UART_IEN_RXFULL_DEFAULT (_UART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IEN */ 1022 #define UART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */ 1023 #define _UART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ 1024 #define _UART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ 1025 #define _UART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1026 #define UART_IEN_RXOF_DEFAULT (_UART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IEN */ 1027 #define UART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */ 1028 #define _UART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ 1029 #define _UART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ 1030 #define _UART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1031 #define UART_IEN_RXUF_DEFAULT (_UART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IEN */ 1032 #define UART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */ 1033 #define _UART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ 1034 #define _UART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ 1035 #define _UART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1036 #define UART_IEN_TXOF_DEFAULT (_UART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IEN */ 1037 #define UART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */ 1038 #define _UART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ 1039 #define _UART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ 1040 #define _UART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1041 #define UART_IEN_TXUF_DEFAULT (_UART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IEN */ 1042 #define UART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */ 1043 #define _UART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ 1044 #define _UART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ 1045 #define _UART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1046 #define UART_IEN_PERR_DEFAULT (_UART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IEN */ 1047 #define UART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */ 1048 #define _UART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ 1049 #define _UART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ 1050 #define _UART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1051 #define UART_IEN_FERR_DEFAULT (_UART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IEN */ 1052 #define UART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */ 1053 #define _UART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ 1054 #define _UART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ 1055 #define _UART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1056 #define UART_IEN_MPAF_DEFAULT (_UART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IEN */ 1057 #define UART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */ 1058 #define _UART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ 1059 #define _UART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ 1060 #define _UART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1061 #define UART_IEN_SSM_DEFAULT (_UART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IEN */ 1062 #define UART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */ 1063 #define _UART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ 1064 #define _UART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ 1065 #define _UART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1066 #define UART_IEN_CCF_DEFAULT (_UART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IEN */ 1067 #define UART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */ 1068 #define _UART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ 1069 #define _UART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ 1070 #define _UART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1071 #define UART_IEN_TXIDLE_DEFAULT (_UART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_IEN */ 1072 #define UART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */ 1073 #define _UART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ 1074 #define _UART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ 1075 #define _UART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1076 #define UART_IEN_TCMP0_DEFAULT (_UART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_IEN */ 1077 #define UART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */ 1078 #define _UART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ 1079 #define _UART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ 1080 #define _UART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1081 #define UART_IEN_TCMP1_DEFAULT (_UART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_IEN */ 1082 #define UART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */ 1083 #define _UART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ 1084 #define _UART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ 1085 #define _UART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ 1086 #define UART_IEN_TCMP2_DEFAULT (_UART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_IEN */ 1087 1088 /* Bit fields for UART IRCTRL */ 1089 #define _UART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_IRCTRL */ 1090 #define _UART_IRCTRL_MASK 0x00000F8FUL /**< Mask for UART_IRCTRL */ 1091 #define UART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ 1092 #define _UART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ 1093 #define _UART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ 1094 #define _UART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ 1095 #define UART_IRCTRL_IREN_DEFAULT (_UART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IRCTRL */ 1096 #define _UART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ 1097 #define _UART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ 1098 #define _UART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ 1099 #define _UART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for UART_IRCTRL */ 1100 #define _UART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for UART_IRCTRL */ 1101 #define _UART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for UART_IRCTRL */ 1102 #define _UART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for UART_IRCTRL */ 1103 #define UART_IRCTRL_IRPW_DEFAULT (_UART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IRCTRL */ 1104 #define UART_IRCTRL_IRPW_ONE (_UART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for UART_IRCTRL */ 1105 #define UART_IRCTRL_IRPW_TWO (_UART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for UART_IRCTRL */ 1106 #define UART_IRCTRL_IRPW_THREE (_UART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for UART_IRCTRL */ 1107 #define UART_IRCTRL_IRPW_FOUR (_UART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for UART_IRCTRL */ 1108 #define UART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ 1109 #define _UART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ 1110 #define _UART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ 1111 #define _UART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ 1112 #define UART_IRCTRL_IRFILT_DEFAULT (_UART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IRCTRL */ 1113 #define UART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */ 1114 #define _UART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ 1115 #define _UART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ 1116 #define _UART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ 1117 #define UART_IRCTRL_IRPRSEN_DEFAULT (_UART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IRCTRL */ 1118 #define _UART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */ 1119 #define _UART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */ 1120 #define _UART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ 1121 #define _UART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_IRCTRL */ 1122 #define _UART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_IRCTRL */ 1123 #define _UART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_IRCTRL */ 1124 #define _UART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_IRCTRL */ 1125 #define _UART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_IRCTRL */ 1126 #define _UART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_IRCTRL */ 1127 #define _UART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_IRCTRL */ 1128 #define _UART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_IRCTRL */ 1129 #define _UART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_IRCTRL */ 1130 #define _UART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_IRCTRL */ 1131 #define _UART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_IRCTRL */ 1132 #define _UART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_IRCTRL */ 1133 #define _UART_IRCTRL_IRPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for UART_IRCTRL */ 1134 #define _UART_IRCTRL_IRPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for UART_IRCTRL */ 1135 #define _UART_IRCTRL_IRPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for UART_IRCTRL */ 1136 #define _UART_IRCTRL_IRPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for UART_IRCTRL */ 1137 #define UART_IRCTRL_IRPRSSEL_DEFAULT (_UART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IRCTRL */ 1138 #define UART_IRCTRL_IRPRSSEL_PRSCH0 (_UART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for UART_IRCTRL */ 1139 #define UART_IRCTRL_IRPRSSEL_PRSCH1 (_UART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for UART_IRCTRL */ 1140 #define UART_IRCTRL_IRPRSSEL_PRSCH2 (_UART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for UART_IRCTRL */ 1141 #define UART_IRCTRL_IRPRSSEL_PRSCH3 (_UART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for UART_IRCTRL */ 1142 #define UART_IRCTRL_IRPRSSEL_PRSCH4 (_UART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for UART_IRCTRL */ 1143 #define UART_IRCTRL_IRPRSSEL_PRSCH5 (_UART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for UART_IRCTRL */ 1144 #define UART_IRCTRL_IRPRSSEL_PRSCH6 (_UART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for UART_IRCTRL */ 1145 #define UART_IRCTRL_IRPRSSEL_PRSCH7 (_UART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for UART_IRCTRL */ 1146 #define UART_IRCTRL_IRPRSSEL_PRSCH8 (_UART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for UART_IRCTRL */ 1147 #define UART_IRCTRL_IRPRSSEL_PRSCH9 (_UART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for UART_IRCTRL */ 1148 #define UART_IRCTRL_IRPRSSEL_PRSCH10 (_UART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for UART_IRCTRL */ 1149 #define UART_IRCTRL_IRPRSSEL_PRSCH11 (_UART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for UART_IRCTRL */ 1150 #define UART_IRCTRL_IRPRSSEL_PRSCH12 (_UART_IRCTRL_IRPRSSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for UART_IRCTRL */ 1151 #define UART_IRCTRL_IRPRSSEL_PRSCH13 (_UART_IRCTRL_IRPRSSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for UART_IRCTRL */ 1152 #define UART_IRCTRL_IRPRSSEL_PRSCH14 (_UART_IRCTRL_IRPRSSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for UART_IRCTRL */ 1153 #define UART_IRCTRL_IRPRSSEL_PRSCH15 (_UART_IRCTRL_IRPRSSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for UART_IRCTRL */ 1154 1155 /* Bit fields for UART INPUT */ 1156 #define _UART_INPUT_RESETVALUE 0x00000000UL /**< Default value for UART_INPUT */ 1157 #define _UART_INPUT_MASK 0x00008F8FUL /**< Mask for UART_INPUT */ 1158 #define _UART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */ 1159 #define _UART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */ 1160 #define _UART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */ 1161 #define _UART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_INPUT */ 1162 #define _UART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_INPUT */ 1163 #define _UART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_INPUT */ 1164 #define _UART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_INPUT */ 1165 #define _UART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_INPUT */ 1166 #define _UART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_INPUT */ 1167 #define _UART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_INPUT */ 1168 #define _UART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_INPUT */ 1169 #define _UART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_INPUT */ 1170 #define _UART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_INPUT */ 1171 #define _UART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_INPUT */ 1172 #define _UART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_INPUT */ 1173 #define _UART_INPUT_RXPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for UART_INPUT */ 1174 #define _UART_INPUT_RXPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for UART_INPUT */ 1175 #define _UART_INPUT_RXPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for UART_INPUT */ 1176 #define _UART_INPUT_RXPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for UART_INPUT */ 1177 #define UART_INPUT_RXPRSSEL_DEFAULT (_UART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_INPUT */ 1178 #define UART_INPUT_RXPRSSEL_PRSCH0 (_UART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for UART_INPUT */ 1179 #define UART_INPUT_RXPRSSEL_PRSCH1 (_UART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for UART_INPUT */ 1180 #define UART_INPUT_RXPRSSEL_PRSCH2 (_UART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for UART_INPUT */ 1181 #define UART_INPUT_RXPRSSEL_PRSCH3 (_UART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for UART_INPUT */ 1182 #define UART_INPUT_RXPRSSEL_PRSCH4 (_UART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for UART_INPUT */ 1183 #define UART_INPUT_RXPRSSEL_PRSCH5 (_UART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for UART_INPUT */ 1184 #define UART_INPUT_RXPRSSEL_PRSCH6 (_UART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for UART_INPUT */ 1185 #define UART_INPUT_RXPRSSEL_PRSCH7 (_UART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for UART_INPUT */ 1186 #define UART_INPUT_RXPRSSEL_PRSCH8 (_UART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for UART_INPUT */ 1187 #define UART_INPUT_RXPRSSEL_PRSCH9 (_UART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for UART_INPUT */ 1188 #define UART_INPUT_RXPRSSEL_PRSCH10 (_UART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for UART_INPUT */ 1189 #define UART_INPUT_RXPRSSEL_PRSCH11 (_UART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for UART_INPUT */ 1190 #define UART_INPUT_RXPRSSEL_PRSCH12 (_UART_INPUT_RXPRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for UART_INPUT */ 1191 #define UART_INPUT_RXPRSSEL_PRSCH13 (_UART_INPUT_RXPRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for UART_INPUT */ 1192 #define UART_INPUT_RXPRSSEL_PRSCH14 (_UART_INPUT_RXPRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for UART_INPUT */ 1193 #define UART_INPUT_RXPRSSEL_PRSCH15 (_UART_INPUT_RXPRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for UART_INPUT */ 1194 #define UART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */ 1195 #define _UART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */ 1196 #define _UART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */ 1197 #define _UART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */ 1198 #define UART_INPUT_RXPRS_DEFAULT (_UART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_INPUT */ 1199 #define _UART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */ 1200 #define _UART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */ 1201 #define _UART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */ 1202 #define _UART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_INPUT */ 1203 #define _UART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_INPUT */ 1204 #define _UART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_INPUT */ 1205 #define _UART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_INPUT */ 1206 #define _UART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_INPUT */ 1207 #define _UART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_INPUT */ 1208 #define _UART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_INPUT */ 1209 #define _UART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_INPUT */ 1210 #define _UART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_INPUT */ 1211 #define _UART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_INPUT */ 1212 #define _UART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_INPUT */ 1213 #define _UART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_INPUT */ 1214 #define _UART_INPUT_CLKPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for UART_INPUT */ 1215 #define _UART_INPUT_CLKPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for UART_INPUT */ 1216 #define _UART_INPUT_CLKPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for UART_INPUT */ 1217 #define _UART_INPUT_CLKPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for UART_INPUT */ 1218 #define UART_INPUT_CLKPRSSEL_DEFAULT (_UART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_INPUT */ 1219 #define UART_INPUT_CLKPRSSEL_PRSCH0 (_UART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for UART_INPUT */ 1220 #define UART_INPUT_CLKPRSSEL_PRSCH1 (_UART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for UART_INPUT */ 1221 #define UART_INPUT_CLKPRSSEL_PRSCH2 (_UART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for UART_INPUT */ 1222 #define UART_INPUT_CLKPRSSEL_PRSCH3 (_UART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for UART_INPUT */ 1223 #define UART_INPUT_CLKPRSSEL_PRSCH4 (_UART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for UART_INPUT */ 1224 #define UART_INPUT_CLKPRSSEL_PRSCH5 (_UART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for UART_INPUT */ 1225 #define UART_INPUT_CLKPRSSEL_PRSCH6 (_UART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for UART_INPUT */ 1226 #define UART_INPUT_CLKPRSSEL_PRSCH7 (_UART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for UART_INPUT */ 1227 #define UART_INPUT_CLKPRSSEL_PRSCH8 (_UART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for UART_INPUT */ 1228 #define UART_INPUT_CLKPRSSEL_PRSCH9 (_UART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for UART_INPUT */ 1229 #define UART_INPUT_CLKPRSSEL_PRSCH10 (_UART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for UART_INPUT */ 1230 #define UART_INPUT_CLKPRSSEL_PRSCH11 (_UART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for UART_INPUT */ 1231 #define UART_INPUT_CLKPRSSEL_PRSCH12 (_UART_INPUT_CLKPRSSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for UART_INPUT */ 1232 #define UART_INPUT_CLKPRSSEL_PRSCH13 (_UART_INPUT_CLKPRSSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for UART_INPUT */ 1233 #define UART_INPUT_CLKPRSSEL_PRSCH14 (_UART_INPUT_CLKPRSSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for UART_INPUT */ 1234 #define UART_INPUT_CLKPRSSEL_PRSCH15 (_UART_INPUT_CLKPRSSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for UART_INPUT */ 1235 #define UART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */ 1236 #define _UART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */ 1237 #define _UART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */ 1238 #define _UART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */ 1239 #define UART_INPUT_CLKPRS_DEFAULT (_UART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_INPUT */ 1240 1241 /* Bit fields for UART I2SCTRL */ 1242 #define _UART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_I2SCTRL */ 1243 #define _UART_I2SCTRL_MASK 0x0000071FUL /**< Mask for UART_I2SCTRL */ 1244 #define UART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ 1245 #define _UART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ 1246 #define _UART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ 1247 #define _UART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */ 1248 #define UART_I2SCTRL_EN_DEFAULT (_UART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_I2SCTRL */ 1249 #define UART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ 1250 #define _UART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ 1251 #define _UART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ 1252 #define _UART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */ 1253 #define UART_I2SCTRL_MONO_DEFAULT (_UART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_I2SCTRL */ 1254 #define UART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ 1255 #define _UART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ 1256 #define _UART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ 1257 #define _UART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */ 1258 #define _UART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for UART_I2SCTRL */ 1259 #define _UART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for UART_I2SCTRL */ 1260 #define UART_I2SCTRL_JUSTIFY_DEFAULT (_UART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_I2SCTRL */ 1261 #define UART_I2SCTRL_JUSTIFY_LEFT (_UART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for UART_I2SCTRL */ 1262 #define UART_I2SCTRL_JUSTIFY_RIGHT (_UART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for UART_I2SCTRL */ 1263 #define UART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request for Left/Right Data */ 1264 #define _UART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ 1265 #define _UART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ 1266 #define _UART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */ 1267 #define UART_I2SCTRL_DMASPLIT_DEFAULT (_UART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_I2SCTRL */ 1268 #define UART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S Data */ 1269 #define _UART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ 1270 #define _UART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ 1271 #define _UART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */ 1272 #define UART_I2SCTRL_DELAY_DEFAULT (_UART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_I2SCTRL */ 1273 #define _UART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ 1274 #define _UART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ 1275 #define _UART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */ 1276 #define _UART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for UART_I2SCTRL */ 1277 #define _UART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for UART_I2SCTRL */ 1278 #define _UART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for UART_I2SCTRL */ 1279 #define _UART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for UART_I2SCTRL */ 1280 #define _UART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for UART_I2SCTRL */ 1281 #define _UART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for UART_I2SCTRL */ 1282 #define _UART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for UART_I2SCTRL */ 1283 #define _UART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for UART_I2SCTRL */ 1284 #define UART_I2SCTRL_FORMAT_DEFAULT (_UART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_I2SCTRL */ 1285 #define UART_I2SCTRL_FORMAT_W32D32 (_UART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for UART_I2SCTRL */ 1286 #define UART_I2SCTRL_FORMAT_W32D24M (_UART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for UART_I2SCTRL */ 1287 #define UART_I2SCTRL_FORMAT_W32D24 (_UART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for UART_I2SCTRL */ 1288 #define UART_I2SCTRL_FORMAT_W32D16 (_UART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for UART_I2SCTRL */ 1289 #define UART_I2SCTRL_FORMAT_W32D8 (_UART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for UART_I2SCTRL */ 1290 #define UART_I2SCTRL_FORMAT_W16D16 (_UART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for UART_I2SCTRL */ 1291 #define UART_I2SCTRL_FORMAT_W16D8 (_UART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for UART_I2SCTRL */ 1292 #define UART_I2SCTRL_FORMAT_W8D8 (_UART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for UART_I2SCTRL */ 1293 1294 /* Bit fields for UART TIMING */ 1295 #define _UART_TIMING_RESETVALUE 0x00000000UL /**< Default value for UART_TIMING */ 1296 #define _UART_TIMING_MASK 0x77770000UL /**< Mask for UART_TIMING */ 1297 #define _UART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ 1298 #define _UART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ 1299 #define _UART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMING */ 1300 #define _UART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for UART_TIMING */ 1301 #define _UART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for UART_TIMING */ 1302 #define _UART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for UART_TIMING */ 1303 #define _UART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for UART_TIMING */ 1304 #define _UART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for UART_TIMING */ 1305 #define _UART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for UART_TIMING */ 1306 #define _UART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for UART_TIMING */ 1307 #define _UART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for UART_TIMING */ 1308 #define UART_TIMING_TXDELAY_DEFAULT (_UART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TIMING */ 1309 #define UART_TIMING_TXDELAY_DISABLE (_UART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for UART_TIMING */ 1310 #define UART_TIMING_TXDELAY_ONE (_UART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for UART_TIMING */ 1311 #define UART_TIMING_TXDELAY_TWO (_UART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for UART_TIMING */ 1312 #define UART_TIMING_TXDELAY_THREE (_UART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for UART_TIMING */ 1313 #define UART_TIMING_TXDELAY_SEVEN (_UART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for UART_TIMING */ 1314 #define UART_TIMING_TXDELAY_TCMP0 (_UART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for UART_TIMING */ 1315 #define UART_TIMING_TXDELAY_TCMP1 (_UART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for UART_TIMING */ 1316 #define UART_TIMING_TXDELAY_TCMP2 (_UART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for UART_TIMING */ 1317 #define _UART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ 1318 #define _UART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ 1319 #define _UART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMING */ 1320 #define _UART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for UART_TIMING */ 1321 #define _UART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for UART_TIMING */ 1322 #define _UART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for UART_TIMING */ 1323 #define _UART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for UART_TIMING */ 1324 #define _UART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for UART_TIMING */ 1325 #define _UART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for UART_TIMING */ 1326 #define _UART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for UART_TIMING */ 1327 #define _UART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for UART_TIMING */ 1328 #define UART_TIMING_CSSETUP_DEFAULT (_UART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_TIMING */ 1329 #define UART_TIMING_CSSETUP_ZERO (_UART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for UART_TIMING */ 1330 #define UART_TIMING_CSSETUP_ONE (_UART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for UART_TIMING */ 1331 #define UART_TIMING_CSSETUP_TWO (_UART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for UART_TIMING */ 1332 #define UART_TIMING_CSSETUP_THREE (_UART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for UART_TIMING */ 1333 #define UART_TIMING_CSSETUP_SEVEN (_UART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for UART_TIMING */ 1334 #define UART_TIMING_CSSETUP_TCMP0 (_UART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for UART_TIMING */ 1335 #define UART_TIMING_CSSETUP_TCMP1 (_UART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for UART_TIMING */ 1336 #define UART_TIMING_CSSETUP_TCMP2 (_UART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for UART_TIMING */ 1337 #define _UART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ 1338 #define _UART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ 1339 #define _UART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMING */ 1340 #define _UART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for UART_TIMING */ 1341 #define _UART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for UART_TIMING */ 1342 #define _UART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for UART_TIMING */ 1343 #define _UART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for UART_TIMING */ 1344 #define _UART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for UART_TIMING */ 1345 #define _UART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for UART_TIMING */ 1346 #define _UART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for UART_TIMING */ 1347 #define _UART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for UART_TIMING */ 1348 #define UART_TIMING_ICS_DEFAULT (_UART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_TIMING */ 1349 #define UART_TIMING_ICS_ZERO (_UART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for UART_TIMING */ 1350 #define UART_TIMING_ICS_ONE (_UART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for UART_TIMING */ 1351 #define UART_TIMING_ICS_TWO (_UART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for UART_TIMING */ 1352 #define UART_TIMING_ICS_THREE (_UART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for UART_TIMING */ 1353 #define UART_TIMING_ICS_SEVEN (_UART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for UART_TIMING */ 1354 #define UART_TIMING_ICS_TCMP0 (_UART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for UART_TIMING */ 1355 #define UART_TIMING_ICS_TCMP1 (_UART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for UART_TIMING */ 1356 #define UART_TIMING_ICS_TCMP2 (_UART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for UART_TIMING */ 1357 #define _UART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ 1358 #define _UART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ 1359 #define _UART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMING */ 1360 #define _UART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for UART_TIMING */ 1361 #define _UART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for UART_TIMING */ 1362 #define _UART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for UART_TIMING */ 1363 #define _UART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for UART_TIMING */ 1364 #define _UART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for UART_TIMING */ 1365 #define _UART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for UART_TIMING */ 1366 #define _UART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for UART_TIMING */ 1367 #define _UART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for UART_TIMING */ 1368 #define UART_TIMING_CSHOLD_DEFAULT (_UART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_TIMING */ 1369 #define UART_TIMING_CSHOLD_ZERO (_UART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for UART_TIMING */ 1370 #define UART_TIMING_CSHOLD_ONE (_UART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for UART_TIMING */ 1371 #define UART_TIMING_CSHOLD_TWO (_UART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for UART_TIMING */ 1372 #define UART_TIMING_CSHOLD_THREE (_UART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for UART_TIMING */ 1373 #define UART_TIMING_CSHOLD_SEVEN (_UART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for UART_TIMING */ 1374 #define UART_TIMING_CSHOLD_TCMP0 (_UART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for UART_TIMING */ 1375 #define UART_TIMING_CSHOLD_TCMP1 (_UART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for UART_TIMING */ 1376 #define UART_TIMING_CSHOLD_TCMP2 (_UART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for UART_TIMING */ 1377 1378 /* Bit fields for UART CTRLX */ 1379 #define _UART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for UART_CTRLX */ 1380 #define _UART_CTRLX_MASK 0x0000000FUL /**< Mask for UART_CTRLX */ 1381 #define UART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug Halt */ 1382 #define _UART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ 1383 #define _UART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ 1384 #define _UART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRLX */ 1385 #define UART_CTRLX_DBGHALT_DEFAULT (_UART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CTRLX */ 1386 #define UART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ 1387 #define _UART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ 1388 #define _UART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ 1389 #define _UART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRLX */ 1390 #define UART_CTRLX_CTSINV_DEFAULT (_UART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CTRLX */ 1391 #define UART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function Enabled */ 1392 #define _UART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ 1393 #define _UART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ 1394 #define _UART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRLX */ 1395 #define UART_CTRLX_CTSEN_DEFAULT (_UART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CTRLX */ 1396 #define UART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ 1397 #define _UART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ 1398 #define _UART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ 1399 #define _UART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRLX */ 1400 #define UART_CTRLX_RTSINV_DEFAULT (_UART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CTRLX */ 1401 1402 /* Bit fields for UART TIMECMP0 */ 1403 #define _UART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for UART_TIMECMP0 */ 1404 #define _UART_TIMECMP0_MASK 0x017700FFUL /**< Mask for UART_TIMECMP0 */ 1405 #define _UART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ 1406 #define _UART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ 1407 #define _UART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP0 */ 1408 #define UART_TIMECMP0_TCMPVAL_DEFAULT (_UART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TIMECMP0 */ 1409 #define _UART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ 1410 #define _UART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ 1411 #define _UART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP0 */ 1412 #define _UART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for UART_TIMECMP0 */ 1413 #define _UART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for UART_TIMECMP0 */ 1414 #define _UART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for UART_TIMECMP0 */ 1415 #define _UART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for UART_TIMECMP0 */ 1416 #define _UART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for UART_TIMECMP0 */ 1417 #define UART_TIMECMP0_TSTART_DEFAULT (_UART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TIMECMP0 */ 1418 #define UART_TIMECMP0_TSTART_DISABLE (_UART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for UART_TIMECMP0 */ 1419 #define UART_TIMECMP0_TSTART_TXEOF (_UART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for UART_TIMECMP0 */ 1420 #define UART_TIMECMP0_TSTART_TXC (_UART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for UART_TIMECMP0 */ 1421 #define UART_TIMECMP0_TSTART_RXACT (_UART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for UART_TIMECMP0 */ 1422 #define UART_TIMECMP0_TSTART_RXEOF (_UART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for UART_TIMECMP0 */ 1423 #define _UART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ 1424 #define _UART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ 1425 #define _UART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP0 */ 1426 #define _UART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for UART_TIMECMP0 */ 1427 #define _UART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for UART_TIMECMP0 */ 1428 #define _UART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for UART_TIMECMP0 */ 1429 #define _UART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for UART_TIMECMP0 */ 1430 #define UART_TIMECMP0_TSTOP_DEFAULT (_UART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_TIMECMP0 */ 1431 #define UART_TIMECMP0_TSTOP_TCMP0 (_UART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for UART_TIMECMP0 */ 1432 #define UART_TIMECMP0_TSTOP_TXST (_UART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for UART_TIMECMP0 */ 1433 #define UART_TIMECMP0_TSTOP_RXACT (_UART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for UART_TIMECMP0 */ 1434 #define UART_TIMECMP0_TSTOP_RXACTN (_UART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for UART_TIMECMP0 */ 1435 #define UART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ 1436 #define _UART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ 1437 #define _UART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ 1438 #define _UART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP0 */ 1439 #define UART_TIMECMP0_RESTARTEN_DEFAULT (_UART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_TIMECMP0 */ 1440 1441 /* Bit fields for UART TIMECMP1 */ 1442 #define _UART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for UART_TIMECMP1 */ 1443 #define _UART_TIMECMP1_MASK 0x017700FFUL /**< Mask for UART_TIMECMP1 */ 1444 #define _UART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ 1445 #define _UART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ 1446 #define _UART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP1 */ 1447 #define UART_TIMECMP1_TCMPVAL_DEFAULT (_UART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TIMECMP1 */ 1448 #define _UART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ 1449 #define _UART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ 1450 #define _UART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP1 */ 1451 #define _UART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for UART_TIMECMP1 */ 1452 #define _UART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for UART_TIMECMP1 */ 1453 #define _UART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for UART_TIMECMP1 */ 1454 #define _UART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for UART_TIMECMP1 */ 1455 #define _UART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for UART_TIMECMP1 */ 1456 #define UART_TIMECMP1_TSTART_DEFAULT (_UART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TIMECMP1 */ 1457 #define UART_TIMECMP1_TSTART_DISABLE (_UART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for UART_TIMECMP1 */ 1458 #define UART_TIMECMP1_TSTART_TXEOF (_UART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for UART_TIMECMP1 */ 1459 #define UART_TIMECMP1_TSTART_TXC (_UART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for UART_TIMECMP1 */ 1460 #define UART_TIMECMP1_TSTART_RXACT (_UART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for UART_TIMECMP1 */ 1461 #define UART_TIMECMP1_TSTART_RXEOF (_UART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for UART_TIMECMP1 */ 1462 #define _UART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ 1463 #define _UART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ 1464 #define _UART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP1 */ 1465 #define _UART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for UART_TIMECMP1 */ 1466 #define _UART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for UART_TIMECMP1 */ 1467 #define _UART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for UART_TIMECMP1 */ 1468 #define _UART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for UART_TIMECMP1 */ 1469 #define UART_TIMECMP1_TSTOP_DEFAULT (_UART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_TIMECMP1 */ 1470 #define UART_TIMECMP1_TSTOP_TCMP1 (_UART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for UART_TIMECMP1 */ 1471 #define UART_TIMECMP1_TSTOP_TXST (_UART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for UART_TIMECMP1 */ 1472 #define UART_TIMECMP1_TSTOP_RXACT (_UART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for UART_TIMECMP1 */ 1473 #define UART_TIMECMP1_TSTOP_RXACTN (_UART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for UART_TIMECMP1 */ 1474 #define UART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ 1475 #define _UART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ 1476 #define _UART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ 1477 #define _UART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP1 */ 1478 #define UART_TIMECMP1_RESTARTEN_DEFAULT (_UART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_TIMECMP1 */ 1479 1480 /* Bit fields for UART TIMECMP2 */ 1481 #define _UART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for UART_TIMECMP2 */ 1482 #define _UART_TIMECMP2_MASK 0x017700FFUL /**< Mask for UART_TIMECMP2 */ 1483 #define _UART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ 1484 #define _UART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ 1485 #define _UART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP2 */ 1486 #define UART_TIMECMP2_TCMPVAL_DEFAULT (_UART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TIMECMP2 */ 1487 #define _UART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ 1488 #define _UART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ 1489 #define _UART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP2 */ 1490 #define _UART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for UART_TIMECMP2 */ 1491 #define _UART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for UART_TIMECMP2 */ 1492 #define _UART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for UART_TIMECMP2 */ 1493 #define _UART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for UART_TIMECMP2 */ 1494 #define _UART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for UART_TIMECMP2 */ 1495 #define UART_TIMECMP2_TSTART_DEFAULT (_UART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TIMECMP2 */ 1496 #define UART_TIMECMP2_TSTART_DISABLE (_UART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for UART_TIMECMP2 */ 1497 #define UART_TIMECMP2_TSTART_TXEOF (_UART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for UART_TIMECMP2 */ 1498 #define UART_TIMECMP2_TSTART_TXC (_UART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for UART_TIMECMP2 */ 1499 #define UART_TIMECMP2_TSTART_RXACT (_UART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for UART_TIMECMP2 */ 1500 #define UART_TIMECMP2_TSTART_RXEOF (_UART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for UART_TIMECMP2 */ 1501 #define _UART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ 1502 #define _UART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ 1503 #define _UART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP2 */ 1504 #define _UART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for UART_TIMECMP2 */ 1505 #define _UART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for UART_TIMECMP2 */ 1506 #define _UART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for UART_TIMECMP2 */ 1507 #define _UART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for UART_TIMECMP2 */ 1508 #define UART_TIMECMP2_TSTOP_DEFAULT (_UART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_TIMECMP2 */ 1509 #define UART_TIMECMP2_TSTOP_TCMP2 (_UART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for UART_TIMECMP2 */ 1510 #define UART_TIMECMP2_TSTOP_TXST (_UART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for UART_TIMECMP2 */ 1511 #define UART_TIMECMP2_TSTOP_RXACT (_UART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for UART_TIMECMP2 */ 1512 #define UART_TIMECMP2_TSTOP_RXACTN (_UART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for UART_TIMECMP2 */ 1513 #define UART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ 1514 #define _UART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ 1515 #define _UART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ 1516 #define _UART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP2 */ 1517 #define UART_TIMECMP2_RESTARTEN_DEFAULT (_UART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_TIMECMP2 */ 1518 1519 /* Bit fields for UART ROUTEPEN */ 1520 #define _UART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTEPEN */ 1521 #define _UART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for UART_ROUTEPEN */ 1522 #define UART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ 1523 #define _UART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ 1524 #define _UART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ 1525 #define _UART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */ 1526 #define UART_ROUTEPEN_RXPEN_DEFAULT (_UART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_ROUTEPEN */ 1527 #define UART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ 1528 #define _UART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ 1529 #define _UART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ 1530 #define _UART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */ 1531 #define UART_ROUTEPEN_TXPEN_DEFAULT (_UART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_ROUTEPEN */ 1532 #define UART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */ 1533 #define _UART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ 1534 #define _UART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ 1535 #define _UART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */ 1536 #define UART_ROUTEPEN_CSPEN_DEFAULT (_UART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_ROUTEPEN */ 1537 #define UART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */ 1538 #define _UART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ 1539 #define _UART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ 1540 #define _UART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */ 1541 #define UART_ROUTEPEN_CLKPEN_DEFAULT (_UART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_ROUTEPEN */ 1542 #define UART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */ 1543 #define _UART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */ 1544 #define _UART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */ 1545 #define _UART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */ 1546 #define UART_ROUTEPEN_CTSPEN_DEFAULT (_UART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_ROUTEPEN */ 1547 #define UART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */ 1548 #define _UART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */ 1549 #define _UART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */ 1550 #define _UART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */ 1551 #define UART_ROUTEPEN_RTSPEN_DEFAULT (_UART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_ROUTEPEN */ 1552 1553 /* Bit fields for UART ROUTELOC0 */ 1554 #define _UART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTELOC0 */ 1555 #define _UART_ROUTELOC0_MASK 0x07070707UL /**< Mask for UART_ROUTELOC0 */ 1556 #define _UART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */ 1557 #define _UART_ROUTELOC0_RXLOC_MASK 0x7UL /**< Bit mask for USART_RXLOC */ 1558 #define _UART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC0 */ 1559 #define _UART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC0 */ 1560 #define _UART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC0 */ 1561 #define _UART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC0 */ 1562 #define _UART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC0 */ 1563 #define _UART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC0 */ 1564 #define _UART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC0 */ 1565 #define _UART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC0 */ 1566 #define UART_ROUTELOC0_RXLOC_LOC0 (_UART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for UART_ROUTELOC0 */ 1567 #define UART_ROUTELOC0_RXLOC_DEFAULT (_UART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_ROUTELOC0 */ 1568 #define UART_ROUTELOC0_RXLOC_LOC1 (_UART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for UART_ROUTELOC0 */ 1569 #define UART_ROUTELOC0_RXLOC_LOC2 (_UART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for UART_ROUTELOC0 */ 1570 #define UART_ROUTELOC0_RXLOC_LOC3 (_UART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for UART_ROUTELOC0 */ 1571 #define UART_ROUTELOC0_RXLOC_LOC4 (_UART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for UART_ROUTELOC0 */ 1572 #define UART_ROUTELOC0_RXLOC_LOC5 (_UART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for UART_ROUTELOC0 */ 1573 #define UART_ROUTELOC0_RXLOC_LOC6 (_UART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for UART_ROUTELOC0 */ 1574 #define _UART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */ 1575 #define _UART_ROUTELOC0_TXLOC_MASK 0x700UL /**< Bit mask for USART_TXLOC */ 1576 #define _UART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC0 */ 1577 #define _UART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC0 */ 1578 #define _UART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC0 */ 1579 #define _UART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC0 */ 1580 #define _UART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC0 */ 1581 #define _UART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC0 */ 1582 #define _UART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC0 */ 1583 #define _UART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC0 */ 1584 #define UART_ROUTELOC0_TXLOC_LOC0 (_UART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for UART_ROUTELOC0 */ 1585 #define UART_ROUTELOC0_TXLOC_DEFAULT (_UART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_ROUTELOC0 */ 1586 #define UART_ROUTELOC0_TXLOC_LOC1 (_UART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for UART_ROUTELOC0 */ 1587 #define UART_ROUTELOC0_TXLOC_LOC2 (_UART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for UART_ROUTELOC0 */ 1588 #define UART_ROUTELOC0_TXLOC_LOC3 (_UART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for UART_ROUTELOC0 */ 1589 #define UART_ROUTELOC0_TXLOC_LOC4 (_UART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for UART_ROUTELOC0 */ 1590 #define UART_ROUTELOC0_TXLOC_LOC5 (_UART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for UART_ROUTELOC0 */ 1591 #define UART_ROUTELOC0_TXLOC_LOC6 (_UART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for UART_ROUTELOC0 */ 1592 #define _UART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */ 1593 #define _UART_ROUTELOC0_CSLOC_MASK 0x70000UL /**< Bit mask for USART_CSLOC */ 1594 #define _UART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC0 */ 1595 #define _UART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC0 */ 1596 #define _UART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC0 */ 1597 #define _UART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC0 */ 1598 #define _UART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC0 */ 1599 #define _UART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC0 */ 1600 #define _UART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC0 */ 1601 #define _UART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC0 */ 1602 #define UART_ROUTELOC0_CSLOC_LOC0 (_UART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for UART_ROUTELOC0 */ 1603 #define UART_ROUTELOC0_CSLOC_DEFAULT (_UART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_ROUTELOC0 */ 1604 #define UART_ROUTELOC0_CSLOC_LOC1 (_UART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for UART_ROUTELOC0 */ 1605 #define UART_ROUTELOC0_CSLOC_LOC2 (_UART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for UART_ROUTELOC0 */ 1606 #define UART_ROUTELOC0_CSLOC_LOC3 (_UART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for UART_ROUTELOC0 */ 1607 #define UART_ROUTELOC0_CSLOC_LOC4 (_UART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for UART_ROUTELOC0 */ 1608 #define UART_ROUTELOC0_CSLOC_LOC5 (_UART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for UART_ROUTELOC0 */ 1609 #define UART_ROUTELOC0_CSLOC_LOC6 (_UART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for UART_ROUTELOC0 */ 1610 #define _UART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */ 1611 #define _UART_ROUTELOC0_CLKLOC_MASK 0x7000000UL /**< Bit mask for USART_CLKLOC */ 1612 #define _UART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC0 */ 1613 #define _UART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC0 */ 1614 #define _UART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC0 */ 1615 #define _UART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC0 */ 1616 #define _UART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC0 */ 1617 #define _UART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC0 */ 1618 #define _UART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC0 */ 1619 #define _UART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC0 */ 1620 #define UART_ROUTELOC0_CLKLOC_LOC0 (_UART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for UART_ROUTELOC0 */ 1621 #define UART_ROUTELOC0_CLKLOC_DEFAULT (_UART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_ROUTELOC0 */ 1622 #define UART_ROUTELOC0_CLKLOC_LOC1 (_UART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for UART_ROUTELOC0 */ 1623 #define UART_ROUTELOC0_CLKLOC_LOC2 (_UART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for UART_ROUTELOC0 */ 1624 #define UART_ROUTELOC0_CLKLOC_LOC3 (_UART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for UART_ROUTELOC0 */ 1625 #define UART_ROUTELOC0_CLKLOC_LOC4 (_UART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for UART_ROUTELOC0 */ 1626 #define UART_ROUTELOC0_CLKLOC_LOC5 (_UART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for UART_ROUTELOC0 */ 1627 #define UART_ROUTELOC0_CLKLOC_LOC6 (_UART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for UART_ROUTELOC0 */ 1628 1629 /* Bit fields for UART ROUTELOC1 */ 1630 #define _UART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTELOC1 */ 1631 #define _UART_ROUTELOC1_MASK 0x00000707UL /**< Mask for UART_ROUTELOC1 */ 1632 #define _UART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */ 1633 #define _UART_ROUTELOC1_CTSLOC_MASK 0x7UL /**< Bit mask for USART_CTSLOC */ 1634 #define _UART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC1 */ 1635 #define _UART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC1 */ 1636 #define _UART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC1 */ 1637 #define _UART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC1 */ 1638 #define _UART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC1 */ 1639 #define _UART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC1 */ 1640 #define _UART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC1 */ 1641 #define UART_ROUTELOC1_CTSLOC_LOC0 (_UART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for UART_ROUTELOC1 */ 1642 #define UART_ROUTELOC1_CTSLOC_DEFAULT (_UART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_ROUTELOC1 */ 1643 #define UART_ROUTELOC1_CTSLOC_LOC1 (_UART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for UART_ROUTELOC1 */ 1644 #define UART_ROUTELOC1_CTSLOC_LOC2 (_UART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for UART_ROUTELOC1 */ 1645 #define UART_ROUTELOC1_CTSLOC_LOC3 (_UART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for UART_ROUTELOC1 */ 1646 #define UART_ROUTELOC1_CTSLOC_LOC4 (_UART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for UART_ROUTELOC1 */ 1647 #define UART_ROUTELOC1_CTSLOC_LOC5 (_UART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for UART_ROUTELOC1 */ 1648 #define _UART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */ 1649 #define _UART_ROUTELOC1_RTSLOC_MASK 0x700UL /**< Bit mask for USART_RTSLOC */ 1650 #define _UART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC1 */ 1651 #define _UART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC1 */ 1652 #define _UART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC1 */ 1653 #define _UART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC1 */ 1654 #define _UART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC1 */ 1655 #define _UART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC1 */ 1656 #define _UART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC1 */ 1657 #define UART_ROUTELOC1_RTSLOC_LOC0 (_UART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for UART_ROUTELOC1 */ 1658 #define UART_ROUTELOC1_RTSLOC_DEFAULT (_UART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_ROUTELOC1 */ 1659 #define UART_ROUTELOC1_RTSLOC_LOC1 (_UART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for UART_ROUTELOC1 */ 1660 #define UART_ROUTELOC1_RTSLOC_LOC2 (_UART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for UART_ROUTELOC1 */ 1661 #define UART_ROUTELOC1_RTSLOC_LOC3 (_UART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for UART_ROUTELOC1 */ 1662 #define UART_ROUTELOC1_RTSLOC_LOC4 (_UART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for UART_ROUTELOC1 */ 1663 #define UART_ROUTELOC1_RTSLOC_LOC5 (_UART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for UART_ROUTELOC1 */ 1664 1665 /** @} */ 1666 /** @} End of group EFM32GG12B_UART */ 1667 /** @} End of group Parts */ 1668
