1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG12B_SMU register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG12B_SMU SMU 43 * @{ 44 * @brief EFM32GG12B_SMU Register Declaration 45 ******************************************************************************/ 46 /** SMU Register Declaration */ 47 typedef struct { 48 uint32_t RESERVED0[3U]; /**< Reserved for future use **/ 49 __IM uint32_t IF; /**< Interrupt Flag Register */ 50 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 51 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 52 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 53 54 uint32_t RESERVED1[9U]; /**< Reserved for future use **/ 55 __IOM uint32_t PPUCTRL; /**< PPU Control Register */ 56 uint32_t RESERVED2[3U]; /**< Reserved for future use **/ 57 __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ 58 __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ 59 __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ 60 61 uint32_t RESERVED3[13U]; /**< Reserved for future use **/ 62 __IM uint32_t PPUFS; /**< PPU Fault Status */ 63 } SMU_TypeDef; /** @} */ 64 65 /***************************************************************************//** 66 * @addtogroup EFM32GG12B_SMU 67 * @{ 68 * @defgroup EFM32GG12B_SMU_BitFields SMU Bit Fields 69 * @{ 70 ******************************************************************************/ 71 72 /* Bit fields for SMU IF */ 73 #define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ 74 #define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ 75 #define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ 76 #define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ 77 #define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ 78 #define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ 79 #define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ 80 81 /* Bit fields for SMU IFS */ 82 #define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ 83 #define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ 84 #define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ 85 #define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ 86 #define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ 87 #define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ 88 #define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ 89 90 /* Bit fields for SMU IFC */ 91 #define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ 92 #define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ 93 #define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ 94 #define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ 95 #define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ 96 #define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ 97 #define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ 98 99 /* Bit fields for SMU IEN */ 100 #define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ 101 #define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ 102 #define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ 103 #define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ 104 #define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ 105 #define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ 106 #define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ 107 108 /* Bit fields for SMU PPUCTRL */ 109 #define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ 110 #define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ 111 #define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ 112 #define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ 113 #define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ 114 #define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ 115 #define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ 116 117 /* Bit fields for SMU PPUPATD0 */ 118 #define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ 119 #define _SMU_PPUPATD0_MASK 0x1FFFFFFFUL /**< Mask for SMU_PPUPATD0 */ 120 #define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ 121 #define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ 122 #define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ 123 #define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 124 #define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 125 #define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ 126 #define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ 127 #define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ 128 #define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 129 #define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 130 #define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 2 access control bit */ 131 #define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ 132 #define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ 133 #define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 134 #define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 135 #define SMU_PPUPATD0_ADC0 (0x1UL << 3) /**< Analog to Digital Converter 0 access control bit */ 136 #define _SMU_PPUPATD0_ADC0_SHIFT 3 /**< Shift value for SMU_ADC0 */ 137 #define _SMU_PPUPATD0_ADC0_MASK 0x8UL /**< Bit mask for SMU_ADC0 */ 138 #define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 139 #define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 140 #define SMU_PPUPATD0_ADC1 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ 141 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value for SMU_ADC1 */ 142 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for SMU_ADC1 */ 143 #define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 144 #define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 145 #define SMU_PPUPATD0_CAN0 (0x1UL << 5) /**< CAN 0 access control bit */ 146 #define _SMU_PPUPATD0_CAN0_SHIFT 5 /**< Shift value for SMU_CAN0 */ 147 #define _SMU_PPUPATD0_CAN0_MASK 0x20UL /**< Bit mask for SMU_CAN0 */ 148 #define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 149 #define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 150 #define SMU_PPUPATD0_CAN1 (0x1UL << 6) /**< CAN 1 access control bit */ 151 #define _SMU_PPUPATD0_CAN1_SHIFT 6 /**< Shift value for SMU_CAN1 */ 152 #define _SMU_PPUPATD0_CAN1_MASK 0x40UL /**< Bit mask for SMU_CAN1 */ 153 #define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 154 #define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 155 #define SMU_PPUPATD0_CMU (0x1UL << 7) /**< Clock Management Unit access control bit */ 156 #define _SMU_PPUPATD0_CMU_SHIFT 7 /**< Shift value for SMU_CMU */ 157 #define _SMU_PPUPATD0_CMU_MASK 0x80UL /**< Bit mask for SMU_CMU */ 158 #define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 159 #define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 160 #define SMU_PPUPATD0_CRYOTIMER (0x1UL << 8) /**< CRYOTIMER access control bit */ 161 #define _SMU_PPUPATD0_CRYOTIMER_SHIFT 8 /**< Shift value for SMU_CRYOTIMER */ 162 #define _SMU_PPUPATD0_CRYOTIMER_MASK 0x100UL /**< Bit mask for SMU_CRYOTIMER */ 163 #define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 164 #define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 165 #define SMU_PPUPATD0_CRYPTO0 (0x1UL << 9) /**< Advanced Encryption Standard Accelerator access control bit */ 166 #define _SMU_PPUPATD0_CRYPTO0_SHIFT 9 /**< Shift value for SMU_CRYPTO0 */ 167 #define _SMU_PPUPATD0_CRYPTO0_MASK 0x200UL /**< Bit mask for SMU_CRYPTO0 */ 168 #define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 169 #define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 170 #define SMU_PPUPATD0_CSEN (0x1UL << 10) /**< Capacitive touch sense module access control bit */ 171 #define _SMU_PPUPATD0_CSEN_SHIFT 10 /**< Shift value for SMU_CSEN */ 172 #define _SMU_PPUPATD0_CSEN_MASK 0x400UL /**< Bit mask for SMU_CSEN */ 173 #define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 174 #define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 175 #define SMU_PPUPATD0_VDAC0 (0x1UL << 11) /**< Digital to Analog Converter 0 access control bit */ 176 #define _SMU_PPUPATD0_VDAC0_SHIFT 11 /**< Shift value for SMU_VDAC0 */ 177 #define _SMU_PPUPATD0_VDAC0_MASK 0x800UL /**< Bit mask for SMU_VDAC0 */ 178 #define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 179 #define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 180 #define SMU_PPUPATD0_PRS (0x1UL << 12) /**< Peripheral Reflex System access control bit */ 181 #define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ 182 #define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ 183 #define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 184 #define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 185 #define SMU_PPUPATD0_EBI (0x1UL << 13) /**< External Bus Interface access control bit */ 186 #define _SMU_PPUPATD0_EBI_SHIFT 13 /**< Shift value for SMU_EBI */ 187 #define _SMU_PPUPATD0_EBI_MASK 0x2000UL /**< Bit mask for SMU_EBI */ 188 #define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 189 #define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 190 #define SMU_PPUPATD0_EMU (0x1UL << 14) /**< Energy Management Unit access control bit */ 191 #define _SMU_PPUPATD0_EMU_SHIFT 14 /**< Shift value for SMU_EMU */ 192 #define _SMU_PPUPATD0_EMU_MASK 0x4000UL /**< Bit mask for SMU_EMU */ 193 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 194 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 195 #define SMU_PPUPATD0_FPUEH (0x1UL << 15) /**< FPU Exception Handler access control bit */ 196 #define _SMU_PPUPATD0_FPUEH_SHIFT 15 /**< Shift value for SMU_FPUEH */ 197 #define _SMU_PPUPATD0_FPUEH_MASK 0x8000UL /**< Bit mask for SMU_FPUEH */ 198 #define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 199 #define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 200 #define SMU_PPUPATD0_GPCRC (0x1UL << 16) /**< General Purpose CRC access control bit */ 201 #define _SMU_PPUPATD0_GPCRC_SHIFT 16 /**< Shift value for SMU_GPCRC */ 202 #define _SMU_PPUPATD0_GPCRC_MASK 0x10000UL /**< Bit mask for SMU_GPCRC */ 203 #define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 204 #define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 205 #define SMU_PPUPATD0_GPIO (0x1UL << 17) /**< General purpose Input/Output access control bit */ 206 #define _SMU_PPUPATD0_GPIO_SHIFT 17 /**< Shift value for SMU_GPIO */ 207 #define _SMU_PPUPATD0_GPIO_MASK 0x20000UL /**< Bit mask for SMU_GPIO */ 208 #define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 209 #define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 210 #define SMU_PPUPATD0_I2C0 (0x1UL << 18) /**< I2C 0 access control bit */ 211 #define _SMU_PPUPATD0_I2C0_SHIFT 18 /**< Shift value for SMU_I2C0 */ 212 #define _SMU_PPUPATD0_I2C0_MASK 0x40000UL /**< Bit mask for SMU_I2C0 */ 213 #define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 214 #define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 215 #define SMU_PPUPATD0_I2C1 (0x1UL << 19) /**< I2C 1 access control bit */ 216 #define _SMU_PPUPATD0_I2C1_SHIFT 19 /**< Shift value for SMU_I2C1 */ 217 #define _SMU_PPUPATD0_I2C1_MASK 0x80000UL /**< Bit mask for SMU_I2C1 */ 218 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 219 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 220 #define SMU_PPUPATD0_IDAC0 (0x1UL << 20) /**< Current Digital to Analog Converter 0 access control bit */ 221 #define _SMU_PPUPATD0_IDAC0_SHIFT 20 /**< Shift value for SMU_IDAC0 */ 222 #define _SMU_PPUPATD0_IDAC0_MASK 0x100000UL /**< Bit mask for SMU_IDAC0 */ 223 #define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 224 #define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 225 #define SMU_PPUPATD0_MSC (0x1UL << 21) /**< Memory System Controller access control bit */ 226 #define _SMU_PPUPATD0_MSC_SHIFT 21 /**< Shift value for SMU_MSC */ 227 #define _SMU_PPUPATD0_MSC_MASK 0x200000UL /**< Bit mask for SMU_MSC */ 228 #define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 229 #define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 230 #define SMU_PPUPATD0_LCD (0x1UL << 22) /**< Liquid Crystal Display Controller access control bit */ 231 #define _SMU_PPUPATD0_LCD_SHIFT 22 /**< Shift value for SMU_LCD */ 232 #define _SMU_PPUPATD0_LCD_MASK 0x400000UL /**< Bit mask for SMU_LCD */ 233 #define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 234 #define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 235 #define SMU_PPUPATD0_LDMA (0x1UL << 23) /**< Linked Direct Memory Access Controller access control bit */ 236 #define _SMU_PPUPATD0_LDMA_SHIFT 23 /**< Shift value for SMU_LDMA */ 237 #define _SMU_PPUPATD0_LDMA_MASK 0x800000UL /**< Bit mask for SMU_LDMA */ 238 #define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 239 #define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 240 #define SMU_PPUPATD0_LESENSE (0x1UL << 24) /**< Low Energy Sensor Interface access control bit */ 241 #define _SMU_PPUPATD0_LESENSE_SHIFT 24 /**< Shift value for SMU_LESENSE */ 242 #define _SMU_PPUPATD0_LESENSE_MASK 0x1000000UL /**< Bit mask for SMU_LESENSE */ 243 #define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 244 #define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 245 #define SMU_PPUPATD0_LETIMER0 (0x1UL << 25) /**< Low Energy Timer 0 access control bit */ 246 #define _SMU_PPUPATD0_LETIMER0_SHIFT 25 /**< Shift value for SMU_LETIMER0 */ 247 #define _SMU_PPUPATD0_LETIMER0_MASK 0x2000000UL /**< Bit mask for SMU_LETIMER0 */ 248 #define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 249 #define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 250 #define SMU_PPUPATD0_LETIMER1 (0x1UL << 26) /**< Low Energy Timer 1 access control bit */ 251 #define _SMU_PPUPATD0_LETIMER1_SHIFT 26 /**< Shift value for SMU_LETIMER1 */ 252 #define _SMU_PPUPATD0_LETIMER1_MASK 0x4000000UL /**< Bit mask for SMU_LETIMER1 */ 253 #define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 254 #define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 255 #define SMU_PPUPATD0_LEUART0 (0x1UL << 27) /**< Low Energy UART 0 access control bit */ 256 #define _SMU_PPUPATD0_LEUART0_SHIFT 27 /**< Shift value for SMU_LEUART0 */ 257 #define _SMU_PPUPATD0_LEUART0_MASK 0x8000000UL /**< Bit mask for SMU_LEUART0 */ 258 #define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 259 #define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 260 #define SMU_PPUPATD0_LEUART1 (0x1UL << 28) /**< Low Energy UART 1 access control bit */ 261 #define _SMU_PPUPATD0_LEUART1_SHIFT 28 /**< Shift value for SMU_LEUART1 */ 262 #define _SMU_PPUPATD0_LEUART1_MASK 0x10000000UL /**< Bit mask for SMU_LEUART1 */ 263 #define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 264 #define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 265 266 /* Bit fields for SMU PPUPATD1 */ 267 #define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ 268 #define _SMU_PPUPATD1_MASK 0x07FFFFFFUL /**< Mask for SMU_PPUPATD1 */ 269 #define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ 270 #define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ 271 #define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ 272 #define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 273 #define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 274 #define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ 275 #define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ 276 #define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ 277 #define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 278 #define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 279 #define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ 280 #define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ 281 #define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ 282 #define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 283 #define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 284 #define SMU_PPUPATD1_PDM (0x1UL << 3) /**< PDM Interface access control bit */ 285 #define _SMU_PPUPATD1_PDM_SHIFT 3 /**< Shift value for SMU_PDM */ 286 #define _SMU_PPUPATD1_PDM_MASK 0x8UL /**< Bit mask for SMU_PDM */ 287 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 288 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 289 #define SMU_PPUPATD1_QSPI0 (0x1UL << 4) /**< Quad-SPI access control bit */ 290 #define _SMU_PPUPATD1_QSPI0_SHIFT 4 /**< Shift value for SMU_QSPI0 */ 291 #define _SMU_PPUPATD1_QSPI0_MASK 0x10UL /**< Bit mask for SMU_QSPI0 */ 292 #define _SMU_PPUPATD1_QSPI0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 293 #define SMU_PPUPATD1_QSPI0_DEFAULT (_SMU_PPUPATD1_QSPI0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 294 #define SMU_PPUPATD1_RMU (0x1UL << 5) /**< Reset Management Unit access control bit */ 295 #define _SMU_PPUPATD1_RMU_SHIFT 5 /**< Shift value for SMU_RMU */ 296 #define _SMU_PPUPATD1_RMU_MASK 0x20UL /**< Bit mask for SMU_RMU */ 297 #define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 298 #define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 299 #define SMU_PPUPATD1_RTC (0x1UL << 6) /**< Real-Time Counter access control bit */ 300 #define _SMU_PPUPATD1_RTC_SHIFT 6 /**< Shift value for SMU_RTC */ 301 #define _SMU_PPUPATD1_RTC_MASK 0x40UL /**< Bit mask for SMU_RTC */ 302 #define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 303 #define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 304 #define SMU_PPUPATD1_RTCC (0x1UL << 7) /**< Real-Time Counter and Calendar access control bit */ 305 #define _SMU_PPUPATD1_RTCC_SHIFT 7 /**< Shift value for SMU_RTCC */ 306 #define _SMU_PPUPATD1_RTCC_MASK 0x80UL /**< Bit mask for SMU_RTCC */ 307 #define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 308 #define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 309 #define SMU_PPUPATD1_SDIO (0x1UL << 8) /**< SDIO Controller access control bit */ 310 #define _SMU_PPUPATD1_SDIO_SHIFT 8 /**< Shift value for SMU_SDIO */ 311 #define _SMU_PPUPATD1_SDIO_MASK 0x100UL /**< Bit mask for SMU_SDIO */ 312 #define _SMU_PPUPATD1_SDIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 313 #define SMU_PPUPATD1_SDIO_DEFAULT (_SMU_PPUPATD1_SDIO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 314 #define SMU_PPUPATD1_SMU (0x1UL << 9) /**< Security Management Unit access control bit */ 315 #define _SMU_PPUPATD1_SMU_SHIFT 9 /**< Shift value for SMU_SMU */ 316 #define _SMU_PPUPATD1_SMU_MASK 0x200UL /**< Bit mask for SMU_SMU */ 317 #define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 318 #define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 319 #define SMU_PPUPATD1_TIMER0 (0x1UL << 10) /**< Timer 0 access control bit */ 320 #define _SMU_PPUPATD1_TIMER0_SHIFT 10 /**< Shift value for SMU_TIMER0 */ 321 #define _SMU_PPUPATD1_TIMER0_MASK 0x400UL /**< Bit mask for SMU_TIMER0 */ 322 #define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 323 #define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 324 #define SMU_PPUPATD1_TIMER1 (0x1UL << 11) /**< Timer 1 access control bit */ 325 #define _SMU_PPUPATD1_TIMER1_SHIFT 11 /**< Shift value for SMU_TIMER1 */ 326 #define _SMU_PPUPATD1_TIMER1_MASK 0x800UL /**< Bit mask for SMU_TIMER1 */ 327 #define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 328 #define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 329 #define SMU_PPUPATD1_TIMER2 (0x1UL << 12) /**< Timer 2 access control bit */ 330 #define _SMU_PPUPATD1_TIMER2_SHIFT 12 /**< Shift value for SMU_TIMER2 */ 331 #define _SMU_PPUPATD1_TIMER2_MASK 0x1000UL /**< Bit mask for SMU_TIMER2 */ 332 #define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 333 #define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 334 #define SMU_PPUPATD1_TIMER3 (0x1UL << 13) /**< Timer 3 access control bit */ 335 #define _SMU_PPUPATD1_TIMER3_SHIFT 13 /**< Shift value for SMU_TIMER3 */ 336 #define _SMU_PPUPATD1_TIMER3_MASK 0x2000UL /**< Bit mask for SMU_TIMER3 */ 337 #define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 338 #define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 339 #define SMU_PPUPATD1_TRNG0 (0x1UL << 14) /**< True Random Number Generator 0 access control bit */ 340 #define _SMU_PPUPATD1_TRNG0_SHIFT 14 /**< Shift value for SMU_TRNG0 */ 341 #define _SMU_PPUPATD1_TRNG0_MASK 0x4000UL /**< Bit mask for SMU_TRNG0 */ 342 #define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 343 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 344 #define SMU_PPUPATD1_UART0 (0x1UL << 15) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ 345 #define _SMU_PPUPATD1_UART0_SHIFT 15 /**< Shift value for SMU_UART0 */ 346 #define _SMU_PPUPATD1_UART0_MASK 0x8000UL /**< Bit mask for SMU_UART0 */ 347 #define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 348 #define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 349 #define SMU_PPUPATD1_UART1 (0x1UL << 16) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ 350 #define _SMU_PPUPATD1_UART1_SHIFT 16 /**< Shift value for SMU_UART1 */ 351 #define _SMU_PPUPATD1_UART1_MASK 0x10000UL /**< Bit mask for SMU_UART1 */ 352 #define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 353 #define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 354 #define SMU_PPUPATD1_USART0 (0x1UL << 17) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ 355 #define _SMU_PPUPATD1_USART0_SHIFT 17 /**< Shift value for SMU_USART0 */ 356 #define _SMU_PPUPATD1_USART0_MASK 0x20000UL /**< Bit mask for SMU_USART0 */ 357 #define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 358 #define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 359 #define SMU_PPUPATD1_USART1 (0x1UL << 18) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ 360 #define _SMU_PPUPATD1_USART1_SHIFT 18 /**< Shift value for SMU_USART1 */ 361 #define _SMU_PPUPATD1_USART1_MASK 0x40000UL /**< Bit mask for SMU_USART1 */ 362 #define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 363 #define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 364 #define SMU_PPUPATD1_USART2 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ 365 #define _SMU_PPUPATD1_USART2_SHIFT 19 /**< Shift value for SMU_USART2 */ 366 #define _SMU_PPUPATD1_USART2_MASK 0x80000UL /**< Bit mask for SMU_USART2 */ 367 #define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 368 #define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 369 #define SMU_PPUPATD1_USART3 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ 370 #define _SMU_PPUPATD1_USART3_SHIFT 20 /**< Shift value for SMU_USART3 */ 371 #define _SMU_PPUPATD1_USART3_MASK 0x100000UL /**< Bit mask for SMU_USART3 */ 372 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 373 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 374 #define SMU_PPUPATD1_USART4 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ 375 #define _SMU_PPUPATD1_USART4_SHIFT 21 /**< Shift value for SMU_USART4 */ 376 #define _SMU_PPUPATD1_USART4_MASK 0x200000UL /**< Bit mask for SMU_USART4 */ 377 #define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 378 #define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 379 #define SMU_PPUPATD1_USB (0x1UL << 22) /**< Universal Serial Bus Interface access control bit */ 380 #define _SMU_PPUPATD1_USB_SHIFT 22 /**< Shift value for SMU_USB */ 381 #define _SMU_PPUPATD1_USB_MASK 0x400000UL /**< Bit mask for SMU_USB */ 382 #define _SMU_PPUPATD1_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 383 #define SMU_PPUPATD1_USB_DEFAULT (_SMU_PPUPATD1_USB_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 384 #define SMU_PPUPATD1_WDOG0 (0x1UL << 23) /**< Watchdog access control bit */ 385 #define _SMU_PPUPATD1_WDOG0_SHIFT 23 /**< Shift value for SMU_WDOG0 */ 386 #define _SMU_PPUPATD1_WDOG0_MASK 0x800000UL /**< Bit mask for SMU_WDOG0 */ 387 #define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 388 #define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 389 #define SMU_PPUPATD1_WDOG1 (0x1UL << 24) /**< Watchdog access control bit */ 390 #define _SMU_PPUPATD1_WDOG1_SHIFT 24 /**< Shift value for SMU_WDOG1 */ 391 #define _SMU_PPUPATD1_WDOG1_MASK 0x1000000UL /**< Bit mask for SMU_WDOG1 */ 392 #define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 393 #define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 394 #define SMU_PPUPATD1_WTIMER0 (0x1UL << 25) /**< Wide Timer 0 access control bit */ 395 #define _SMU_PPUPATD1_WTIMER0_SHIFT 25 /**< Shift value for SMU_WTIMER0 */ 396 #define _SMU_PPUPATD1_WTIMER0_MASK 0x2000000UL /**< Bit mask for SMU_WTIMER0 */ 397 #define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 398 #define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 399 #define SMU_PPUPATD1_WTIMER1 (0x1UL << 26) /**< Wide Timer 0 access control bit */ 400 #define _SMU_PPUPATD1_WTIMER1_SHIFT 26 /**< Shift value for SMU_WTIMER1 */ 401 #define _SMU_PPUPATD1_WTIMER1_MASK 0x4000000UL /**< Bit mask for SMU_WTIMER1 */ 402 #define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 403 #define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 404 405 /* Bit fields for SMU PPUPATD2 */ 406 #define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ 407 #define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ 408 409 /* Bit fields for SMU PPUFS */ 410 #define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ 411 #define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ 412 #define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ 413 #define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ 414 #define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ 415 #define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ 416 #define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ 417 #define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ 418 #define _SMU_PPUFS_PERIPHID_ADC0 0x00000003UL /**< Mode ADC0 for SMU_PPUFS */ 419 #define _SMU_PPUFS_PERIPHID_ADC1 0x00000004UL /**< Mode ADC1 for SMU_PPUFS */ 420 #define _SMU_PPUFS_PERIPHID_CAN0 0x00000005UL /**< Mode CAN0 for SMU_PPUFS */ 421 #define _SMU_PPUFS_PERIPHID_CAN1 0x00000006UL /**< Mode CAN1 for SMU_PPUFS */ 422 #define _SMU_PPUFS_PERIPHID_CMU 0x00000007UL /**< Mode CMU for SMU_PPUFS */ 423 #define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000008UL /**< Mode CRYOTIMER for SMU_PPUFS */ 424 #define _SMU_PPUFS_PERIPHID_CRYPTO0 0x00000009UL /**< Mode CRYPTO0 for SMU_PPUFS */ 425 #define _SMU_PPUFS_PERIPHID_CSEN 0x0000000AUL /**< Mode CSEN for SMU_PPUFS */ 426 #define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000BUL /**< Mode VDAC0 for SMU_PPUFS */ 427 #define _SMU_PPUFS_PERIPHID_PRS 0x0000000CUL /**< Mode PRS for SMU_PPUFS */ 428 #define _SMU_PPUFS_PERIPHID_EBI 0x0000000DUL /**< Mode EBI for SMU_PPUFS */ 429 #define _SMU_PPUFS_PERIPHID_EMU 0x0000000EUL /**< Mode EMU for SMU_PPUFS */ 430 #define _SMU_PPUFS_PERIPHID_FPUEH 0x0000000FUL /**< Mode FPUEH for SMU_PPUFS */ 431 #define _SMU_PPUFS_PERIPHID_GPCRC 0x00000010UL /**< Mode GPCRC for SMU_PPUFS */ 432 #define _SMU_PPUFS_PERIPHID_GPIO 0x00000011UL /**< Mode GPIO for SMU_PPUFS */ 433 #define _SMU_PPUFS_PERIPHID_I2C0 0x00000012UL /**< Mode I2C0 for SMU_PPUFS */ 434 #define _SMU_PPUFS_PERIPHID_I2C1 0x00000013UL /**< Mode I2C1 for SMU_PPUFS */ 435 #define _SMU_PPUFS_PERIPHID_IDAC0 0x00000014UL /**< Mode IDAC0 for SMU_PPUFS */ 436 #define _SMU_PPUFS_PERIPHID_MSC 0x00000015UL /**< Mode MSC for SMU_PPUFS */ 437 #define _SMU_PPUFS_PERIPHID_LCD 0x00000016UL /**< Mode LCD for SMU_PPUFS */ 438 #define _SMU_PPUFS_PERIPHID_LDMA 0x00000017UL /**< Mode LDMA for SMU_PPUFS */ 439 #define _SMU_PPUFS_PERIPHID_LESENSE 0x00000018UL /**< Mode LESENSE for SMU_PPUFS */ 440 #define _SMU_PPUFS_PERIPHID_LETIMER0 0x00000019UL /**< Mode LETIMER0 for SMU_PPUFS */ 441 #define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001AUL /**< Mode LETIMER1 for SMU_PPUFS */ 442 #define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001BUL /**< Mode LEUART0 for SMU_PPUFS */ 443 #define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001CUL /**< Mode LEUART1 for SMU_PPUFS */ 444 #define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ 445 #define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ 446 #define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ 447 #define _SMU_PPUFS_PERIPHID_PDM 0x00000023UL /**< Mode PDM for SMU_PPUFS */ 448 #define _SMU_PPUFS_PERIPHID_QSPI0 0x00000024UL /**< Mode QSPI0 for SMU_PPUFS */ 449 #define _SMU_PPUFS_PERIPHID_RMU 0x00000025UL /**< Mode RMU for SMU_PPUFS */ 450 #define _SMU_PPUFS_PERIPHID_RTC 0x00000026UL /**< Mode RTC for SMU_PPUFS */ 451 #define _SMU_PPUFS_PERIPHID_RTCC 0x00000027UL /**< Mode RTCC for SMU_PPUFS */ 452 #define _SMU_PPUFS_PERIPHID_SDIO 0x00000028UL /**< Mode SDIO for SMU_PPUFS */ 453 #define _SMU_PPUFS_PERIPHID_SMU 0x00000029UL /**< Mode SMU for SMU_PPUFS */ 454 #define _SMU_PPUFS_PERIPHID_TIMER0 0x0000002AUL /**< Mode TIMER0 for SMU_PPUFS */ 455 #define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002BUL /**< Mode TIMER1 for SMU_PPUFS */ 456 #define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002CUL /**< Mode TIMER2 for SMU_PPUFS */ 457 #define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002DUL /**< Mode TIMER3 for SMU_PPUFS */ 458 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for SMU_PPUFS */ 459 #define _SMU_PPUFS_PERIPHID_UART0 0x0000002FUL /**< Mode UART0 for SMU_PPUFS */ 460 #define _SMU_PPUFS_PERIPHID_UART1 0x00000030UL /**< Mode UART1 for SMU_PPUFS */ 461 #define _SMU_PPUFS_PERIPHID_USART0 0x00000031UL /**< Mode USART0 for SMU_PPUFS */ 462 #define _SMU_PPUFS_PERIPHID_USART1 0x00000032UL /**< Mode USART1 for SMU_PPUFS */ 463 #define _SMU_PPUFS_PERIPHID_USART2 0x00000033UL /**< Mode USART2 for SMU_PPUFS */ 464 #define _SMU_PPUFS_PERIPHID_USART3 0x00000034UL /**< Mode USART3 for SMU_PPUFS */ 465 #define _SMU_PPUFS_PERIPHID_USART4 0x00000035UL /**< Mode USART4 for SMU_PPUFS */ 466 #define _SMU_PPUFS_PERIPHID_USB 0x00000036UL /**< Mode USB for SMU_PPUFS */ 467 #define _SMU_PPUFS_PERIPHID_WDOG0 0x00000037UL /**< Mode WDOG0 for SMU_PPUFS */ 468 #define _SMU_PPUFS_PERIPHID_WDOG1 0x00000038UL /**< Mode WDOG1 for SMU_PPUFS */ 469 #define _SMU_PPUFS_PERIPHID_WTIMER0 0x00000039UL /**< Mode WTIMER0 for SMU_PPUFS */ 470 #define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003AUL /**< Mode WTIMER1 for SMU_PPUFS */ 471 #define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ 472 #define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ 473 #define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ 474 #define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ 475 #define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ 476 #define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ 477 #define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ 478 #define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ 479 #define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ 480 #define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ 481 #define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ 482 #define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ 483 #define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ 484 #define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ 485 #define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ 486 #define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ 487 #define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ 488 #define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ 489 #define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ 490 #define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ 491 #define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ 492 #define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ 493 #define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ 494 #define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ 495 #define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ 496 #define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ 497 #define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ 498 #define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ 499 #define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ 500 #define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ 501 #define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ 502 #define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ 503 #define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ 504 #define SMU_PPUFS_PERIPHID_PDM (_SMU_PPUFS_PERIPHID_PDM << 0) /**< Shifted mode PDM for SMU_PPUFS */ 505 #define SMU_PPUFS_PERIPHID_QSPI0 (_SMU_PPUFS_PERIPHID_QSPI0 << 0) /**< Shifted mode QSPI0 for SMU_PPUFS */ 506 #define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ 507 #define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ 508 #define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ 509 #define SMU_PPUFS_PERIPHID_SDIO (_SMU_PPUFS_PERIPHID_SDIO << 0) /**< Shifted mode SDIO for SMU_PPUFS */ 510 #define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ 511 #define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ 512 #define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ 513 #define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ 514 #define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ 515 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ 516 #define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ 517 #define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ 518 #define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ 519 #define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ 520 #define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ 521 #define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ 522 #define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ 523 #define SMU_PPUFS_PERIPHID_USB (_SMU_PPUFS_PERIPHID_USB << 0) /**< Shifted mode USB for SMU_PPUFS */ 524 #define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ 525 #define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ 526 #define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ 527 #define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ 528 529 /** @} */ 530 /** @} End of group EFM32GG12B_SMU */ 531 /** @} End of group Parts */ 532
