1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG12B_SDIO register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG12B_SDIO SDIO 43 * @{ 44 * @brief EFM32GG12B_SDIO Register Declaration 45 ******************************************************************************/ 46 /** SDIO Register Declaration */ 47 typedef struct { 48 __IOM uint32_t SDMASYSADDR; /**< SDMA System Address Register */ 49 __IOM uint32_t BLKSIZE; /**< Block Size and Block Count Register */ 50 __IOM uint32_t CMDARG1; /**< SD Command Argument Register */ 51 __IOM uint32_t TFRMODE; /**< Transfer Mode and Command Register */ 52 __IM uint32_t RESP0; /**< Response0 and Response1 Register */ 53 __IM uint32_t RESP2; /**< Response2 and Response3 Register */ 54 __IM uint32_t RESP4; /**< Response4 and Response5 Register */ 55 __IM uint32_t RESP6; /**< Response6 and Response7 Register */ 56 __IOM uint32_t BUFDATPORT; /**< Buffer Data Register */ 57 __IM uint32_t PRSSTAT; /**< Present State Register */ 58 __IOM uint32_t HOSTCTRL1; /**< Host Control1, Power, Block Gap and Wakeup-up Control Register */ 59 __IOM uint32_t CLOCKCTRL; /**< Clock Control, Timeout Control and Software Register */ 60 __IOM uint32_t IFCR; /**< Normal and Error Interrupt Status Register */ 61 __IOM uint32_t IFENC; /**< Normal and Error Interrupt Status Enable Register */ 62 __IOM uint32_t IEN; /**< Normal and Error Interrupt Signal Enable Register */ 63 __IOM uint32_t AC12ERRSTAT; /**< AUTO CMD12 Error Status and Host Control2 Register */ 64 __IM uint32_t CAPAB0; /**< Capabilities Register to Hold Bits 31~0 */ 65 __IM uint32_t CAPAB2; /**< Capabilities Register to Hold Bits 63~32 */ 66 __IM uint32_t MAXCURCAPAB; /**< Maximum Current Capabilities Register */ 67 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 68 __IOM uint32_t FEVTERRSTAT; /**< Force Event Register for Auto CMD Error Status */ 69 __IM uint32_t ADMAES; /**< ADMA Error Status Register */ 70 __IOM uint32_t ADSADDR; /**< ADMA System Address Register */ 71 uint32_t RESERVED1[1U]; /**< Reserved for future use **/ 72 __IM uint32_t PRSTVAL0; /**< Preset Value for Initialization and Default Speed Mode */ 73 __IM uint32_t PRSTVAL2; /**< Preset Value for High Speed and SDR12 Modes */ 74 __IM uint32_t PRSTVAL4; /**< Preset Value for SDR25 and SDR50 Modes */ 75 __IM uint32_t PRSTVAL6; /**< Preset Value for SDR104 and DDR50 Modes */ 76 __IOM uint32_t BOOTTOCTRL; /**< Boot Timeout Control Register */ 77 uint32_t RESERVED2[34U]; /**< Reserved for future use **/ 78 __IM uint32_t SLOTINTSTAT; /**< Slot Interrupt Status Register */ 79 80 uint32_t RESERVED3[448U]; /**< Reserved for future use **/ 81 __IOM uint32_t CTRL; /**< Core Control Signals */ 82 __IOM uint32_t CFG0; /**< Core Configuration 0 */ 83 __IOM uint32_t CFG1; /**< Core Configuration 1 */ 84 __IOM uint32_t CFGPRESETVAL0; /**< Core Configuration Preset Value 0 */ 85 __IOM uint32_t CFGPRESETVAL1; /**< Core Configuration Preset Value 1 */ 86 __IOM uint32_t CFGPRESETVAL2; /**< Core Configuration Preset Value 2 */ 87 __IOM uint32_t CFGPRESETVAL3; /**< Core Configuration Preset Value 3 */ 88 __IOM uint32_t ROUTELOC0; /**< I/O LOCATION Register */ 89 __IOM uint32_t ROUTELOC1; /**< I/O LOCATION Register */ 90 __IOM uint32_t ROUTEPEN; /**< I/O LOCATION Enable Register */ 91 } SDIO_TypeDef; /** @} */ 92 93 /***************************************************************************//** 94 * @addtogroup EFM32GG12B_SDIO 95 * @{ 96 * @defgroup EFM32GG12B_SDIO_BitFields SDIO Bit Fields 97 * @{ 98 ******************************************************************************/ 99 100 /* Bit fields for SDIO SDMASYSADDR */ 101 #define _SDIO_SDMASYSADDR_RESETVALUE 0x00000000UL /**< Default value for SDIO_SDMASYSADDR */ 102 #define _SDIO_SDMASYSADDR_MASK 0xFFFFFFFFUL /**< Mask for SDIO_SDMASYSADDR */ 103 #define _SDIO_SDMASYSADDR_SDMASYSADDRARG_SHIFT 0 /**< Shift value for SDIO_SDMASYSADDRARG */ 104 #define _SDIO_SDMASYSADDR_SDMASYSADDRARG_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_SDMASYSADDRARG */ 105 #define _SDIO_SDMASYSADDR_SDMASYSADDRARG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_SDMASYSADDR */ 106 #define SDIO_SDMASYSADDR_SDMASYSADDRARG_DEFAULT (_SDIO_SDMASYSADDR_SDMASYSADDRARG_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_SDMASYSADDR */ 107 108 /* Bit fields for SDIO BLKSIZE */ 109 #define _SDIO_BLKSIZE_RESETVALUE 0x00000000UL /**< Default value for SDIO_BLKSIZE */ 110 #define _SDIO_BLKSIZE_MASK 0xFFFF7FFFUL /**< Mask for SDIO_BLKSIZE */ 111 #define _SDIO_BLKSIZE_TFRBLKSIZE_SHIFT 0 /**< Shift value for SDIO_TFRBLKSIZE */ 112 #define _SDIO_BLKSIZE_TFRBLKSIZE_MASK 0xFFFUL /**< Bit mask for SDIO_TFRBLKSIZE */ 113 #define _SDIO_BLKSIZE_TFRBLKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BLKSIZE */ 114 #define _SDIO_BLKSIZE_TFRBLKSIZE_NOXFER 0x00000000UL /**< Mode NOXFER for SDIO_BLKSIZE */ 115 #define SDIO_BLKSIZE_TFRBLKSIZE_DEFAULT (_SDIO_BLKSIZE_TFRBLKSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_BLKSIZE */ 116 #define SDIO_BLKSIZE_TFRBLKSIZE_NOXFER (_SDIO_BLKSIZE_TFRBLKSIZE_NOXFER << 0) /**< Shifted mode NOXFER for SDIO_BLKSIZE */ 117 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SHIFT 12 /**< Shift value for SDIO_HSTSDMABUFSIZE */ 118 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_MASK 0x7000UL /**< Bit mask for SDIO_HSTSDMABUFSIZE */ 119 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BLKSIZE */ 120 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE4 0x00000000UL /**< Mode SIZE4 for SDIO_BLKSIZE */ 121 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE8 0x00000001UL /**< Mode SIZE8 for SDIO_BLKSIZE */ 122 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE16 0x00000002UL /**< Mode SIZE16 for SDIO_BLKSIZE */ 123 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE32 0x00000003UL /**< Mode SIZE32 for SDIO_BLKSIZE */ 124 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE64 0x00000004UL /**< Mode SIZE64 for SDIO_BLKSIZE */ 125 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE128 0x00000005UL /**< Mode SIZE128 for SDIO_BLKSIZE */ 126 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE256 0x00000006UL /**< Mode SIZE256 for SDIO_BLKSIZE */ 127 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE512 0x00000007UL /**< Mode SIZE512 for SDIO_BLKSIZE */ 128 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_DEFAULT (_SDIO_BLKSIZE_HSTSDMABUFSIZE_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_BLKSIZE */ 129 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE4 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE4 << 12) /**< Shifted mode SIZE4 for SDIO_BLKSIZE */ 130 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE8 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE8 << 12) /**< Shifted mode SIZE8 for SDIO_BLKSIZE */ 131 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE16 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE16 << 12) /**< Shifted mode SIZE16 for SDIO_BLKSIZE */ 132 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE32 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE32 << 12) /**< Shifted mode SIZE32 for SDIO_BLKSIZE */ 133 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE64 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE64 << 12) /**< Shifted mode SIZE64 for SDIO_BLKSIZE */ 134 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE128 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE128 << 12) /**< Shifted mode SIZE128 for SDIO_BLKSIZE */ 135 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE256 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE256 << 12) /**< Shifted mode SIZE256 for SDIO_BLKSIZE */ 136 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE512 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE512 << 12) /**< Shifted mode SIZE512 for SDIO_BLKSIZE */ 137 #define _SDIO_BLKSIZE_BLKSCNTFORCURRTFR_SHIFT 16 /**< Shift value for SDIO_BLKSCNTFORCURRTFR */ 138 #define _SDIO_BLKSIZE_BLKSCNTFORCURRTFR_MASK 0xFFFF0000UL /**< Bit mask for SDIO_BLKSCNTFORCURRTFR */ 139 #define _SDIO_BLKSIZE_BLKSCNTFORCURRTFR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BLKSIZE */ 140 #define _SDIO_BLKSIZE_BLKSCNTFORCURRTFR_STOPCNT 0x00000000UL /**< Mode STOPCNT for SDIO_BLKSIZE */ 141 #define SDIO_BLKSIZE_BLKSCNTFORCURRTFR_DEFAULT (_SDIO_BLKSIZE_BLKSCNTFORCURRTFR_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_BLKSIZE */ 142 #define SDIO_BLKSIZE_BLKSCNTFORCURRTFR_STOPCNT (_SDIO_BLKSIZE_BLKSCNTFORCURRTFR_STOPCNT << 16) /**< Shifted mode STOPCNT for SDIO_BLKSIZE */ 143 144 /* Bit fields for SDIO CMDARG1 */ 145 #define _SDIO_CMDARG1_RESETVALUE 0x00000000UL /**< Default value for SDIO_CMDARG1 */ 146 #define _SDIO_CMDARG1_MASK 0xFFFFFFFFUL /**< Mask for SDIO_CMDARG1 */ 147 #define _SDIO_CMDARG1_CMDARG1_SHIFT 0 /**< Shift value for SDIO_CMDARG1 */ 148 #define _SDIO_CMDARG1_CMDARG1_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDARG1 */ 149 #define _SDIO_CMDARG1_CMDARG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CMDARG1 */ 150 #define SDIO_CMDARG1_CMDARG1_DEFAULT (_SDIO_CMDARG1_CMDARG1_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CMDARG1 */ 151 152 /* Bit fields for SDIO TFRMODE */ 153 #define _SDIO_TFRMODE_RESETVALUE 0x00000000UL /**< Default value for SDIO_TFRMODE */ 154 #define _SDIO_TFRMODE_MASK 0x3FFB003FUL /**< Mask for SDIO_TFRMODE */ 155 #define SDIO_TFRMODE_DMAEN (0x1UL << 0) /**< DMA Enable */ 156 #define _SDIO_TFRMODE_DMAEN_SHIFT 0 /**< Shift value for SDIO_DMAEN */ 157 #define _SDIO_TFRMODE_DMAEN_MASK 0x1UL /**< Bit mask for SDIO_DMAEN */ 158 #define _SDIO_TFRMODE_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ 159 #define _SDIO_TFRMODE_DMAEN_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */ 160 #define _SDIO_TFRMODE_DMAEN_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */ 161 #define SDIO_TFRMODE_DMAEN_DEFAULT (_SDIO_TFRMODE_DMAEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ 162 #define SDIO_TFRMODE_DMAEN_DISABLE (_SDIO_TFRMODE_DMAEN_DISABLE << 0) /**< Shifted mode DISABLE for SDIO_TFRMODE */ 163 #define SDIO_TFRMODE_DMAEN_ENABLE (_SDIO_TFRMODE_DMAEN_ENABLE << 0) /**< Shifted mode ENABLE for SDIO_TFRMODE */ 164 #define SDIO_TFRMODE_BLKCNTEN (0x1UL << 1) /**< Block Count Enable */ 165 #define _SDIO_TFRMODE_BLKCNTEN_SHIFT 1 /**< Shift value for SDIO_BLKCNTEN */ 166 #define _SDIO_TFRMODE_BLKCNTEN_MASK 0x2UL /**< Bit mask for SDIO_BLKCNTEN */ 167 #define _SDIO_TFRMODE_BLKCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ 168 #define _SDIO_TFRMODE_BLKCNTEN_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */ 169 #define _SDIO_TFRMODE_BLKCNTEN_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */ 170 #define SDIO_TFRMODE_BLKCNTEN_DEFAULT (_SDIO_TFRMODE_BLKCNTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ 171 #define SDIO_TFRMODE_BLKCNTEN_DISABLE (_SDIO_TFRMODE_BLKCNTEN_DISABLE << 1) /**< Shifted mode DISABLE for SDIO_TFRMODE */ 172 #define SDIO_TFRMODE_BLKCNTEN_ENABLE (_SDIO_TFRMODE_BLKCNTEN_ENABLE << 1) /**< Shifted mode ENABLE for SDIO_TFRMODE */ 173 #define _SDIO_TFRMODE_AUTOCMDEN_SHIFT 2 /**< Shift value for SDIO_AUTOCMDEN */ 174 #define _SDIO_TFRMODE_AUTOCMDEN_MASK 0xCUL /**< Bit mask for SDIO_AUTOCMDEN */ 175 #define _SDIO_TFRMODE_AUTOCMDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ 176 #define _SDIO_TFRMODE_AUTOCMDEN_ACMDDISABLED 0x00000000UL /**< Mode ACMDDISABLED for SDIO_TFRMODE */ 177 #define _SDIO_TFRMODE_AUTOCMDEN_ACMD12EN 0x00000001UL /**< Mode ACMD12EN for SDIO_TFRMODE */ 178 #define _SDIO_TFRMODE_AUTOCMDEN_ACMD23EN 0x00000002UL /**< Mode ACMD23EN for SDIO_TFRMODE */ 179 #define SDIO_TFRMODE_AUTOCMDEN_DEFAULT (_SDIO_TFRMODE_AUTOCMDEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ 180 #define SDIO_TFRMODE_AUTOCMDEN_ACMDDISABLED (_SDIO_TFRMODE_AUTOCMDEN_ACMDDISABLED << 2) /**< Shifted mode ACMDDISABLED for SDIO_TFRMODE */ 181 #define SDIO_TFRMODE_AUTOCMDEN_ACMD12EN (_SDIO_TFRMODE_AUTOCMDEN_ACMD12EN << 2) /**< Shifted mode ACMD12EN for SDIO_TFRMODE */ 182 #define SDIO_TFRMODE_AUTOCMDEN_ACMD23EN (_SDIO_TFRMODE_AUTOCMDEN_ACMD23EN << 2) /**< Shifted mode ACMD23EN for SDIO_TFRMODE */ 183 #define SDIO_TFRMODE_DATDIRSEL (0x1UL << 4) /**< Data Transfer Direction Select */ 184 #define _SDIO_TFRMODE_DATDIRSEL_SHIFT 4 /**< Shift value for SDIO_DATDIRSEL */ 185 #define _SDIO_TFRMODE_DATDIRSEL_MASK 0x10UL /**< Bit mask for SDIO_DATDIRSEL */ 186 #define _SDIO_TFRMODE_DATDIRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ 187 #define _SDIO_TFRMODE_DATDIRSEL_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */ 188 #define _SDIO_TFRMODE_DATDIRSEL_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */ 189 #define SDIO_TFRMODE_DATDIRSEL_DEFAULT (_SDIO_TFRMODE_DATDIRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ 190 #define SDIO_TFRMODE_DATDIRSEL_DISABLE (_SDIO_TFRMODE_DATDIRSEL_DISABLE << 4) /**< Shifted mode DISABLE for SDIO_TFRMODE */ 191 #define SDIO_TFRMODE_DATDIRSEL_ENABLE (_SDIO_TFRMODE_DATDIRSEL_ENABLE << 4) /**< Shifted mode ENABLE for SDIO_TFRMODE */ 192 #define SDIO_TFRMODE_MULTSINGBLKSEL (0x1UL << 5) /**< Multiple or Single Block Data Transfer Selection */ 193 #define _SDIO_TFRMODE_MULTSINGBLKSEL_SHIFT 5 /**< Shift value for SDIO_MULTSINGBLKSEL */ 194 #define _SDIO_TFRMODE_MULTSINGBLKSEL_MASK 0x20UL /**< Bit mask for SDIO_MULTSINGBLKSEL */ 195 #define _SDIO_TFRMODE_MULTSINGBLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ 196 #define _SDIO_TFRMODE_MULTSINGBLKSEL_SINGLEBLK 0x00000000UL /**< Mode SINGLEBLK for SDIO_TFRMODE */ 197 #define _SDIO_TFRMODE_MULTSINGBLKSEL_MULTIBLK 0x00000001UL /**< Mode MULTIBLK for SDIO_TFRMODE */ 198 #define SDIO_TFRMODE_MULTSINGBLKSEL_DEFAULT (_SDIO_TFRMODE_MULTSINGBLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ 199 #define SDIO_TFRMODE_MULTSINGBLKSEL_SINGLEBLK (_SDIO_TFRMODE_MULTSINGBLKSEL_SINGLEBLK << 5) /**< Shifted mode SINGLEBLK for SDIO_TFRMODE */ 200 #define SDIO_TFRMODE_MULTSINGBLKSEL_MULTIBLK (_SDIO_TFRMODE_MULTSINGBLKSEL_MULTIBLK << 5) /**< Shifted mode MULTIBLK for SDIO_TFRMODE */ 201 #define _SDIO_TFRMODE_RESPTYPESEL_SHIFT 16 /**< Shift value for SDIO_RESPTYPESEL */ 202 #define _SDIO_TFRMODE_RESPTYPESEL_MASK 0x30000UL /**< Bit mask for SDIO_RESPTYPESEL */ 203 #define _SDIO_TFRMODE_RESPTYPESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ 204 #define _SDIO_TFRMODE_RESPTYPESEL_NORESP 0x00000000UL /**< Mode NORESP for SDIO_TFRMODE */ 205 #define _SDIO_TFRMODE_RESPTYPESEL_RESP136 0x00000001UL /**< Mode RESP136 for SDIO_TFRMODE */ 206 #define _SDIO_TFRMODE_RESPTYPESEL_RESP48 0x00000002UL /**< Mode RESP48 for SDIO_TFRMODE */ 207 #define _SDIO_TFRMODE_RESPTYPESEL_BUSYAFTRESP 0x00000003UL /**< Mode BUSYAFTRESP for SDIO_TFRMODE */ 208 #define SDIO_TFRMODE_RESPTYPESEL_DEFAULT (_SDIO_TFRMODE_RESPTYPESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ 209 #define SDIO_TFRMODE_RESPTYPESEL_NORESP (_SDIO_TFRMODE_RESPTYPESEL_NORESP << 16) /**< Shifted mode NORESP for SDIO_TFRMODE */ 210 #define SDIO_TFRMODE_RESPTYPESEL_RESP136 (_SDIO_TFRMODE_RESPTYPESEL_RESP136 << 16) /**< Shifted mode RESP136 for SDIO_TFRMODE */ 211 #define SDIO_TFRMODE_RESPTYPESEL_RESP48 (_SDIO_TFRMODE_RESPTYPESEL_RESP48 << 16) /**< Shifted mode RESP48 for SDIO_TFRMODE */ 212 #define SDIO_TFRMODE_RESPTYPESEL_BUSYAFTRESP (_SDIO_TFRMODE_RESPTYPESEL_BUSYAFTRESP << 16) /**< Shifted mode BUSYAFTRESP for SDIO_TFRMODE */ 213 #define SDIO_TFRMODE_CMDCRCCHKEN (0x1UL << 19) /**< Command CRC Check Enable */ 214 #define _SDIO_TFRMODE_CMDCRCCHKEN_SHIFT 19 /**< Shift value for SDIO_CMDCRCCHKEN */ 215 #define _SDIO_TFRMODE_CMDCRCCHKEN_MASK 0x80000UL /**< Bit mask for SDIO_CMDCRCCHKEN */ 216 #define _SDIO_TFRMODE_CMDCRCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ 217 #define _SDIO_TFRMODE_CMDCRCCHKEN_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */ 218 #define _SDIO_TFRMODE_CMDCRCCHKEN_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */ 219 #define SDIO_TFRMODE_CMDCRCCHKEN_DEFAULT (_SDIO_TFRMODE_CMDCRCCHKEN_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ 220 #define SDIO_TFRMODE_CMDCRCCHKEN_DISABLE (_SDIO_TFRMODE_CMDCRCCHKEN_DISABLE << 19) /**< Shifted mode DISABLE for SDIO_TFRMODE */ 221 #define SDIO_TFRMODE_CMDCRCCHKEN_ENABLE (_SDIO_TFRMODE_CMDCRCCHKEN_ENABLE << 19) /**< Shifted mode ENABLE for SDIO_TFRMODE */ 222 #define SDIO_TFRMODE_CMDINDXCHKEN (0x1UL << 20) /**< Command Index Check Enable */ 223 #define _SDIO_TFRMODE_CMDINDXCHKEN_SHIFT 20 /**< Shift value for SDIO_CMDINDXCHKEN */ 224 #define _SDIO_TFRMODE_CMDINDXCHKEN_MASK 0x100000UL /**< Bit mask for SDIO_CMDINDXCHKEN */ 225 #define _SDIO_TFRMODE_CMDINDXCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ 226 #define _SDIO_TFRMODE_CMDINDXCHKEN_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */ 227 #define _SDIO_TFRMODE_CMDINDXCHKEN_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */ 228 #define SDIO_TFRMODE_CMDINDXCHKEN_DEFAULT (_SDIO_TFRMODE_CMDINDXCHKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ 229 #define SDIO_TFRMODE_CMDINDXCHKEN_DISABLE (_SDIO_TFRMODE_CMDINDXCHKEN_DISABLE << 20) /**< Shifted mode DISABLE for SDIO_TFRMODE */ 230 #define SDIO_TFRMODE_CMDINDXCHKEN_ENABLE (_SDIO_TFRMODE_CMDINDXCHKEN_ENABLE << 20) /**< Shifted mode ENABLE for SDIO_TFRMODE */ 231 #define SDIO_TFRMODE_DATPRESSEL (0x1UL << 21) /**< Data Present Select */ 232 #define _SDIO_TFRMODE_DATPRESSEL_SHIFT 21 /**< Shift value for SDIO_DATPRESSEL */ 233 #define _SDIO_TFRMODE_DATPRESSEL_MASK 0x200000UL /**< Bit mask for SDIO_DATPRESSEL */ 234 #define _SDIO_TFRMODE_DATPRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ 235 #define _SDIO_TFRMODE_DATPRESSEL_NODATA 0x00000000UL /**< Mode NODATA for SDIO_TFRMODE */ 236 #define _SDIO_TFRMODE_DATPRESSEL_DATA 0x00000001UL /**< Mode DATA for SDIO_TFRMODE */ 237 #define SDIO_TFRMODE_DATPRESSEL_DEFAULT (_SDIO_TFRMODE_DATPRESSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ 238 #define SDIO_TFRMODE_DATPRESSEL_NODATA (_SDIO_TFRMODE_DATPRESSEL_NODATA << 21) /**< Shifted mode NODATA for SDIO_TFRMODE */ 239 #define SDIO_TFRMODE_DATPRESSEL_DATA (_SDIO_TFRMODE_DATPRESSEL_DATA << 21) /**< Shifted mode DATA for SDIO_TFRMODE */ 240 #define _SDIO_TFRMODE_CMDTYPE_SHIFT 22 /**< Shift value for SDIO_CMDTYPE */ 241 #define _SDIO_TFRMODE_CMDTYPE_MASK 0xC00000UL /**< Bit mask for SDIO_CMDTYPE */ 242 #define _SDIO_TFRMODE_CMDTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ 243 #define _SDIO_TFRMODE_CMDTYPE_NORMAL 0x00000000UL /**< Mode NORMAL for SDIO_TFRMODE */ 244 #define _SDIO_TFRMODE_CMDTYPE_SUSPEND 0x00000001UL /**< Mode SUSPEND for SDIO_TFRMODE */ 245 #define _SDIO_TFRMODE_CMDTYPE_RESUME 0x00000002UL /**< Mode RESUME for SDIO_TFRMODE */ 246 #define _SDIO_TFRMODE_CMDTYPE_ABORT 0x00000003UL /**< Mode ABORT for SDIO_TFRMODE */ 247 #define SDIO_TFRMODE_CMDTYPE_DEFAULT (_SDIO_TFRMODE_CMDTYPE_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ 248 #define SDIO_TFRMODE_CMDTYPE_NORMAL (_SDIO_TFRMODE_CMDTYPE_NORMAL << 22) /**< Shifted mode NORMAL for SDIO_TFRMODE */ 249 #define SDIO_TFRMODE_CMDTYPE_SUSPEND (_SDIO_TFRMODE_CMDTYPE_SUSPEND << 22) /**< Shifted mode SUSPEND for SDIO_TFRMODE */ 250 #define SDIO_TFRMODE_CMDTYPE_RESUME (_SDIO_TFRMODE_CMDTYPE_RESUME << 22) /**< Shifted mode RESUME for SDIO_TFRMODE */ 251 #define SDIO_TFRMODE_CMDTYPE_ABORT (_SDIO_TFRMODE_CMDTYPE_ABORT << 22) /**< Shifted mode ABORT for SDIO_TFRMODE */ 252 #define _SDIO_TFRMODE_CMDINDEX_SHIFT 24 /**< Shift value for SDIO_CMDINDEX */ 253 #define _SDIO_TFRMODE_CMDINDEX_MASK 0x3F000000UL /**< Bit mask for SDIO_CMDINDEX */ 254 #define _SDIO_TFRMODE_CMDINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ 255 #define SDIO_TFRMODE_CMDINDEX_DEFAULT (_SDIO_TFRMODE_CMDINDEX_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ 256 257 /* Bit fields for SDIO RESP0 */ 258 #define _SDIO_RESP0_RESETVALUE 0x00000000UL /**< Default value for SDIO_RESP0 */ 259 #define _SDIO_RESP0_MASK 0xFFFFFFFFUL /**< Mask for SDIO_RESP0 */ 260 #define _SDIO_RESP0_CMDRESP0_SHIFT 0 /**< Shift value for SDIO_CMDRESP0 */ 261 #define _SDIO_RESP0_CMDRESP0_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDRESP0 */ 262 #define _SDIO_RESP0_CMDRESP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_RESP0 */ 263 #define SDIO_RESP0_CMDRESP0_DEFAULT (_SDIO_RESP0_CMDRESP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_RESP0 */ 264 265 /* Bit fields for SDIO RESP2 */ 266 #define _SDIO_RESP2_RESETVALUE 0x00000000UL /**< Default value for SDIO_RESP2 */ 267 #define _SDIO_RESP2_MASK 0xFFFFFFFFUL /**< Mask for SDIO_RESP2 */ 268 #define _SDIO_RESP2_CMDRESP1_SHIFT 0 /**< Shift value for SDIO_CMDRESP1 */ 269 #define _SDIO_RESP2_CMDRESP1_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDRESP1 */ 270 #define _SDIO_RESP2_CMDRESP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_RESP2 */ 271 #define SDIO_RESP2_CMDRESP1_DEFAULT (_SDIO_RESP2_CMDRESP1_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_RESP2 */ 272 273 /* Bit fields for SDIO RESP4 */ 274 #define _SDIO_RESP4_RESETVALUE 0x00000000UL /**< Default value for SDIO_RESP4 */ 275 #define _SDIO_RESP4_MASK 0xFFFFFFFFUL /**< Mask for SDIO_RESP4 */ 276 #define _SDIO_RESP4_CMDRESP2_SHIFT 0 /**< Shift value for SDIO_CMDRESP2 */ 277 #define _SDIO_RESP4_CMDRESP2_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDRESP2 */ 278 #define _SDIO_RESP4_CMDRESP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_RESP4 */ 279 #define SDIO_RESP4_CMDRESP2_DEFAULT (_SDIO_RESP4_CMDRESP2_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_RESP4 */ 280 281 /* Bit fields for SDIO RESP6 */ 282 #define _SDIO_RESP6_RESETVALUE 0x00000000UL /**< Default value for SDIO_RESP6 */ 283 #define _SDIO_RESP6_MASK 0xFFFFFFFFUL /**< Mask for SDIO_RESP6 */ 284 #define _SDIO_RESP6_CMDRESP3_SHIFT 0 /**< Shift value for SDIO_CMDRESP3 */ 285 #define _SDIO_RESP6_CMDRESP3_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDRESP3 */ 286 #define _SDIO_RESP6_CMDRESP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_RESP6 */ 287 #define SDIO_RESP6_CMDRESP3_DEFAULT (_SDIO_RESP6_CMDRESP3_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_RESP6 */ 288 289 /* Bit fields for SDIO BUFDATPORT */ 290 #define _SDIO_BUFDATPORT_RESETVALUE 0x00000000UL /**< Default value for SDIO_BUFDATPORT */ 291 #define _SDIO_BUFDATPORT_MASK 0xFFFFFFFFUL /**< Mask for SDIO_BUFDATPORT */ 292 #define _SDIO_BUFDATPORT_BUFDAT_SHIFT 0 /**< Shift value for SDIO_BUFDAT */ 293 #define _SDIO_BUFDATPORT_BUFDAT_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_BUFDAT */ 294 #define _SDIO_BUFDATPORT_BUFDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BUFDATPORT */ 295 #define SDIO_BUFDATPORT_BUFDAT_DEFAULT (_SDIO_BUFDATPORT_BUFDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_BUFDATPORT */ 296 297 /* Bit fields for SDIO PRSSTAT */ 298 #define _SDIO_PRSSTAT_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSSTAT */ 299 #define _SDIO_PRSSTAT_MASK 0x1FFF0F0FUL /**< Mask for SDIO_PRSSTAT */ 300 #define SDIO_PRSSTAT_CMDINHIBITCMD (0x1UL << 0) /**< Command Inhibit (CMD) */ 301 #define _SDIO_PRSSTAT_CMDINHIBITCMD_SHIFT 0 /**< Shift value for SDIO_CMDINHIBITCMD */ 302 #define _SDIO_PRSSTAT_CMDINHIBITCMD_MASK 0x1UL /**< Bit mask for SDIO_CMDINHIBITCMD */ 303 #define _SDIO_PRSSTAT_CMDINHIBITCMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 304 #define SDIO_PRSSTAT_CMDINHIBITCMD_DEFAULT (_SDIO_PRSSTAT_CMDINHIBITCMD_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 305 #define SDIO_PRSSTAT_CMDINHIBITDAT (0x1UL << 1) /**< Command Inhibit (DAT) */ 306 #define _SDIO_PRSSTAT_CMDINHIBITDAT_SHIFT 1 /**< Shift value for SDIO_CMDINHIBITDAT */ 307 #define _SDIO_PRSSTAT_CMDINHIBITDAT_MASK 0x2UL /**< Bit mask for SDIO_CMDINHIBITDAT */ 308 #define _SDIO_PRSSTAT_CMDINHIBITDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 309 #define SDIO_PRSSTAT_CMDINHIBITDAT_DEFAULT (_SDIO_PRSSTAT_CMDINHIBITDAT_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 310 #define SDIO_PRSSTAT_DATLINEACTIVE (0x1UL << 2) /**< DAT Line Active */ 311 #define _SDIO_PRSSTAT_DATLINEACTIVE_SHIFT 2 /**< Shift value for SDIO_DATLINEACTIVE */ 312 #define _SDIO_PRSSTAT_DATLINEACTIVE_MASK 0x4UL /**< Bit mask for SDIO_DATLINEACTIVE */ 313 #define _SDIO_PRSSTAT_DATLINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 314 #define SDIO_PRSSTAT_DATLINEACTIVE_DEFAULT (_SDIO_PRSSTAT_DATLINEACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 315 #define SDIO_PRSSTAT_RETUNINGREQ (0x1UL << 3) /**< Re-Tuning Request */ 316 #define _SDIO_PRSSTAT_RETUNINGREQ_SHIFT 3 /**< Shift value for SDIO_RETUNINGREQ */ 317 #define _SDIO_PRSSTAT_RETUNINGREQ_MASK 0x8UL /**< Bit mask for SDIO_RETUNINGREQ */ 318 #define _SDIO_PRSSTAT_RETUNINGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 319 #define SDIO_PRSSTAT_RETUNINGREQ_DEFAULT (_SDIO_PRSSTAT_RETUNINGREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 320 #define SDIO_PRSSTAT_WRTRANACT (0x1UL << 8) /**< Write Transfer Active */ 321 #define _SDIO_PRSSTAT_WRTRANACT_SHIFT 8 /**< Shift value for SDIO_WRTRANACT */ 322 #define _SDIO_PRSSTAT_WRTRANACT_MASK 0x100UL /**< Bit mask for SDIO_WRTRANACT */ 323 #define _SDIO_PRSSTAT_WRTRANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 324 #define SDIO_PRSSTAT_WRTRANACT_DEFAULT (_SDIO_PRSSTAT_WRTRANACT_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 325 #define SDIO_PRSSTAT_RDTRANACT (0x1UL << 9) /**< Read Transfer Active */ 326 #define _SDIO_PRSSTAT_RDTRANACT_SHIFT 9 /**< Shift value for SDIO_RDTRANACT */ 327 #define _SDIO_PRSSTAT_RDTRANACT_MASK 0x200UL /**< Bit mask for SDIO_RDTRANACT */ 328 #define _SDIO_PRSSTAT_RDTRANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 329 #define SDIO_PRSSTAT_RDTRANACT_DEFAULT (_SDIO_PRSSTAT_RDTRANACT_DEFAULT << 9) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 330 #define SDIO_PRSSTAT_BUFFERWRITEENABLE (0x1UL << 10) /**< Buffer Write Enable */ 331 #define _SDIO_PRSSTAT_BUFFERWRITEENABLE_SHIFT 10 /**< Shift value for SDIO_BUFFERWRITEENABLE */ 332 #define _SDIO_PRSSTAT_BUFFERWRITEENABLE_MASK 0x400UL /**< Bit mask for SDIO_BUFFERWRITEENABLE */ 333 #define _SDIO_PRSSTAT_BUFFERWRITEENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 334 #define SDIO_PRSSTAT_BUFFERWRITEENABLE_DEFAULT (_SDIO_PRSSTAT_BUFFERWRITEENABLE_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 335 #define SDIO_PRSSTAT_BUFRDEN (0x1UL << 11) /**< Buffer Read Enable */ 336 #define _SDIO_PRSSTAT_BUFRDEN_SHIFT 11 /**< Shift value for SDIO_BUFRDEN */ 337 #define _SDIO_PRSSTAT_BUFRDEN_MASK 0x800UL /**< Bit mask for SDIO_BUFRDEN */ 338 #define _SDIO_PRSSTAT_BUFRDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 339 #define SDIO_PRSSTAT_BUFRDEN_DEFAULT (_SDIO_PRSSTAT_BUFRDEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 340 #define SDIO_PRSSTAT_CARDINS (0x1UL << 16) /**< Card Inserted Status */ 341 #define _SDIO_PRSSTAT_CARDINS_SHIFT 16 /**< Shift value for SDIO_CARDINS */ 342 #define _SDIO_PRSSTAT_CARDINS_MASK 0x10000UL /**< Bit mask for SDIO_CARDINS */ 343 #define _SDIO_PRSSTAT_CARDINS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 344 #define SDIO_PRSSTAT_CARDINS_DEFAULT (_SDIO_PRSSTAT_CARDINS_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 345 #define SDIO_PRSSTAT_CARDSTATESTABLE (0x1UL << 17) /**< Card State Stable Status */ 346 #define _SDIO_PRSSTAT_CARDSTATESTABLE_SHIFT 17 /**< Shift value for SDIO_CARDSTATESTABLE */ 347 #define _SDIO_PRSSTAT_CARDSTATESTABLE_MASK 0x20000UL /**< Bit mask for SDIO_CARDSTATESTABLE */ 348 #define _SDIO_PRSSTAT_CARDSTATESTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 349 #define SDIO_PRSSTAT_CARDSTATESTABLE_DEFAULT (_SDIO_PRSSTAT_CARDSTATESTABLE_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 350 #define SDIO_PRSSTAT_CARDDETPINLVL (0x1UL << 18) /**< Card Detect Pin Level */ 351 #define _SDIO_PRSSTAT_CARDDETPINLVL_SHIFT 18 /**< Shift value for SDIO_CARDDETPINLVL */ 352 #define _SDIO_PRSSTAT_CARDDETPINLVL_MASK 0x40000UL /**< Bit mask for SDIO_CARDDETPINLVL */ 353 #define _SDIO_PRSSTAT_CARDDETPINLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 354 #define SDIO_PRSSTAT_CARDDETPINLVL_DEFAULT (_SDIO_PRSSTAT_CARDDETPINLVL_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 355 #define SDIO_PRSSTAT_WRPROTSWPINLVL (0x1UL << 19) /**< Write Protect Switch Pin Level */ 356 #define _SDIO_PRSSTAT_WRPROTSWPINLVL_SHIFT 19 /**< Shift value for SDIO_WRPROTSWPINLVL */ 357 #define _SDIO_PRSSTAT_WRPROTSWPINLVL_MASK 0x80000UL /**< Bit mask for SDIO_WRPROTSWPINLVL */ 358 #define _SDIO_PRSSTAT_WRPROTSWPINLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 359 #define SDIO_PRSSTAT_WRPROTSWPINLVL_DEFAULT (_SDIO_PRSSTAT_WRPROTSWPINLVL_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 360 #define _SDIO_PRSSTAT_DAT3TO0SIGLVL_SHIFT 20 /**< Shift value for SDIO_DAT3TO0SIGLVL */ 361 #define _SDIO_PRSSTAT_DAT3TO0SIGLVL_MASK 0xF00000UL /**< Bit mask for SDIO_DAT3TO0SIGLVL */ 362 #define _SDIO_PRSSTAT_DAT3TO0SIGLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 363 #define SDIO_PRSSTAT_DAT3TO0SIGLVL_DEFAULT (_SDIO_PRSSTAT_DAT3TO0SIGLVL_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 364 #define SDIO_PRSSTAT_CMDSIGLVL (0x1UL << 24) /**< Command Line Signal Level */ 365 #define _SDIO_PRSSTAT_CMDSIGLVL_SHIFT 24 /**< Shift value for SDIO_CMDSIGLVL */ 366 #define _SDIO_PRSSTAT_CMDSIGLVL_MASK 0x1000000UL /**< Bit mask for SDIO_CMDSIGLVL */ 367 #define _SDIO_PRSSTAT_CMDSIGLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 368 #define SDIO_PRSSTAT_CMDSIGLVL_DEFAULT (_SDIO_PRSSTAT_CMDSIGLVL_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 369 #define _SDIO_PRSSTAT_DAT7TO4SIGLVL_SHIFT 25 /**< Shift value for SDIO_DAT7TO4SIGLVL */ 370 #define _SDIO_PRSSTAT_DAT7TO4SIGLVL_MASK 0x1E000000UL /**< Bit mask for SDIO_DAT7TO4SIGLVL */ 371 #define _SDIO_PRSSTAT_DAT7TO4SIGLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ 372 #define SDIO_PRSSTAT_DAT7TO4SIGLVL_DEFAULT (_SDIO_PRSSTAT_DAT7TO4SIGLVL_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ 373 374 /* Bit fields for SDIO HOSTCTRL1 */ 375 #define _SDIO_HOSTCTRL1_RESETVALUE 0x00800000UL /**< Default value for SDIO_HOSTCTRL1 */ 376 #define _SDIO_HOSTCTRL1_MASK 0x07FF1FFFUL /**< Mask for SDIO_HOSTCTRL1 */ 377 #define SDIO_HOSTCTRL1_LEDCTRL (0x1UL << 0) /**< LED Control */ 378 #define _SDIO_HOSTCTRL1_LEDCTRL_SHIFT 0 /**< Shift value for SDIO_LEDCTRL */ 379 #define _SDIO_HOSTCTRL1_LEDCTRL_MASK 0x1UL /**< Bit mask for SDIO_LEDCTRL */ 380 #define _SDIO_HOSTCTRL1_LEDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 381 #define _SDIO_HOSTCTRL1_LEDCTRL_LEDOFF 0x00000000UL /**< Mode LEDOFF for SDIO_HOSTCTRL1 */ 382 #define _SDIO_HOSTCTRL1_LEDCTRL_LEDON 0x00000001UL /**< Mode LEDON for SDIO_HOSTCTRL1 */ 383 #define SDIO_HOSTCTRL1_LEDCTRL_DEFAULT (_SDIO_HOSTCTRL1_LEDCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 384 #define SDIO_HOSTCTRL1_LEDCTRL_LEDOFF (_SDIO_HOSTCTRL1_LEDCTRL_LEDOFF << 0) /**< Shifted mode LEDOFF for SDIO_HOSTCTRL1 */ 385 #define SDIO_HOSTCTRL1_LEDCTRL_LEDON (_SDIO_HOSTCTRL1_LEDCTRL_LEDON << 0) /**< Shifted mode LEDON for SDIO_HOSTCTRL1 */ 386 #define SDIO_HOSTCTRL1_DATTRANWD (0x1UL << 1) /**< Data Transfer Width 1-bit or 4-bit Mode */ 387 #define _SDIO_HOSTCTRL1_DATTRANWD_SHIFT 1 /**< Shift value for SDIO_DATTRANWD */ 388 #define _SDIO_HOSTCTRL1_DATTRANWD_MASK 0x2UL /**< Bit mask for SDIO_DATTRANWD */ 389 #define _SDIO_HOSTCTRL1_DATTRANWD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 390 #define _SDIO_HOSTCTRL1_DATTRANWD_SD1 0x00000000UL /**< Mode SD1 for SDIO_HOSTCTRL1 */ 391 #define _SDIO_HOSTCTRL1_DATTRANWD_SD4 0x00000001UL /**< Mode SD4 for SDIO_HOSTCTRL1 */ 392 #define SDIO_HOSTCTRL1_DATTRANWD_DEFAULT (_SDIO_HOSTCTRL1_DATTRANWD_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 393 #define SDIO_HOSTCTRL1_DATTRANWD_SD1 (_SDIO_HOSTCTRL1_DATTRANWD_SD1 << 1) /**< Shifted mode SD1 for SDIO_HOSTCTRL1 */ 394 #define SDIO_HOSTCTRL1_DATTRANWD_SD4 (_SDIO_HOSTCTRL1_DATTRANWD_SD4 << 1) /**< Shifted mode SD4 for SDIO_HOSTCTRL1 */ 395 #define SDIO_HOSTCTRL1_HSEN (0x1UL << 2) /**< High Speed Enable */ 396 #define _SDIO_HOSTCTRL1_HSEN_SHIFT 2 /**< Shift value for SDIO_HSEN */ 397 #define _SDIO_HOSTCTRL1_HSEN_MASK 0x4UL /**< Bit mask for SDIO_HSEN */ 398 #define _SDIO_HOSTCTRL1_HSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 399 #define _SDIO_HOSTCTRL1_HSEN_NS 0x00000000UL /**< Mode NS for SDIO_HOSTCTRL1 */ 400 #define _SDIO_HOSTCTRL1_HSEN_HS 0x00000001UL /**< Mode HS for SDIO_HOSTCTRL1 */ 401 #define SDIO_HOSTCTRL1_HSEN_DEFAULT (_SDIO_HOSTCTRL1_HSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 402 #define SDIO_HOSTCTRL1_HSEN_NS (_SDIO_HOSTCTRL1_HSEN_NS << 2) /**< Shifted mode NS for SDIO_HOSTCTRL1 */ 403 #define SDIO_HOSTCTRL1_HSEN_HS (_SDIO_HOSTCTRL1_HSEN_HS << 2) /**< Shifted mode HS for SDIO_HOSTCTRL1 */ 404 #define _SDIO_HOSTCTRL1_DMASEL_SHIFT 3 /**< Shift value for SDIO_DMASEL */ 405 #define _SDIO_HOSTCTRL1_DMASEL_MASK 0x18UL /**< Bit mask for SDIO_DMASEL */ 406 #define _SDIO_HOSTCTRL1_DMASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 407 #define _SDIO_HOSTCTRL1_DMASEL_SDMA 0x00000000UL /**< Mode SDMA for SDIO_HOSTCTRL1 */ 408 #define _SDIO_HOSTCTRL1_DMASEL_ADMA1 0x00000001UL /**< Mode ADMA1 for SDIO_HOSTCTRL1 */ 409 #define _SDIO_HOSTCTRL1_DMASEL_ADMA2 0x00000002UL /**< Mode ADMA2 for SDIO_HOSTCTRL1 */ 410 #define _SDIO_HOSTCTRL1_DMASEL_64BITADMA2 0x00000003UL /**< Mode 64BITADMA2 for SDIO_HOSTCTRL1 */ 411 #define SDIO_HOSTCTRL1_DMASEL_DEFAULT (_SDIO_HOSTCTRL1_DMASEL_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 412 #define SDIO_HOSTCTRL1_DMASEL_SDMA (_SDIO_HOSTCTRL1_DMASEL_SDMA << 3) /**< Shifted mode SDMA for SDIO_HOSTCTRL1 */ 413 #define SDIO_HOSTCTRL1_DMASEL_ADMA1 (_SDIO_HOSTCTRL1_DMASEL_ADMA1 << 3) /**< Shifted mode ADMA1 for SDIO_HOSTCTRL1 */ 414 #define SDIO_HOSTCTRL1_DMASEL_ADMA2 (_SDIO_HOSTCTRL1_DMASEL_ADMA2 << 3) /**< Shifted mode ADMA2 for SDIO_HOSTCTRL1 */ 415 #define SDIO_HOSTCTRL1_DMASEL_64BITADMA2 (_SDIO_HOSTCTRL1_DMASEL_64BITADMA2 << 3) /**< Shifted mode 64BITADMA2 for SDIO_HOSTCTRL1 */ 416 #define SDIO_HOSTCTRL1_EXTDATTRANWD (0x1UL << 5) /**< Extended Data Transfer Width */ 417 #define _SDIO_HOSTCTRL1_EXTDATTRANWD_SHIFT 5 /**< Shift value for SDIO_EXTDATTRANWD */ 418 #define _SDIO_HOSTCTRL1_EXTDATTRANWD_MASK 0x20UL /**< Bit mask for SDIO_EXTDATTRANWD */ 419 #define _SDIO_HOSTCTRL1_EXTDATTRANWD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 420 #define _SDIO_HOSTCTRL1_EXTDATTRANWD_8BIT 0x00000000UL /**< Mode 8BIT for SDIO_HOSTCTRL1 */ 421 #define _SDIO_HOSTCTRL1_EXTDATTRANWD_DATXFR 0x00000001UL /**< Mode DATXFR for SDIO_HOSTCTRL1 */ 422 #define SDIO_HOSTCTRL1_EXTDATTRANWD_DEFAULT (_SDIO_HOSTCTRL1_EXTDATTRANWD_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 423 #define SDIO_HOSTCTRL1_EXTDATTRANWD_8BIT (_SDIO_HOSTCTRL1_EXTDATTRANWD_8BIT << 5) /**< Shifted mode 8BIT for SDIO_HOSTCTRL1 */ 424 #define SDIO_HOSTCTRL1_EXTDATTRANWD_DATXFR (_SDIO_HOSTCTRL1_EXTDATTRANWD_DATXFR << 5) /**< Shifted mode DATXFR for SDIO_HOSTCTRL1 */ 425 #define SDIO_HOSTCTRL1_CDTSTLVL (0x1UL << 6) /**< Card Detect Test Level */ 426 #define _SDIO_HOSTCTRL1_CDTSTLVL_SHIFT 6 /**< Shift value for SDIO_CDTSTLVL */ 427 #define _SDIO_HOSTCTRL1_CDTSTLVL_MASK 0x40UL /**< Bit mask for SDIO_CDTSTLVL */ 428 #define _SDIO_HOSTCTRL1_CDTSTLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 429 #define _SDIO_HOSTCTRL1_CDTSTLVL_NOCARD 0x00000000UL /**< Mode NOCARD for SDIO_HOSTCTRL1 */ 430 #define _SDIO_HOSTCTRL1_CDTSTLVL_CARDIN 0x00000001UL /**< Mode CARDIN for SDIO_HOSTCTRL1 */ 431 #define SDIO_HOSTCTRL1_CDTSTLVL_DEFAULT (_SDIO_HOSTCTRL1_CDTSTLVL_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 432 #define SDIO_HOSTCTRL1_CDTSTLVL_NOCARD (_SDIO_HOSTCTRL1_CDTSTLVL_NOCARD << 6) /**< Shifted mode NOCARD for SDIO_HOSTCTRL1 */ 433 #define SDIO_HOSTCTRL1_CDTSTLVL_CARDIN (_SDIO_HOSTCTRL1_CDTSTLVL_CARDIN << 6) /**< Shifted mode CARDIN for SDIO_HOSTCTRL1 */ 434 #define SDIO_HOSTCTRL1_CDSIGDET (0x1UL << 7) /**< Card Detetct Signal Detection */ 435 #define _SDIO_HOSTCTRL1_CDSIGDET_SHIFT 7 /**< Shift value for SDIO_CDSIGDET */ 436 #define _SDIO_HOSTCTRL1_CDSIGDET_MASK 0x80UL /**< Bit mask for SDIO_CDSIGDET */ 437 #define _SDIO_HOSTCTRL1_CDSIGDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 438 #define _SDIO_HOSTCTRL1_CDSIGDET_SDCD 0x00000000UL /**< Mode SDCD for SDIO_HOSTCTRL1 */ 439 #define _SDIO_HOSTCTRL1_CDSIGDET_TSTLVL 0x00000001UL /**< Mode TSTLVL for SDIO_HOSTCTRL1 */ 440 #define SDIO_HOSTCTRL1_CDSIGDET_DEFAULT (_SDIO_HOSTCTRL1_CDSIGDET_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 441 #define SDIO_HOSTCTRL1_CDSIGDET_SDCD (_SDIO_HOSTCTRL1_CDSIGDET_SDCD << 7) /**< Shifted mode SDCD for SDIO_HOSTCTRL1 */ 442 #define SDIO_HOSTCTRL1_CDSIGDET_TSTLVL (_SDIO_HOSTCTRL1_CDSIGDET_TSTLVL << 7) /**< Shifted mode TSTLVL for SDIO_HOSTCTRL1 */ 443 #define SDIO_HOSTCTRL1_SDBUSPOWER (0x1UL << 8) /**< SD Bus Power */ 444 #define _SDIO_HOSTCTRL1_SDBUSPOWER_SHIFT 8 /**< Shift value for SDIO_SDBUSPOWER */ 445 #define _SDIO_HOSTCTRL1_SDBUSPOWER_MASK 0x100UL /**< Bit mask for SDIO_SDBUSPOWER */ 446 #define _SDIO_HOSTCTRL1_SDBUSPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 447 #define SDIO_HOSTCTRL1_SDBUSPOWER_DEFAULT (_SDIO_HOSTCTRL1_SDBUSPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 448 #define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_SHIFT 9 /**< Shift value for SDIO_SDBUSVOLTSEL */ 449 #define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_MASK 0xE00UL /**< Bit mask for SDIO_SDBUSVOLTSEL */ 450 #define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 451 #define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_1P8V 0x00000005UL /**< Mode 1P8V for SDIO_HOSTCTRL1 */ 452 #define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P0V 0x00000006UL /**< Mode 3P0V for SDIO_HOSTCTRL1 */ 453 #define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P3V 0x00000007UL /**< Mode 3P3V for SDIO_HOSTCTRL1 */ 454 #define SDIO_HOSTCTRL1_SDBUSVOLTSEL_DEFAULT (_SDIO_HOSTCTRL1_SDBUSVOLTSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 455 #define SDIO_HOSTCTRL1_SDBUSVOLTSEL_1P8V (_SDIO_HOSTCTRL1_SDBUSVOLTSEL_1P8V << 9) /**< Shifted mode 1P8V for SDIO_HOSTCTRL1 */ 456 #define SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P0V (_SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P0V << 9) /**< Shifted mode 3P0V for SDIO_HOSTCTRL1 */ 457 #define SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P3V (_SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P3V << 9) /**< Shifted mode 3P3V for SDIO_HOSTCTRL1 */ 458 #define SDIO_HOSTCTRL1_HRDRST (0x1UL << 12) /**< Hardware Reset Signal */ 459 #define _SDIO_HOSTCTRL1_HRDRST_SHIFT 12 /**< Shift value for SDIO_HRDRST */ 460 #define _SDIO_HOSTCTRL1_HRDRST_MASK 0x1000UL /**< Bit mask for SDIO_HRDRST */ 461 #define _SDIO_HOSTCTRL1_HRDRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 462 #define SDIO_HOSTCTRL1_HRDRST_DEFAULT (_SDIO_HOSTCTRL1_HRDRST_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 463 #define SDIO_HOSTCTRL1_STOPATBLKGAPREQ (0x1UL << 16) /**< Stop at Block Gap Request */ 464 #define _SDIO_HOSTCTRL1_STOPATBLKGAPREQ_SHIFT 16 /**< Shift value for SDIO_STOPATBLKGAPREQ */ 465 #define _SDIO_HOSTCTRL1_STOPATBLKGAPREQ_MASK 0x10000UL /**< Bit mask for SDIO_STOPATBLKGAPREQ */ 466 #define _SDIO_HOSTCTRL1_STOPATBLKGAPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 467 #define SDIO_HOSTCTRL1_STOPATBLKGAPREQ_DEFAULT (_SDIO_HOSTCTRL1_STOPATBLKGAPREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 468 #define SDIO_HOSTCTRL1_CONTINUEREQ (0x1UL << 17) /**< Continue Request */ 469 #define _SDIO_HOSTCTRL1_CONTINUEREQ_SHIFT 17 /**< Shift value for SDIO_CONTINUEREQ */ 470 #define _SDIO_HOSTCTRL1_CONTINUEREQ_MASK 0x20000UL /**< Bit mask for SDIO_CONTINUEREQ */ 471 #define _SDIO_HOSTCTRL1_CONTINUEREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 472 #define SDIO_HOSTCTRL1_CONTINUEREQ_DEFAULT (_SDIO_HOSTCTRL1_CONTINUEREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 473 #define SDIO_HOSTCTRL1_RDWAITCTRL (0x1UL << 18) /**< Read Wait Control */ 474 #define _SDIO_HOSTCTRL1_RDWAITCTRL_SHIFT 18 /**< Shift value for SDIO_RDWAITCTRL */ 475 #define _SDIO_HOSTCTRL1_RDWAITCTRL_MASK 0x40000UL /**< Bit mask for SDIO_RDWAITCTRL */ 476 #define _SDIO_HOSTCTRL1_RDWAITCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 477 #define SDIO_HOSTCTRL1_RDWAITCTRL_DEFAULT (_SDIO_HOSTCTRL1_RDWAITCTRL_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 478 #define SDIO_HOSTCTRL1_INTATBLKGAP (0x1UL << 19) /**< Interrupt at Block Gap */ 479 #define _SDIO_HOSTCTRL1_INTATBLKGAP_SHIFT 19 /**< Shift value for SDIO_INTATBLKGAP */ 480 #define _SDIO_HOSTCTRL1_INTATBLKGAP_MASK 0x80000UL /**< Bit mask for SDIO_INTATBLKGAP */ 481 #define _SDIO_HOSTCTRL1_INTATBLKGAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 482 #define SDIO_HOSTCTRL1_INTATBLKGAP_DEFAULT (_SDIO_HOSTCTRL1_INTATBLKGAP_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 483 #define SDIO_HOSTCTRL1_SPIMODE (0x1UL << 20) /**< SPI Mode Enable */ 484 #define _SDIO_HOSTCTRL1_SPIMODE_SHIFT 20 /**< Shift value for SDIO_SPIMODE */ 485 #define _SDIO_HOSTCTRL1_SPIMODE_MASK 0x100000UL /**< Bit mask for SDIO_SPIMODE */ 486 #define _SDIO_HOSTCTRL1_SPIMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 487 #define SDIO_HOSTCTRL1_SPIMODE_DEFAULT (_SDIO_HOSTCTRL1_SPIMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 488 #define SDIO_HOSTCTRL1_BOOTEN (0x1UL << 21) /**< Boot Enable */ 489 #define _SDIO_HOSTCTRL1_BOOTEN_SHIFT 21 /**< Shift value for SDIO_BOOTEN */ 490 #define _SDIO_HOSTCTRL1_BOOTEN_MASK 0x200000UL /**< Bit mask for SDIO_BOOTEN */ 491 #define _SDIO_HOSTCTRL1_BOOTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 492 #define SDIO_HOSTCTRL1_BOOTEN_DEFAULT (_SDIO_HOSTCTRL1_BOOTEN_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 493 #define SDIO_HOSTCTRL1_ALTBOOTEN (0x1UL << 22) /**< Alternate Boot Enable */ 494 #define _SDIO_HOSTCTRL1_ALTBOOTEN_SHIFT 22 /**< Shift value for SDIO_ALTBOOTEN */ 495 #define _SDIO_HOSTCTRL1_ALTBOOTEN_MASK 0x400000UL /**< Bit mask for SDIO_ALTBOOTEN */ 496 #define _SDIO_HOSTCTRL1_ALTBOOTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 497 #define SDIO_HOSTCTRL1_ALTBOOTEN_DEFAULT (_SDIO_HOSTCTRL1_ALTBOOTEN_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 498 #define SDIO_HOSTCTRL1_BOOTACKCHK (0x1UL << 23) /**< Boot Ack Check */ 499 #define _SDIO_HOSTCTRL1_BOOTACKCHK_SHIFT 23 /**< Shift value for SDIO_BOOTACKCHK */ 500 #define _SDIO_HOSTCTRL1_BOOTACKCHK_MASK 0x800000UL /**< Bit mask for SDIO_BOOTACKCHK */ 501 #define _SDIO_HOSTCTRL1_BOOTACKCHK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 502 #define SDIO_HOSTCTRL1_BOOTACKCHK_DEFAULT (_SDIO_HOSTCTRL1_BOOTACKCHK_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 503 #define SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT (0x1UL << 24) /**< Wakeup Event Enable on Card Interrupt */ 504 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_SHIFT 24 /**< Shift value for SDIO_WKUPEVNTENONCARDINT */ 505 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_MASK 0x1000000UL /**< Bit mask for SDIO_WKUPEVNTENONCARDINT */ 506 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 507 #define SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_DEFAULT (_SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 508 #define SDIO_HOSTCTRL1_WKUPEVNTENONCINS (0x1UL << 25) /**< Wakeup Event Enable on SD Card Insertion */ 509 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCINS_SHIFT 25 /**< Shift value for SDIO_WKUPEVNTENONCINS */ 510 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCINS_MASK 0x2000000UL /**< Bit mask for SDIO_WKUPEVNTENONCINS */ 511 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCINS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 512 #define SDIO_HOSTCTRL1_WKUPEVNTENONCINS_DEFAULT (_SDIO_HOSTCTRL1_WKUPEVNTENONCINS_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 513 #define SDIO_HOSTCTRL1_WKUPEVNTENONCRM (0x1UL << 26) /**< Wakeup Event Enable on SD Card Removal */ 514 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCRM_SHIFT 26 /**< Shift value for SDIO_WKUPEVNTENONCRM */ 515 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCRM_MASK 0x4000000UL /**< Bit mask for SDIO_WKUPEVNTENONCRM */ 516 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ 517 #define SDIO_HOSTCTRL1_WKUPEVNTENONCRM_DEFAULT (_SDIO_HOSTCTRL1_WKUPEVNTENONCRM_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ 518 519 /* Bit fields for SDIO CLOCKCTRL */ 520 #define _SDIO_CLOCKCTRL_RESETVALUE 0x00000000UL /**< Default value for SDIO_CLOCKCTRL */ 521 #define _SDIO_CLOCKCTRL_MASK 0x070FFFE7UL /**< Mask for SDIO_CLOCKCTRL */ 522 #define SDIO_CLOCKCTRL_INTCLKEN (0x1UL << 0) /**< Internal Clock Enable */ 523 #define _SDIO_CLOCKCTRL_INTCLKEN_SHIFT 0 /**< Shift value for SDIO_INTCLKEN */ 524 #define _SDIO_CLOCKCTRL_INTCLKEN_MASK 0x1UL /**< Bit mask for SDIO_INTCLKEN */ 525 #define _SDIO_CLOCKCTRL_INTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ 526 #define SDIO_CLOCKCTRL_INTCLKEN_DEFAULT (_SDIO_CLOCKCTRL_INTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ 527 #define SDIO_CLOCKCTRL_INTCLKSTABLE (0x1UL << 1) /**< Internal Clock Stable */ 528 #define _SDIO_CLOCKCTRL_INTCLKSTABLE_SHIFT 1 /**< Shift value for SDIO_INTCLKSTABLE */ 529 #define _SDIO_CLOCKCTRL_INTCLKSTABLE_MASK 0x2UL /**< Bit mask for SDIO_INTCLKSTABLE */ 530 #define _SDIO_CLOCKCTRL_INTCLKSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ 531 #define SDIO_CLOCKCTRL_INTCLKSTABLE_DEFAULT (_SDIO_CLOCKCTRL_INTCLKSTABLE_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ 532 #define SDIO_CLOCKCTRL_SDCLKEN (0x1UL << 2) /**< SDIO_CLK Pin Clock Enable */ 533 #define _SDIO_CLOCKCTRL_SDCLKEN_SHIFT 2 /**< Shift value for SDIO_SDCLKEN */ 534 #define _SDIO_CLOCKCTRL_SDCLKEN_MASK 0x4UL /**< Bit mask for SDIO_SDCLKEN */ 535 #define _SDIO_CLOCKCTRL_SDCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ 536 #define SDIO_CLOCKCTRL_SDCLKEN_DEFAULT (_SDIO_CLOCKCTRL_SDCLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ 537 #define SDIO_CLOCKCTRL_CLKGENSEL (0x1UL << 5) /**< Clock Generator Select */ 538 #define _SDIO_CLOCKCTRL_CLKGENSEL_SHIFT 5 /**< Shift value for SDIO_CLKGENSEL */ 539 #define _SDIO_CLOCKCTRL_CLKGENSEL_MASK 0x20UL /**< Bit mask for SDIO_CLKGENSEL */ 540 #define _SDIO_CLOCKCTRL_CLKGENSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ 541 #define SDIO_CLOCKCTRL_CLKGENSEL_DEFAULT (_SDIO_CLOCKCTRL_CLKGENSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ 542 #define _SDIO_CLOCKCTRL_UPPSDCLKFRE_SHIFT 6 /**< Shift value for SDIO_UPPSDCLKFRE */ 543 #define _SDIO_CLOCKCTRL_UPPSDCLKFRE_MASK 0xC0UL /**< Bit mask for SDIO_UPPSDCLKFRE */ 544 #define _SDIO_CLOCKCTRL_UPPSDCLKFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ 545 #define SDIO_CLOCKCTRL_UPPSDCLKFRE_DEFAULT (_SDIO_CLOCKCTRL_UPPSDCLKFRE_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ 546 #define _SDIO_CLOCKCTRL_SDCLKFREQSEL_SHIFT 8 /**< Shift value for SDIO_SDCLKFREQSEL */ 547 #define _SDIO_CLOCKCTRL_SDCLKFREQSEL_MASK 0xFF00UL /**< Bit mask for SDIO_SDCLKFREQSEL */ 548 #define _SDIO_CLOCKCTRL_SDCLKFREQSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ 549 #define _SDIO_CLOCKCTRL_SDCLKFREQSEL_NODIVISION 0x00000000UL /**< Mode NODIVISION for SDIO_CLOCKCTRL */ 550 #define SDIO_CLOCKCTRL_SDCLKFREQSEL_DEFAULT (_SDIO_CLOCKCTRL_SDCLKFREQSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ 551 #define SDIO_CLOCKCTRL_SDCLKFREQSEL_NODIVISION (_SDIO_CLOCKCTRL_SDCLKFREQSEL_NODIVISION << 8) /**< Shifted mode NODIVISION for SDIO_CLOCKCTRL */ 552 #define _SDIO_CLOCKCTRL_DATTOUTCNTVAL_SHIFT 16 /**< Shift value for SDIO_DATTOUTCNTVAL */ 553 #define _SDIO_CLOCKCTRL_DATTOUTCNTVAL_MASK 0xF0000UL /**< Bit mask for SDIO_DATTOUTCNTVAL */ 554 #define _SDIO_CLOCKCTRL_DATTOUTCNTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ 555 #define SDIO_CLOCKCTRL_DATTOUTCNTVAL_DEFAULT (_SDIO_CLOCKCTRL_DATTOUTCNTVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ 556 #define SDIO_CLOCKCTRL_SFTRSTA (0x1UL << 24) /**< Software Reset for All */ 557 #define _SDIO_CLOCKCTRL_SFTRSTA_SHIFT 24 /**< Shift value for SDIO_SFTRSTA */ 558 #define _SDIO_CLOCKCTRL_SFTRSTA_MASK 0x1000000UL /**< Bit mask for SDIO_SFTRSTA */ 559 #define _SDIO_CLOCKCTRL_SFTRSTA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ 560 #define SDIO_CLOCKCTRL_SFTRSTA_DEFAULT (_SDIO_CLOCKCTRL_SFTRSTA_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ 561 #define SDIO_CLOCKCTRL_SFTRSTCMD (0x1UL << 25) /**< Software Reset for CMD Line */ 562 #define _SDIO_CLOCKCTRL_SFTRSTCMD_SHIFT 25 /**< Shift value for SDIO_SFTRSTCMD */ 563 #define _SDIO_CLOCKCTRL_SFTRSTCMD_MASK 0x2000000UL /**< Bit mask for SDIO_SFTRSTCMD */ 564 #define _SDIO_CLOCKCTRL_SFTRSTCMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ 565 #define SDIO_CLOCKCTRL_SFTRSTCMD_DEFAULT (_SDIO_CLOCKCTRL_SFTRSTCMD_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ 566 #define SDIO_CLOCKCTRL_SFTRSTDAT (0x1UL << 26) /**< Software Reset for DAT Line */ 567 #define _SDIO_CLOCKCTRL_SFTRSTDAT_SHIFT 26 /**< Shift value for SDIO_SFTRSTDAT */ 568 #define _SDIO_CLOCKCTRL_SFTRSTDAT_MASK 0x4000000UL /**< Bit mask for SDIO_SFTRSTDAT */ 569 #define _SDIO_CLOCKCTRL_SFTRSTDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ 570 #define SDIO_CLOCKCTRL_SFTRSTDAT_DEFAULT (_SDIO_CLOCKCTRL_SFTRSTDAT_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ 571 572 /* Bit fields for SDIO IFCR */ 573 #define _SDIO_IFCR_RESETVALUE 0x00000000UL /**< Default value for SDIO_IFCR */ 574 #define _SDIO_IFCR_MASK 0x13FFF1FFUL /**< Mask for SDIO_IFCR */ 575 #define SDIO_IFCR_CMDCOM (0x1UL << 0) /**< Command Complete */ 576 #define _SDIO_IFCR_CMDCOM_SHIFT 0 /**< Shift value for SDIO_CMDCOM */ 577 #define _SDIO_IFCR_CMDCOM_MASK 0x1UL /**< Bit mask for SDIO_CMDCOM */ 578 #define _SDIO_IFCR_CMDCOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 579 #define SDIO_IFCR_CMDCOM_DEFAULT (_SDIO_IFCR_CMDCOM_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_IFCR */ 580 #define SDIO_IFCR_TRANCOM (0x1UL << 1) /**< Transfer Complete */ 581 #define _SDIO_IFCR_TRANCOM_SHIFT 1 /**< Shift value for SDIO_TRANCOM */ 582 #define _SDIO_IFCR_TRANCOM_MASK 0x2UL /**< Bit mask for SDIO_TRANCOM */ 583 #define _SDIO_IFCR_TRANCOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 584 #define SDIO_IFCR_TRANCOM_DEFAULT (_SDIO_IFCR_TRANCOM_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_IFCR */ 585 #define SDIO_IFCR_BLKGAPEVT (0x1UL << 2) /**< Block Gap Event */ 586 #define _SDIO_IFCR_BLKGAPEVT_SHIFT 2 /**< Shift value for SDIO_BLKGAPEVT */ 587 #define _SDIO_IFCR_BLKGAPEVT_MASK 0x4UL /**< Bit mask for SDIO_BLKGAPEVT */ 588 #define _SDIO_IFCR_BLKGAPEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 589 #define SDIO_IFCR_BLKGAPEVT_DEFAULT (_SDIO_IFCR_BLKGAPEVT_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_IFCR */ 590 #define SDIO_IFCR_DMAINT (0x1UL << 3) /**< DMA Interrupt */ 591 #define _SDIO_IFCR_DMAINT_SHIFT 3 /**< Shift value for SDIO_DMAINT */ 592 #define _SDIO_IFCR_DMAINT_MASK 0x8UL /**< Bit mask for SDIO_DMAINT */ 593 #define _SDIO_IFCR_DMAINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 594 #define SDIO_IFCR_DMAINT_DEFAULT (_SDIO_IFCR_DMAINT_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_IFCR */ 595 #define SDIO_IFCR_BFRWRRDY (0x1UL << 4) /**< Buffer Write Ready */ 596 #define _SDIO_IFCR_BFRWRRDY_SHIFT 4 /**< Shift value for SDIO_BFRWRRDY */ 597 #define _SDIO_IFCR_BFRWRRDY_MASK 0x10UL /**< Bit mask for SDIO_BFRWRRDY */ 598 #define _SDIO_IFCR_BFRWRRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 599 #define SDIO_IFCR_BFRWRRDY_DEFAULT (_SDIO_IFCR_BFRWRRDY_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_IFCR */ 600 #define SDIO_IFCR_BFRRDRDY (0x1UL << 5) /**< Buffer Read Ready */ 601 #define _SDIO_IFCR_BFRRDRDY_SHIFT 5 /**< Shift value for SDIO_BFRRDRDY */ 602 #define _SDIO_IFCR_BFRRDRDY_MASK 0x20UL /**< Bit mask for SDIO_BFRRDRDY */ 603 #define _SDIO_IFCR_BFRRDRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 604 #define SDIO_IFCR_BFRRDRDY_DEFAULT (_SDIO_IFCR_BFRRDRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_IFCR */ 605 #define SDIO_IFCR_CARDINS (0x1UL << 6) /**< Card Insertion */ 606 #define _SDIO_IFCR_CARDINS_SHIFT 6 /**< Shift value for SDIO_CARDINS */ 607 #define _SDIO_IFCR_CARDINS_MASK 0x40UL /**< Bit mask for SDIO_CARDINS */ 608 #define _SDIO_IFCR_CARDINS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 609 #define SDIO_IFCR_CARDINS_DEFAULT (_SDIO_IFCR_CARDINS_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_IFCR */ 610 #define SDIO_IFCR_CARDRM (0x1UL << 7) /**< Card Removal */ 611 #define _SDIO_IFCR_CARDRM_SHIFT 7 /**< Shift value for SDIO_CARDRM */ 612 #define _SDIO_IFCR_CARDRM_MASK 0x80UL /**< Bit mask for SDIO_CARDRM */ 613 #define _SDIO_IFCR_CARDRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 614 #define SDIO_IFCR_CARDRM_DEFAULT (_SDIO_IFCR_CARDRM_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_IFCR */ 615 #define SDIO_IFCR_CARDINT (0x1UL << 8) /**< Card Interrupt */ 616 #define _SDIO_IFCR_CARDINT_SHIFT 8 /**< Shift value for SDIO_CARDINT */ 617 #define _SDIO_IFCR_CARDINT_MASK 0x100UL /**< Bit mask for SDIO_CARDINT */ 618 #define _SDIO_IFCR_CARDINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 619 #define SDIO_IFCR_CARDINT_DEFAULT (_SDIO_IFCR_CARDINT_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_IFCR */ 620 #define SDIO_IFCR_RETUNINGEVT (0x1UL << 12) /**< Re-Tunning Event */ 621 #define _SDIO_IFCR_RETUNINGEVT_SHIFT 12 /**< Shift value for SDIO_RETUNINGEVT */ 622 #define _SDIO_IFCR_RETUNINGEVT_MASK 0x1000UL /**< Bit mask for SDIO_RETUNINGEVT */ 623 #define _SDIO_IFCR_RETUNINGEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 624 #define SDIO_IFCR_RETUNINGEVT_DEFAULT (_SDIO_IFCR_RETUNINGEVT_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_IFCR */ 625 #define SDIO_IFCR_BOOTACKRCV (0x1UL << 13) /**< Boot Ack Received */ 626 #define _SDIO_IFCR_BOOTACKRCV_SHIFT 13 /**< Shift value for SDIO_BOOTACKRCV */ 627 #define _SDIO_IFCR_BOOTACKRCV_MASK 0x2000UL /**< Bit mask for SDIO_BOOTACKRCV */ 628 #define _SDIO_IFCR_BOOTACKRCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 629 #define SDIO_IFCR_BOOTACKRCV_DEFAULT (_SDIO_IFCR_BOOTACKRCV_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_IFCR */ 630 #define SDIO_IFCR_BOOTTERMINATE (0x1UL << 14) /**< Boot Terminate Interrupt */ 631 #define _SDIO_IFCR_BOOTTERMINATE_SHIFT 14 /**< Shift value for SDIO_BOOTTERMINATE */ 632 #define _SDIO_IFCR_BOOTTERMINATE_MASK 0x4000UL /**< Bit mask for SDIO_BOOTTERMINATE */ 633 #define _SDIO_IFCR_BOOTTERMINATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 634 #define SDIO_IFCR_BOOTTERMINATE_DEFAULT (_SDIO_IFCR_BOOTTERMINATE_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_IFCR */ 635 #define SDIO_IFCR_ERRINT (0x1UL << 15) /**< Error Interrupt */ 636 #define _SDIO_IFCR_ERRINT_SHIFT 15 /**< Shift value for SDIO_ERRINT */ 637 #define _SDIO_IFCR_ERRINT_MASK 0x8000UL /**< Bit mask for SDIO_ERRINT */ 638 #define _SDIO_IFCR_ERRINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 639 #define SDIO_IFCR_ERRINT_DEFAULT (_SDIO_IFCR_ERRINT_DEFAULT << 15) /**< Shifted mode DEFAULT for SDIO_IFCR */ 640 #define SDIO_IFCR_CMDTOUTERR (0x1UL << 16) /**< Command Timeout Error */ 641 #define _SDIO_IFCR_CMDTOUTERR_SHIFT 16 /**< Shift value for SDIO_CMDTOUTERR */ 642 #define _SDIO_IFCR_CMDTOUTERR_MASK 0x10000UL /**< Bit mask for SDIO_CMDTOUTERR */ 643 #define _SDIO_IFCR_CMDTOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 644 #define SDIO_IFCR_CMDTOUTERR_DEFAULT (_SDIO_IFCR_CMDTOUTERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_IFCR */ 645 #define SDIO_IFCR_CMDCRCERR (0x1UL << 17) /**< CMD CRC Error */ 646 #define _SDIO_IFCR_CMDCRCERR_SHIFT 17 /**< Shift value for SDIO_CMDCRCERR */ 647 #define _SDIO_IFCR_CMDCRCERR_MASK 0x20000UL /**< Bit mask for SDIO_CMDCRCERR */ 648 #define _SDIO_IFCR_CMDCRCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 649 #define SDIO_IFCR_CMDCRCERR_DEFAULT (_SDIO_IFCR_CMDCRCERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_IFCR */ 650 #define SDIO_IFCR_CMDENDBITERR (0x1UL << 18) /**< Command End Bit Error */ 651 #define _SDIO_IFCR_CMDENDBITERR_SHIFT 18 /**< Shift value for SDIO_CMDENDBITERR */ 652 #define _SDIO_IFCR_CMDENDBITERR_MASK 0x40000UL /**< Bit mask for SDIO_CMDENDBITERR */ 653 #define _SDIO_IFCR_CMDENDBITERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 654 #define SDIO_IFCR_CMDENDBITERR_DEFAULT (_SDIO_IFCR_CMDENDBITERR_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_IFCR */ 655 #define SDIO_IFCR_CMDINDEXERR (0x1UL << 19) /**< Command Index Error */ 656 #define _SDIO_IFCR_CMDINDEXERR_SHIFT 19 /**< Shift value for SDIO_CMDINDEXERR */ 657 #define _SDIO_IFCR_CMDINDEXERR_MASK 0x80000UL /**< Bit mask for SDIO_CMDINDEXERR */ 658 #define _SDIO_IFCR_CMDINDEXERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 659 #define SDIO_IFCR_CMDINDEXERR_DEFAULT (_SDIO_IFCR_CMDINDEXERR_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_IFCR */ 660 #define SDIO_IFCR_DATTOUTERR (0x1UL << 20) /**< Data Time-out Error */ 661 #define _SDIO_IFCR_DATTOUTERR_SHIFT 20 /**< Shift value for SDIO_DATTOUTERR */ 662 #define _SDIO_IFCR_DATTOUTERR_MASK 0x100000UL /**< Bit mask for SDIO_DATTOUTERR */ 663 #define _SDIO_IFCR_DATTOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 664 #define SDIO_IFCR_DATTOUTERR_DEFAULT (_SDIO_IFCR_DATTOUTERR_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_IFCR */ 665 #define SDIO_IFCR_DATCRCERR (0x1UL << 21) /**< Data CRC Error */ 666 #define _SDIO_IFCR_DATCRCERR_SHIFT 21 /**< Shift value for SDIO_DATCRCERR */ 667 #define _SDIO_IFCR_DATCRCERR_MASK 0x200000UL /**< Bit mask for SDIO_DATCRCERR */ 668 #define _SDIO_IFCR_DATCRCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 669 #define SDIO_IFCR_DATCRCERR_DEFAULT (_SDIO_IFCR_DATCRCERR_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_IFCR */ 670 #define SDIO_IFCR_DATENDBITERR (0x1UL << 22) /**< Data End Bit Error */ 671 #define _SDIO_IFCR_DATENDBITERR_SHIFT 22 /**< Shift value for SDIO_DATENDBITERR */ 672 #define _SDIO_IFCR_DATENDBITERR_MASK 0x400000UL /**< Bit mask for SDIO_DATENDBITERR */ 673 #define _SDIO_IFCR_DATENDBITERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 674 #define SDIO_IFCR_DATENDBITERR_DEFAULT (_SDIO_IFCR_DATENDBITERR_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_IFCR */ 675 #define SDIO_IFCR_CURRENTLIMITERR (0x1UL << 23) /**< Current Limit Error */ 676 #define _SDIO_IFCR_CURRENTLIMITERR_SHIFT 23 /**< Shift value for SDIO_CURRENTLIMITERR */ 677 #define _SDIO_IFCR_CURRENTLIMITERR_MASK 0x800000UL /**< Bit mask for SDIO_CURRENTLIMITERR */ 678 #define _SDIO_IFCR_CURRENTLIMITERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 679 #define SDIO_IFCR_CURRENTLIMITERR_DEFAULT (_SDIO_IFCR_CURRENTLIMITERR_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_IFCR */ 680 #define SDIO_IFCR_AUTOCMDERR (0x1UL << 24) /**< Auto CMD Error */ 681 #define _SDIO_IFCR_AUTOCMDERR_SHIFT 24 /**< Shift value for SDIO_AUTOCMDERR */ 682 #define _SDIO_IFCR_AUTOCMDERR_MASK 0x1000000UL /**< Bit mask for SDIO_AUTOCMDERR */ 683 #define _SDIO_IFCR_AUTOCMDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 684 #define SDIO_IFCR_AUTOCMDERR_DEFAULT (_SDIO_IFCR_AUTOCMDERR_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_IFCR */ 685 #define SDIO_IFCR_ADMAERR (0x1UL << 25) /**< ADMA Error */ 686 #define _SDIO_IFCR_ADMAERR_SHIFT 25 /**< Shift value for SDIO_ADMAERR */ 687 #define _SDIO_IFCR_ADMAERR_MASK 0x2000000UL /**< Bit mask for SDIO_ADMAERR */ 688 #define _SDIO_IFCR_ADMAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 689 #define SDIO_IFCR_ADMAERR_DEFAULT (_SDIO_IFCR_ADMAERR_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_IFCR */ 690 #define SDIO_IFCR_TARGETRESP (0x1UL << 28) /**< Specific Error STAT */ 691 #define _SDIO_IFCR_TARGETRESP_SHIFT 28 /**< Shift value for SDIO_TARGETRESP */ 692 #define _SDIO_IFCR_TARGETRESP_MASK 0x10000000UL /**< Bit mask for SDIO_TARGETRESP */ 693 #define _SDIO_IFCR_TARGETRESP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ 694 #define SDIO_IFCR_TARGETRESP_DEFAULT (_SDIO_IFCR_TARGETRESP_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_IFCR */ 695 696 /* Bit fields for SDIO IFENC */ 697 #define _SDIO_IFENC_RESETVALUE 0x00000000UL /**< Default value for SDIO_IFENC */ 698 #define _SDIO_IFENC_MASK 0x17FF71FFUL /**< Mask for SDIO_IFENC */ 699 #define SDIO_IFENC_CMDCOMEN (0x1UL << 0) /**< Command Complete Signal Enable */ 700 #define _SDIO_IFENC_CMDCOMEN_SHIFT 0 /**< Shift value for SDIO_CMDCOMEN */ 701 #define _SDIO_IFENC_CMDCOMEN_MASK 0x1UL /**< Bit mask for SDIO_CMDCOMEN */ 702 #define _SDIO_IFENC_CMDCOMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 703 #define SDIO_IFENC_CMDCOMEN_DEFAULT (_SDIO_IFENC_CMDCOMEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_IFENC */ 704 #define SDIO_IFENC_TRANCOMEN (0x1UL << 1) /**< Transfer Complete Signal Enable */ 705 #define _SDIO_IFENC_TRANCOMEN_SHIFT 1 /**< Shift value for SDIO_TRANCOMEN */ 706 #define _SDIO_IFENC_TRANCOMEN_MASK 0x2UL /**< Bit mask for SDIO_TRANCOMEN */ 707 #define _SDIO_IFENC_TRANCOMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 708 #define SDIO_IFENC_TRANCOMEN_DEFAULT (_SDIO_IFENC_TRANCOMEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_IFENC */ 709 #define SDIO_IFENC_BLKGAPEVTEN (0x1UL << 2) /**< Block Gap Event Signal Enable */ 710 #define _SDIO_IFENC_BLKGAPEVTEN_SHIFT 2 /**< Shift value for SDIO_BLKGAPEVTEN */ 711 #define _SDIO_IFENC_BLKGAPEVTEN_MASK 0x4UL /**< Bit mask for SDIO_BLKGAPEVTEN */ 712 #define _SDIO_IFENC_BLKGAPEVTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 713 #define SDIO_IFENC_BLKGAPEVTEN_DEFAULT (_SDIO_IFENC_BLKGAPEVTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_IFENC */ 714 #define SDIO_IFENC_DMAINTEN (0x1UL << 3) /**< DMA Interrupt Signal Enable */ 715 #define _SDIO_IFENC_DMAINTEN_SHIFT 3 /**< Shift value for SDIO_DMAINTEN */ 716 #define _SDIO_IFENC_DMAINTEN_MASK 0x8UL /**< Bit mask for SDIO_DMAINTEN */ 717 #define _SDIO_IFENC_DMAINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 718 #define SDIO_IFENC_DMAINTEN_DEFAULT (_SDIO_IFENC_DMAINTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_IFENC */ 719 #define SDIO_IFENC_BUFWRRDYEN (0x1UL << 4) /**< Buffer Write Ready Signal Enable */ 720 #define _SDIO_IFENC_BUFWRRDYEN_SHIFT 4 /**< Shift value for SDIO_BUFWRRDYEN */ 721 #define _SDIO_IFENC_BUFWRRDYEN_MASK 0x10UL /**< Bit mask for SDIO_BUFWRRDYEN */ 722 #define _SDIO_IFENC_BUFWRRDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 723 #define SDIO_IFENC_BUFWRRDYEN_DEFAULT (_SDIO_IFENC_BUFWRRDYEN_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_IFENC */ 724 #define SDIO_IFENC_BUFRDRDYEN (0x1UL << 5) /**< Buffer Read Ready Signal Enable */ 725 #define _SDIO_IFENC_BUFRDRDYEN_SHIFT 5 /**< Shift value for SDIO_BUFRDRDYEN */ 726 #define _SDIO_IFENC_BUFRDRDYEN_MASK 0x20UL /**< Bit mask for SDIO_BUFRDRDYEN */ 727 #define _SDIO_IFENC_BUFRDRDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 728 #define SDIO_IFENC_BUFRDRDYEN_DEFAULT (_SDIO_IFENC_BUFRDRDYEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_IFENC */ 729 #define SDIO_IFENC_CARDINSEN (0x1UL << 6) /**< Card Insertion Signal Enable */ 730 #define _SDIO_IFENC_CARDINSEN_SHIFT 6 /**< Shift value for SDIO_CARDINSEN */ 731 #define _SDIO_IFENC_CARDINSEN_MASK 0x40UL /**< Bit mask for SDIO_CARDINSEN */ 732 #define _SDIO_IFENC_CARDINSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 733 #define SDIO_IFENC_CARDINSEN_DEFAULT (_SDIO_IFENC_CARDINSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_IFENC */ 734 #define SDIO_IFENC_CARDRMEN (0x1UL << 7) /**< Card Removal Signal Enable */ 735 #define _SDIO_IFENC_CARDRMEN_SHIFT 7 /**< Shift value for SDIO_CARDRMEN */ 736 #define _SDIO_IFENC_CARDRMEN_MASK 0x80UL /**< Bit mask for SDIO_CARDRMEN */ 737 #define _SDIO_IFENC_CARDRMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 738 #define SDIO_IFENC_CARDRMEN_DEFAULT (_SDIO_IFENC_CARDRMEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_IFENC */ 739 #define SDIO_IFENC_CARDINTEN (0x1UL << 8) /**< Card Interrupt Signal Enable */ 740 #define _SDIO_IFENC_CARDINTEN_SHIFT 8 /**< Shift value for SDIO_CARDINTEN */ 741 #define _SDIO_IFENC_CARDINTEN_MASK 0x100UL /**< Bit mask for SDIO_CARDINTEN */ 742 #define _SDIO_IFENC_CARDINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 743 #define SDIO_IFENC_CARDINTEN_DEFAULT (_SDIO_IFENC_CARDINTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_IFENC */ 744 #define SDIO_IFENC_RETUNINGEVTEN (0x1UL << 12) /**< Re-Tunning Event Signal Enable */ 745 #define _SDIO_IFENC_RETUNINGEVTEN_SHIFT 12 /**< Shift value for SDIO_RETUNINGEVTEN */ 746 #define _SDIO_IFENC_RETUNINGEVTEN_MASK 0x1000UL /**< Bit mask for SDIO_RETUNINGEVTEN */ 747 #define _SDIO_IFENC_RETUNINGEVTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 748 #define SDIO_IFENC_RETUNINGEVTEN_DEFAULT (_SDIO_IFENC_RETUNINGEVTEN_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_IFENC */ 749 #define SDIO_IFENC_BOOTACKRCVEN (0x1UL << 13) /**< Boot Ack Received Signal Enable */ 750 #define _SDIO_IFENC_BOOTACKRCVEN_SHIFT 13 /**< Shift value for SDIO_BOOTACKRCVEN */ 751 #define _SDIO_IFENC_BOOTACKRCVEN_MASK 0x2000UL /**< Bit mask for SDIO_BOOTACKRCVEN */ 752 #define _SDIO_IFENC_BOOTACKRCVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 753 #define SDIO_IFENC_BOOTACKRCVEN_DEFAULT (_SDIO_IFENC_BOOTACKRCVEN_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_IFENC */ 754 #define SDIO_IFENC_BOOTTERMINATEEN (0x1UL << 14) /**< Boot Terminate Interrupt Signal Enable */ 755 #define _SDIO_IFENC_BOOTTERMINATEEN_SHIFT 14 /**< Shift value for SDIO_BOOTTERMINATEEN */ 756 #define _SDIO_IFENC_BOOTTERMINATEEN_MASK 0x4000UL /**< Bit mask for SDIO_BOOTTERMINATEEN */ 757 #define _SDIO_IFENC_BOOTTERMINATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 758 #define SDIO_IFENC_BOOTTERMINATEEN_DEFAULT (_SDIO_IFENC_BOOTTERMINATEEN_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_IFENC */ 759 #define SDIO_IFENC_CMDTOUTERREN (0x1UL << 16) /**< Command Time-out Error Status Enable */ 760 #define _SDIO_IFENC_CMDTOUTERREN_SHIFT 16 /**< Shift value for SDIO_CMDTOUTERREN */ 761 #define _SDIO_IFENC_CMDTOUTERREN_MASK 0x10000UL /**< Bit mask for SDIO_CMDTOUTERREN */ 762 #define _SDIO_IFENC_CMDTOUTERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 763 #define SDIO_IFENC_CMDTOUTERREN_DEFAULT (_SDIO_IFENC_CMDTOUTERREN_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_IFENC */ 764 #define SDIO_IFENC_CMDCRCERREN (0x1UL << 17) /**< Command CRC Error Status Enable */ 765 #define _SDIO_IFENC_CMDCRCERREN_SHIFT 17 /**< Shift value for SDIO_CMDCRCERREN */ 766 #define _SDIO_IFENC_CMDCRCERREN_MASK 0x20000UL /**< Bit mask for SDIO_CMDCRCERREN */ 767 #define _SDIO_IFENC_CMDCRCERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 768 #define SDIO_IFENC_CMDCRCERREN_DEFAULT (_SDIO_IFENC_CMDCRCERREN_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_IFENC */ 769 #define SDIO_IFENC_CMDENDBITERREN (0x1UL << 18) /**< Command End Bit Error Status Enable */ 770 #define _SDIO_IFENC_CMDENDBITERREN_SHIFT 18 /**< Shift value for SDIO_CMDENDBITERREN */ 771 #define _SDIO_IFENC_CMDENDBITERREN_MASK 0x40000UL /**< Bit mask for SDIO_CMDENDBITERREN */ 772 #define _SDIO_IFENC_CMDENDBITERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 773 #define SDIO_IFENC_CMDENDBITERREN_DEFAULT (_SDIO_IFENC_CMDENDBITERREN_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_IFENC */ 774 #define SDIO_IFENC_CMDINDEXERREN (0x1UL << 19) /**< Command Index Error Status Enable */ 775 #define _SDIO_IFENC_CMDINDEXERREN_SHIFT 19 /**< Shift value for SDIO_CMDINDEXERREN */ 776 #define _SDIO_IFENC_CMDINDEXERREN_MASK 0x80000UL /**< Bit mask for SDIO_CMDINDEXERREN */ 777 #define _SDIO_IFENC_CMDINDEXERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 778 #define SDIO_IFENC_CMDINDEXERREN_DEFAULT (_SDIO_IFENC_CMDINDEXERREN_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_IFENC */ 779 #define SDIO_IFENC_DATTOUTERREN (0x1UL << 20) /**< Data Timeout Error Status Enable */ 780 #define _SDIO_IFENC_DATTOUTERREN_SHIFT 20 /**< Shift value for SDIO_DATTOUTERREN */ 781 #define _SDIO_IFENC_DATTOUTERREN_MASK 0x100000UL /**< Bit mask for SDIO_DATTOUTERREN */ 782 #define _SDIO_IFENC_DATTOUTERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 783 #define SDIO_IFENC_DATTOUTERREN_DEFAULT (_SDIO_IFENC_DATTOUTERREN_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_IFENC */ 784 #define SDIO_IFENC_DATCRCERREN (0x1UL << 21) /**< Data CRC Error Status Enable */ 785 #define _SDIO_IFENC_DATCRCERREN_SHIFT 21 /**< Shift value for SDIO_DATCRCERREN */ 786 #define _SDIO_IFENC_DATCRCERREN_MASK 0x200000UL /**< Bit mask for SDIO_DATCRCERREN */ 787 #define _SDIO_IFENC_DATCRCERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 788 #define SDIO_IFENC_DATCRCERREN_DEFAULT (_SDIO_IFENC_DATCRCERREN_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_IFENC */ 789 #define SDIO_IFENC_DATENDBITERREN (0x1UL << 22) /**< Data End Bit Error Status Enable */ 790 #define _SDIO_IFENC_DATENDBITERREN_SHIFT 22 /**< Shift value for SDIO_DATENDBITERREN */ 791 #define _SDIO_IFENC_DATENDBITERREN_MASK 0x400000UL /**< Bit mask for SDIO_DATENDBITERREN */ 792 #define _SDIO_IFENC_DATENDBITERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 793 #define SDIO_IFENC_DATENDBITERREN_DEFAULT (_SDIO_IFENC_DATENDBITERREN_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_IFENC */ 794 #define SDIO_IFENC_CURRENTLIMITERREN (0x1UL << 23) /**< Current Limit Error Status Enable */ 795 #define _SDIO_IFENC_CURRENTLIMITERREN_SHIFT 23 /**< Shift value for SDIO_CURRENTLIMITERREN */ 796 #define _SDIO_IFENC_CURRENTLIMITERREN_MASK 0x800000UL /**< Bit mask for SDIO_CURRENTLIMITERREN */ 797 #define _SDIO_IFENC_CURRENTLIMITERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 798 #define SDIO_IFENC_CURRENTLIMITERREN_DEFAULT (_SDIO_IFENC_CURRENTLIMITERREN_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_IFENC */ 799 #define SDIO_IFENC_AUTOCMDERREN (0x1UL << 24) /**< Auto CMD12 Error Status Enable */ 800 #define _SDIO_IFENC_AUTOCMDERREN_SHIFT 24 /**< Shift value for SDIO_AUTOCMDERREN */ 801 #define _SDIO_IFENC_AUTOCMDERREN_MASK 0x1000000UL /**< Bit mask for SDIO_AUTOCMDERREN */ 802 #define _SDIO_IFENC_AUTOCMDERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 803 #define SDIO_IFENC_AUTOCMDERREN_DEFAULT (_SDIO_IFENC_AUTOCMDERREN_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_IFENC */ 804 #define SDIO_IFENC_ADMAERREN (0x1UL << 25) /**< ADMA Error Status Enable */ 805 #define _SDIO_IFENC_ADMAERREN_SHIFT 25 /**< Shift value for SDIO_ADMAERREN */ 806 #define _SDIO_IFENC_ADMAERREN_MASK 0x2000000UL /**< Bit mask for SDIO_ADMAERREN */ 807 #define _SDIO_IFENC_ADMAERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 808 #define SDIO_IFENC_ADMAERREN_DEFAULT (_SDIO_IFENC_ADMAERREN_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_IFENC */ 809 #define SDIO_IFENC_TUNINGERREN (0x1UL << 26) /**< Tuning Error Status Enable */ 810 #define _SDIO_IFENC_TUNINGERREN_SHIFT 26 /**< Shift value for SDIO_TUNINGERREN */ 811 #define _SDIO_IFENC_TUNINGERREN_MASK 0x4000000UL /**< Bit mask for SDIO_TUNINGERREN */ 812 #define _SDIO_IFENC_TUNINGERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 813 #define SDIO_IFENC_TUNINGERREN_DEFAULT (_SDIO_IFENC_TUNINGERREN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_IFENC */ 814 #define SDIO_IFENC_TARGETRESPEN (0x1UL << 28) /**< Target Response/Host Error Status Enable */ 815 #define _SDIO_IFENC_TARGETRESPEN_SHIFT 28 /**< Shift value for SDIO_TARGETRESPEN */ 816 #define _SDIO_IFENC_TARGETRESPEN_MASK 0x10000000UL /**< Bit mask for SDIO_TARGETRESPEN */ 817 #define _SDIO_IFENC_TARGETRESPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ 818 #define SDIO_IFENC_TARGETRESPEN_DEFAULT (_SDIO_IFENC_TARGETRESPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_IFENC */ 819 820 /* Bit fields for SDIO IEN */ 821 #define _SDIO_IEN_RESETVALUE 0x00000000UL /**< Default value for SDIO_IEN */ 822 #define _SDIO_IEN_MASK 0x17FF71FFUL /**< Mask for SDIO_IEN */ 823 #define SDIO_IEN_CMDCOMSEN (0x1UL << 0) /**< Command Complete Signal Enable */ 824 #define _SDIO_IEN_CMDCOMSEN_SHIFT 0 /**< Shift value for SDIO_CMDCOMSEN */ 825 #define _SDIO_IEN_CMDCOMSEN_MASK 0x1UL /**< Bit mask for SDIO_CMDCOMSEN */ 826 #define _SDIO_IEN_CMDCOMSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 827 #define SDIO_IEN_CMDCOMSEN_DEFAULT (_SDIO_IEN_CMDCOMSEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_IEN */ 828 #define SDIO_IEN_TRANCOMSEN (0x1UL << 1) /**< Transfer Complete Signal Enable */ 829 #define _SDIO_IEN_TRANCOMSEN_SHIFT 1 /**< Shift value for SDIO_TRANCOMSEN */ 830 #define _SDIO_IEN_TRANCOMSEN_MASK 0x2UL /**< Bit mask for SDIO_TRANCOMSEN */ 831 #define _SDIO_IEN_TRANCOMSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 832 #define SDIO_IEN_TRANCOMSEN_DEFAULT (_SDIO_IEN_TRANCOMSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_IEN */ 833 #define SDIO_IEN_BLKGAPEVTSEN (0x1UL << 2) /**< Block Gap Event Signal Enable */ 834 #define _SDIO_IEN_BLKGAPEVTSEN_SHIFT 2 /**< Shift value for SDIO_BLKGAPEVTSEN */ 835 #define _SDIO_IEN_BLKGAPEVTSEN_MASK 0x4UL /**< Bit mask for SDIO_BLKGAPEVTSEN */ 836 #define _SDIO_IEN_BLKGAPEVTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 837 #define SDIO_IEN_BLKGAPEVTSEN_DEFAULT (_SDIO_IEN_BLKGAPEVTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_IEN */ 838 #define SDIO_IEN_DMAINTSEN (0x1UL << 3) /**< DMA Interrupt Signal Enable */ 839 #define _SDIO_IEN_DMAINTSEN_SHIFT 3 /**< Shift value for SDIO_DMAINTSEN */ 840 #define _SDIO_IEN_DMAINTSEN_MASK 0x8UL /**< Bit mask for SDIO_DMAINTSEN */ 841 #define _SDIO_IEN_DMAINTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 842 #define SDIO_IEN_DMAINTSEN_DEFAULT (_SDIO_IEN_DMAINTSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_IEN */ 843 #define SDIO_IEN_BUFWRRDYSEN (0x1UL << 4) /**< Buffer Write Ready Signal Enable */ 844 #define _SDIO_IEN_BUFWRRDYSEN_SHIFT 4 /**< Shift value for SDIO_BUFWRRDYSEN */ 845 #define _SDIO_IEN_BUFWRRDYSEN_MASK 0x10UL /**< Bit mask for SDIO_BUFWRRDYSEN */ 846 #define _SDIO_IEN_BUFWRRDYSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 847 #define SDIO_IEN_BUFWRRDYSEN_DEFAULT (_SDIO_IEN_BUFWRRDYSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_IEN */ 848 #define SDIO_IEN_BUFRDRDYSEN (0x1UL << 5) /**< Buffer Read Ready Signal Enable */ 849 #define _SDIO_IEN_BUFRDRDYSEN_SHIFT 5 /**< Shift value for SDIO_BUFRDRDYSEN */ 850 #define _SDIO_IEN_BUFRDRDYSEN_MASK 0x20UL /**< Bit mask for SDIO_BUFRDRDYSEN */ 851 #define _SDIO_IEN_BUFRDRDYSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 852 #define SDIO_IEN_BUFRDRDYSEN_DEFAULT (_SDIO_IEN_BUFRDRDYSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_IEN */ 853 #define SDIO_IEN_CARDINSSEN (0x1UL << 6) /**< Card Insertion Signal Enable */ 854 #define _SDIO_IEN_CARDINSSEN_SHIFT 6 /**< Shift value for SDIO_CARDINSSEN */ 855 #define _SDIO_IEN_CARDINSSEN_MASK 0x40UL /**< Bit mask for SDIO_CARDINSSEN */ 856 #define _SDIO_IEN_CARDINSSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 857 #define SDIO_IEN_CARDINSSEN_DEFAULT (_SDIO_IEN_CARDINSSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_IEN */ 858 #define SDIO_IEN_CARDREMSEN (0x1UL << 7) /**< Card Removal Signal Enable */ 859 #define _SDIO_IEN_CARDREMSEN_SHIFT 7 /**< Shift value for SDIO_CARDREMSEN */ 860 #define _SDIO_IEN_CARDREMSEN_MASK 0x80UL /**< Bit mask for SDIO_CARDREMSEN */ 861 #define _SDIO_IEN_CARDREMSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 862 #define SDIO_IEN_CARDREMSEN_DEFAULT (_SDIO_IEN_CARDREMSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_IEN */ 863 #define SDIO_IEN_CARDINTSEN (0x1UL << 8) /**< Card Interrupt Signal Enable */ 864 #define _SDIO_IEN_CARDINTSEN_SHIFT 8 /**< Shift value for SDIO_CARDINTSEN */ 865 #define _SDIO_IEN_CARDINTSEN_MASK 0x100UL /**< Bit mask for SDIO_CARDINTSEN */ 866 #define _SDIO_IEN_CARDINTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 867 #define SDIO_IEN_CARDINTSEN_DEFAULT (_SDIO_IEN_CARDINTSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_IEN */ 868 #define SDIO_IEN_RETUNINGEVTSEN (0x1UL << 12) /**< Re-Tuning Event Signal Enable */ 869 #define _SDIO_IEN_RETUNINGEVTSEN_SHIFT 12 /**< Shift value for SDIO_RETUNINGEVTSEN */ 870 #define _SDIO_IEN_RETUNINGEVTSEN_MASK 0x1000UL /**< Bit mask for SDIO_RETUNINGEVTSEN */ 871 #define _SDIO_IEN_RETUNINGEVTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 872 #define SDIO_IEN_RETUNINGEVTSEN_DEFAULT (_SDIO_IEN_RETUNINGEVTSEN_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_IEN */ 873 #define SDIO_IEN_BOOTACKRCVSEN (0x1UL << 13) /**< Boot Ack Received Signal Enable */ 874 #define _SDIO_IEN_BOOTACKRCVSEN_SHIFT 13 /**< Shift value for SDIO_BOOTACKRCVSEN */ 875 #define _SDIO_IEN_BOOTACKRCVSEN_MASK 0x2000UL /**< Bit mask for SDIO_BOOTACKRCVSEN */ 876 #define _SDIO_IEN_BOOTACKRCVSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 877 #define SDIO_IEN_BOOTACKRCVSEN_DEFAULT (_SDIO_IEN_BOOTACKRCVSEN_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_IEN */ 878 #define SDIO_IEN_BOOTTERMINATESEN (0x1UL << 14) /**< Boot Terminate Interrupt Signal Enable */ 879 #define _SDIO_IEN_BOOTTERMINATESEN_SHIFT 14 /**< Shift value for SDIO_BOOTTERMINATESEN */ 880 #define _SDIO_IEN_BOOTTERMINATESEN_MASK 0x4000UL /**< Bit mask for SDIO_BOOTTERMINATESEN */ 881 #define _SDIO_IEN_BOOTTERMINATESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 882 #define SDIO_IEN_BOOTTERMINATESEN_DEFAULT (_SDIO_IEN_BOOTTERMINATESEN_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_IEN */ 883 #define SDIO_IEN_CMDTOUTERRSEN (0x1UL << 16) /**< Command Timeout Error Signal Enable */ 884 #define _SDIO_IEN_CMDTOUTERRSEN_SHIFT 16 /**< Shift value for SDIO_CMDTOUTERRSEN */ 885 #define _SDIO_IEN_CMDTOUTERRSEN_MASK 0x10000UL /**< Bit mask for SDIO_CMDTOUTERRSEN */ 886 #define _SDIO_IEN_CMDTOUTERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 887 #define SDIO_IEN_CMDTOUTERRSEN_DEFAULT (_SDIO_IEN_CMDTOUTERRSEN_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_IEN */ 888 #define SDIO_IEN_CMDCRCERRSEN (0x1UL << 17) /**< Command CRC Error Signal Enable */ 889 #define _SDIO_IEN_CMDCRCERRSEN_SHIFT 17 /**< Shift value for SDIO_CMDCRCERRSEN */ 890 #define _SDIO_IEN_CMDCRCERRSEN_MASK 0x20000UL /**< Bit mask for SDIO_CMDCRCERRSEN */ 891 #define _SDIO_IEN_CMDCRCERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 892 #define SDIO_IEN_CMDCRCERRSEN_DEFAULT (_SDIO_IEN_CMDCRCERRSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_IEN */ 893 #define SDIO_IEN_CMDENDBITERRSEN (0x1UL << 18) /**< Command End Bit Error Signal Enable */ 894 #define _SDIO_IEN_CMDENDBITERRSEN_SHIFT 18 /**< Shift value for SDIO_CMDENDBITERRSEN */ 895 #define _SDIO_IEN_CMDENDBITERRSEN_MASK 0x40000UL /**< Bit mask for SDIO_CMDENDBITERRSEN */ 896 #define _SDIO_IEN_CMDENDBITERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 897 #define SDIO_IEN_CMDENDBITERRSEN_DEFAULT (_SDIO_IEN_CMDENDBITERRSEN_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_IEN */ 898 #define SDIO_IEN_CMDINDEXERRSEN (0x1UL << 19) /**< Command Index Error Signal Enable */ 899 #define _SDIO_IEN_CMDINDEXERRSEN_SHIFT 19 /**< Shift value for SDIO_CMDINDEXERRSEN */ 900 #define _SDIO_IEN_CMDINDEXERRSEN_MASK 0x80000UL /**< Bit mask for SDIO_CMDINDEXERRSEN */ 901 #define _SDIO_IEN_CMDINDEXERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 902 #define SDIO_IEN_CMDINDEXERRSEN_DEFAULT (_SDIO_IEN_CMDINDEXERRSEN_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_IEN */ 903 #define SDIO_IEN_DATTOUTERRSEN (0x1UL << 20) /**< Data Timeout Error Signal Enable */ 904 #define _SDIO_IEN_DATTOUTERRSEN_SHIFT 20 /**< Shift value for SDIO_DATTOUTERRSEN */ 905 #define _SDIO_IEN_DATTOUTERRSEN_MASK 0x100000UL /**< Bit mask for SDIO_DATTOUTERRSEN */ 906 #define _SDIO_IEN_DATTOUTERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 907 #define SDIO_IEN_DATTOUTERRSEN_DEFAULT (_SDIO_IEN_DATTOUTERRSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_IEN */ 908 #define SDIO_IEN_DATCRCERRSEN (0x1UL << 21) /**< Data CRC Error Signal Enable */ 909 #define _SDIO_IEN_DATCRCERRSEN_SHIFT 21 /**< Shift value for SDIO_DATCRCERRSEN */ 910 #define _SDIO_IEN_DATCRCERRSEN_MASK 0x200000UL /**< Bit mask for SDIO_DATCRCERRSEN */ 911 #define _SDIO_IEN_DATCRCERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 912 #define SDIO_IEN_DATCRCERRSEN_DEFAULT (_SDIO_IEN_DATCRCERRSEN_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_IEN */ 913 #define SDIO_IEN_DATENDBITERRSEN (0x1UL << 22) /**< Data End Bit Error Signal Enable */ 914 #define _SDIO_IEN_DATENDBITERRSEN_SHIFT 22 /**< Shift value for SDIO_DATENDBITERRSEN */ 915 #define _SDIO_IEN_DATENDBITERRSEN_MASK 0x400000UL /**< Bit mask for SDIO_DATENDBITERRSEN */ 916 #define _SDIO_IEN_DATENDBITERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 917 #define SDIO_IEN_DATENDBITERRSEN_DEFAULT (_SDIO_IEN_DATENDBITERRSEN_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_IEN */ 918 #define SDIO_IEN_CURRENTLIMITERRSEN (0x1UL << 23) /**< Current Limit Error Signal Enable */ 919 #define _SDIO_IEN_CURRENTLIMITERRSEN_SHIFT 23 /**< Shift value for SDIO_CURRENTLIMITERRSEN */ 920 #define _SDIO_IEN_CURRENTLIMITERRSEN_MASK 0x800000UL /**< Bit mask for SDIO_CURRENTLIMITERRSEN */ 921 #define _SDIO_IEN_CURRENTLIMITERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 922 #define SDIO_IEN_CURRENTLIMITERRSEN_DEFAULT (_SDIO_IEN_CURRENTLIMITERRSEN_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_IEN */ 923 #define SDIO_IEN_AUTOCMDERRSEN (0x1UL << 24) /**< Auto CMD12 Error Signal Enable */ 924 #define _SDIO_IEN_AUTOCMDERRSEN_SHIFT 24 /**< Shift value for SDIO_AUTOCMDERRSEN */ 925 #define _SDIO_IEN_AUTOCMDERRSEN_MASK 0x1000000UL /**< Bit mask for SDIO_AUTOCMDERRSEN */ 926 #define _SDIO_IEN_AUTOCMDERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 927 #define SDIO_IEN_AUTOCMDERRSEN_DEFAULT (_SDIO_IEN_AUTOCMDERRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_IEN */ 928 #define SDIO_IEN_ADMAERRSEN (0x1UL << 25) /**< ADMA Error Signal Enable */ 929 #define _SDIO_IEN_ADMAERRSEN_SHIFT 25 /**< Shift value for SDIO_ADMAERRSEN */ 930 #define _SDIO_IEN_ADMAERRSEN_MASK 0x2000000UL /**< Bit mask for SDIO_ADMAERRSEN */ 931 #define _SDIO_IEN_ADMAERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 932 #define SDIO_IEN_ADMAERRSEN_DEFAULT (_SDIO_IEN_ADMAERRSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_IEN */ 933 #define SDIO_IEN_TUNINGERRSIGNALENABLE (0x1UL << 26) /**< Tuning Error Signal Enable */ 934 #define _SDIO_IEN_TUNINGERRSIGNALENABLE_SHIFT 26 /**< Shift value for SDIO_TUNINGERRSIGNALENABLE */ 935 #define _SDIO_IEN_TUNINGERRSIGNALENABLE_MASK 0x4000000UL /**< Bit mask for SDIO_TUNINGERRSIGNALENABLE */ 936 #define _SDIO_IEN_TUNINGERRSIGNALENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 937 #define SDIO_IEN_TUNINGERRSIGNALENABLE_DEFAULT (_SDIO_IEN_TUNINGERRSIGNALENABLE_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_IEN */ 938 #define SDIO_IEN_TARGETRESPERRSEN (0x1UL << 28) /**< Target Response Error Signal Enable */ 939 #define _SDIO_IEN_TARGETRESPERRSEN_SHIFT 28 /**< Shift value for SDIO_TARGETRESPERRSEN */ 940 #define _SDIO_IEN_TARGETRESPERRSEN_MASK 0x10000000UL /**< Bit mask for SDIO_TARGETRESPERRSEN */ 941 #define _SDIO_IEN_TARGETRESPERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ 942 #define SDIO_IEN_TARGETRESPERRSEN_DEFAULT (_SDIO_IEN_TARGETRESPERRSEN_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_IEN */ 943 944 /* Bit fields for SDIO AC12ERRSTAT */ 945 #define _SDIO_AC12ERRSTAT_RESETVALUE 0x00000000UL /**< Default value for SDIO_AC12ERRSTAT */ 946 #define _SDIO_AC12ERRSTAT_MASK 0xC0FF009FUL /**< Mask for SDIO_AC12ERRSTAT */ 947 #define SDIO_AC12ERRSTAT_AC12NOTEXE (0x1UL << 0) /**< Auto CMD12 Not Executed */ 948 #define _SDIO_AC12ERRSTAT_AC12NOTEXE_SHIFT 0 /**< Shift value for SDIO_AC12NOTEXE */ 949 #define _SDIO_AC12ERRSTAT_AC12NOTEXE_MASK 0x1UL /**< Bit mask for SDIO_AC12NOTEXE */ 950 #define _SDIO_AC12ERRSTAT_AC12NOTEXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 951 #define SDIO_AC12ERRSTAT_AC12NOTEXE_DEFAULT (_SDIO_AC12ERRSTAT_AC12NOTEXE_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 952 #define SDIO_AC12ERRSTAT_AC12TOE (0x1UL << 1) /**< Auto CMD12 Timeout Error */ 953 #define _SDIO_AC12ERRSTAT_AC12TOE_SHIFT 1 /**< Shift value for SDIO_AC12TOE */ 954 #define _SDIO_AC12ERRSTAT_AC12TOE_MASK 0x2UL /**< Bit mask for SDIO_AC12TOE */ 955 #define _SDIO_AC12ERRSTAT_AC12TOE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 956 #define SDIO_AC12ERRSTAT_AC12TOE_DEFAULT (_SDIO_AC12ERRSTAT_AC12TOE_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 957 #define SDIO_AC12ERRSTAT_AC12CRCERR (0x1UL << 2) /**< Auto CMD CRC Error */ 958 #define _SDIO_AC12ERRSTAT_AC12CRCERR_SHIFT 2 /**< Shift value for SDIO_AC12CRCERR */ 959 #define _SDIO_AC12ERRSTAT_AC12CRCERR_MASK 0x4UL /**< Bit mask for SDIO_AC12CRCERR */ 960 #define _SDIO_AC12ERRSTAT_AC12CRCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 961 #define SDIO_AC12ERRSTAT_AC12CRCERR_DEFAULT (_SDIO_AC12ERRSTAT_AC12CRCERR_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 962 #define SDIO_AC12ERRSTAT_AC12ENDBITERR (0x1UL << 3) /**< Auto CMD End Bit Error */ 963 #define _SDIO_AC12ERRSTAT_AC12ENDBITERR_SHIFT 3 /**< Shift value for SDIO_AC12ENDBITERR */ 964 #define _SDIO_AC12ERRSTAT_AC12ENDBITERR_MASK 0x8UL /**< Bit mask for SDIO_AC12ENDBITERR */ 965 #define _SDIO_AC12ERRSTAT_AC12ENDBITERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 966 #define SDIO_AC12ERRSTAT_AC12ENDBITERR_DEFAULT (_SDIO_AC12ERRSTAT_AC12ENDBITERR_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 967 #define SDIO_AC12ERRSTAT_AC12INDEXERR (0x1UL << 4) /**< Auto CMD Index Error */ 968 #define _SDIO_AC12ERRSTAT_AC12INDEXERR_SHIFT 4 /**< Shift value for SDIO_AC12INDEXERR */ 969 #define _SDIO_AC12ERRSTAT_AC12INDEXERR_MASK 0x10UL /**< Bit mask for SDIO_AC12INDEXERR */ 970 #define _SDIO_AC12ERRSTAT_AC12INDEXERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 971 #define SDIO_AC12ERRSTAT_AC12INDEXERR_DEFAULT (_SDIO_AC12ERRSTAT_AC12INDEXERR_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 972 #define SDIO_AC12ERRSTAT_CNIBAC12ERR (0x1UL << 7) /**< Command Not Issued By Auto CMD12 Error */ 973 #define _SDIO_AC12ERRSTAT_CNIBAC12ERR_SHIFT 7 /**< Shift value for SDIO_CNIBAC12ERR */ 974 #define _SDIO_AC12ERRSTAT_CNIBAC12ERR_MASK 0x80UL /**< Bit mask for SDIO_CNIBAC12ERR */ 975 #define _SDIO_AC12ERRSTAT_CNIBAC12ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 976 #define SDIO_AC12ERRSTAT_CNIBAC12ERR_DEFAULT (_SDIO_AC12ERRSTAT_CNIBAC12ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 977 #define _SDIO_AC12ERRSTAT_UHSMODESEL_SHIFT 16 /**< Shift value for SDIO_UHSMODESEL */ 978 #define _SDIO_AC12ERRSTAT_UHSMODESEL_MASK 0x70000UL /**< Bit mask for SDIO_UHSMODESEL */ 979 #define _SDIO_AC12ERRSTAT_UHSMODESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 980 #define _SDIO_AC12ERRSTAT_UHSMODESEL_SDR12 0x00000000UL /**< Mode SDR12 for SDIO_AC12ERRSTAT */ 981 #define _SDIO_AC12ERRSTAT_UHSMODESEL_SDR25 0x00000001UL /**< Mode SDR25 for SDIO_AC12ERRSTAT */ 982 #define _SDIO_AC12ERRSTAT_UHSMODESEL_SDR50 0x00000002UL /**< Mode SDR50 for SDIO_AC12ERRSTAT */ 983 #define _SDIO_AC12ERRSTAT_UHSMODESEL_SDR104 0x00000003UL /**< Mode SDR104 for SDIO_AC12ERRSTAT */ 984 #define _SDIO_AC12ERRSTAT_UHSMODESEL_DDR50 0x00000004UL /**< Mode DDR50 for SDIO_AC12ERRSTAT */ 985 #define SDIO_AC12ERRSTAT_UHSMODESEL_DEFAULT (_SDIO_AC12ERRSTAT_UHSMODESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 986 #define SDIO_AC12ERRSTAT_UHSMODESEL_SDR12 (_SDIO_AC12ERRSTAT_UHSMODESEL_SDR12 << 16) /**< Shifted mode SDR12 for SDIO_AC12ERRSTAT */ 987 #define SDIO_AC12ERRSTAT_UHSMODESEL_SDR25 (_SDIO_AC12ERRSTAT_UHSMODESEL_SDR25 << 16) /**< Shifted mode SDR25 for SDIO_AC12ERRSTAT */ 988 #define SDIO_AC12ERRSTAT_UHSMODESEL_SDR50 (_SDIO_AC12ERRSTAT_UHSMODESEL_SDR50 << 16) /**< Shifted mode SDR50 for SDIO_AC12ERRSTAT */ 989 #define SDIO_AC12ERRSTAT_UHSMODESEL_SDR104 (_SDIO_AC12ERRSTAT_UHSMODESEL_SDR104 << 16) /**< Shifted mode SDR104 for SDIO_AC12ERRSTAT */ 990 #define SDIO_AC12ERRSTAT_UHSMODESEL_DDR50 (_SDIO_AC12ERRSTAT_UHSMODESEL_DDR50 << 16) /**< Shifted mode DDR50 for SDIO_AC12ERRSTAT */ 991 #define SDIO_AC12ERRSTAT_SIGEN1P8V (0x1UL << 19) /**< Voltage 1.8V Signal Enable */ 992 #define _SDIO_AC12ERRSTAT_SIGEN1P8V_SHIFT 19 /**< Shift value for SDIO_SIGEN1P8V */ 993 #define _SDIO_AC12ERRSTAT_SIGEN1P8V_MASK 0x80000UL /**< Bit mask for SDIO_SIGEN1P8V */ 994 #define _SDIO_AC12ERRSTAT_SIGEN1P8V_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 995 #define SDIO_AC12ERRSTAT_SIGEN1P8V_DEFAULT (_SDIO_AC12ERRSTAT_SIGEN1P8V_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 996 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_SHIFT 20 /**< Shift value for SDIO_DRVSTNSEL */ 997 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_MASK 0x300000UL /**< Bit mask for SDIO_DRVSTNSEL */ 998 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 999 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_AC12ERRSTAT */ 1000 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_AC12ERRSTAT */ 1001 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_AC12ERRSTAT */ 1002 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_AC12ERRSTAT */ 1003 #define SDIO_AC12ERRSTAT_DRVSTNSEL_DEFAULT (_SDIO_AC12ERRSTAT_DRVSTNSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 1004 #define SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEB (_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEB << 20) /**< Shifted mode TYPEB for SDIO_AC12ERRSTAT */ 1005 #define SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEA (_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEA << 20) /**< Shifted mode TYPEA for SDIO_AC12ERRSTAT */ 1006 #define SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEC (_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEC << 20) /**< Shifted mode TYPEC for SDIO_AC12ERRSTAT */ 1007 #define SDIO_AC12ERRSTAT_DRVSTNSEL_TYPED (_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPED << 20) /**< Shifted mode TYPED for SDIO_AC12ERRSTAT */ 1008 #define SDIO_AC12ERRSTAT_EXETUNING (0x1UL << 22) /**< Execute Tuning */ 1009 #define _SDIO_AC12ERRSTAT_EXETUNING_SHIFT 22 /**< Shift value for SDIO_EXETUNING */ 1010 #define _SDIO_AC12ERRSTAT_EXETUNING_MASK 0x400000UL /**< Bit mask for SDIO_EXETUNING */ 1011 #define _SDIO_AC12ERRSTAT_EXETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 1012 #define SDIO_AC12ERRSTAT_EXETUNING_DEFAULT (_SDIO_AC12ERRSTAT_EXETUNING_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 1013 #define SDIO_AC12ERRSTAT_SAMPCLKSEL (0x1UL << 23) /**< Sampling Clock Select */ 1014 #define _SDIO_AC12ERRSTAT_SAMPCLKSEL_SHIFT 23 /**< Shift value for SDIO_SAMPCLKSEL */ 1015 #define _SDIO_AC12ERRSTAT_SAMPCLKSEL_MASK 0x800000UL /**< Bit mask for SDIO_SAMPCLKSEL */ 1016 #define _SDIO_AC12ERRSTAT_SAMPCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 1017 #define SDIO_AC12ERRSTAT_SAMPCLKSEL_DEFAULT (_SDIO_AC12ERRSTAT_SAMPCLKSEL_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 1018 #define SDIO_AC12ERRSTAT_ASYNCINTEN (0x1UL << 30) /**< Asynchronous Interrupt Enable */ 1019 #define _SDIO_AC12ERRSTAT_ASYNCINTEN_SHIFT 30 /**< Shift value for SDIO_ASYNCINTEN */ 1020 #define _SDIO_AC12ERRSTAT_ASYNCINTEN_MASK 0x40000000UL /**< Bit mask for SDIO_ASYNCINTEN */ 1021 #define _SDIO_AC12ERRSTAT_ASYNCINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 1022 #define SDIO_AC12ERRSTAT_ASYNCINTEN_DEFAULT (_SDIO_AC12ERRSTAT_ASYNCINTEN_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 1023 #define SDIO_AC12ERRSTAT_PRSTVALEN (0x1UL << 31) /**< Preset Value Enable */ 1024 #define _SDIO_AC12ERRSTAT_PRSTVALEN_SHIFT 31 /**< Shift value for SDIO_PRSTVALEN */ 1025 #define _SDIO_AC12ERRSTAT_PRSTVALEN_MASK 0x80000000UL /**< Bit mask for SDIO_PRSTVALEN */ 1026 #define _SDIO_AC12ERRSTAT_PRSTVALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ 1027 #define SDIO_AC12ERRSTAT_PRSTVALEN_DEFAULT (_SDIO_AC12ERRSTAT_PRSTVALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ 1028 1029 /* Bit fields for SDIO CAPAB0 */ 1030 #define _SDIO_CAPAB0_RESETVALUE 0x00000000UL /**< Default value for SDIO_CAPAB0 */ 1031 #define _SDIO_CAPAB0_MASK 0xF7EFFFBFUL /**< Mask for SDIO_CAPAB0 */ 1032 #define _SDIO_CAPAB0_TMOUTCLKFREQ_SHIFT 0 /**< Shift value for SDIO_TMOUTCLKFREQ */ 1033 #define _SDIO_CAPAB0_TMOUTCLKFREQ_MASK 0x3FUL /**< Bit mask for SDIO_TMOUTCLKFREQ */ 1034 #define _SDIO_CAPAB0_TMOUTCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1035 #define SDIO_CAPAB0_TMOUTCLKFREQ_DEFAULT (_SDIO_CAPAB0_TMOUTCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1036 #define SDIO_CAPAB0_TMOUTCLKUNIT (0x1UL << 7) /**< Timeout Clock Unit */ 1037 #define _SDIO_CAPAB0_TMOUTCLKUNIT_SHIFT 7 /**< Shift value for SDIO_TMOUTCLKUNIT */ 1038 #define _SDIO_CAPAB0_TMOUTCLKUNIT_MASK 0x80UL /**< Bit mask for SDIO_TMOUTCLKUNIT */ 1039 #define _SDIO_CAPAB0_TMOUTCLKUNIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1040 #define SDIO_CAPAB0_TMOUTCLKUNIT_DEFAULT (_SDIO_CAPAB0_TMOUTCLKUNIT_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1041 #define _SDIO_CAPAB0_BASECLKFREQSD_SHIFT 8 /**< Shift value for SDIO_BASECLKFREQSD */ 1042 #define _SDIO_CAPAB0_BASECLKFREQSD_MASK 0xFF00UL /**< Bit mask for SDIO_BASECLKFREQSD */ 1043 #define _SDIO_CAPAB0_BASECLKFREQSD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1044 #define SDIO_CAPAB0_BASECLKFREQSD_DEFAULT (_SDIO_CAPAB0_BASECLKFREQSD_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1045 #define _SDIO_CAPAB0_MAXBLOCKLEN_SHIFT 16 /**< Shift value for SDIO_MAXBLOCKLEN */ 1046 #define _SDIO_CAPAB0_MAXBLOCKLEN_MASK 0x30000UL /**< Bit mask for SDIO_MAXBLOCKLEN */ 1047 #define _SDIO_CAPAB0_MAXBLOCKLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1048 #define SDIO_CAPAB0_MAXBLOCKLEN_DEFAULT (_SDIO_CAPAB0_MAXBLOCKLEN_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1049 #define SDIO_CAPAB0_EXTMEDIABUSSUP (0x1UL << 18) /**< Extended Media Bus Support */ 1050 #define _SDIO_CAPAB0_EXTMEDIABUSSUP_SHIFT 18 /**< Shift value for SDIO_EXTMEDIABUSSUP */ 1051 #define _SDIO_CAPAB0_EXTMEDIABUSSUP_MASK 0x40000UL /**< Bit mask for SDIO_EXTMEDIABUSSUP */ 1052 #define _SDIO_CAPAB0_EXTMEDIABUSSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1053 #define SDIO_CAPAB0_EXTMEDIABUSSUP_DEFAULT (_SDIO_CAPAB0_EXTMEDIABUSSUP_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1054 #define SDIO_CAPAB0_ADMA2SUP (0x1UL << 19) /**< ADMA2 Support */ 1055 #define _SDIO_CAPAB0_ADMA2SUP_SHIFT 19 /**< Shift value for SDIO_ADMA2SUP */ 1056 #define _SDIO_CAPAB0_ADMA2SUP_MASK 0x80000UL /**< Bit mask for SDIO_ADMA2SUP */ 1057 #define _SDIO_CAPAB0_ADMA2SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1058 #define SDIO_CAPAB0_ADMA2SUP_DEFAULT (_SDIO_CAPAB0_ADMA2SUP_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1059 #define SDIO_CAPAB0_HSSUP (0x1UL << 21) /**< High Speed Support */ 1060 #define _SDIO_CAPAB0_HSSUP_SHIFT 21 /**< Shift value for SDIO_HSSUP */ 1061 #define _SDIO_CAPAB0_HSSUP_MASK 0x200000UL /**< Bit mask for SDIO_HSSUP */ 1062 #define _SDIO_CAPAB0_HSSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1063 #define SDIO_CAPAB0_HSSUP_DEFAULT (_SDIO_CAPAB0_HSSUP_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1064 #define SDIO_CAPAB0_SDMASUP (0x1UL << 22) /**< SDMA Support */ 1065 #define _SDIO_CAPAB0_SDMASUP_SHIFT 22 /**< Shift value for SDIO_SDMASUP */ 1066 #define _SDIO_CAPAB0_SDMASUP_MASK 0x400000UL /**< Bit mask for SDIO_SDMASUP */ 1067 #define _SDIO_CAPAB0_SDMASUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1068 #define SDIO_CAPAB0_SDMASUP_DEFAULT (_SDIO_CAPAB0_SDMASUP_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1069 #define SDIO_CAPAB0_SUSRESSUP (0x1UL << 23) /**< Suspend / Resume Support */ 1070 #define _SDIO_CAPAB0_SUSRESSUP_SHIFT 23 /**< Shift value for SDIO_SUSRESSUP */ 1071 #define _SDIO_CAPAB0_SUSRESSUP_MASK 0x800000UL /**< Bit mask for SDIO_SUSRESSUP */ 1072 #define _SDIO_CAPAB0_SUSRESSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1073 #define SDIO_CAPAB0_SUSRESSUP_DEFAULT (_SDIO_CAPAB0_SUSRESSUP_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1074 #define SDIO_CAPAB0_VOLTSUP3P3V (0x1UL << 24) /**< Voltage Support 3.3V */ 1075 #define _SDIO_CAPAB0_VOLTSUP3P3V_SHIFT 24 /**< Shift value for SDIO_VOLTSUP3P3V */ 1076 #define _SDIO_CAPAB0_VOLTSUP3P3V_MASK 0x1000000UL /**< Bit mask for SDIO_VOLTSUP3P3V */ 1077 #define _SDIO_CAPAB0_VOLTSUP3P3V_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1078 #define SDIO_CAPAB0_VOLTSUP3P3V_DEFAULT (_SDIO_CAPAB0_VOLTSUP3P3V_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1079 #define SDIO_CAPAB0_VOLTSUP3P0V (0x1UL << 25) /**< Voltage Support 3.0V */ 1080 #define _SDIO_CAPAB0_VOLTSUP3P0V_SHIFT 25 /**< Shift value for SDIO_VOLTSUP3P0V */ 1081 #define _SDIO_CAPAB0_VOLTSUP3P0V_MASK 0x2000000UL /**< Bit mask for SDIO_VOLTSUP3P0V */ 1082 #define _SDIO_CAPAB0_VOLTSUP3P0V_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1083 #define SDIO_CAPAB0_VOLTSUP3P0V_DEFAULT (_SDIO_CAPAB0_VOLTSUP3P0V_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1084 #define SDIO_CAPAB0_VOLTSUP1P8V (0x1UL << 26) /**< Voltage Support 1.8V */ 1085 #define _SDIO_CAPAB0_VOLTSUP1P8V_SHIFT 26 /**< Shift value for SDIO_VOLTSUP1P8V */ 1086 #define _SDIO_CAPAB0_VOLTSUP1P8V_MASK 0x4000000UL /**< Bit mask for SDIO_VOLTSUP1P8V */ 1087 #define _SDIO_CAPAB0_VOLTSUP1P8V_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1088 #define SDIO_CAPAB0_VOLTSUP1P8V_DEFAULT (_SDIO_CAPAB0_VOLTSUP1P8V_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1089 #define SDIO_CAPAB0_SYSBUS64BSUP (0x1UL << 28) /**< System Bus 64-bit Support */ 1090 #define _SDIO_CAPAB0_SYSBUS64BSUP_SHIFT 28 /**< Shift value for SDIO_SYSBUS64BSUP */ 1091 #define _SDIO_CAPAB0_SYSBUS64BSUP_MASK 0x10000000UL /**< Bit mask for SDIO_SYSBUS64BSUP */ 1092 #define _SDIO_CAPAB0_SYSBUS64BSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1093 #define SDIO_CAPAB0_SYSBUS64BSUP_DEFAULT (_SDIO_CAPAB0_SYSBUS64BSUP_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1094 #define SDIO_CAPAB0_ASYNCINTSUP (0x1UL << 29) /**< Asynchronous Interrupt Support */ 1095 #define _SDIO_CAPAB0_ASYNCINTSUP_SHIFT 29 /**< Shift value for SDIO_ASYNCINTSUP */ 1096 #define _SDIO_CAPAB0_ASYNCINTSUP_MASK 0x20000000UL /**< Bit mask for SDIO_ASYNCINTSUP */ 1097 #define _SDIO_CAPAB0_ASYNCINTSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1098 #define SDIO_CAPAB0_ASYNCINTSUP_DEFAULT (_SDIO_CAPAB0_ASYNCINTSUP_DEFAULT << 29) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1099 #define _SDIO_CAPAB0_IFSLOTTYPE_SHIFT 30 /**< Shift value for SDIO_IFSLOTTYPE */ 1100 #define _SDIO_CAPAB0_IFSLOTTYPE_MASK 0xC0000000UL /**< Bit mask for SDIO_IFSLOTTYPE */ 1101 #define _SDIO_CAPAB0_IFSLOTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ 1102 #define _SDIO_CAPAB0_IFSLOTTYPE_REMOVABLE 0x00000000UL /**< Mode REMOVABLE for SDIO_CAPAB0 */ 1103 #define _SDIO_CAPAB0_IFSLOTTYPE_EMBEDDED 0x00000001UL /**< Mode EMBEDDED for SDIO_CAPAB0 */ 1104 #define _SDIO_CAPAB0_IFSLOTTYPE_SHARED 0x00000002UL /**< Mode SHARED for SDIO_CAPAB0 */ 1105 #define SDIO_CAPAB0_IFSLOTTYPE_DEFAULT (_SDIO_CAPAB0_IFSLOTTYPE_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ 1106 #define SDIO_CAPAB0_IFSLOTTYPE_REMOVABLE (_SDIO_CAPAB0_IFSLOTTYPE_REMOVABLE << 30) /**< Shifted mode REMOVABLE for SDIO_CAPAB0 */ 1107 #define SDIO_CAPAB0_IFSLOTTYPE_EMBEDDED (_SDIO_CAPAB0_IFSLOTTYPE_EMBEDDED << 30) /**< Shifted mode EMBEDDED for SDIO_CAPAB0 */ 1108 #define SDIO_CAPAB0_IFSLOTTYPE_SHARED (_SDIO_CAPAB0_IFSLOTTYPE_SHARED << 30) /**< Shifted mode SHARED for SDIO_CAPAB0 */ 1109 1110 /* Bit fields for SDIO CAPAB2 */ 1111 #define _SDIO_CAPAB2_RESETVALUE 0x00000000UL /**< Default value for SDIO_CAPAB2 */ 1112 #define _SDIO_CAPAB2_MASK 0x03FFEF77UL /**< Mask for SDIO_CAPAB2 */ 1113 #define SDIO_CAPAB2_SDR50SUP (0x1UL << 0) /**< SDR50 Support */ 1114 #define _SDIO_CAPAB2_SDR50SUP_SHIFT 0 /**< Shift value for SDIO_SDR50SUP */ 1115 #define _SDIO_CAPAB2_SDR50SUP_MASK 0x1UL /**< Bit mask for SDIO_SDR50SUP */ 1116 #define _SDIO_CAPAB2_SDR50SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ 1117 #define SDIO_CAPAB2_SDR50SUP_DEFAULT (_SDIO_CAPAB2_SDR50SUP_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ 1118 #define SDIO_CAPAB2_SDR104SUP (0x1UL << 1) /**< SDR104 Support */ 1119 #define _SDIO_CAPAB2_SDR104SUP_SHIFT 1 /**< Shift value for SDIO_SDR104SUP */ 1120 #define _SDIO_CAPAB2_SDR104SUP_MASK 0x2UL /**< Bit mask for SDIO_SDR104SUP */ 1121 #define _SDIO_CAPAB2_SDR104SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ 1122 #define SDIO_CAPAB2_SDR104SUP_DEFAULT (_SDIO_CAPAB2_SDR104SUP_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ 1123 #define SDIO_CAPAB2_DDR50SUP (0x1UL << 2) /**< DDR50 Support */ 1124 #define _SDIO_CAPAB2_DDR50SUP_SHIFT 2 /**< Shift value for SDIO_DDR50SUP */ 1125 #define _SDIO_CAPAB2_DDR50SUP_MASK 0x4UL /**< Bit mask for SDIO_DDR50SUP */ 1126 #define _SDIO_CAPAB2_DDR50SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ 1127 #define SDIO_CAPAB2_DDR50SUP_DEFAULT (_SDIO_CAPAB2_DDR50SUP_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ 1128 #define SDIO_CAPAB2_DRVTYPASUP (0x1UL << 4) /**< Driver Type a Support */ 1129 #define _SDIO_CAPAB2_DRVTYPASUP_SHIFT 4 /**< Shift value for SDIO_DRVTYPASUP */ 1130 #define _SDIO_CAPAB2_DRVTYPASUP_MASK 0x10UL /**< Bit mask for SDIO_DRVTYPASUP */ 1131 #define _SDIO_CAPAB2_DRVTYPASUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ 1132 #define SDIO_CAPAB2_DRVTYPASUP_DEFAULT (_SDIO_CAPAB2_DRVTYPASUP_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ 1133 #define SDIO_CAPAB2_DRVTYPCSUP (0x1UL << 5) /**< Driver Type C Support */ 1134 #define _SDIO_CAPAB2_DRVTYPCSUP_SHIFT 5 /**< Shift value for SDIO_DRVTYPCSUP */ 1135 #define _SDIO_CAPAB2_DRVTYPCSUP_MASK 0x20UL /**< Bit mask for SDIO_DRVTYPCSUP */ 1136 #define _SDIO_CAPAB2_DRVTYPCSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ 1137 #define SDIO_CAPAB2_DRVTYPCSUP_DEFAULT (_SDIO_CAPAB2_DRVTYPCSUP_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ 1138 #define SDIO_CAPAB2_DRVTYPDSUP (0x1UL << 6) /**< Driver Type D Support */ 1139 #define _SDIO_CAPAB2_DRVTYPDSUP_SHIFT 6 /**< Shift value for SDIO_DRVTYPDSUP */ 1140 #define _SDIO_CAPAB2_DRVTYPDSUP_MASK 0x40UL /**< Bit mask for SDIO_DRVTYPDSUP */ 1141 #define _SDIO_CAPAB2_DRVTYPDSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ 1142 #define SDIO_CAPAB2_DRVTYPDSUP_DEFAULT (_SDIO_CAPAB2_DRVTYPDSUP_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ 1143 #define _SDIO_CAPAB2_TIMCNTRETUN_SHIFT 8 /**< Shift value for SDIO_TIMCNTRETUN */ 1144 #define _SDIO_CAPAB2_TIMCNTRETUN_MASK 0xF00UL /**< Bit mask for SDIO_TIMCNTRETUN */ 1145 #define _SDIO_CAPAB2_TIMCNTRETUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ 1146 #define SDIO_CAPAB2_TIMCNTRETUN_DEFAULT (_SDIO_CAPAB2_TIMCNTRETUN_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ 1147 #define SDIO_CAPAB2_USETUNSDR50 (0x1UL << 13) /**< Use Tuning for SDR50 */ 1148 #define _SDIO_CAPAB2_USETUNSDR50_SHIFT 13 /**< Shift value for SDIO_USETUNSDR50 */ 1149 #define _SDIO_CAPAB2_USETUNSDR50_MASK 0x2000UL /**< Bit mask for SDIO_USETUNSDR50 */ 1150 #define _SDIO_CAPAB2_USETUNSDR50_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ 1151 #define SDIO_CAPAB2_USETUNSDR50_DEFAULT (_SDIO_CAPAB2_USETUNSDR50_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ 1152 #define _SDIO_CAPAB2_RETUNEMODES_SHIFT 14 /**< Shift value for SDIO_RETUNEMODES */ 1153 #define _SDIO_CAPAB2_RETUNEMODES_MASK 0xC000UL /**< Bit mask for SDIO_RETUNEMODES */ 1154 #define _SDIO_CAPAB2_RETUNEMODES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ 1155 #define SDIO_CAPAB2_RETUNEMODES_DEFAULT (_SDIO_CAPAB2_RETUNEMODES_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ 1156 #define _SDIO_CAPAB2_CLOCKKMUL_SHIFT 16 /**< Shift value for SDIO_CLOCKKMUL */ 1157 #define _SDIO_CAPAB2_CLOCKKMUL_MASK 0xFF0000UL /**< Bit mask for SDIO_CLOCKKMUL */ 1158 #define _SDIO_CAPAB2_CLOCKKMUL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ 1159 #define SDIO_CAPAB2_CLOCKKMUL_DEFAULT (_SDIO_CAPAB2_CLOCKKMUL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ 1160 #define SDIO_CAPAB2_SPIMODE (0x1UL << 24) /**< SPI Mode Support */ 1161 #define _SDIO_CAPAB2_SPIMODE_SHIFT 24 /**< Shift value for SDIO_SPIMODE */ 1162 #define _SDIO_CAPAB2_SPIMODE_MASK 0x1000000UL /**< Bit mask for SDIO_SPIMODE */ 1163 #define _SDIO_CAPAB2_SPIMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ 1164 #define SDIO_CAPAB2_SPIMODE_DEFAULT (_SDIO_CAPAB2_SPIMODE_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ 1165 #define SDIO_CAPAB2_SPIBLOCKMODE (0x1UL << 25) /**< SPI Block Mode Support */ 1166 #define _SDIO_CAPAB2_SPIBLOCKMODE_SHIFT 25 /**< Shift value for SDIO_SPIBLOCKMODE */ 1167 #define _SDIO_CAPAB2_SPIBLOCKMODE_MASK 0x2000000UL /**< Bit mask for SDIO_SPIBLOCKMODE */ 1168 #define _SDIO_CAPAB2_SPIBLOCKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ 1169 #define SDIO_CAPAB2_SPIBLOCKMODE_DEFAULT (_SDIO_CAPAB2_SPIBLOCKMODE_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ 1170 1171 /* Bit fields for SDIO MAXCURCAPAB */ 1172 #define _SDIO_MAXCURCAPAB_RESETVALUE 0x00000000UL /**< Default value for SDIO_MAXCURCAPAB */ 1173 #define _SDIO_MAXCURCAPAB_MASK 0x00FFFFFFUL /**< Mask for SDIO_MAXCURCAPAB */ 1174 #define _SDIO_MAXCURCAPAB_MAXCUR3P3VAL_SHIFT 0 /**< Shift value for SDIO_MAXCUR3P3VAL */ 1175 #define _SDIO_MAXCURCAPAB_MAXCUR3P3VAL_MASK 0xFFUL /**< Bit mask for SDIO_MAXCUR3P3VAL */ 1176 #define _SDIO_MAXCURCAPAB_MAXCUR3P3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_MAXCURCAPAB */ 1177 #define SDIO_MAXCURCAPAB_MAXCUR3P3VAL_DEFAULT (_SDIO_MAXCURCAPAB_MAXCUR3P3VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_MAXCURCAPAB */ 1178 #define _SDIO_MAXCURCAPAB_MAXCUR3P0VAL_SHIFT 8 /**< Shift value for SDIO_MAXCUR3P0VAL */ 1179 #define _SDIO_MAXCURCAPAB_MAXCUR3P0VAL_MASK 0xFF00UL /**< Bit mask for SDIO_MAXCUR3P0VAL */ 1180 #define _SDIO_MAXCURCAPAB_MAXCUR3P0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_MAXCURCAPAB */ 1181 #define SDIO_MAXCURCAPAB_MAXCUR3P0VAL_DEFAULT (_SDIO_MAXCURCAPAB_MAXCUR3P0VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_MAXCURCAPAB */ 1182 #define _SDIO_MAXCURCAPAB_MAXCUR1P8VAL_SHIFT 16 /**< Shift value for SDIO_MAXCUR1P8VAL */ 1183 #define _SDIO_MAXCURCAPAB_MAXCUR1P8VAL_MASK 0xFF0000UL /**< Bit mask for SDIO_MAXCUR1P8VAL */ 1184 #define _SDIO_MAXCURCAPAB_MAXCUR1P8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_MAXCURCAPAB */ 1185 #define SDIO_MAXCURCAPAB_MAXCUR1P8VAL_DEFAULT (_SDIO_MAXCURCAPAB_MAXCUR1P8VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_MAXCURCAPAB */ 1186 1187 /* Bit fields for SDIO FEVTERRSTAT */ 1188 #define _SDIO_FEVTERRSTAT_RESETVALUE 0x00000000UL /**< Default value for SDIO_FEVTERRSTAT */ 1189 #define _SDIO_FEVTERRSTAT_MASK 0xF7FF009FUL /**< Mask for SDIO_FEVTERRSTAT */ 1190 #define SDIO_FEVTERRSTAT_AC12NEX (0x1UL << 0) /**< Force Event for Command Not Issued By Auto CM12 Not Executed */ 1191 #define _SDIO_FEVTERRSTAT_AC12NEX_SHIFT 0 /**< Shift value for SDIO_AC12NEX */ 1192 #define _SDIO_FEVTERRSTAT_AC12NEX_MASK 0x1UL /**< Bit mask for SDIO_AC12NEX */ 1193 #define _SDIO_FEVTERRSTAT_AC12NEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1194 #define SDIO_FEVTERRSTAT_AC12NEX_DEFAULT (_SDIO_FEVTERRSTAT_AC12NEX_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1195 #define SDIO_FEVTERRSTAT_AC12TOE (0x1UL << 1) /**< Force Event for Auto CMD Timeout Error */ 1196 #define _SDIO_FEVTERRSTAT_AC12TOE_SHIFT 1 /**< Shift value for SDIO_AC12TOE */ 1197 #define _SDIO_FEVTERRSTAT_AC12TOE_MASK 0x2UL /**< Bit mask for SDIO_AC12TOE */ 1198 #define _SDIO_FEVTERRSTAT_AC12TOE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1199 #define SDIO_FEVTERRSTAT_AC12TOE_DEFAULT (_SDIO_FEVTERRSTAT_AC12TOE_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1200 #define SDIO_FEVTERRSTAT_AC12CRCE (0x1UL << 2) /**< Force Event for Auto CMD CRC Error */ 1201 #define _SDIO_FEVTERRSTAT_AC12CRCE_SHIFT 2 /**< Shift value for SDIO_AC12CRCE */ 1202 #define _SDIO_FEVTERRSTAT_AC12CRCE_MASK 0x4UL /**< Bit mask for SDIO_AC12CRCE */ 1203 #define _SDIO_FEVTERRSTAT_AC12CRCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1204 #define SDIO_FEVTERRSTAT_AC12CRCE_DEFAULT (_SDIO_FEVTERRSTAT_AC12CRCE_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1205 #define SDIO_FEVTERRSTAT_AC12EBE (0x1UL << 3) /**< Force Event for Auto CMD End Bit Error */ 1206 #define _SDIO_FEVTERRSTAT_AC12EBE_SHIFT 3 /**< Shift value for SDIO_AC12EBE */ 1207 #define _SDIO_FEVTERRSTAT_AC12EBE_MASK 0x8UL /**< Bit mask for SDIO_AC12EBE */ 1208 #define _SDIO_FEVTERRSTAT_AC12EBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1209 #define SDIO_FEVTERRSTAT_AC12EBE_DEFAULT (_SDIO_FEVTERRSTAT_AC12EBE_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1210 #define SDIO_FEVTERRSTAT_AC12INDXE (0x1UL << 4) /**< Force Event for Auto CMD Index Error */ 1211 #define _SDIO_FEVTERRSTAT_AC12INDXE_SHIFT 4 /**< Shift value for SDIO_AC12INDXE */ 1212 #define _SDIO_FEVTERRSTAT_AC12INDXE_MASK 0x10UL /**< Bit mask for SDIO_AC12INDXE */ 1213 #define _SDIO_FEVTERRSTAT_AC12INDXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1214 #define SDIO_FEVTERRSTAT_AC12INDXE_DEFAULT (_SDIO_FEVTERRSTAT_AC12INDXE_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1215 #define SDIO_FEVTERRSTAT_CNIBAC12E (0x1UL << 7) /**< Force Event for Command Not Issued By Auto CMD12 Error */ 1216 #define _SDIO_FEVTERRSTAT_CNIBAC12E_SHIFT 7 /**< Shift value for SDIO_CNIBAC12E */ 1217 #define _SDIO_FEVTERRSTAT_CNIBAC12E_MASK 0x80UL /**< Bit mask for SDIO_CNIBAC12E */ 1218 #define _SDIO_FEVTERRSTAT_CNIBAC12E_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1219 #define SDIO_FEVTERRSTAT_CNIBAC12E_DEFAULT (_SDIO_FEVTERRSTAT_CNIBAC12E_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1220 #define SDIO_FEVTERRSTAT_CMDTOE (0x1UL << 16) /**< Force Event for Command Timeout Error */ 1221 #define _SDIO_FEVTERRSTAT_CMDTOE_SHIFT 16 /**< Shift value for SDIO_CMDTOE */ 1222 #define _SDIO_FEVTERRSTAT_CMDTOE_MASK 0x10000UL /**< Bit mask for SDIO_CMDTOE */ 1223 #define _SDIO_FEVTERRSTAT_CMDTOE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1224 #define SDIO_FEVTERRSTAT_CMDTOE_DEFAULT (_SDIO_FEVTERRSTAT_CMDTOE_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1225 #define SDIO_FEVTERRSTAT_CMDCRCE (0x1UL << 17) /**< Force Event for Command CRC Error */ 1226 #define _SDIO_FEVTERRSTAT_CMDCRCE_SHIFT 17 /**< Shift value for SDIO_CMDCRCE */ 1227 #define _SDIO_FEVTERRSTAT_CMDCRCE_MASK 0x20000UL /**< Bit mask for SDIO_CMDCRCE */ 1228 #define _SDIO_FEVTERRSTAT_CMDCRCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1229 #define SDIO_FEVTERRSTAT_CMDCRCE_DEFAULT (_SDIO_FEVTERRSTAT_CMDCRCE_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1230 #define SDIO_FEVTERRSTAT_CMDEBE (0x1UL << 18) /**< Force Event for Command End Bit Error */ 1231 #define _SDIO_FEVTERRSTAT_CMDEBE_SHIFT 18 /**< Shift value for SDIO_CMDEBE */ 1232 #define _SDIO_FEVTERRSTAT_CMDEBE_MASK 0x40000UL /**< Bit mask for SDIO_CMDEBE */ 1233 #define _SDIO_FEVTERRSTAT_CMDEBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1234 #define SDIO_FEVTERRSTAT_CMDEBE_DEFAULT (_SDIO_FEVTERRSTAT_CMDEBE_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1235 #define SDIO_FEVTERRSTAT_CMDINDXE (0x1UL << 19) /**< Force Event for Command Index Error */ 1236 #define _SDIO_FEVTERRSTAT_CMDINDXE_SHIFT 19 /**< Shift value for SDIO_CMDINDXE */ 1237 #define _SDIO_FEVTERRSTAT_CMDINDXE_MASK 0x80000UL /**< Bit mask for SDIO_CMDINDXE */ 1238 #define _SDIO_FEVTERRSTAT_CMDINDXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1239 #define SDIO_FEVTERRSTAT_CMDINDXE_DEFAULT (_SDIO_FEVTERRSTAT_CMDINDXE_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1240 #define SDIO_FEVTERRSTAT_DATTOE (0x1UL << 20) /**< Force Event for Data Timeout Error */ 1241 #define _SDIO_FEVTERRSTAT_DATTOE_SHIFT 20 /**< Shift value for SDIO_DATTOE */ 1242 #define _SDIO_FEVTERRSTAT_DATTOE_MASK 0x100000UL /**< Bit mask for SDIO_DATTOE */ 1243 #define _SDIO_FEVTERRSTAT_DATTOE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1244 #define SDIO_FEVTERRSTAT_DATTOE_DEFAULT (_SDIO_FEVTERRSTAT_DATTOE_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1245 #define SDIO_FEVTERRSTAT_DATCRCE (0x1UL << 21) /**< Force Event for Data CRC Error */ 1246 #define _SDIO_FEVTERRSTAT_DATCRCE_SHIFT 21 /**< Shift value for SDIO_DATCRCE */ 1247 #define _SDIO_FEVTERRSTAT_DATCRCE_MASK 0x200000UL /**< Bit mask for SDIO_DATCRCE */ 1248 #define _SDIO_FEVTERRSTAT_DATCRCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1249 #define SDIO_FEVTERRSTAT_DATCRCE_DEFAULT (_SDIO_FEVTERRSTAT_DATCRCE_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1250 #define SDIO_FEVTERRSTAT_DATEBE (0x1UL << 22) /**< Force Event for Data End Bit Error */ 1251 #define _SDIO_FEVTERRSTAT_DATEBE_SHIFT 22 /**< Shift value for SDIO_DATEBE */ 1252 #define _SDIO_FEVTERRSTAT_DATEBE_MASK 0x400000UL /**< Bit mask for SDIO_DATEBE */ 1253 #define _SDIO_FEVTERRSTAT_DATEBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1254 #define SDIO_FEVTERRSTAT_DATEBE_DEFAULT (_SDIO_FEVTERRSTAT_DATEBE_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1255 #define SDIO_FEVTERRSTAT_CURLIMITE (0x1UL << 23) /**< Force Event for Current Limit Error */ 1256 #define _SDIO_FEVTERRSTAT_CURLIMITE_SHIFT 23 /**< Shift value for SDIO_CURLIMITE */ 1257 #define _SDIO_FEVTERRSTAT_CURLIMITE_MASK 0x800000UL /**< Bit mask for SDIO_CURLIMITE */ 1258 #define _SDIO_FEVTERRSTAT_CURLIMITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1259 #define SDIO_FEVTERRSTAT_CURLIMITE_DEFAULT (_SDIO_FEVTERRSTAT_CURLIMITE_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1260 #define SDIO_FEVTERRSTAT_AC12E (0x1UL << 24) /**< Force Event for Auto CMD Error */ 1261 #define _SDIO_FEVTERRSTAT_AC12E_SHIFT 24 /**< Shift value for SDIO_AC12E */ 1262 #define _SDIO_FEVTERRSTAT_AC12E_MASK 0x1000000UL /**< Bit mask for SDIO_AC12E */ 1263 #define _SDIO_FEVTERRSTAT_AC12E_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1264 #define SDIO_FEVTERRSTAT_AC12E_DEFAULT (_SDIO_FEVTERRSTAT_AC12E_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1265 #define SDIO_FEVTERRSTAT_ADMAE (0x1UL << 25) /**< Force Event for ADMA Error */ 1266 #define _SDIO_FEVTERRSTAT_ADMAE_SHIFT 25 /**< Shift value for SDIO_ADMAE */ 1267 #define _SDIO_FEVTERRSTAT_ADMAE_MASK 0x2000000UL /**< Bit mask for SDIO_ADMAE */ 1268 #define _SDIO_FEVTERRSTAT_ADMAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1269 #define SDIO_FEVTERRSTAT_ADMAE_DEFAULT (_SDIO_FEVTERRSTAT_ADMAE_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1270 #define SDIO_FEVTERRSTAT_TUNINGE (0x1UL << 26) /**< Force Event for Tuning Errro */ 1271 #define _SDIO_FEVTERRSTAT_TUNINGE_SHIFT 26 /**< Shift value for SDIO_TUNINGE */ 1272 #define _SDIO_FEVTERRSTAT_TUNINGE_MASK 0x4000000UL /**< Bit mask for SDIO_TUNINGE */ 1273 #define _SDIO_FEVTERRSTAT_TUNINGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1274 #define SDIO_FEVTERRSTAT_TUNINGE_DEFAULT (_SDIO_FEVTERRSTAT_TUNINGE_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1275 #define _SDIO_FEVTERRSTAT_VENSPECE_SHIFT 28 /**< Shift value for SDIO_VENSPECE */ 1276 #define _SDIO_FEVTERRSTAT_VENSPECE_MASK 0xF0000000UL /**< Bit mask for SDIO_VENSPECE */ 1277 #define _SDIO_FEVTERRSTAT_VENSPECE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ 1278 #define SDIO_FEVTERRSTAT_VENSPECE_DEFAULT (_SDIO_FEVTERRSTAT_VENSPECE_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ 1279 1280 /* Bit fields for SDIO ADMAES */ 1281 #define _SDIO_ADMAES_RESETVALUE 0x00000000UL /**< Default value for SDIO_ADMAES */ 1282 #define _SDIO_ADMAES_MASK 0x00000007UL /**< Mask for SDIO_ADMAES */ 1283 #define _SDIO_ADMAES_ADMAES_SHIFT 0 /**< Shift value for SDIO_ADMAES */ 1284 #define _SDIO_ADMAES_ADMAES_MASK 0x3UL /**< Bit mask for SDIO_ADMAES */ 1285 #define _SDIO_ADMAES_ADMAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ADMAES */ 1286 #define SDIO_ADMAES_ADMAES_DEFAULT (_SDIO_ADMAES_ADMAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ADMAES */ 1287 #define SDIO_ADMAES_ADMALME (0x1UL << 2) /**< ADMA Length Mismatch Error */ 1288 #define _SDIO_ADMAES_ADMALME_SHIFT 2 /**< Shift value for SDIO_ADMALME */ 1289 #define _SDIO_ADMAES_ADMALME_MASK 0x4UL /**< Bit mask for SDIO_ADMALME */ 1290 #define _SDIO_ADMAES_ADMALME_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ADMAES */ 1291 #define SDIO_ADMAES_ADMALME_DEFAULT (_SDIO_ADMAES_ADMALME_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_ADMAES */ 1292 1293 /* Bit fields for SDIO ADSADDR */ 1294 #define _SDIO_ADSADDR_RESETVALUE 0x00000000UL /**< Default value for SDIO_ADSADDR */ 1295 #define _SDIO_ADSADDR_MASK 0xFFFFFFFFUL /**< Mask for SDIO_ADSADDR */ 1296 #define _SDIO_ADSADDR_ADSADDR_SHIFT 0 /**< Shift value for SDIO_ADSADDR */ 1297 #define _SDIO_ADSADDR_ADSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_ADSADDR */ 1298 #define _SDIO_ADSADDR_ADSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ADSADDR */ 1299 #define SDIO_ADSADDR_ADSADDR_DEFAULT (_SDIO_ADSADDR_ADSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ADSADDR */ 1300 1301 /* Bit fields for SDIO PRSTVAL0 */ 1302 #define _SDIO_PRSTVAL0_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSTVAL0 */ 1303 #define _SDIO_PRSTVAL0_MASK 0xC7FFC7FFUL /**< Mask for SDIO_PRSTVAL0 */ 1304 #define _SDIO_PRSTVAL0_INITSDCLKFREQVAL_SHIFT 0 /**< Shift value for SDIO_INITSDCLKFREQVAL */ 1305 #define _SDIO_PRSTVAL0_INITSDCLKFREQVAL_MASK 0x3FFUL /**< Bit mask for SDIO_INITSDCLKFREQVAL */ 1306 #define _SDIO_PRSTVAL0_INITSDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */ 1307 #define SDIO_PRSTVAL0_INITSDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL0_INITSDCLKFREQVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */ 1308 #define SDIO_PRSTVAL0_INITCLCKGENVAL (0x1UL << 10) /**< Clock Generator Select Value for Initialization */ 1309 #define _SDIO_PRSTVAL0_INITCLCKGENVAL_SHIFT 10 /**< Shift value for SDIO_INITCLCKGENVAL */ 1310 #define _SDIO_PRSTVAL0_INITCLCKGENVAL_MASK 0x400UL /**< Bit mask for SDIO_INITCLCKGENVAL */ 1311 #define _SDIO_PRSTVAL0_INITCLCKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */ 1312 #define SDIO_PRSTVAL0_INITCLCKGENVAL_DEFAULT (_SDIO_PRSTVAL0_INITCLCKGENVAL_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */ 1313 #define _SDIO_PRSTVAL0_INITDRVSTVAL_SHIFT 14 /**< Shift value for SDIO_INITDRVSTVAL */ 1314 #define _SDIO_PRSTVAL0_INITDRVSTVAL_MASK 0xC000UL /**< Bit mask for SDIO_INITDRVSTVAL */ 1315 #define _SDIO_PRSTVAL0_INITDRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */ 1316 #define _SDIO_PRSTVAL0_INITDRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL0 */ 1317 #define _SDIO_PRSTVAL0_INITDRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL0 */ 1318 #define _SDIO_PRSTVAL0_INITDRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL0 */ 1319 #define _SDIO_PRSTVAL0_INITDRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL0 */ 1320 #define SDIO_PRSTVAL0_INITDRVSTVAL_DEFAULT (_SDIO_PRSTVAL0_INITDRVSTVAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */ 1321 #define SDIO_PRSTVAL0_INITDRVSTVAL_TYPEB (_SDIO_PRSTVAL0_INITDRVSTVAL_TYPEB << 14) /**< Shifted mode TYPEB for SDIO_PRSTVAL0 */ 1322 #define SDIO_PRSTVAL0_INITDRVSTVAL_TYPEA (_SDIO_PRSTVAL0_INITDRVSTVAL_TYPEA << 14) /**< Shifted mode TYPEA for SDIO_PRSTVAL0 */ 1323 #define SDIO_PRSTVAL0_INITDRVSTVAL_TYPEC (_SDIO_PRSTVAL0_INITDRVSTVAL_TYPEC << 14) /**< Shifted mode TYPEC for SDIO_PRSTVAL0 */ 1324 #define SDIO_PRSTVAL0_INITDRVSTVAL_TYPED (_SDIO_PRSTVAL0_INITDRVSTVAL_TYPED << 14) /**< Shifted mode TYPED for SDIO_PRSTVAL0 */ 1325 #define _SDIO_PRSTVAL0_DSPSDCLKFREQVAL_SHIFT 16 /**< Shift value for SDIO_DSPSDCLKFREQVAL */ 1326 #define _SDIO_PRSTVAL0_DSPSDCLKFREQVAL_MASK 0x3FF0000UL /**< Bit mask for SDIO_DSPSDCLKFREQVAL */ 1327 #define _SDIO_PRSTVAL0_DSPSDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */ 1328 #define SDIO_PRSTVAL0_DSPSDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL0_DSPSDCLKFREQVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */ 1329 #define SDIO_PRSTVAL0_DSPCLKGENVAL (0x1UL << 26) /**< Clock Generator Select Value for Default Speed */ 1330 #define _SDIO_PRSTVAL0_DSPCLKGENVAL_SHIFT 26 /**< Shift value for SDIO_DSPCLKGENVAL */ 1331 #define _SDIO_PRSTVAL0_DSPCLKGENVAL_MASK 0x4000000UL /**< Bit mask for SDIO_DSPCLKGENVAL */ 1332 #define _SDIO_PRSTVAL0_DSPCLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */ 1333 #define SDIO_PRSTVAL0_DSPCLKGENVAL_DEFAULT (_SDIO_PRSTVAL0_DSPCLKGENVAL_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */ 1334 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_SHIFT 30 /**< Shift value for SDIO_DSPDRVSTVAL */ 1335 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_MASK 0xC0000000UL /**< Bit mask for SDIO_DSPDRVSTVAL */ 1336 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */ 1337 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL0 */ 1338 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL0 */ 1339 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL0 */ 1340 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL0 */ 1341 #define SDIO_PRSTVAL0_DSPDRVSTVAL_DEFAULT (_SDIO_PRSTVAL0_DSPDRVSTVAL_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */ 1342 #define SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEB (_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEB << 30) /**< Shifted mode TYPEB for SDIO_PRSTVAL0 */ 1343 #define SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEA (_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEA << 30) /**< Shifted mode TYPEA for SDIO_PRSTVAL0 */ 1344 #define SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEC (_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEC << 30) /**< Shifted mode TYPEC for SDIO_PRSTVAL0 */ 1345 #define SDIO_PRSTVAL0_DSPDRVSTVAL_TYPED (_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPED << 30) /**< Shifted mode TYPED for SDIO_PRSTVAL0 */ 1346 1347 /* Bit fields for SDIO PRSTVAL2 */ 1348 #define _SDIO_PRSTVAL2_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSTVAL2 */ 1349 #define _SDIO_PRSTVAL2_MASK 0xC7FFC7FFUL /**< Mask for SDIO_PRSTVAL2 */ 1350 #define _SDIO_PRSTVAL2_HSPSDCLKFREQVAL_SHIFT 0 /**< Shift value for SDIO_HSPSDCLKFREQVAL */ 1351 #define _SDIO_PRSTVAL2_HSPSDCLKFREQVAL_MASK 0x3FFUL /**< Bit mask for SDIO_HSPSDCLKFREQVAL */ 1352 #define _SDIO_PRSTVAL2_HSPSDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */ 1353 #define SDIO_PRSTVAL2_HSPSDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL2_HSPSDCLKFREQVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */ 1354 #define SDIO_PRSTVAL2_HSPCLKGENVAL (0x1UL << 10) /**< Clock Generator Select Value for High Speed */ 1355 #define _SDIO_PRSTVAL2_HSPCLKGENVAL_SHIFT 10 /**< Shift value for SDIO_HSPCLKGENVAL */ 1356 #define _SDIO_PRSTVAL2_HSPCLKGENVAL_MASK 0x400UL /**< Bit mask for SDIO_HSPCLKGENVAL */ 1357 #define _SDIO_PRSTVAL2_HSPCLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */ 1358 #define SDIO_PRSTVAL2_HSPCLKGENVAL_DEFAULT (_SDIO_PRSTVAL2_HSPCLKGENVAL_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */ 1359 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_SHIFT 14 /**< Shift value for SDIO_HSPDRVSTVAL */ 1360 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_MASK 0xC000UL /**< Bit mask for SDIO_HSPDRVSTVAL */ 1361 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */ 1362 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL2 */ 1363 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL2 */ 1364 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL2 */ 1365 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL2 */ 1366 #define SDIO_PRSTVAL2_HSPDRVSTVAL_DEFAULT (_SDIO_PRSTVAL2_HSPDRVSTVAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */ 1367 #define SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEB (_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEB << 14) /**< Shifted mode TYPEB for SDIO_PRSTVAL2 */ 1368 #define SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEA (_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEA << 14) /**< Shifted mode TYPEA for SDIO_PRSTVAL2 */ 1369 #define SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEC (_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEC << 14) /**< Shifted mode TYPEC for SDIO_PRSTVAL2 */ 1370 #define SDIO_PRSTVAL2_HSPDRVSTVAL_TYPED (_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPED << 14) /**< Shifted mode TYPED for SDIO_PRSTVAL2 */ 1371 #define _SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_SHIFT 16 /**< Shift value for SDIO_SDR12SDCLKFREQVAL */ 1372 #define _SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_MASK 0x3FF0000UL /**< Bit mask for SDIO_SDR12SDCLKFREQVAL */ 1373 #define _SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */ 1374 #define SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */ 1375 #define SDIO_PRSTVAL2_SDR12CLKGENVAL (0x1UL << 26) /**< Clock Generator Select Value for SDR12 */ 1376 #define _SDIO_PRSTVAL2_SDR12CLKGENVAL_SHIFT 26 /**< Shift value for SDIO_SDR12CLKGENVAL */ 1377 #define _SDIO_PRSTVAL2_SDR12CLKGENVAL_MASK 0x4000000UL /**< Bit mask for SDIO_SDR12CLKGENVAL */ 1378 #define _SDIO_PRSTVAL2_SDR12CLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */ 1379 #define SDIO_PRSTVAL2_SDR12CLKGENVAL_DEFAULT (_SDIO_PRSTVAL2_SDR12CLKGENVAL_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */ 1380 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_SHIFT 30 /**< Shift value for SDIO_SDR12DRVSTVAL */ 1381 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_MASK 0xC0000000UL /**< Bit mask for SDIO_SDR12DRVSTVAL */ 1382 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */ 1383 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL2 */ 1384 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL2 */ 1385 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL2 */ 1386 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL2 */ 1387 #define SDIO_PRSTVAL2_SDR12DRVSTVAL_DEFAULT (_SDIO_PRSTVAL2_SDR12DRVSTVAL_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */ 1388 #define SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEB (_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEB << 30) /**< Shifted mode TYPEB for SDIO_PRSTVAL2 */ 1389 #define SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEA (_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEA << 30) /**< Shifted mode TYPEA for SDIO_PRSTVAL2 */ 1390 #define SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEC (_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEC << 30) /**< Shifted mode TYPEC for SDIO_PRSTVAL2 */ 1391 #define SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPED (_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPED << 30) /**< Shifted mode TYPED for SDIO_PRSTVAL2 */ 1392 1393 /* Bit fields for SDIO PRSTVAL4 */ 1394 #define _SDIO_PRSTVAL4_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSTVAL4 */ 1395 #define _SDIO_PRSTVAL4_MASK 0xC7FFC7FFUL /**< Mask for SDIO_PRSTVAL4 */ 1396 #define _SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_SHIFT 0 /**< Shift value for SDIO_SDR25SDCLKFREQVAL */ 1397 #define _SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_MASK 0x3FFUL /**< Bit mask for SDIO_SDR25SDCLKFREQVAL */ 1398 #define _SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */ 1399 #define SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */ 1400 #define SDIO_PRSTVAL4_SDR25CLKGENVAL (0x1UL << 10) /**< Clock Generator Select Value for SDR25 */ 1401 #define _SDIO_PRSTVAL4_SDR25CLKGENVAL_SHIFT 10 /**< Shift value for SDIO_SDR25CLKGENVAL */ 1402 #define _SDIO_PRSTVAL4_SDR25CLKGENVAL_MASK 0x400UL /**< Bit mask for SDIO_SDR25CLKGENVAL */ 1403 #define _SDIO_PRSTVAL4_SDR25CLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */ 1404 #define SDIO_PRSTVAL4_SDR25CLKGENVAL_DEFAULT (_SDIO_PRSTVAL4_SDR25CLKGENVAL_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */ 1405 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_SHIFT 14 /**< Shift value for SDIO_SDR25DRVSTVAL */ 1406 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_MASK 0xC000UL /**< Bit mask for SDIO_SDR25DRVSTVAL */ 1407 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */ 1408 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL4 */ 1409 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL4 */ 1410 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL4 */ 1411 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL4 */ 1412 #define SDIO_PRSTVAL4_SDR25DRVSTVAL_DEFAULT (_SDIO_PRSTVAL4_SDR25DRVSTVAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */ 1413 #define SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEB (_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEB << 14) /**< Shifted mode TYPEB for SDIO_PRSTVAL4 */ 1414 #define SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEA (_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEA << 14) /**< Shifted mode TYPEA for SDIO_PRSTVAL4 */ 1415 #define SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEC (_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEC << 14) /**< Shifted mode TYPEC for SDIO_PRSTVAL4 */ 1416 #define SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPED (_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPED << 14) /**< Shifted mode TYPED for SDIO_PRSTVAL4 */ 1417 #define _SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_SHIFT 16 /**< Shift value for SDIO_SDR50SDCLKFREQVAL */ 1418 #define _SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_MASK 0x3FF0000UL /**< Bit mask for SDIO_SDR50SDCLKFREQVAL */ 1419 #define _SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */ 1420 #define SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */ 1421 #define SDIO_PRSTVAL4_SDR50CLCKGENVAL (0x1UL << 26) /**< Clock Generator Select Value for SDR50 */ 1422 #define _SDIO_PRSTVAL4_SDR50CLCKGENVAL_SHIFT 26 /**< Shift value for SDIO_SDR50CLCKGENVAL */ 1423 #define _SDIO_PRSTVAL4_SDR50CLCKGENVAL_MASK 0x4000000UL /**< Bit mask for SDIO_SDR50CLCKGENVAL */ 1424 #define _SDIO_PRSTVAL4_SDR50CLCKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */ 1425 #define SDIO_PRSTVAL4_SDR50CLCKGENVAL_DEFAULT (_SDIO_PRSTVAL4_SDR50CLCKGENVAL_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */ 1426 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_SHIFT 30 /**< Shift value for SDIO_SDR50DRVSTVAL */ 1427 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_MASK 0xC0000000UL /**< Bit mask for SDIO_SDR50DRVSTVAL */ 1428 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */ 1429 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL4 */ 1430 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL4 */ 1431 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL4 */ 1432 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL4 */ 1433 #define SDIO_PRSTVAL4_SDR50DRVSTVAL_DEFAULT (_SDIO_PRSTVAL4_SDR50DRVSTVAL_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */ 1434 #define SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEB (_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEB << 30) /**< Shifted mode TYPEB for SDIO_PRSTVAL4 */ 1435 #define SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEA (_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEA << 30) /**< Shifted mode TYPEA for SDIO_PRSTVAL4 */ 1436 #define SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEC (_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEC << 30) /**< Shifted mode TYPEC for SDIO_PRSTVAL4 */ 1437 #define SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPED (_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPED << 30) /**< Shifted mode TYPED for SDIO_PRSTVAL4 */ 1438 1439 /* Bit fields for SDIO PRSTVAL6 */ 1440 #define _SDIO_PRSTVAL6_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSTVAL6 */ 1441 #define _SDIO_PRSTVAL6_MASK 0xC7FFC7FFUL /**< Mask for SDIO_PRSTVAL6 */ 1442 #define _SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_SHIFT 0 /**< Shift value for SDIO_SDR104SDCLKFREQVAL */ 1443 #define _SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_MASK 0x3FFUL /**< Bit mask for SDIO_SDR104SDCLKFREQVAL */ 1444 #define _SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */ 1445 #define SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */ 1446 #define SDIO_PRSTVAL6_SDR104CLKGENVAL (0x1UL << 10) /**< Clock Generator Select Value for SDR104 */ 1447 #define _SDIO_PRSTVAL6_SDR104CLKGENVAL_SHIFT 10 /**< Shift value for SDIO_SDR104CLKGENVAL */ 1448 #define _SDIO_PRSTVAL6_SDR104CLKGENVAL_MASK 0x400UL /**< Bit mask for SDIO_SDR104CLKGENVAL */ 1449 #define _SDIO_PRSTVAL6_SDR104CLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */ 1450 #define SDIO_PRSTVAL6_SDR104CLKGENVAL_DEFAULT (_SDIO_PRSTVAL6_SDR104CLKGENVAL_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */ 1451 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_SHIFT 14 /**< Shift value for SDIO_SDR104DRVSTVAL */ 1452 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_MASK 0xC000UL /**< Bit mask for SDIO_SDR104DRVSTVAL */ 1453 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */ 1454 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL6 */ 1455 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL6 */ 1456 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL6 */ 1457 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL6 */ 1458 #define SDIO_PRSTVAL6_SDR104DRVSTVAL_DEFAULT (_SDIO_PRSTVAL6_SDR104DRVSTVAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */ 1459 #define SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEB (_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEB << 14) /**< Shifted mode TYPEB for SDIO_PRSTVAL6 */ 1460 #define SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEA (_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEA << 14) /**< Shifted mode TYPEA for SDIO_PRSTVAL6 */ 1461 #define SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEC (_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEC << 14) /**< Shifted mode TYPEC for SDIO_PRSTVAL6 */ 1462 #define SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPED (_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPED << 14) /**< Shifted mode TYPED for SDIO_PRSTVAL6 */ 1463 #define _SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_SHIFT 16 /**< Shift value for SDIO_DDR50SDCLKFREQVAL */ 1464 #define _SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_MASK 0x3FF0000UL /**< Bit mask for SDIO_DDR50SDCLKFREQVAL */ 1465 #define _SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */ 1466 #define SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */ 1467 #define SDIO_PRSTVAL6_DDR50CLKGENVAL (0x1UL << 26) /**< Clock Generator Select Value for DDR50 */ 1468 #define _SDIO_PRSTVAL6_DDR50CLKGENVAL_SHIFT 26 /**< Shift value for SDIO_DDR50CLKGENVAL */ 1469 #define _SDIO_PRSTVAL6_DDR50CLKGENVAL_MASK 0x4000000UL /**< Bit mask for SDIO_DDR50CLKGENVAL */ 1470 #define _SDIO_PRSTVAL6_DDR50CLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */ 1471 #define SDIO_PRSTVAL6_DDR50CLKGENVAL_DEFAULT (_SDIO_PRSTVAL6_DDR50CLKGENVAL_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */ 1472 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_SHIFT 30 /**< Shift value for SDIO_DDR50DRVSTVAL */ 1473 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_MASK 0xC0000000UL /**< Bit mask for SDIO_DDR50DRVSTVAL */ 1474 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */ 1475 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL6 */ 1476 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL6 */ 1477 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL6 */ 1478 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL6 */ 1479 #define SDIO_PRSTVAL6_DDR50DRVSTVAL_DEFAULT (_SDIO_PRSTVAL6_DDR50DRVSTVAL_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */ 1480 #define SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEB (_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEB << 30) /**< Shifted mode TYPEB for SDIO_PRSTVAL6 */ 1481 #define SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEA (_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEA << 30) /**< Shifted mode TYPEA for SDIO_PRSTVAL6 */ 1482 #define SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEC (_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEC << 30) /**< Shifted mode TYPEC for SDIO_PRSTVAL6 */ 1483 #define SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPED (_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPED << 30) /**< Shifted mode TYPED for SDIO_PRSTVAL6 */ 1484 1485 /* Bit fields for SDIO BOOTTOCTRL */ 1486 #define _SDIO_BOOTTOCTRL_RESETVALUE 0x00000000UL /**< Default value for SDIO_BOOTTOCTRL */ 1487 #define _SDIO_BOOTTOCTRL_MASK 0xFFFFFFFFUL /**< Mask for SDIO_BOOTTOCTRL */ 1488 #define _SDIO_BOOTTOCTRL_BOOTDATTOCNT_SHIFT 0 /**< Shift value for SDIO_BOOTDATTOCNT */ 1489 #define _SDIO_BOOTTOCTRL_BOOTDATTOCNT_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_BOOTDATTOCNT */ 1490 #define _SDIO_BOOTTOCTRL_BOOTDATTOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BOOTTOCTRL */ 1491 #define SDIO_BOOTTOCTRL_BOOTDATTOCNT_DEFAULT (_SDIO_BOOTTOCTRL_BOOTDATTOCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_BOOTTOCTRL */ 1492 1493 /* Bit fields for SDIO SLOTINTSTAT */ 1494 #define _SDIO_SLOTINTSTAT_RESETVALUE 0x10020000UL /**< Default value for SDIO_SLOTINTSTAT */ 1495 #define _SDIO_SLOTINTSTAT_MASK 0xFFFF0001UL /**< Mask for SDIO_SLOTINTSTAT */ 1496 #define SDIO_SLOTINTSTAT_INTSLOT0 (0x1UL << 0) /**< Interrupt Signal for Slot#0 */ 1497 #define _SDIO_SLOTINTSTAT_INTSLOT0_SHIFT 0 /**< Shift value for SDIO_INTSLOT0 */ 1498 #define _SDIO_SLOTINTSTAT_INTSLOT0_MASK 0x1UL /**< Bit mask for SDIO_INTSLOT0 */ 1499 #define _SDIO_SLOTINTSTAT_INTSLOT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_SLOTINTSTAT */ 1500 #define SDIO_SLOTINTSTAT_INTSLOT0_DEFAULT (_SDIO_SLOTINTSTAT_INTSLOT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_SLOTINTSTAT */ 1501 #define _SDIO_SLOTINTSTAT_SPECVERNUM_SHIFT 16 /**< Shift value for SDIO_SPECVERNUM */ 1502 #define _SDIO_SLOTINTSTAT_SPECVERNUM_MASK 0xFF0000UL /**< Bit mask for SDIO_SPECVERNUM */ 1503 #define _SDIO_SLOTINTSTAT_SPECVERNUM_DEFAULT 0x00000002UL /**< Mode DEFAULT for SDIO_SLOTINTSTAT */ 1504 #define SDIO_SLOTINTSTAT_SPECVERNUM_DEFAULT (_SDIO_SLOTINTSTAT_SPECVERNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_SLOTINTSTAT */ 1505 #define _SDIO_SLOTINTSTAT_VENDVERNUM_SHIFT 24 /**< Shift value for SDIO_VENDVERNUM */ 1506 #define _SDIO_SLOTINTSTAT_VENDVERNUM_MASK 0xFF000000UL /**< Bit mask for SDIO_VENDVERNUM */ 1507 #define _SDIO_SLOTINTSTAT_VENDVERNUM_DEFAULT 0x00000010UL /**< Mode DEFAULT for SDIO_SLOTINTSTAT */ 1508 #define SDIO_SLOTINTSTAT_VENDVERNUM_DEFAULT (_SDIO_SLOTINTSTAT_VENDVERNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_SLOTINTSTAT */ 1509 1510 /* Bit fields for SDIO CTRL */ 1511 #define _SDIO_CTRL_RESETVALUE 0x00000000UL /**< Default value for SDIO_CTRL */ 1512 #define _SDIO_CTRL_MASK 0x00030FFFUL /**< Mask for SDIO_CTRL */ 1513 #define SDIO_CTRL_ITAPDLYEN (0x1UL << 0) /**< Selective Tap Delay Line Enable on Rxclk_in */ 1514 #define _SDIO_CTRL_ITAPDLYEN_SHIFT 0 /**< Shift value for SDIO_ITAPDLYEN */ 1515 #define _SDIO_CTRL_ITAPDLYEN_MASK 0x1UL /**< Bit mask for SDIO_ITAPDLYEN */ 1516 #define _SDIO_CTRL_ITAPDLYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */ 1517 #define SDIO_CTRL_ITAPDLYEN_DEFAULT (_SDIO_CTRL_ITAPDLYEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CTRL */ 1518 #define _SDIO_CTRL_ITAPDLYSEL_SHIFT 1 /**< Shift value for SDIO_ITAPDLYSEL */ 1519 #define _SDIO_CTRL_ITAPDLYSEL_MASK 0x3EUL /**< Bit mask for SDIO_ITAPDLYSEL */ 1520 #define _SDIO_CTRL_ITAPDLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */ 1521 #define SDIO_CTRL_ITAPDLYSEL_DEFAULT (_SDIO_CTRL_ITAPDLYSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_CTRL */ 1522 #define SDIO_CTRL_ITAPCHGWIN (0x1UL << 6) /**< Gating Signal for Tap Delay Change */ 1523 #define _SDIO_CTRL_ITAPCHGWIN_SHIFT 6 /**< Shift value for SDIO_ITAPCHGWIN */ 1524 #define _SDIO_CTRL_ITAPCHGWIN_MASK 0x40UL /**< Bit mask for SDIO_ITAPCHGWIN */ 1525 #define _SDIO_CTRL_ITAPCHGWIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */ 1526 #define SDIO_CTRL_ITAPCHGWIN_DEFAULT (_SDIO_CTRL_ITAPCHGWIN_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CTRL */ 1527 #define SDIO_CTRL_OTAPDLYEN (0x1UL << 7) /**< Selective Tap Delay Line Enable on SDIO_CLK Pin */ 1528 #define _SDIO_CTRL_OTAPDLYEN_SHIFT 7 /**< Shift value for SDIO_OTAPDLYEN */ 1529 #define _SDIO_CTRL_OTAPDLYEN_MASK 0x80UL /**< Bit mask for SDIO_OTAPDLYEN */ 1530 #define _SDIO_CTRL_OTAPDLYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */ 1531 #define SDIO_CTRL_OTAPDLYEN_DEFAULT (_SDIO_CTRL_OTAPDLYEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_CTRL */ 1532 #define _SDIO_CTRL_OTAPDLYSEL_SHIFT 8 /**< Shift value for SDIO_OTAPDLYSEL */ 1533 #define _SDIO_CTRL_OTAPDLYSEL_MASK 0xF00UL /**< Bit mask for SDIO_OTAPDLYSEL */ 1534 #define _SDIO_CTRL_OTAPDLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */ 1535 #define SDIO_CTRL_OTAPDLYSEL_DEFAULT (_SDIO_CTRL_OTAPDLYSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CTRL */ 1536 #define _SDIO_CTRL_TXDLYMUXSEL_SHIFT 16 /**< Shift value for SDIO_TXDLYMUXSEL */ 1537 #define _SDIO_CTRL_TXDLYMUXSEL_MASK 0x30000UL /**< Bit mask for SDIO_TXDLYMUXSEL */ 1538 #define _SDIO_CTRL_TXDLYMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */ 1539 #define SDIO_CTRL_TXDLYMUXSEL_DEFAULT (_SDIO_CTRL_TXDLYMUXSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CTRL */ 1540 1541 /* Bit fields for SDIO CFG0 */ 1542 #define _SDIO_CFG0_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFG0 */ 1543 #define _SDIO_CFG0_MASK 0x7FFFFFFFUL /**< Mask for SDIO_CFG0 */ 1544 #define _SDIO_CFG0_TUNINGCNT_SHIFT 0 /**< Shift value for SDIO_TUNINGCNT */ 1545 #define _SDIO_CFG0_TUNINGCNT_MASK 0x3FUL /**< Bit mask for SDIO_TUNINGCNT */ 1546 #define _SDIO_CFG0_TUNINGCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1547 #define SDIO_CFG0_TUNINGCNT_DEFAULT (_SDIO_CFG0_TUNINGCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1548 #define _SDIO_CFG0_TOUTCLKFREQ_SHIFT 6 /**< Shift value for SDIO_TOUTCLKFREQ */ 1549 #define _SDIO_CFG0_TOUTCLKFREQ_MASK 0xFC0UL /**< Bit mask for SDIO_TOUTCLKFREQ */ 1550 #define _SDIO_CFG0_TOUTCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1551 #define SDIO_CFG0_TOUTCLKFREQ_DEFAULT (_SDIO_CFG0_TOUTCLKFREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1552 #define SDIO_CFG0_TOUTCLKUNIT (0x1UL << 12) /**< Timeout Clock Unit in kHz or MHz */ 1553 #define _SDIO_CFG0_TOUTCLKUNIT_SHIFT 12 /**< Shift value for SDIO_TOUTCLKUNIT */ 1554 #define _SDIO_CFG0_TOUTCLKUNIT_MASK 0x1000UL /**< Bit mask for SDIO_TOUTCLKUNIT */ 1555 #define _SDIO_CFG0_TOUTCLKUNIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1556 #define SDIO_CFG0_TOUTCLKUNIT_DEFAULT (_SDIO_CFG0_TOUTCLKUNIT_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1557 #define _SDIO_CFG0_BASECLKFREQ_SHIFT 13 /**< Shift value for SDIO_BASECLKFREQ */ 1558 #define _SDIO_CFG0_BASECLKFREQ_MASK 0x1FE000UL /**< Bit mask for SDIO_BASECLKFREQ */ 1559 #define _SDIO_CFG0_BASECLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1560 #define SDIO_CFG0_BASECLKFREQ_DEFAULT (_SDIO_CFG0_BASECLKFREQ_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1561 #define _SDIO_CFG0_MAXBLKLEN_SHIFT 21 /**< Shift value for SDIO_MAXBLKLEN */ 1562 #define _SDIO_CFG0_MAXBLKLEN_MASK 0x600000UL /**< Bit mask for SDIO_MAXBLKLEN */ 1563 #define _SDIO_CFG0_MAXBLKLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1564 #define _SDIO_CFG0_MAXBLKLEN_512B 0x00000000UL /**< Mode 512B for SDIO_CFG0 */ 1565 #define _SDIO_CFG0_MAXBLKLEN_1024B 0x00000001UL /**< Mode 1024B for SDIO_CFG0 */ 1566 #define _SDIO_CFG0_MAXBLKLEN_2048B 0x00000002UL /**< Mode 2048B for SDIO_CFG0 */ 1567 #define SDIO_CFG0_MAXBLKLEN_DEFAULT (_SDIO_CFG0_MAXBLKLEN_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1568 #define SDIO_CFG0_MAXBLKLEN_512B (_SDIO_CFG0_MAXBLKLEN_512B << 21) /**< Shifted mode 512B for SDIO_CFG0 */ 1569 #define SDIO_CFG0_MAXBLKLEN_1024B (_SDIO_CFG0_MAXBLKLEN_1024B << 21) /**< Shifted mode 1024B for SDIO_CFG0 */ 1570 #define SDIO_CFG0_MAXBLKLEN_2048B (_SDIO_CFG0_MAXBLKLEN_2048B << 21) /**< Shifted mode 2048B for SDIO_CFG0 */ 1571 #define SDIO_CFG0_C8BITSUP (0x1UL << 23) /**< 8-bit Interface Support */ 1572 #define _SDIO_CFG0_C8BITSUP_SHIFT 23 /**< Shift value for SDIO_C8BITSUP */ 1573 #define _SDIO_CFG0_C8BITSUP_MASK 0x800000UL /**< Bit mask for SDIO_C8BITSUP */ 1574 #define _SDIO_CFG0_C8BITSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1575 #define SDIO_CFG0_C8BITSUP_DEFAULT (_SDIO_CFG0_C8BITSUP_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1576 #define SDIO_CFG0_CADMA2SUP (0x1UL << 24) /**< ADMA2 Mode Support */ 1577 #define _SDIO_CFG0_CADMA2SUP_SHIFT 24 /**< Shift value for SDIO_CADMA2SUP */ 1578 #define _SDIO_CFG0_CADMA2SUP_MASK 0x1000000UL /**< Bit mask for SDIO_CADMA2SUP */ 1579 #define _SDIO_CFG0_CADMA2SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1580 #define SDIO_CFG0_CADMA2SUP_DEFAULT (_SDIO_CFG0_CADMA2SUP_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1581 #define SDIO_CFG0_CHSSUP (0x1UL << 25) /**< High Speed Mode Support */ 1582 #define _SDIO_CFG0_CHSSUP_SHIFT 25 /**< Shift value for SDIO_CHSSUP */ 1583 #define _SDIO_CFG0_CHSSUP_MASK 0x2000000UL /**< Bit mask for SDIO_CHSSUP */ 1584 #define _SDIO_CFG0_CHSSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1585 #define SDIO_CFG0_CHSSUP_DEFAULT (_SDIO_CFG0_CHSSUP_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1586 #define SDIO_CFG0_CSDMASUP (0x1UL << 26) /**< SDMA Mode Support */ 1587 #define _SDIO_CFG0_CSDMASUP_SHIFT 26 /**< Shift value for SDIO_CSDMASUP */ 1588 #define _SDIO_CFG0_CSDMASUP_MASK 0x4000000UL /**< Bit mask for SDIO_CSDMASUP */ 1589 #define _SDIO_CFG0_CSDMASUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1590 #define SDIO_CFG0_CSDMASUP_DEFAULT (_SDIO_CFG0_CSDMASUP_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1591 #define SDIO_CFG0_CSUSPRESSUP (0x1UL << 27) /**< Suspend/Resume Support */ 1592 #define _SDIO_CFG0_CSUSPRESSUP_SHIFT 27 /**< Shift value for SDIO_CSUSPRESSUP */ 1593 #define _SDIO_CFG0_CSUSPRESSUP_MASK 0x8000000UL /**< Bit mask for SDIO_CSUSPRESSUP */ 1594 #define _SDIO_CFG0_CSUSPRESSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1595 #define SDIO_CFG0_CSUSPRESSUP_DEFAULT (_SDIO_CFG0_CSUSPRESSUP_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1596 #define SDIO_CFG0_C3P3VSUP (0x1UL << 28) /**< Core 3P3V Support */ 1597 #define _SDIO_CFG0_C3P3VSUP_SHIFT 28 /**< Shift value for SDIO_C3P3VSUP */ 1598 #define _SDIO_CFG0_C3P3VSUP_MASK 0x10000000UL /**< Bit mask for SDIO_C3P3VSUP */ 1599 #define _SDIO_CFG0_C3P3VSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1600 #define SDIO_CFG0_C3P3VSUP_DEFAULT (_SDIO_CFG0_C3P3VSUP_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1601 #define SDIO_CFG0_C3P0VSUP (0x1UL << 29) /**< 3P0V Support */ 1602 #define _SDIO_CFG0_C3P0VSUP_SHIFT 29 /**< Shift value for SDIO_C3P0VSUP */ 1603 #define _SDIO_CFG0_C3P0VSUP_MASK 0x20000000UL /**< Bit mask for SDIO_C3P0VSUP */ 1604 #define _SDIO_CFG0_C3P0VSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1605 #define SDIO_CFG0_C3P0VSUP_DEFAULT (_SDIO_CFG0_C3P0VSUP_DEFAULT << 29) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1606 #define SDIO_CFG0_C1P8VSUP (0x1UL << 30) /**< 1P8V Support */ 1607 #define _SDIO_CFG0_C1P8VSUP_SHIFT 30 /**< Shift value for SDIO_C1P8VSUP */ 1608 #define _SDIO_CFG0_C1P8VSUP_MASK 0x40000000UL /**< Bit mask for SDIO_C1P8VSUP */ 1609 #define _SDIO_CFG0_C1P8VSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ 1610 #define SDIO_CFG0_C1P8VSUP_DEFAULT (_SDIO_CFG0_C1P8VSUP_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_CFG0 */ 1611 1612 /* Bit fields for SDIO CFG1 */ 1613 #define _SDIO_CFG1_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFG1 */ 1614 #define _SDIO_CFG1_MASK 0x0005FFFFUL /**< Mask for SDIO_CFG1 */ 1615 #define SDIO_CFG1_ASYNCINTRSUP (0x1UL << 0) /**< Asynchronous Interrupt Support */ 1616 #define _SDIO_CFG1_ASYNCINTRSUP_SHIFT 0 /**< Shift value for SDIO_ASYNCINTRSUP */ 1617 #define _SDIO_CFG1_ASYNCINTRSUP_MASK 0x1UL /**< Bit mask for SDIO_ASYNCINTRSUP */ 1618 #define _SDIO_CFG1_ASYNCINTRSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1619 #define SDIO_CFG1_ASYNCINTRSUP_DEFAULT (_SDIO_CFG1_ASYNCINTRSUP_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1620 #define _SDIO_CFG1_SLOTTYPE_SHIFT 1 /**< Shift value for SDIO_SLOTTYPE */ 1621 #define _SDIO_CFG1_SLOTTYPE_MASK 0x6UL /**< Bit mask for SDIO_SLOTTYPE */ 1622 #define _SDIO_CFG1_SLOTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1623 #define _SDIO_CFG1_SLOTTYPE_RMSDSLOT 0x00000000UL /**< Mode RMSDSLOT for SDIO_CFG1 */ 1624 #define _SDIO_CFG1_SLOTTYPE_EMSDSLOT 0x00000001UL /**< Mode EMSDSLOT for SDIO_CFG1 */ 1625 #define _SDIO_CFG1_SLOTTYPE_SHBUSSLOT 0x00000002UL /**< Mode SHBUSSLOT for SDIO_CFG1 */ 1626 #define SDIO_CFG1_SLOTTYPE_DEFAULT (_SDIO_CFG1_SLOTTYPE_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1627 #define SDIO_CFG1_SLOTTYPE_RMSDSLOT (_SDIO_CFG1_SLOTTYPE_RMSDSLOT << 1) /**< Shifted mode RMSDSLOT for SDIO_CFG1 */ 1628 #define SDIO_CFG1_SLOTTYPE_EMSDSLOT (_SDIO_CFG1_SLOTTYPE_EMSDSLOT << 1) /**< Shifted mode EMSDSLOT for SDIO_CFG1 */ 1629 #define SDIO_CFG1_SLOTTYPE_SHBUSSLOT (_SDIO_CFG1_SLOTTYPE_SHBUSSLOT << 1) /**< Shifted mode SHBUSSLOT for SDIO_CFG1 */ 1630 #define SDIO_CFG1_CSDR50SUP (0x1UL << 3) /**< Core Support SDR50 */ 1631 #define _SDIO_CFG1_CSDR50SUP_SHIFT 3 /**< Shift value for SDIO_CSDR50SUP */ 1632 #define _SDIO_CFG1_CSDR50SUP_MASK 0x8UL /**< Bit mask for SDIO_CSDR50SUP */ 1633 #define _SDIO_CFG1_CSDR50SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1634 #define SDIO_CFG1_CSDR50SUP_DEFAULT (_SDIO_CFG1_CSDR50SUP_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1635 #define SDIO_CFG1_CSDR104SUP (0x1UL << 4) /**< Support SDR104 */ 1636 #define _SDIO_CFG1_CSDR104SUP_SHIFT 4 /**< Shift value for SDIO_CSDR104SUP */ 1637 #define _SDIO_CFG1_CSDR104SUP_MASK 0x10UL /**< Bit mask for SDIO_CSDR104SUP */ 1638 #define _SDIO_CFG1_CSDR104SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1639 #define SDIO_CFG1_CSDR104SUP_DEFAULT (_SDIO_CFG1_CSDR104SUP_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1640 #define SDIO_CFG1_CDDR50SUP (0x1UL << 5) /**< Support DDR50 */ 1641 #define _SDIO_CFG1_CDDR50SUP_SHIFT 5 /**< Shift value for SDIO_CDDR50SUP */ 1642 #define _SDIO_CFG1_CDDR50SUP_MASK 0x20UL /**< Bit mask for SDIO_CDDR50SUP */ 1643 #define _SDIO_CFG1_CDDR50SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1644 #define SDIO_CFG1_CDDR50SUP_DEFAULT (_SDIO_CFG1_CDDR50SUP_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1645 #define SDIO_CFG1_CDRVASUP (0x1UL << 6) /**< Support Type a Driver */ 1646 #define _SDIO_CFG1_CDRVASUP_SHIFT 6 /**< Shift value for SDIO_CDRVASUP */ 1647 #define _SDIO_CFG1_CDRVASUP_MASK 0x40UL /**< Bit mask for SDIO_CDRVASUP */ 1648 #define _SDIO_CFG1_CDRVASUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1649 #define SDIO_CFG1_CDRVASUP_DEFAULT (_SDIO_CFG1_CDRVASUP_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1650 #define SDIO_CFG1_CDRVCSUP (0x1UL << 7) /**< Support Type C Driver */ 1651 #define _SDIO_CFG1_CDRVCSUP_SHIFT 7 /**< Shift value for SDIO_CDRVCSUP */ 1652 #define _SDIO_CFG1_CDRVCSUP_MASK 0x80UL /**< Bit mask for SDIO_CDRVCSUP */ 1653 #define _SDIO_CFG1_CDRVCSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1654 #define SDIO_CFG1_CDRVCSUP_DEFAULT (_SDIO_CFG1_CDRVCSUP_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1655 #define SDIO_CFG1_CDRVDSUP (0x1UL << 8) /**< Support Type D Driver */ 1656 #define _SDIO_CFG1_CDRVDSUP_SHIFT 8 /**< Shift value for SDIO_CDRVDSUP */ 1657 #define _SDIO_CFG1_CDRVDSUP_MASK 0x100UL /**< Bit mask for SDIO_CDRVDSUP */ 1658 #define _SDIO_CFG1_CDRVDSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1659 #define SDIO_CFG1_CDRVDSUP_DEFAULT (_SDIO_CFG1_CDRVDSUP_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1660 #define _SDIO_CFG1_RETUNTMRCTL_SHIFT 9 /**< Shift value for SDIO_RETUNTMRCTL */ 1661 #define _SDIO_CFG1_RETUNTMRCTL_MASK 0x1E00UL /**< Bit mask for SDIO_RETUNTMRCTL */ 1662 #define _SDIO_CFG1_RETUNTMRCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1663 #define SDIO_CFG1_RETUNTMRCTL_DEFAULT (_SDIO_CFG1_RETUNTMRCTL_DEFAULT << 9) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1664 #define SDIO_CFG1_TUNSDR50 (0x1UL << 13) /**< Tuning for SDR50 */ 1665 #define _SDIO_CFG1_TUNSDR50_SHIFT 13 /**< Shift value for SDIO_TUNSDR50 */ 1666 #define _SDIO_CFG1_TUNSDR50_MASK 0x2000UL /**< Bit mask for SDIO_TUNSDR50 */ 1667 #define _SDIO_CFG1_TUNSDR50_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1668 #define SDIO_CFG1_TUNSDR50_DEFAULT (_SDIO_CFG1_TUNSDR50_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1669 #define _SDIO_CFG1_RETUNMODES_SHIFT 14 /**< Shift value for SDIO_RETUNMODES */ 1670 #define _SDIO_CFG1_RETUNMODES_MASK 0xC000UL /**< Bit mask for SDIO_RETUNMODES */ 1671 #define _SDIO_CFG1_RETUNMODES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1672 #define SDIO_CFG1_RETUNMODES_DEFAULT (_SDIO_CFG1_RETUNMODES_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1673 #define SDIO_CFG1_SPISUP (0x1UL << 16) /**< SPI Support */ 1674 #define _SDIO_CFG1_SPISUP_SHIFT 16 /**< Shift value for SDIO_SPISUP */ 1675 #define _SDIO_CFG1_SPISUP_MASK 0x10000UL /**< Bit mask for SDIO_SPISUP */ 1676 #define _SDIO_CFG1_SPISUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1677 #define SDIO_CFG1_SPISUP_DEFAULT (_SDIO_CFG1_SPISUP_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1678 #define SDIO_CFG1_ASYNCWKUPEN (0x1UL << 18) /**< Asynchronous Wakeup Enable */ 1679 #define _SDIO_CFG1_ASYNCWKUPEN_SHIFT 18 /**< Shift value for SDIO_ASYNCWKUPEN */ 1680 #define _SDIO_CFG1_ASYNCWKUPEN_MASK 0x40000UL /**< Bit mask for SDIO_ASYNCWKUPEN */ 1681 #define _SDIO_CFG1_ASYNCWKUPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ 1682 #define SDIO_CFG1_ASYNCWKUPEN_DEFAULT (_SDIO_CFG1_ASYNCWKUPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_CFG1 */ 1683 1684 /* Bit fields for SDIO CFGPRESETVAL0 */ 1685 #define _SDIO_CFGPRESETVAL0_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFGPRESETVAL0 */ 1686 #define _SDIO_CFGPRESETVAL0_MASK 0x1FFF1FFFUL /**< Mask for SDIO_CFGPRESETVAL0 */ 1687 #define _SDIO_CFGPRESETVAL0_INITSDCLKFREQ_SHIFT 0 /**< Shift value for SDIO_INITSDCLKFREQ */ 1688 #define _SDIO_CFGPRESETVAL0_INITSDCLKFREQ_MASK 0x3FFUL /**< Bit mask for SDIO_INITSDCLKFREQ */ 1689 #define _SDIO_CFGPRESETVAL0_INITSDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */ 1690 #define SDIO_CFGPRESETVAL0_INITSDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL0_INITSDCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */ 1691 #define SDIO_CFGPRESETVAL0_INITCLKGENEN (0x1UL << 10) /**< Initial Clock Gen Enable */ 1692 #define _SDIO_CFGPRESETVAL0_INITCLKGENEN_SHIFT 10 /**< Shift value for SDIO_INITCLKGENEN */ 1693 #define _SDIO_CFGPRESETVAL0_INITCLKGENEN_MASK 0x400UL /**< Bit mask for SDIO_INITCLKGENEN */ 1694 #define _SDIO_CFGPRESETVAL0_INITCLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */ 1695 #define SDIO_CFGPRESETVAL0_INITCLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL0_INITCLKGENEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */ 1696 #define _SDIO_CFGPRESETVAL0_INITDRVST_SHIFT 11 /**< Shift value for SDIO_INITDRVST */ 1697 #define _SDIO_CFGPRESETVAL0_INITDRVST_MASK 0x1800UL /**< Bit mask for SDIO_INITDRVST */ 1698 #define _SDIO_CFGPRESETVAL0_INITDRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */ 1699 #define SDIO_CFGPRESETVAL0_INITDRVST_DEFAULT (_SDIO_CFGPRESETVAL0_INITDRVST_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */ 1700 #define _SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_SHIFT 16 /**< Shift value for SDIO_DSPSDCLKFREQ */ 1701 #define _SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_MASK 0x3FF0000UL /**< Bit mask for SDIO_DSPSDCLKFREQ */ 1702 #define _SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */ 1703 #define SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */ 1704 #define SDIO_CFGPRESETVAL0_DSPCLKGENEN (0x1UL << 26) /**< Default Speed Clock Gen Enable */ 1705 #define _SDIO_CFGPRESETVAL0_DSPCLKGENEN_SHIFT 26 /**< Shift value for SDIO_DSPCLKGENEN */ 1706 #define _SDIO_CFGPRESETVAL0_DSPCLKGENEN_MASK 0x4000000UL /**< Bit mask for SDIO_DSPCLKGENEN */ 1707 #define _SDIO_CFGPRESETVAL0_DSPCLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */ 1708 #define SDIO_CFGPRESETVAL0_DSPCLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL0_DSPCLKGENEN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */ 1709 #define _SDIO_CFGPRESETVAL0_DSPDRVST_SHIFT 27 /**< Shift value for SDIO_DSPDRVST */ 1710 #define _SDIO_CFGPRESETVAL0_DSPDRVST_MASK 0x18000000UL /**< Bit mask for SDIO_DSPDRVST */ 1711 #define _SDIO_CFGPRESETVAL0_DSPDRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */ 1712 #define SDIO_CFGPRESETVAL0_DSPDRVST_DEFAULT (_SDIO_CFGPRESETVAL0_DSPDRVST_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */ 1713 1714 /* Bit fields for SDIO CFGPRESETVAL1 */ 1715 #define _SDIO_CFGPRESETVAL1_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFGPRESETVAL1 */ 1716 #define _SDIO_CFGPRESETVAL1_MASK 0x1FFF1FFFUL /**< Mask for SDIO_CFGPRESETVAL1 */ 1717 #define _SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_SHIFT 0 /**< Shift value for SDIO_HSPSDCLKFREQ */ 1718 #define _SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_MASK 0x3FFUL /**< Bit mask for SDIO_HSPSDCLKFREQ */ 1719 #define _SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */ 1720 #define SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */ 1721 #define SDIO_CFGPRESETVAL1_HSPCLKGENEN (0x1UL << 10) /**< High Speed SD_CLK Gen Enable */ 1722 #define _SDIO_CFGPRESETVAL1_HSPCLKGENEN_SHIFT 10 /**< Shift value for SDIO_HSPCLKGENEN */ 1723 #define _SDIO_CFGPRESETVAL1_HSPCLKGENEN_MASK 0x400UL /**< Bit mask for SDIO_HSPCLKGENEN */ 1724 #define _SDIO_CFGPRESETVAL1_HSPCLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */ 1725 #define SDIO_CFGPRESETVAL1_HSPCLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL1_HSPCLKGENEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */ 1726 #define _SDIO_CFGPRESETVAL1_HSPDRVST_SHIFT 11 /**< Shift value for SDIO_HSPDRVST */ 1727 #define _SDIO_CFGPRESETVAL1_HSPDRVST_MASK 0x1800UL /**< Bit mask for SDIO_HSPDRVST */ 1728 #define _SDIO_CFGPRESETVAL1_HSPDRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */ 1729 #define SDIO_CFGPRESETVAL1_HSPDRVST_DEFAULT (_SDIO_CFGPRESETVAL1_HSPDRVST_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */ 1730 #define _SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_SHIFT 16 /**< Shift value for SDIO_SDR12SDCLKFREQ */ 1731 #define _SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_MASK 0x3FF0000UL /**< Bit mask for SDIO_SDR12SDCLKFREQ */ 1732 #define _SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */ 1733 #define SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */ 1734 #define SDIO_CFGPRESETVAL1_SDR12CLKGENEN (0x1UL << 26) /**< SDR12 Speed Clock Gen Enable */ 1735 #define _SDIO_CFGPRESETVAL1_SDR12CLKGENEN_SHIFT 26 /**< Shift value for SDIO_SDR12CLKGENEN */ 1736 #define _SDIO_CFGPRESETVAL1_SDR12CLKGENEN_MASK 0x4000000UL /**< Bit mask for SDIO_SDR12CLKGENEN */ 1737 #define _SDIO_CFGPRESETVAL1_SDR12CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */ 1738 #define SDIO_CFGPRESETVAL1_SDR12CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL1_SDR12CLKGENEN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */ 1739 #define _SDIO_CFGPRESETVAL1_SDR12DRVST_SHIFT 27 /**< Shift value for SDIO_SDR12DRVST */ 1740 #define _SDIO_CFGPRESETVAL1_SDR12DRVST_MASK 0x18000000UL /**< Bit mask for SDIO_SDR12DRVST */ 1741 #define _SDIO_CFGPRESETVAL1_SDR12DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */ 1742 #define SDIO_CFGPRESETVAL1_SDR12DRVST_DEFAULT (_SDIO_CFGPRESETVAL1_SDR12DRVST_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */ 1743 1744 /* Bit fields for SDIO CFGPRESETVAL2 */ 1745 #define _SDIO_CFGPRESETVAL2_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFGPRESETVAL2 */ 1746 #define _SDIO_CFGPRESETVAL2_MASK 0x1FFF1FFFUL /**< Mask for SDIO_CFGPRESETVAL2 */ 1747 #define _SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_SHIFT 0 /**< Shift value for SDIO_SDR25SDCLKFREQ */ 1748 #define _SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_MASK 0x3FFUL /**< Bit mask for SDIO_SDR25SDCLKFREQ */ 1749 #define _SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */ 1750 #define SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */ 1751 #define SDIO_CFGPRESETVAL2_SDR25CLKGENEN (0x1UL << 10) /**< SDR25 SD_CLK Gen Enable */ 1752 #define _SDIO_CFGPRESETVAL2_SDR25CLKGENEN_SHIFT 10 /**< Shift value for SDIO_SDR25CLKGENEN */ 1753 #define _SDIO_CFGPRESETVAL2_SDR25CLKGENEN_MASK 0x400UL /**< Bit mask for SDIO_SDR25CLKGENEN */ 1754 #define _SDIO_CFGPRESETVAL2_SDR25CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */ 1755 #define SDIO_CFGPRESETVAL2_SDR25CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL2_SDR25CLKGENEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */ 1756 #define _SDIO_CFGPRESETVAL2_SDR25DRVST_SHIFT 11 /**< Shift value for SDIO_SDR25DRVST */ 1757 #define _SDIO_CFGPRESETVAL2_SDR25DRVST_MASK 0x1800UL /**< Bit mask for SDIO_SDR25DRVST */ 1758 #define _SDIO_CFGPRESETVAL2_SDR25DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */ 1759 #define SDIO_CFGPRESETVAL2_SDR25DRVST_DEFAULT (_SDIO_CFGPRESETVAL2_SDR25DRVST_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */ 1760 #define _SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_SHIFT 16 /**< Shift value for SDIO_SDR50SDCLKFREQ */ 1761 #define _SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_MASK 0x3FF0000UL /**< Bit mask for SDIO_SDR50SDCLKFREQ */ 1762 #define _SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */ 1763 #define SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */ 1764 #define SDIO_CFGPRESETVAL2_SDR50CLKGENEN (0x1UL << 26) /**< SDR50 Speed Clock Gen Enable */ 1765 #define _SDIO_CFGPRESETVAL2_SDR50CLKGENEN_SHIFT 26 /**< Shift value for SDIO_SDR50CLKGENEN */ 1766 #define _SDIO_CFGPRESETVAL2_SDR50CLKGENEN_MASK 0x4000000UL /**< Bit mask for SDIO_SDR50CLKGENEN */ 1767 #define _SDIO_CFGPRESETVAL2_SDR50CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */ 1768 #define SDIO_CFGPRESETVAL2_SDR50CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL2_SDR50CLKGENEN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */ 1769 #define _SDIO_CFGPRESETVAL2_SDR50DRVST_SHIFT 27 /**< Shift value for SDIO_SDR50DRVST */ 1770 #define _SDIO_CFGPRESETVAL2_SDR50DRVST_MASK 0x18000000UL /**< Bit mask for SDIO_SDR50DRVST */ 1771 #define _SDIO_CFGPRESETVAL2_SDR50DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */ 1772 #define SDIO_CFGPRESETVAL2_SDR50DRVST_DEFAULT (_SDIO_CFGPRESETVAL2_SDR50DRVST_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */ 1773 1774 /* Bit fields for SDIO CFGPRESETVAL3 */ 1775 #define _SDIO_CFGPRESETVAL3_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFGPRESETVAL3 */ 1776 #define _SDIO_CFGPRESETVAL3_MASK 0x1FFF1FFFUL /**< Mask for SDIO_CFGPRESETVAL3 */ 1777 #define _SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_SHIFT 0 /**< Shift value for SDIO_SDR104SDCLKFREQ */ 1778 #define _SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_MASK 0x3FFUL /**< Bit mask for SDIO_SDR104SDCLKFREQ */ 1779 #define _SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */ 1780 #define SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */ 1781 #define SDIO_CFGPRESETVAL3_SDR104CLKGENEN (0x1UL << 10) /**< SDR104 SD_CLK Gen Enable */ 1782 #define _SDIO_CFGPRESETVAL3_SDR104CLKGENEN_SHIFT 10 /**< Shift value for SDIO_SDR104CLKGENEN */ 1783 #define _SDIO_CFGPRESETVAL3_SDR104CLKGENEN_MASK 0x400UL /**< Bit mask for SDIO_SDR104CLKGENEN */ 1784 #define _SDIO_CFGPRESETVAL3_SDR104CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */ 1785 #define SDIO_CFGPRESETVAL3_SDR104CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL3_SDR104CLKGENEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */ 1786 #define _SDIO_CFGPRESETVAL3_SDR104DRVST_SHIFT 11 /**< Shift value for SDIO_SDR104DRVST */ 1787 #define _SDIO_CFGPRESETVAL3_SDR104DRVST_MASK 0x1800UL /**< Bit mask for SDIO_SDR104DRVST */ 1788 #define _SDIO_CFGPRESETVAL3_SDR104DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */ 1789 #define SDIO_CFGPRESETVAL3_SDR104DRVST_DEFAULT (_SDIO_CFGPRESETVAL3_SDR104DRVST_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */ 1790 #define _SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_SHIFT 16 /**< Shift value for SDIO_DDR50SDCLKFREQ */ 1791 #define _SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_MASK 0x3FF0000UL /**< Bit mask for SDIO_DDR50SDCLKFREQ */ 1792 #define _SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */ 1793 #define SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */ 1794 #define SDIO_CFGPRESETVAL3_DDR50CLKGENEN (0x1UL << 26) /**< DDR50 Speed Clock Gen Enable */ 1795 #define _SDIO_CFGPRESETVAL3_DDR50CLKGENEN_SHIFT 26 /**< Shift value for SDIO_DDR50CLKGENEN */ 1796 #define _SDIO_CFGPRESETVAL3_DDR50CLKGENEN_MASK 0x4000000UL /**< Bit mask for SDIO_DDR50CLKGENEN */ 1797 #define _SDIO_CFGPRESETVAL3_DDR50CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */ 1798 #define SDIO_CFGPRESETVAL3_DDR50CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL3_DDR50CLKGENEN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */ 1799 #define _SDIO_CFGPRESETVAL3_DDR50DRVST_SHIFT 27 /**< Shift value for SDIO_DDR50DRVST */ 1800 #define _SDIO_CFGPRESETVAL3_DDR50DRVST_MASK 0x18000000UL /**< Bit mask for SDIO_DDR50DRVST */ 1801 #define _SDIO_CFGPRESETVAL3_DDR50DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */ 1802 #define SDIO_CFGPRESETVAL3_DDR50DRVST_DEFAULT (_SDIO_CFGPRESETVAL3_DDR50DRVST_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */ 1803 1804 /* Bit fields for SDIO ROUTELOC0 */ 1805 #define _SDIO_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for SDIO_ROUTELOC0 */ 1806 #define _SDIO_ROUTELOC0_MASK 0x01030301UL /**< Mask for SDIO_ROUTELOC0 */ 1807 #define _SDIO_ROUTELOC0_DATLOC_SHIFT 0 /**< Shift value for SDIO_DATLOC */ 1808 #define _SDIO_ROUTELOC0_DATLOC_MASK 0x1UL /**< Bit mask for SDIO_DATLOC */ 1809 #define _SDIO_ROUTELOC0_DATLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC0 */ 1810 #define _SDIO_ROUTELOC0_DATLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC0 */ 1811 #define _SDIO_ROUTELOC0_DATLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC0 */ 1812 #define SDIO_ROUTELOC0_DATLOC_LOC0 (_SDIO_ROUTELOC0_DATLOC_LOC0 << 0) /**< Shifted mode LOC0 for SDIO_ROUTELOC0 */ 1813 #define SDIO_ROUTELOC0_DATLOC_DEFAULT (_SDIO_ROUTELOC0_DATLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ROUTELOC0 */ 1814 #define SDIO_ROUTELOC0_DATLOC_LOC1 (_SDIO_ROUTELOC0_DATLOC_LOC1 << 0) /**< Shifted mode LOC1 for SDIO_ROUTELOC0 */ 1815 #define _SDIO_ROUTELOC0_CDLOC_SHIFT 8 /**< Shift value for SDIO_CDLOC */ 1816 #define _SDIO_ROUTELOC0_CDLOC_MASK 0x300UL /**< Bit mask for SDIO_CDLOC */ 1817 #define _SDIO_ROUTELOC0_CDLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC0 */ 1818 #define _SDIO_ROUTELOC0_CDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC0 */ 1819 #define _SDIO_ROUTELOC0_CDLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC0 */ 1820 #define _SDIO_ROUTELOC0_CDLOC_LOC2 0x00000002UL /**< Mode LOC2 for SDIO_ROUTELOC0 */ 1821 #define _SDIO_ROUTELOC0_CDLOC_LOC3 0x00000003UL /**< Mode LOC3 for SDIO_ROUTELOC0 */ 1822 #define SDIO_ROUTELOC0_CDLOC_LOC0 (_SDIO_ROUTELOC0_CDLOC_LOC0 << 8) /**< Shifted mode LOC0 for SDIO_ROUTELOC0 */ 1823 #define SDIO_ROUTELOC0_CDLOC_DEFAULT (_SDIO_ROUTELOC0_CDLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_ROUTELOC0 */ 1824 #define SDIO_ROUTELOC0_CDLOC_LOC1 (_SDIO_ROUTELOC0_CDLOC_LOC1 << 8) /**< Shifted mode LOC1 for SDIO_ROUTELOC0 */ 1825 #define SDIO_ROUTELOC0_CDLOC_LOC2 (_SDIO_ROUTELOC0_CDLOC_LOC2 << 8) /**< Shifted mode LOC2 for SDIO_ROUTELOC0 */ 1826 #define SDIO_ROUTELOC0_CDLOC_LOC3 (_SDIO_ROUTELOC0_CDLOC_LOC3 << 8) /**< Shifted mode LOC3 for SDIO_ROUTELOC0 */ 1827 #define _SDIO_ROUTELOC0_WPLOC_SHIFT 16 /**< Shift value for SDIO_WPLOC */ 1828 #define _SDIO_ROUTELOC0_WPLOC_MASK 0x30000UL /**< Bit mask for SDIO_WPLOC */ 1829 #define _SDIO_ROUTELOC0_WPLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC0 */ 1830 #define _SDIO_ROUTELOC0_WPLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC0 */ 1831 #define _SDIO_ROUTELOC0_WPLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC0 */ 1832 #define _SDIO_ROUTELOC0_WPLOC_LOC2 0x00000002UL /**< Mode LOC2 for SDIO_ROUTELOC0 */ 1833 #define _SDIO_ROUTELOC0_WPLOC_LOC3 0x00000003UL /**< Mode LOC3 for SDIO_ROUTELOC0 */ 1834 #define SDIO_ROUTELOC0_WPLOC_LOC0 (_SDIO_ROUTELOC0_WPLOC_LOC0 << 16) /**< Shifted mode LOC0 for SDIO_ROUTELOC0 */ 1835 #define SDIO_ROUTELOC0_WPLOC_DEFAULT (_SDIO_ROUTELOC0_WPLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_ROUTELOC0 */ 1836 #define SDIO_ROUTELOC0_WPLOC_LOC1 (_SDIO_ROUTELOC0_WPLOC_LOC1 << 16) /**< Shifted mode LOC1 for SDIO_ROUTELOC0 */ 1837 #define SDIO_ROUTELOC0_WPLOC_LOC2 (_SDIO_ROUTELOC0_WPLOC_LOC2 << 16) /**< Shifted mode LOC2 for SDIO_ROUTELOC0 */ 1838 #define SDIO_ROUTELOC0_WPLOC_LOC3 (_SDIO_ROUTELOC0_WPLOC_LOC3 << 16) /**< Shifted mode LOC3 for SDIO_ROUTELOC0 */ 1839 #define _SDIO_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for SDIO_CLKLOC */ 1840 #define _SDIO_ROUTELOC0_CLKLOC_MASK 0x1000000UL /**< Bit mask for SDIO_CLKLOC */ 1841 #define _SDIO_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC0 */ 1842 #define _SDIO_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC0 */ 1843 #define _SDIO_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC0 */ 1844 #define SDIO_ROUTELOC0_CLKLOC_LOC0 (_SDIO_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for SDIO_ROUTELOC0 */ 1845 #define SDIO_ROUTELOC0_CLKLOC_DEFAULT (_SDIO_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_ROUTELOC0 */ 1846 #define SDIO_ROUTELOC0_CLKLOC_LOC1 (_SDIO_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for SDIO_ROUTELOC0 */ 1847 1848 /* Bit fields for SDIO ROUTELOC1 */ 1849 #define _SDIO_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for SDIO_ROUTELOC1 */ 1850 #define _SDIO_ROUTELOC1_MASK 0x00000001UL /**< Mask for SDIO_ROUTELOC1 */ 1851 #define _SDIO_ROUTELOC1_CMDLOC_SHIFT 0 /**< Shift value for SDIO_CMDLOC */ 1852 #define _SDIO_ROUTELOC1_CMDLOC_MASK 0x1UL /**< Bit mask for SDIO_CMDLOC */ 1853 #define _SDIO_ROUTELOC1_CMDLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC1 */ 1854 #define _SDIO_ROUTELOC1_CMDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC1 */ 1855 #define _SDIO_ROUTELOC1_CMDLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC1 */ 1856 #define SDIO_ROUTELOC1_CMDLOC_LOC0 (_SDIO_ROUTELOC1_CMDLOC_LOC0 << 0) /**< Shifted mode LOC0 for SDIO_ROUTELOC1 */ 1857 #define SDIO_ROUTELOC1_CMDLOC_DEFAULT (_SDIO_ROUTELOC1_CMDLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ROUTELOC1 */ 1858 #define SDIO_ROUTELOC1_CMDLOC_LOC1 (_SDIO_ROUTELOC1_CMDLOC_LOC1 << 0) /**< Shifted mode LOC1 for SDIO_ROUTELOC1 */ 1859 1860 /* Bit fields for SDIO ROUTEPEN */ 1861 #define _SDIO_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for SDIO_ROUTEPEN */ 1862 #define _SDIO_ROUTEPEN_MASK 0x000003FFUL /**< Mask for SDIO_ROUTEPEN */ 1863 #define SDIO_ROUTEPEN_CLKPEN (0x1UL << 0) /**< CLK I/O Enable */ 1864 #define _SDIO_ROUTEPEN_CLKPEN_SHIFT 0 /**< Shift value for SDIO_CLKPEN */ 1865 #define _SDIO_ROUTEPEN_CLKPEN_MASK 0x1UL /**< Bit mask for SDIO_CLKPEN */ 1866 #define _SDIO_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ 1867 #define SDIO_ROUTEPEN_CLKPEN_DEFAULT (_SDIO_ROUTEPEN_CLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ 1868 #define SDIO_ROUTEPEN_CMDPEN (0x1UL << 1) /**< CMD I/O Enable */ 1869 #define _SDIO_ROUTEPEN_CMDPEN_SHIFT 1 /**< Shift value for SDIO_CMDPEN */ 1870 #define _SDIO_ROUTEPEN_CMDPEN_MASK 0x2UL /**< Bit mask for SDIO_CMDPEN */ 1871 #define _SDIO_ROUTEPEN_CMDPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ 1872 #define SDIO_ROUTEPEN_CMDPEN_DEFAULT (_SDIO_ROUTEPEN_CMDPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ 1873 #define SDIO_ROUTEPEN_D0PEN (0x1UL << 2) /**< Dat0 I/O Enable */ 1874 #define _SDIO_ROUTEPEN_D0PEN_SHIFT 2 /**< Shift value for SDIO_D0PEN */ 1875 #define _SDIO_ROUTEPEN_D0PEN_MASK 0x4UL /**< Bit mask for SDIO_D0PEN */ 1876 #define _SDIO_ROUTEPEN_D0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ 1877 #define SDIO_ROUTEPEN_D0PEN_DEFAULT (_SDIO_ROUTEPEN_D0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ 1878 #define SDIO_ROUTEPEN_D1PEN (0x1UL << 3) /**< Dat1 I/O Enable */ 1879 #define _SDIO_ROUTEPEN_D1PEN_SHIFT 3 /**< Shift value for SDIO_D1PEN */ 1880 #define _SDIO_ROUTEPEN_D1PEN_MASK 0x8UL /**< Bit mask for SDIO_D1PEN */ 1881 #define _SDIO_ROUTEPEN_D1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ 1882 #define SDIO_ROUTEPEN_D1PEN_DEFAULT (_SDIO_ROUTEPEN_D1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ 1883 #define SDIO_ROUTEPEN_D2PEN (0x1UL << 4) /**< Dat2 I/O Enable */ 1884 #define _SDIO_ROUTEPEN_D2PEN_SHIFT 4 /**< Shift value for SDIO_D2PEN */ 1885 #define _SDIO_ROUTEPEN_D2PEN_MASK 0x10UL /**< Bit mask for SDIO_D2PEN */ 1886 #define _SDIO_ROUTEPEN_D2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ 1887 #define SDIO_ROUTEPEN_D2PEN_DEFAULT (_SDIO_ROUTEPEN_D2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ 1888 #define SDIO_ROUTEPEN_D3PEN (0x1UL << 5) /**< Dat3 I/O Enable */ 1889 #define _SDIO_ROUTEPEN_D3PEN_SHIFT 5 /**< Shift value for SDIO_D3PEN */ 1890 #define _SDIO_ROUTEPEN_D3PEN_MASK 0x20UL /**< Bit mask for SDIO_D3PEN */ 1891 #define _SDIO_ROUTEPEN_D3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ 1892 #define SDIO_ROUTEPEN_D3PEN_DEFAULT (_SDIO_ROUTEPEN_D3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ 1893 #define SDIO_ROUTEPEN_D4PEN (0x1UL << 6) /**< Dat4 I/O Enable */ 1894 #define _SDIO_ROUTEPEN_D4PEN_SHIFT 6 /**< Shift value for SDIO_D4PEN */ 1895 #define _SDIO_ROUTEPEN_D4PEN_MASK 0x40UL /**< Bit mask for SDIO_D4PEN */ 1896 #define _SDIO_ROUTEPEN_D4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ 1897 #define SDIO_ROUTEPEN_D4PEN_DEFAULT (_SDIO_ROUTEPEN_D4PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ 1898 #define SDIO_ROUTEPEN_D5PEN (0x1UL << 7) /**< Dat5 Enable */ 1899 #define _SDIO_ROUTEPEN_D5PEN_SHIFT 7 /**< Shift value for SDIO_D5PEN */ 1900 #define _SDIO_ROUTEPEN_D5PEN_MASK 0x80UL /**< Bit mask for SDIO_D5PEN */ 1901 #define _SDIO_ROUTEPEN_D5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ 1902 #define SDIO_ROUTEPEN_D5PEN_DEFAULT (_SDIO_ROUTEPEN_D5PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ 1903 #define SDIO_ROUTEPEN_D6PEN (0x1UL << 8) /**< Dat6 Enable */ 1904 #define _SDIO_ROUTEPEN_D6PEN_SHIFT 8 /**< Shift value for SDIO_D6PEN */ 1905 #define _SDIO_ROUTEPEN_D6PEN_MASK 0x100UL /**< Bit mask for SDIO_D6PEN */ 1906 #define _SDIO_ROUTEPEN_D6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ 1907 #define SDIO_ROUTEPEN_D6PEN_DEFAULT (_SDIO_ROUTEPEN_D6PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ 1908 #define SDIO_ROUTEPEN_D7PEN (0x1UL << 9) /**< Data7 I/O Enable */ 1909 #define _SDIO_ROUTEPEN_D7PEN_SHIFT 9 /**< Shift value for SDIO_D7PEN */ 1910 #define _SDIO_ROUTEPEN_D7PEN_MASK 0x200UL /**< Bit mask for SDIO_D7PEN */ 1911 #define _SDIO_ROUTEPEN_D7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ 1912 #define SDIO_ROUTEPEN_D7PEN_DEFAULT (_SDIO_ROUTEPEN_D7PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ 1913 1914 /** @} */ 1915 /** @} End of group EFM32GG12B_SDIO */ 1916 /** @} End of group Parts */ 1917
