1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG12B_RTC register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG12B_RTC RTC 43 * @{ 44 * @brief EFM32GG12B_RTC Register Declaration 45 ******************************************************************************/ 46 /** RTC Register Declaration */ 47 typedef struct { 48 __IOM uint32_t CTRL; /**< Control Register */ 49 __IOM uint32_t CNT; /**< Counter Value Register */ 50 __IM uint32_t IF; /**< Interrupt Flag Register */ 51 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 52 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 53 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 54 55 uint32_t RESERVED0[2U]; /**< Reserved registers */ 56 RTC_COMP_TypeDef COMP[6U]; /**< Compare channels */ 57 } RTC_TypeDef; /** @} */ 58 59 /***************************************************************************//** 60 * @addtogroup EFM32GG12B_RTC 61 * @{ 62 * @defgroup EFM32GG12B_RTC_BitFields RTC Bit Fields 63 * @{ 64 ******************************************************************************/ 65 66 /* Bit fields for RTC CTRL */ 67 #define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */ 68 #define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */ 69 #define RTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */ 70 #define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */ 71 #define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */ 72 #define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ 73 #define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CTRL */ 74 #define RTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ 75 #define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */ 76 #define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */ 77 #define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ 78 #define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */ 79 #define RTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */ 80 #define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */ 81 #define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */ 82 #define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ 83 #define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */ 84 #define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */ 85 #define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */ 86 #define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */ 87 #define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for RTC_CTRL */ 88 89 /* Bit fields for RTC CNT */ 90 #define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */ 91 #define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */ 92 #define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */ 93 #define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */ 94 #define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */ 95 #define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */ 96 97 /* Bit fields for RTC IF */ 98 #define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */ 99 #define _RTC_IF_MASK 0x0000007FUL /**< Mask for RTC_IF */ 100 #define RTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ 101 #define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */ 102 #define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 103 #define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ 104 #define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IF */ 105 #define _RTC_IF_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ 106 #define _RTC_IF_COMP_MASK 0x7EUL /**< Bit mask for RTC_COMP */ 107 #define _RTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ 108 #define RTC_IF_COMP_DEFAULT (_RTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */ 109 110 /* Bit fields for RTC IFS */ 111 #define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */ 112 #define _RTC_IFS_MASK 0x0000007FUL /**< Mask for RTC_IFS */ 113 #define RTC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ 114 #define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */ 115 #define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 116 #define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ 117 #define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFS */ 118 #define _RTC_IFS_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ 119 #define _RTC_IFS_COMP_MASK 0x7EUL /**< Bit mask for RTC_COMP */ 120 #define _RTC_IFS_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ 121 #define RTC_IFS_COMP_DEFAULT (_RTC_IFS_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */ 122 123 /* Bit fields for RTC IFC */ 124 #define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */ 125 #define _RTC_IFC_MASK 0x0000007FUL /**< Mask for RTC_IFC */ 126 #define RTC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ 127 #define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */ 128 #define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 129 #define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ 130 #define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFC */ 131 #define _RTC_IFC_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ 132 #define _RTC_IFC_COMP_MASK 0x7EUL /**< Bit mask for RTC_COMP */ 133 #define _RTC_IFC_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ 134 #define RTC_IFC_COMP_DEFAULT (_RTC_IFC_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */ 135 136 /* Bit fields for RTC IEN */ 137 #define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */ 138 #define _RTC_IEN_MASK 0x0000007FUL /**< Mask for RTC_IEN */ 139 #define RTC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ 140 #define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */ 141 #define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 142 #define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ 143 #define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IEN */ 144 #define _RTC_IEN_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ 145 #define _RTC_IEN_COMP_MASK 0x7EUL /**< Bit mask for RTC_COMP */ 146 #define _RTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ 147 #define RTC_IEN_COMP_DEFAULT (_RTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */ 148 149 /* Bit fields for RTC COMP_COMP */ 150 #define _RTC_COMP_COMP_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP_COMP */ 151 #define _RTC_COMP_COMP_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP_COMP */ 152 #define _RTC_COMP_COMP_COMP_SHIFT 0 /**< Shift value for RTC_COMP */ 153 #define _RTC_COMP_COMP_COMP_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP */ 154 #define _RTC_COMP_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP_COMP */ 155 #define RTC_COMP_COMP_COMP_DEFAULT (_RTC_COMP_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP_COMP */ 156 157 /** @} */ 158 /** @} End of group EFM32GG12B_RTC */ 159 /** @} End of group Parts */ 160
