1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG12B_PRS register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG12B_PRS PRS 43 * @{ 44 * @brief EFM32GG12B_PRS Register Declaration 45 ******************************************************************************/ 46 /** PRS Register Declaration */ 47 typedef struct { 48 __IOM uint32_t SWPULSE; /**< Software Pulse Register */ 49 __IOM uint32_t SWLEVEL; /**< Software Level Register */ 50 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ 51 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 52 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ 53 __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ 54 __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ 55 __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ 56 57 uint32_t RESERVED1[4U]; /**< Reserved for future use **/ 58 __IOM uint32_t CTRL; /**< Control Register */ 59 __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ 60 __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ 61 uint32_t RESERVED2[1U]; /**< Reserved for future use **/ 62 __IM uint32_t PEEK; /**< PRS Channel Values */ 63 64 uint32_t RESERVED3[3U]; /**< Reserved registers */ 65 PRS_CH_TypeDef CH[16U]; /**< Channel registers */ 66 } PRS_TypeDef; /** @} */ 67 68 /***************************************************************************//** 69 * @addtogroup EFM32GG12B_PRS 70 * @{ 71 * @defgroup EFM32GG12B_PRS_BitFields PRS Bit Fields 72 * @{ 73 ******************************************************************************/ 74 75 /* Bit fields for PRS SWPULSE */ 76 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ 77 #define _PRS_SWPULSE_MASK 0x0000FFFFUL /**< Mask for PRS_SWPULSE */ 78 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ 79 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ 80 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ 81 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 82 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 83 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ 84 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ 85 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ 86 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 87 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 88 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ 89 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ 90 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ 91 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 92 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 93 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ 94 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ 95 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ 96 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 97 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 98 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ 99 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ 100 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ 101 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 102 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 103 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ 104 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ 105 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ 106 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 107 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 108 #define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ 109 #define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ 110 #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ 111 #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 112 #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 113 #define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ 114 #define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ 115 #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ 116 #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 117 #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 118 #define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ 119 #define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ 120 #define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ 121 #define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 122 #define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 123 #define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ 124 #define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ 125 #define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ 126 #define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 127 #define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 128 #define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ 129 #define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ 130 #define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ 131 #define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 132 #define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 133 #define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ 134 #define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ 135 #define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ 136 #define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 137 #define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 138 #define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ 139 #define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ 140 #define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ 141 #define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 142 #define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 143 #define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ 144 #define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ 145 #define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ 146 #define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 147 #define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 148 #define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ 149 #define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ 150 #define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ 151 #define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 152 #define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 153 #define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ 154 #define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ 155 #define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ 156 #define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 157 #define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 158 159 /* Bit fields for PRS SWLEVEL */ 160 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ 161 #define _PRS_SWLEVEL_MASK 0x0000FFFFUL /**< Mask for PRS_SWLEVEL */ 162 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ 163 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ 164 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ 165 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 166 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 167 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ 168 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ 169 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ 170 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 171 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 172 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ 173 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ 174 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ 175 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 176 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 177 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ 178 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ 179 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ 180 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 181 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 182 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ 183 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ 184 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ 185 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 186 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 187 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ 188 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ 189 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ 190 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 191 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 192 #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ 193 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ 194 #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ 195 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 196 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 197 #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ 198 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ 199 #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ 200 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 201 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 202 #define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ 203 #define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ 204 #define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ 205 #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 206 #define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 207 #define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ 208 #define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ 209 #define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ 210 #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 211 #define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 212 #define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ 213 #define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ 214 #define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ 215 #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 216 #define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 217 #define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ 218 #define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ 219 #define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ 220 #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 221 #define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 222 #define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ 223 #define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ 224 #define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ 225 #define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 226 #define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 227 #define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ 228 #define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ 229 #define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ 230 #define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 231 #define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 232 #define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ 233 #define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ 234 #define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ 235 #define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 236 #define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 237 #define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ 238 #define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ 239 #define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ 240 #define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 241 #define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 242 243 /* Bit fields for PRS ROUTEPEN */ 244 #define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ 245 #define _PRS_ROUTEPEN_MASK 0x0000FFFFUL /**< Mask for PRS_ROUTEPEN */ 246 #define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ 247 #define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ 248 #define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ 249 #define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 250 #define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 251 #define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ 252 #define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ 253 #define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ 254 #define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 255 #define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 256 #define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ 257 #define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ 258 #define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ 259 #define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 260 #define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 261 #define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ 262 #define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ 263 #define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ 264 #define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 265 #define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 266 #define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ 267 #define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ 268 #define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ 269 #define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 270 #define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 271 #define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ 272 #define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ 273 #define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ 274 #define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 275 #define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 276 #define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ 277 #define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ 278 #define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ 279 #define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 280 #define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 281 #define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ 282 #define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ 283 #define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ 284 #define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 285 #define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 286 #define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ 287 #define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ 288 #define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ 289 #define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 290 #define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 291 #define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ 292 #define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ 293 #define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ 294 #define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 295 #define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 296 #define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ 297 #define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ 298 #define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ 299 #define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 300 #define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 301 #define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ 302 #define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ 303 #define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ 304 #define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 305 #define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 306 #define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ 307 #define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ 308 #define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ 309 #define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 310 #define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 311 #define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ 312 #define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ 313 #define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ 314 #define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 315 #define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 316 #define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ 317 #define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ 318 #define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ 319 #define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 320 #define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 321 #define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ 322 #define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ 323 #define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ 324 #define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 325 #define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 326 327 /* Bit fields for PRS ROUTELOC0 */ 328 #define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ 329 #define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ 330 #define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ 331 #define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ 332 #define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ 333 #define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ 334 #define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ 335 #define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ 336 #define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ 337 #define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ 338 #define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ 339 #define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ 340 #define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ 341 #define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ 342 #define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ 343 #define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ 344 #define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ 345 #define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ 346 #define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ 347 #define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ 348 #define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ 349 #define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ 350 #define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ 351 #define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ 352 #define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ 353 #define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ 354 #define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ 355 #define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ 356 #define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ 357 #define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ 358 #define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ 359 #define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ 360 #define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ 361 #define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ 362 #define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ 363 #define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ 364 #define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ 365 #define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ 366 #define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ 367 #define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ 368 #define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ 369 #define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ 370 #define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ 371 #define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ 372 #define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ 373 #define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ 374 #define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ 375 #define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ 376 #define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ 377 #define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ 378 379 /* Bit fields for PRS ROUTELOC1 */ 380 #define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ 381 #define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ 382 #define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ 383 #define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ 384 #define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ 385 #define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ 386 #define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ 387 #define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ 388 #define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ 389 #define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ 390 #define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ 391 #define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ 392 #define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ 393 #define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ 394 #define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ 395 #define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ 396 #define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ 397 #define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ 398 #define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ 399 #define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ 400 #define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ 401 #define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ 402 #define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ 403 #define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ 404 #define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ 405 #define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ 406 #define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ 407 #define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ 408 #define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ 409 #define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ 410 #define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ 411 #define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ 412 #define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ 413 #define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ 414 #define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ 415 #define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ 416 #define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ 417 #define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ 418 #define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ 419 #define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ 420 #define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ 421 #define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ 422 423 /* Bit fields for PRS ROUTELOC2 */ 424 #define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ 425 #define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ 426 #define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ 427 #define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ 428 #define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ 429 #define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ 430 #define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ 431 #define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ 432 #define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ 433 #define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ 434 #define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ 435 #define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ 436 #define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ 437 #define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ 438 #define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ 439 #define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ 440 #define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ 441 #define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ 442 #define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ 443 #define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ 444 #define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ 445 #define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ 446 #define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ 447 #define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ 448 #define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ 449 #define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ 450 #define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ 451 #define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ 452 #define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ 453 #define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ 454 #define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ 455 #define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ 456 #define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ 457 #define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ 458 #define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ 459 #define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ 460 #define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ 461 #define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ 462 #define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ 463 #define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ 464 #define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ 465 #define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ 466 467 /* Bit fields for PRS ROUTELOC3 */ 468 #define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ 469 #define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ 470 #define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ 471 #define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ 472 #define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ 473 #define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ 474 #define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ 475 #define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ 476 #define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ 477 #define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ 478 #define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ 479 #define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ 480 #define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ 481 #define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ 482 #define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ 483 #define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ 484 #define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ 485 #define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ 486 #define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ 487 #define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ 488 #define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ 489 #define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ 490 #define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ 491 #define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ 492 #define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ 493 #define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ 494 #define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ 495 #define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ 496 #define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ 497 #define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ 498 #define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ 499 #define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ 500 #define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ 501 #define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ 502 #define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ 503 #define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ 504 #define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ 505 #define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ 506 #define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ 507 #define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ 508 #define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ 509 #define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ 510 511 /* Bit fields for PRS CTRL */ 512 #define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ 513 #define _PRS_CTRL_MASK 0x0000001FUL /**< Mask for PRS_CTRL */ 514 #define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ 515 #define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ 516 #define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ 517 #define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ 518 #define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ 519 #define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ 520 #define _PRS_CTRL_SEVONPRSSEL_MASK 0x1EUL /**< Bit mask for PRS_SEVONPRSSEL */ 521 #define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ 522 #define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ 523 #define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ 524 #define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ 525 #define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ 526 #define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ 527 #define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ 528 #define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ 529 #define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ 530 #define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ 531 #define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ 532 #define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ 533 #define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ 534 #define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ 535 #define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ 536 #define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ 537 #define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ 538 #define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ 539 #define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ 540 #define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ 541 #define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ 542 #define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ 543 #define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ 544 #define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ 545 #define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ 546 #define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ 547 #define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ 548 #define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ 549 #define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ 550 #define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ 551 #define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ 552 #define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ 553 #define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ 554 #define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ 555 556 /* Bit fields for PRS DMAREQ0 */ 557 #define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ 558 #define _PRS_DMAREQ0_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ0 */ 559 #define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ 560 #define _PRS_DMAREQ0_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */ 561 #define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ 562 #define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ 563 #define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ 564 #define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ 565 #define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ 566 #define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ 567 #define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ 568 #define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ 569 #define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ 570 #define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ 571 #define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ 572 #define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ 573 #define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ 574 #define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ 575 #define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ 576 #define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ 577 #define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ 578 #define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ 579 #define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ 580 #define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ 581 #define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ 582 #define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ 583 #define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ 584 #define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ 585 #define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ 586 #define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ 587 #define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ 588 #define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ 589 #define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ 590 #define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ 591 #define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ 592 #define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ 593 #define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ 594 #define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ 595 596 /* Bit fields for PRS DMAREQ1 */ 597 #define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ 598 #define _PRS_DMAREQ1_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ1 */ 599 #define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ 600 #define _PRS_DMAREQ1_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */ 601 #define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ 602 #define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ 603 #define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ 604 #define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ 605 #define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ 606 #define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ 607 #define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ 608 #define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ 609 #define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ 610 #define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ 611 #define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ 612 #define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ 613 #define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ 614 #define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ 615 #define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ 616 #define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ 617 #define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ 618 #define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ 619 #define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ 620 #define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ 621 #define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ 622 #define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ 623 #define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ 624 #define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ 625 #define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ 626 #define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ 627 #define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ 628 #define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ 629 #define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ 630 #define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ 631 #define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ 632 #define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ 633 #define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ 634 #define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ 635 636 /* Bit fields for PRS PEEK */ 637 #define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ 638 #define _PRS_PEEK_MASK 0x0000FFFFUL /**< Mask for PRS_PEEK */ 639 #define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ 640 #define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ 641 #define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ 642 #define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 643 #define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ 644 #define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ 645 #define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ 646 #define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ 647 #define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 648 #define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ 649 #define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ 650 #define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ 651 #define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ 652 #define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 653 #define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ 654 #define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ 655 #define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ 656 #define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ 657 #define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 658 #define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ 659 #define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ 660 #define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ 661 #define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ 662 #define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 663 #define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ 664 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ 665 #define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ 666 #define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ 667 #define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 668 #define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ 669 #define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ 670 #define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ 671 #define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ 672 #define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 673 #define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ 674 #define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ 675 #define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ 676 #define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ 677 #define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 678 #define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ 679 #define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ 680 #define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ 681 #define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ 682 #define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 683 #define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ 684 #define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ 685 #define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ 686 #define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ 687 #define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 688 #define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ 689 #define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ 690 #define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ 691 #define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ 692 #define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 693 #define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ 694 #define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ 695 #define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ 696 #define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ 697 #define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 698 #define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ 699 #define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ 700 #define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ 701 #define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ 702 #define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 703 #define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ 704 #define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ 705 #define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ 706 #define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ 707 #define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 708 #define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ 709 #define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ 710 #define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ 711 #define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ 712 #define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 713 #define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ 714 #define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ 715 #define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ 716 #define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ 717 #define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 718 #define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ 719 720 /* Bit fields for PRS CH_CTRL */ 721 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ 722 #define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ 723 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ 724 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ 725 #define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ 726 #define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ 727 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ 728 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ 729 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ 730 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ 731 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ 732 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ 733 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ 734 #define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ 735 #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ 736 #define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ 737 #define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ 738 #define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ 739 #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ 740 #define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ 741 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ 742 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ 743 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ 744 #define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ 745 #define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ 746 #define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ 747 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ 748 #define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ 749 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ 750 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ 751 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ 752 #define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */ 753 #define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ 754 #define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ 755 #define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ 756 #define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ 757 #define _PRS_CH_CTRL_SIGSEL_PDMDSRPULSE 0x00000000UL /**< Mode PDMDSRPULSE for PRS_CH_CTRL */ 758 #define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ 759 #define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ 760 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ 761 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ 762 #define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ 763 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ 764 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ 765 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ 766 #define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ 767 #define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ 768 #define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ 769 #define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ 770 #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ 771 #define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ 772 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ 773 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ 774 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ 775 #define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ 776 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ 777 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ 778 #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ 779 #define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ 780 #define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ 781 #define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ 782 #define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ 783 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ 784 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ 785 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ 786 #define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */ 787 #define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ 788 #define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ 789 #define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ 790 #define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ 791 #define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ 792 #define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ 793 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ 794 #define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ 795 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ 796 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ 797 #define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ 798 #define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ 799 #define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ 800 #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ 801 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ 802 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ 803 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ 804 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ 805 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ 806 #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ 807 #define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ 808 #define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ 809 #define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ 810 #define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ 811 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ 812 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ 813 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ 814 #define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ 815 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ 816 #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ 817 #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ 818 #define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ 819 #define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ 820 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ 821 #define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ 822 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ 823 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ 824 #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ 825 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ 826 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ 827 #define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ 828 #define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ 829 #define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ 830 #define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ 831 #define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ 832 #define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ 833 #define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ 834 #define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ 835 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ 836 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ 837 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ 838 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ 839 #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ 840 #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ 841 #define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ 842 #define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ 843 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ 844 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ 845 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ 846 #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ 847 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ 848 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ 849 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ 850 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ 851 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ 852 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ 853 #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ 854 #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ 855 #define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ 856 #define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ 857 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ 858 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ 859 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ 860 #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ 861 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ 862 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ 863 #define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ 864 #define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ 865 #define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ 866 #define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ 867 #define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ 868 #define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ 869 #define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ 870 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ 871 #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ 872 #define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ 873 #define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ 874 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ 875 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ 876 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ 877 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ 878 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ 879 #define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ 880 #define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ 881 #define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ 882 #define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ 883 #define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ 884 #define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ 885 #define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ 886 #define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ 887 #define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ 888 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ 889 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ 890 #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ 891 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ 892 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ 893 #define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ 894 #define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ 895 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ 896 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ 897 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ 898 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ 899 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ 900 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ 901 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ 902 #define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ 903 #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ 904 #define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ 905 #define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ 906 #define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ 907 #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ 908 #define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ 909 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ 910 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ 911 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ 912 #define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ 913 #define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ 914 #define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ 915 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ 916 #define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ 917 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ 918 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ 919 #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ 920 #define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */ 921 #define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ 922 #define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ 923 #define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ 924 #define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ 925 #define PRS_CH_CTRL_SIGSEL_PDMDSRPULSE (_PRS_CH_CTRL_SIGSEL_PDMDSRPULSE << 0) /**< Shifted mode PDMDSRPULSE for PRS_CH_CTRL */ 926 #define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ 927 #define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ 928 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ 929 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ 930 #define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ 931 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ 932 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ 933 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ 934 #define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ 935 #define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ 936 #define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ 937 #define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ 938 #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ 939 #define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ 940 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ 941 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ 942 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ 943 #define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ 944 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ 945 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ 946 #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ 947 #define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ 948 #define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ 949 #define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ 950 #define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ 951 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ 952 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ 953 #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ 954 #define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */ 955 #define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ 956 #define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ 957 #define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ 958 #define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ 959 #define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ 960 #define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ 961 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ 962 #define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ 963 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ 964 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ 965 #define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ 966 #define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ 967 #define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ 968 #define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ 969 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ 970 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ 971 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ 972 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ 973 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ 974 #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ 975 #define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ 976 #define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ 977 #define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ 978 #define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ 979 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ 980 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ 981 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ 982 #define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ 983 #define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ 984 #define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ 985 #define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ 986 #define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ 987 #define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ 988 #define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ 989 #define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ 990 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ 991 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ 992 #define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ 993 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ 994 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ 995 #define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ 996 #define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ 997 #define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ 998 #define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ 999 #define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ 1000 #define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ 1001 #define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ 1002 #define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ 1003 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ 1004 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ 1005 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ 1006 #define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ 1007 #define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ 1008 #define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ 1009 #define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ 1010 #define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ 1011 #define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ 1012 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ 1013 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ 1014 #define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ 1015 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ 1016 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ 1017 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ 1018 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ 1019 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ 1020 #define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ 1021 #define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ 1022 #define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ 1023 #define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ 1024 #define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ 1025 #define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ 1026 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ 1027 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ 1028 #define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ 1029 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ 1030 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ 1031 #define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ 1032 #define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ 1033 #define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ 1034 #define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ 1035 #define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ 1036 #define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ 1037 #define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ 1038 #define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ 1039 #define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ 1040 #define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ 1041 #define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ 1042 #define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ 1043 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ 1044 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ 1045 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ 1046 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ 1047 #define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ 1048 #define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ 1049 #define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ 1050 #define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ 1051 #define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ 1052 #define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ 1053 #define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ 1054 #define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ 1055 #define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ 1056 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ 1057 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ 1058 #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ 1059 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ 1060 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ 1061 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ 1062 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ 1063 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ 1064 #define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ 1065 #define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ 1066 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ 1067 #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ 1068 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ 1069 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ 1070 #define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ 1071 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ 1072 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ 1073 #define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ 1074 #define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ 1075 #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ 1076 #define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ 1077 #define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ 1078 #define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ 1079 #define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ 1080 #define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ 1081 #define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ 1082 #define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ 1083 #define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ 1084 #define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ 1085 #define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ 1086 #define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001DUL /**< Mode ADC1 for PRS_CH_CTRL */ 1087 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ 1088 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ 1089 #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ 1090 #define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ 1091 #define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ 1092 #define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ 1093 #define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ 1094 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ 1095 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ 1096 #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ 1097 #define _PRS_CH_CTRL_SOURCESEL_USB 0x00000040UL /**< Mode USB for PRS_CH_CTRL */ 1098 #define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ 1099 #define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ 1100 #define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ 1101 #define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ 1102 #define _PRS_CH_CTRL_SOURCESEL_PDM 0x00000079UL /**< Mode PDM for PRS_CH_CTRL */ 1103 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ 1104 #define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ 1105 #define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ 1106 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ 1107 #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ 1108 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ 1109 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ 1110 #define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ 1111 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ 1112 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ 1113 #define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ 1114 #define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ 1115 #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ 1116 #define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ 1117 #define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ 1118 #define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ 1119 #define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ 1120 #define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ 1121 #define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ 1122 #define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ 1123 #define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ 1124 #define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ 1125 #define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ 1126 #define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ 1127 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ 1128 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ 1129 #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ 1130 #define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ 1131 #define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ 1132 #define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ 1133 #define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ 1134 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ 1135 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ 1136 #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ 1137 #define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 8) /**< Shifted mode USB for PRS_CH_CTRL */ 1138 #define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ 1139 #define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ 1140 #define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ 1141 #define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ 1142 #define PRS_CH_CTRL_SOURCESEL_PDM (_PRS_CH_CTRL_SOURCESEL_PDM << 8) /**< Shifted mode PDM for PRS_CH_CTRL */ 1143 #define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ 1144 #define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ 1145 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 1146 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ 1147 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ 1148 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ 1149 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ 1150 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 1151 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ 1152 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ 1153 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ 1154 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ 1155 #define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ 1156 #define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ 1157 #define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ 1158 #define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 1159 #define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 1160 #define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ 1161 #define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ 1162 #define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ 1163 #define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 1164 #define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 1165 #define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ 1166 #define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ 1167 #define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ 1168 #define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 1169 #define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 1170 #define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ 1171 #define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ 1172 #define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ 1173 #define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 1174 #define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 1175 #define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ 1176 #define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ 1177 #define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ 1178 #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 1179 #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 1180 1181 /** @} */ 1182 /** @} End of group EFM32GG12B_PRS */ 1183 /** @} End of group Parts */ 1184
