1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG12B_EMU register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG12B_EMU EMU 43 * @{ 44 * @brief EFM32GG12B_EMU Register Declaration 45 ******************************************************************************/ 46 /** EMU Register Declaration */ 47 typedef struct { 48 __IOM uint32_t CTRL; /**< Control Register */ 49 __IM uint32_t STATUS; /**< Status Register */ 50 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 51 __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ 52 __IOM uint32_t CMD; /**< Command Register */ 53 54 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 55 __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ 56 __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ 57 __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ 58 __IM uint32_t IF; /**< Interrupt Flag Register */ 59 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 60 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 61 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 62 __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ 63 64 uint32_t RESERVED1[1U]; /**< Reserved for future use **/ 65 __IOM uint32_t PWRCTRL; /**< Power Control Register */ 66 __IOM uint32_t DCDCCTRL; /**< DCDC Control */ 67 68 uint32_t RESERVED2[2U]; /**< Reserved for future use **/ 69 __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ 70 __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ 71 __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ 72 __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ 73 __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ 74 75 uint32_t RESERVED3[1U]; /**< Reserved for future use **/ 76 __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ 77 78 uint32_t RESERVED4[1U]; /**< Reserved for future use **/ 79 __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ 80 __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ 81 82 uint32_t RESERVED5[1U]; /**< Reserved for future use **/ 83 __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ 84 85 uint32_t RESERVED6[5U]; /**< Reserved for future use **/ 86 __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ 87 __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ 88 __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ 89 __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ 90 __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ 91 __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ 92 93 uint32_t RESERVED7[3U]; /**< Reserved for future use **/ 94 __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ 95 __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ 96 __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ 97 uint32_t RESERVED8[2U]; /**< Reserved for future use **/ 98 __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ 99 __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ 100 __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ 101 102 uint32_t RESERVED9[2U]; /**< Reserved for future use **/ 103 __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ 104 105 uint32_t RESERVED10[3U]; /**< Reserved for future use **/ 106 __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ 107 __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ 108 109 uint32_t RESERVED11[1U]; /**< Reserved for future use **/ 110 __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ 111 112 uint32_t RESERVED12[1U]; /**< Reserved for future use **/ 113 __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ 114 __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ 115 __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ 116 } EMU_TypeDef; /** @} */ 117 118 /***************************************************************************//** 119 * @addtogroup EFM32GG12B_EMU 120 * @{ 121 * @defgroup EFM32GG12B_EMU_BitFields EMU Bit Fields 122 * @{ 123 ******************************************************************************/ 124 125 /* Bit fields for EMU CTRL */ 126 #define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ 127 #define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ 128 #define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ 129 #define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ 130 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ 131 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 132 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ 133 #define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ 134 #define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ 135 #define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ 136 #define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 137 #define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ 138 #define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ 139 #define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ 140 #define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ 141 #define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 142 #define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ 143 #define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ 144 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ 145 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ 146 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 147 #define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ 148 #define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ 149 #define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ 150 #define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 151 #define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ 152 #define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ 153 #define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ 154 #define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ 155 #define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ 156 #define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ 157 #define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ 158 #define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ 159 #define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ 160 #define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 161 #define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ 162 #define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ 163 #define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ 164 #define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ 165 #define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ 166 #define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ 167 #define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ 168 169 /* Bit fields for EMU STATUS */ 170 #define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ 171 #define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ 172 #define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ 173 #define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ 174 #define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ 175 #define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 176 #define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ 177 #define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ 178 #define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ 179 #define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ 180 #define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 181 #define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ 182 #define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ 183 #define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ 184 #define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ 185 #define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 186 #define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ 187 #define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ 188 #define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ 189 #define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ 190 #define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 191 #define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ 192 #define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ 193 #define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ 194 #define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ 195 #define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 196 #define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ 197 #define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ 198 #define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ 199 #define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ 200 #define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 201 #define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ 202 #define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ 203 #define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ 204 #define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ 205 #define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 206 #define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ 207 #define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ 208 #define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ 209 #define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ 210 #define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 211 #define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ 212 #define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ 213 #define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ 214 #define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 215 #define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ 216 #define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ 217 #define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ 218 #define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ 219 #define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ 220 #define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ 221 #define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ 222 #define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ 223 #define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ 224 #define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ 225 #define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 226 #define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ 227 #define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ 228 #define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ 229 #define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ 230 #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 231 #define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ 232 #define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ 233 #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ 234 #define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ 235 #define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ 236 #define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ 237 #define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ 238 #define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ 239 #define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 240 #define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ 241 242 /* Bit fields for EMU LOCK */ 243 #define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ 244 #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ 245 #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ 246 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ 247 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ 248 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ 249 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ 250 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ 251 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ 252 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ 253 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ 254 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ 255 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ 256 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ 257 258 /* Bit fields for EMU RAM0CTRL */ 259 #define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ 260 #define _EMU_RAM0CTRL_MASK 0x00000007UL /**< Mask for EMU_RAM0CTRL */ 261 #define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ 262 #define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7UL /**< Bit mask for EMU_RAMPOWERDOWN */ 263 #define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ 264 #define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ 265 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3 0x00000004UL /**< Mode BLK3 for EMU_RAM0CTRL */ 266 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO3 0x00000006UL /**< Mode BLK2TO3 for EMU_RAM0CTRL */ 267 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO3 0x00000007UL /**< Mode BLK1TO3 for EMU_RAM0CTRL */ 268 #define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ 269 #define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ 270 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM0CTRL */ 271 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM0CTRL */ 272 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM0CTRL */ 273 274 /* Bit fields for EMU CMD */ 275 #define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ 276 #define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ 277 #define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ 278 #define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ 279 #define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ 280 #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 281 #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ 282 #define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ 283 #define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ 284 #define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ 285 #define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 286 #define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ 287 #define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ 288 #define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ 289 #define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ 290 #define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 291 #define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ 292 293 /* Bit fields for EMU EM4CTRL */ 294 #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ 295 #define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ 296 #define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ 297 #define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ 298 #define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ 299 #define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 300 #define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ 301 #define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ 302 #define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 303 #define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ 304 #define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ 305 #define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ 306 #define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ 307 #define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ 308 #define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 309 #define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 310 #define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ 311 #define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ 312 #define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ 313 #define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 314 #define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 315 #define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ 316 #define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ 317 #define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ 318 #define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 319 #define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 320 #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ 321 #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ 322 #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 323 #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ 324 #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ 325 #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ 326 #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 327 #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ 328 #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ 329 #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ 330 #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ 331 #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ 332 #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 333 #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 334 335 /* Bit fields for EMU TEMPLIMITS */ 336 #define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ 337 #define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ 338 #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ 339 #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ 340 #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ 341 #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ 342 #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ 343 #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ 344 #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ 345 #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ 346 #define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ 347 #define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ 348 #define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ 349 #define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ 350 #define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ 351 352 /* Bit fields for EMU TEMP */ 353 #define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ 354 #define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ 355 #define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ 356 #define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ 357 #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ 358 #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ 359 360 /* Bit fields for EMU IF */ 361 #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ 362 #define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ 363 #define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ 364 #define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ 365 #define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ 366 #define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 367 #define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ 368 #define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ 369 #define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ 370 #define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ 371 #define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 372 #define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ 373 #define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ 374 #define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ 375 #define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ 376 #define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 377 #define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ 378 #define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ 379 #define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ 380 #define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ 381 #define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 382 #define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ 383 #define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ 384 #define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ 385 #define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ 386 #define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 387 #define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ 388 #define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ 389 #define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ 390 #define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ 391 #define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 392 #define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ 393 #define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ 394 #define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ 395 #define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ 396 #define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 397 #define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ 398 #define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ 399 #define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ 400 #define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ 401 #define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 402 #define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ 403 #define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ 404 #define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ 405 #define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ 406 #define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 407 #define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ 408 #define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ 409 #define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ 410 #define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ 411 #define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 412 #define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ 413 #define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ 414 #define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ 415 #define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ 416 #define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 417 #define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ 418 #define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ 419 #define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ 420 #define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ 421 #define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 422 #define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ 423 #define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ 424 #define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ 425 #define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ 426 #define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 427 #define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ 428 #define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ 429 #define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ 430 #define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ 431 #define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 432 #define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ 433 #define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ 434 #define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ 435 #define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ 436 #define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 437 #define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ 438 #define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ 439 #define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ 440 #define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ 441 #define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 442 #define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ 443 #define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ 444 #define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ 445 #define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ 446 #define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 447 #define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ 448 #define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ 449 #define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ 450 #define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ 451 #define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 452 #define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ 453 #define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ 454 #define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ 455 #define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ 456 #define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 457 #define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ 458 #define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ 459 #define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ 460 #define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ 461 #define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 462 #define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ 463 #define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ 464 #define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 465 #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 466 #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 467 #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ 468 #define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ 469 #define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ 470 #define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ 471 #define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 472 #define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ 473 #define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ 474 #define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 475 #define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 476 #define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 477 #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ 478 #define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ 479 #define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 480 #define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 481 #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 482 #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ 483 #define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ 484 #define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 485 #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 486 #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 487 #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ 488 489 /* Bit fields for EMU IFS */ 490 #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ 491 #define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ 492 #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ 493 #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ 494 #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ 495 #define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 496 #define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ 497 #define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ 498 #define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ 499 #define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ 500 #define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 501 #define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ 502 #define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ 503 #define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ 504 #define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ 505 #define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 506 #define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ 507 #define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ 508 #define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ 509 #define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ 510 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 511 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ 512 #define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ 513 #define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ 514 #define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ 515 #define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 516 #define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ 517 #define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ 518 #define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ 519 #define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ 520 #define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 521 #define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ 522 #define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ 523 #define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ 524 #define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ 525 #define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 526 #define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ 527 #define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ 528 #define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ 529 #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ 530 #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 531 #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ 532 #define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ 533 #define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ 534 #define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ 535 #define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 536 #define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ 537 #define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ 538 #define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ 539 #define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ 540 #define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 541 #define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ 542 #define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ 543 #define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ 544 #define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ 545 #define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 546 #define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ 547 #define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ 548 #define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ 549 #define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ 550 #define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 551 #define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ 552 #define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ 553 #define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ 554 #define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ 555 #define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 556 #define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ 557 #define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ 558 #define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ 559 #define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ 560 #define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 561 #define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ 562 #define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ 563 #define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ 564 #define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ 565 #define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 566 #define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ 567 #define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ 568 #define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ 569 #define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ 570 #define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 571 #define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ 572 #define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ 573 #define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ 574 #define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ 575 #define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 576 #define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ 577 #define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ 578 #define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ 579 #define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ 580 #define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 581 #define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ 582 #define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ 583 #define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ 584 #define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ 585 #define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 586 #define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ 587 #define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ 588 #define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ 589 #define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ 590 #define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 591 #define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ 592 #define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ 593 #define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 594 #define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 595 #define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 596 #define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ 597 #define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ 598 #define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ 599 #define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ 600 #define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 601 #define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ 602 #define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ 603 #define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 604 #define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 605 #define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 606 #define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ 607 #define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ 608 #define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 609 #define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 610 #define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 611 #define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ 612 #define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ 613 #define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 614 #define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 615 #define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 616 #define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ 617 618 /* Bit fields for EMU IFC */ 619 #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ 620 #define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ 621 #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ 622 #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ 623 #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ 624 #define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 625 #define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ 626 #define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ 627 #define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ 628 #define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ 629 #define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 630 #define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ 631 #define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ 632 #define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ 633 #define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ 634 #define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 635 #define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ 636 #define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ 637 #define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ 638 #define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ 639 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 640 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ 641 #define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ 642 #define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ 643 #define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ 644 #define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 645 #define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ 646 #define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ 647 #define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ 648 #define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ 649 #define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 650 #define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ 651 #define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ 652 #define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ 653 #define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ 654 #define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 655 #define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ 656 #define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ 657 #define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ 658 #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ 659 #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 660 #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ 661 #define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ 662 #define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ 663 #define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ 664 #define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 665 #define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ 666 #define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ 667 #define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ 668 #define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ 669 #define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 670 #define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ 671 #define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ 672 #define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ 673 #define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ 674 #define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 675 #define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ 676 #define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ 677 #define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ 678 #define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ 679 #define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 680 #define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ 681 #define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ 682 #define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ 683 #define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ 684 #define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 685 #define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ 686 #define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ 687 #define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ 688 #define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ 689 #define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 690 #define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ 691 #define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ 692 #define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ 693 #define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ 694 #define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 695 #define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ 696 #define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ 697 #define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ 698 #define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ 699 #define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 700 #define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ 701 #define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ 702 #define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ 703 #define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ 704 #define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 705 #define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ 706 #define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ 707 #define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ 708 #define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ 709 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 710 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ 711 #define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ 712 #define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ 713 #define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ 714 #define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 715 #define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ 716 #define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ 717 #define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ 718 #define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ 719 #define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 720 #define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ 721 #define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ 722 #define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 723 #define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 724 #define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 725 #define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ 726 #define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ 727 #define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ 728 #define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ 729 #define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 730 #define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ 731 #define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ 732 #define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 733 #define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 734 #define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 735 #define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ 736 #define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ 737 #define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 738 #define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 739 #define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 740 #define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ 741 #define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ 742 #define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 743 #define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 744 #define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 745 #define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ 746 747 /* Bit fields for EMU IEN */ 748 #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ 749 #define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ 750 #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ 751 #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ 752 #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ 753 #define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 754 #define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ 755 #define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ 756 #define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ 757 #define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ 758 #define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 759 #define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ 760 #define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ 761 #define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ 762 #define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ 763 #define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 764 #define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ 765 #define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ 766 #define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ 767 #define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ 768 #define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 769 #define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ 770 #define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ 771 #define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ 772 #define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ 773 #define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 774 #define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ 775 #define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ 776 #define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ 777 #define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ 778 #define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 779 #define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ 780 #define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ 781 #define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ 782 #define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ 783 #define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 784 #define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ 785 #define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ 786 #define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ 787 #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ 788 #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 789 #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ 790 #define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ 791 #define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ 792 #define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ 793 #define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 794 #define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ 795 #define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ 796 #define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ 797 #define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ 798 #define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 799 #define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ 800 #define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ 801 #define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ 802 #define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ 803 #define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 804 #define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ 805 #define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ 806 #define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ 807 #define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ 808 #define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 809 #define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ 810 #define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ 811 #define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ 812 #define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ 813 #define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 814 #define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ 815 #define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ 816 #define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ 817 #define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ 818 #define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 819 #define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ 820 #define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ 821 #define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ 822 #define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ 823 #define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 824 #define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ 825 #define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ 826 #define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ 827 #define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ 828 #define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 829 #define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ 830 #define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ 831 #define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ 832 #define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ 833 #define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 834 #define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ 835 #define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ 836 #define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ 837 #define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ 838 #define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 839 #define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ 840 #define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ 841 #define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ 842 #define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ 843 #define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 844 #define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ 845 #define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ 846 #define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ 847 #define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ 848 #define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 849 #define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ 850 #define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ 851 #define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 852 #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 853 #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 854 #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ 855 #define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ 856 #define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ 857 #define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ 858 #define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 859 #define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ 860 #define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ 861 #define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 862 #define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 863 #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 864 #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ 865 #define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ 866 #define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 867 #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 868 #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 869 #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ 870 #define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ 871 #define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 872 #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 873 #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 874 #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ 875 876 /* Bit fields for EMU PWRLOCK */ 877 #define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ 878 #define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ 879 #define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ 880 #define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ 881 #define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ 882 #define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ 883 #define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ 884 #define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ 885 #define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ 886 #define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ 887 #define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ 888 #define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ 889 #define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ 890 #define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ 891 892 /* Bit fields for EMU PWRCTRL */ 893 #define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ 894 #define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ 895 #define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ 896 #define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ 897 #define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ 898 #define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ 899 #define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ 900 #define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ 901 #define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ 902 #define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ 903 #define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ 904 #define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ 905 #define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ 906 #define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ 907 #define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ 908 #define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ 909 #define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ 910 #define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ 911 #define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ 912 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ 913 #define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ 914 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ 915 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ 916 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ 917 #define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ 918 919 /* Bit fields for EMU DCDCCTRL */ 920 #define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ 921 #define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ 922 #define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ 923 #define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ 924 #define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ 925 #define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ 926 #define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ 927 #define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ 928 #define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ 929 #define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ 930 #define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ 931 #define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ 932 #define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ 933 #define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ 934 #define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ 935 #define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ 936 #define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ 937 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ 938 #define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ 939 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ 940 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ 941 #define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ 942 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ 943 #define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ 944 #define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ 945 #define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ 946 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ 947 #define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ 948 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ 949 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ 950 #define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ 951 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ 952 953 /* Bit fields for EMU DCDCMISCCTRL */ 954 #define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ 955 #define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ 956 #define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ 957 #define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ 958 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ 959 #define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 960 #define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 961 #define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ 962 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ 963 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ 964 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 965 #define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 966 #define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ 967 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ 968 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ 969 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 970 #define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 971 #define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ 972 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ 973 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ 974 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 975 #define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 976 #define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ 977 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ 978 #define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 979 #define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 980 #define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ 981 #define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ 982 #define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 983 #define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 984 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ 985 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ 986 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 987 #define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 988 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ 989 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ 990 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 991 #define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 992 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ 993 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ 994 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 995 #define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 996 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ 997 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ 998 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 999 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ 1000 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ 1001 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ 1002 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ 1003 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 1004 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ 1005 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ 1006 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ 1007 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ 1008 1009 /* Bit fields for EMU DCDCZDETCTRL */ 1010 #define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ 1011 #define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ 1012 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ 1013 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ 1014 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ 1015 #define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ 1016 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ 1017 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ 1018 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ 1019 #define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ 1020 1021 /* Bit fields for EMU DCDCCLIMCTRL */ 1022 #define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ 1023 #define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ 1024 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ 1025 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ 1026 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ 1027 #define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ 1028 #define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ 1029 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ 1030 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ 1031 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ 1032 #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ 1033 1034 /* Bit fields for EMU DCDCLNCOMPCTRL */ 1035 #define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ 1036 #define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ 1037 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ 1038 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ 1039 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 1040 #define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 1041 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ 1042 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ 1043 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 1044 #define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 1045 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ 1046 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ 1047 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 1048 #define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 1049 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ 1050 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ 1051 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 1052 #define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 1053 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ 1054 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ 1055 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 1056 #define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 1057 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ 1058 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ 1059 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 1060 #define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 1061 1062 /* Bit fields for EMU DCDCLNVCTRL */ 1063 #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ 1064 #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ 1065 #define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ 1066 #define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ 1067 #define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ 1068 #define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ 1069 #define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ 1070 #define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ 1071 #define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ 1072 #define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ 1073 #define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ 1074 #define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ 1075 #define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ 1076 #define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ 1077 #define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ 1078 1079 /* Bit fields for EMU DCDCLPVCTRL */ 1080 #define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ 1081 #define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ 1082 #define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ 1083 #define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ 1084 #define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ 1085 #define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ 1086 #define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ 1087 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ 1088 #define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ 1089 #define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ 1090 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ 1091 #define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ 1092 #define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ 1093 #define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ 1094 #define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ 1095 1096 /* Bit fields for EMU DCDCLPCTRL */ 1097 #define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ 1098 #define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ 1099 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ 1100 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ 1101 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ 1102 #define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ 1103 #define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ 1104 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ 1105 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ 1106 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ 1107 #define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ 1108 #define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ 1109 #define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ 1110 #define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ 1111 #define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ 1112 1113 /* Bit fields for EMU DCDCLNFREQCTRL */ 1114 #define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ 1115 #define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ 1116 #define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ 1117 #define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ 1118 #define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ 1119 #define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ 1120 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ 1121 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ 1122 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ 1123 #define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ 1124 1125 /* Bit fields for EMU DCDCSYNC */ 1126 #define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ 1127 #define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ 1128 #define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ 1129 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ 1130 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ 1131 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ 1132 #define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ 1133 1134 /* Bit fields for EMU VMONAVDDCTRL */ 1135 #define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ 1136 #define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ 1137 #define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ 1138 #define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 1139 #define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 1140 #define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 1141 #define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 1142 #define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ 1143 #define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ 1144 #define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ 1145 #define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 1146 #define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 1147 #define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ 1148 #define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ 1149 #define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ 1150 #define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 1151 #define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 1152 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ 1153 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ 1154 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 1155 #define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 1156 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ 1157 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ 1158 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 1159 #define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 1160 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ 1161 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ 1162 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 1163 #define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 1164 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ 1165 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ 1166 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 1167 #define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 1168 1169 /* Bit fields for EMU VMONALTAVDDCTRL */ 1170 #define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ 1171 #define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ 1172 #define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ 1173 #define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 1174 #define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 1175 #define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ 1176 #define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ 1177 #define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ 1178 #define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ 1179 #define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ 1180 #define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ 1181 #define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ 1182 #define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ 1183 #define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ 1184 #define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ 1185 #define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ 1186 #define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ 1187 #define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ 1188 #define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ 1189 #define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ 1190 #define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ 1191 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ 1192 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ 1193 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ 1194 #define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ 1195 1196 /* Bit fields for EMU VMONDVDDCTRL */ 1197 #define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ 1198 #define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ 1199 #define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ 1200 #define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 1201 #define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 1202 #define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ 1203 #define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ 1204 #define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ 1205 #define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ 1206 #define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ 1207 #define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ 1208 #define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ 1209 #define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ 1210 #define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ 1211 #define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ 1212 #define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ 1213 #define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ 1214 #define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ 1215 #define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ 1216 #define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ 1217 #define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ 1218 #define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ 1219 #define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ 1220 #define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ 1221 #define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ 1222 1223 /* Bit fields for EMU VMONIO0CTRL */ 1224 #define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ 1225 #define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ 1226 #define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ 1227 #define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 1228 #define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 1229 #define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ 1230 #define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ 1231 #define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ 1232 #define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ 1233 #define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ 1234 #define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ 1235 #define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ 1236 #define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ 1237 #define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ 1238 #define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ 1239 #define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ 1240 #define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ 1241 #define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ 1242 #define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ 1243 #define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ 1244 #define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ 1245 #define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ 1246 #define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ 1247 #define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ 1248 #define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ 1249 #define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ 1250 #define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ 1251 #define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ 1252 #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ 1253 #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ 1254 1255 /* Bit fields for EMU VMONIO1CTRL */ 1256 #define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ 1257 #define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ 1258 #define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ 1259 #define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 1260 #define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 1261 #define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ 1262 #define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ 1263 #define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ 1264 #define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ 1265 #define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ 1266 #define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ 1267 #define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ 1268 #define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ 1269 #define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ 1270 #define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ 1271 #define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ 1272 #define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ 1273 #define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ 1274 #define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ 1275 #define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ 1276 #define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ 1277 #define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ 1278 #define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ 1279 #define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ 1280 #define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ 1281 #define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ 1282 #define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ 1283 #define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ 1284 #define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ 1285 #define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ 1286 1287 /* Bit fields for EMU VMONBUVDDCTRL */ 1288 #define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ 1289 #define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ 1290 #define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ 1291 #define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 1292 #define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 1293 #define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ 1294 #define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ 1295 #define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ 1296 #define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ 1297 #define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ 1298 #define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ 1299 #define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ 1300 #define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ 1301 #define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ 1302 #define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ 1303 #define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ 1304 #define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ 1305 #define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ 1306 #define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ 1307 #define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ 1308 #define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ 1309 #define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ 1310 #define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ 1311 #define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ 1312 #define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ 1313 1314 /* Bit fields for EMU RAM1CTRL */ 1315 #define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ 1316 #define _EMU_RAM1CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM1CTRL */ 1317 #define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ 1318 #define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ 1319 #define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ 1320 #define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ 1321 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM1CTRL */ 1322 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM1CTRL */ 1323 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM1CTRL */ 1324 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM1CTRL */ 1325 #define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ 1326 #define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ 1327 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM1CTRL */ 1328 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM1CTRL */ 1329 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM1CTRL */ 1330 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM1CTRL */ 1331 1332 /* Bit fields for EMU RAM2CTRL */ 1333 #define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ 1334 #define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ 1335 #define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ 1336 #define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ 1337 #define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ 1338 #define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ 1339 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ 1340 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ 1341 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ 1342 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ 1343 #define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ 1344 #define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ 1345 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ 1346 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ 1347 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ 1348 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ 1349 1350 /* Bit fields for EMU BUCTRL */ 1351 #define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ 1352 #define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ 1353 #define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ 1354 #define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 1355 #define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 1356 #define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 1357 #define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 1358 #define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ 1359 #define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ 1360 #define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ 1361 #define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 1362 #define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 1363 #define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ 1364 #define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ 1365 #define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ 1366 #define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 1367 #define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 1368 #define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ 1369 #define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ 1370 #define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 1371 #define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ 1372 #define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ 1373 #define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ 1374 #define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ 1375 #define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 1376 #define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ 1377 #define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ 1378 #define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ 1379 #define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ 1380 #define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ 1381 #define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ 1382 #define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 1383 #define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ 1384 #define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ 1385 #define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ 1386 #define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ 1387 #define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 1388 #define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ 1389 #define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ 1390 #define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ 1391 #define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ 1392 #define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ 1393 #define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ 1394 #define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 1395 #define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ 1396 #define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ 1397 #define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ 1398 #define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ 1399 #define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 1400 #define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ 1401 #define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ 1402 #define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ 1403 #define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ 1404 #define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ 1405 #define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ 1406 #define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 1407 #define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ 1408 #define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ 1409 #define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ 1410 #define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ 1411 #define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 1412 #define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ 1413 #define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ 1414 #define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ 1415 #define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ 1416 #define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ 1417 #define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ 1418 #define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ 1419 #define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 1420 #define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 1421 1422 /* Bit fields for EMU R5VCTRL */ 1423 #define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ 1424 #define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ 1425 #define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ 1426 #define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ 1427 #define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ 1428 #define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ 1429 #define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ 1430 #define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ 1431 #define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ 1432 #define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ 1433 #define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ 1434 #define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ 1435 #define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ 1436 #define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ 1437 #define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ 1438 #define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ 1439 #define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ 1440 #define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ 1441 #define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ 1442 #define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ 1443 #define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ 1444 #define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ 1445 #define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ 1446 #define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ 1447 #define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ 1448 #define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ 1449 #define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ 1450 1451 /* Bit fields for EMU R5VADCCTRL */ 1452 #define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ 1453 #define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ 1454 #define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ 1455 #define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ 1456 #define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ 1457 #define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ 1458 #define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ 1459 #define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ 1460 #define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ 1461 #define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ 1462 #define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ 1463 #define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ 1464 #define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ 1465 #define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ 1466 #define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ 1467 #define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ 1468 #define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ 1469 #define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ 1470 #define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ 1471 #define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ 1472 #define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ 1473 1474 /* Bit fields for EMU R5VOUTLEVEL */ 1475 #define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ 1476 #define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ 1477 #define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ 1478 #define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ 1479 #define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ 1480 #define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ 1481 1482 /* Bit fields for EMU R5VDETCTRL */ 1483 #define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ 1484 #define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ 1485 #define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ 1486 #define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ 1487 #define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ 1488 #define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ 1489 #define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ 1490 #define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ 1491 #define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ 1492 #define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ 1493 #define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ 1494 #define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ 1495 #define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ 1496 #define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ 1497 #define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ 1498 #define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ 1499 #define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ 1500 1501 /* Bit fields for EMU DCDCLPEM01CFG */ 1502 #define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ 1503 #define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ 1504 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ 1505 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ 1506 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ 1507 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ 1508 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ 1509 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ 1510 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ 1511 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ 1512 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ 1513 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ 1514 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ 1515 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ 1516 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ 1517 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ 1518 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ 1519 #define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ 1520 1521 /* Bit fields for EMU R5VSTATUS */ 1522 #define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ 1523 #define _EMU_R5VSTATUS_MASK 0x0000003FUL /**< Mask for EMU_R5VSTATUS */ 1524 #define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ 1525 #define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ 1526 #define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ 1527 #define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ 1528 #define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ 1529 #define EMU_R5VSTATUS_VBUSDET (0x1UL << 1) /**< USB VBUS Detected */ 1530 #define _EMU_R5VSTATUS_VBUSDET_SHIFT 1 /**< Shift value for EMU_VBUSDET */ 1531 #define _EMU_R5VSTATUS_VBUSDET_MASK 0x2UL /**< Bit mask for EMU_VBUSDET */ 1532 #define _EMU_R5VSTATUS_VBUSDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ 1533 #define EMU_R5VSTATUS_VBUSDET_DEFAULT (_EMU_R5VSTATUS_VBUSDET_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ 1534 #define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ 1535 #define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ 1536 #define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ 1537 #define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ 1538 #define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ 1539 #define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ 1540 #define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ 1541 #define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ 1542 #define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ 1543 #define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ 1544 #define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ 1545 #define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ 1546 #define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ 1547 #define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ 1548 #define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ 1549 #define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ 1550 #define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ 1551 #define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ 1552 #define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ 1553 #define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ 1554 1555 /* Bit fields for EMU R5VSYNC */ 1556 #define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ 1557 #define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ 1558 #define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ 1559 #define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ 1560 #define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ 1561 #define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ 1562 #define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ 1563 1564 /* Bit fields for EMU EM23PERNORETAINCMD */ 1565 #define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ 1566 #define _EMU_EM23PERNORETAINCMD_MASK 0x01B7FFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ 1567 #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ 1568 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ 1569 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ 1570 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1571 #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1572 #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ 1573 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ 1574 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ 1575 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1576 #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1577 #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ 1578 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ 1579 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ 1580 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1581 #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1582 #define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ 1583 #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ 1584 #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ 1585 #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1586 #define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1587 #define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ 1588 #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ 1589 #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ 1590 #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1591 #define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1592 #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ 1593 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ 1594 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ 1595 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1596 #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1597 #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ 1598 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ 1599 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ 1600 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1601 #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1602 #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ 1603 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ 1604 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ 1605 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1606 #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1607 #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ 1608 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ 1609 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ 1610 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1611 #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1612 #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ 1613 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ 1614 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ 1615 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1616 #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1617 #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ 1618 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ 1619 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ 1620 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1621 #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1622 #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ 1623 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ 1624 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ 1625 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1626 #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1627 #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ 1628 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ 1629 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ 1630 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1631 #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1632 #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ 1633 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ 1634 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ 1635 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1636 #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1637 #define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ 1638 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ 1639 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ 1640 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1641 #define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1642 #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ 1643 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ 1644 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ 1645 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1646 #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1647 #define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ 1648 #define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ 1649 #define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ 1650 #define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1651 #define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1652 #define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ 1653 #define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ 1654 #define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ 1655 #define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1656 #define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1657 #define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ 1658 #define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ 1659 #define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ 1660 #define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1661 #define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1662 #define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ 1663 #define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ 1664 #define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ 1665 #define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1666 #define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1667 #define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ 1668 #define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ 1669 #define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ 1670 #define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1671 #define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1672 #define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ 1673 #define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ 1674 #define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ 1675 #define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1676 #define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1677 #define EMU_EM23PERNORETAINCMD_USBUNLOCK (0x1UL << 24) /**< Clears Status Bit of USB and Unlocks Access to It */ 1678 #define _EMU_EM23PERNORETAINCMD_USBUNLOCK_SHIFT 24 /**< Shift value for EMU_USBUNLOCK */ 1679 #define _EMU_EM23PERNORETAINCMD_USBUNLOCK_MASK 0x1000000UL /**< Bit mask for EMU_USBUNLOCK */ 1680 #define _EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1681 #define EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 1682 1683 /* Bit fields for EMU EM23PERNORETAINSTATUS */ 1684 #define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ 1685 #define _EMU_EM23PERNORETAINSTATUS_MASK 0x01B7FFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ 1686 #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ 1687 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ 1688 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ 1689 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1690 #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1691 #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ 1692 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ 1693 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ 1694 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1695 #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1696 #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ 1697 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ 1698 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ 1699 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1700 #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1701 #define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ 1702 #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ 1703 #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ 1704 #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1705 #define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1706 #define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ 1707 #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ 1708 #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ 1709 #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1710 #define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1711 #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ 1712 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ 1713 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ 1714 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1715 #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1716 #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ 1717 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ 1718 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ 1719 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1720 #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1721 #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ 1722 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ 1723 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ 1724 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1725 #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1726 #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ 1727 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ 1728 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ 1729 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1730 #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1731 #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ 1732 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ 1733 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ 1734 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1735 #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1736 #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ 1737 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ 1738 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ 1739 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1740 #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1741 #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ 1742 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ 1743 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ 1744 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1745 #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1746 #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ 1747 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ 1748 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ 1749 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1750 #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1751 #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ 1752 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ 1753 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ 1754 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1755 #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1756 #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ 1757 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ 1758 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ 1759 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1760 #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1761 #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ 1762 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ 1763 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ 1764 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1765 #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1766 #define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ 1767 #define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ 1768 #define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ 1769 #define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1770 #define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1771 #define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ 1772 #define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ 1773 #define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ 1774 #define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1775 #define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1776 #define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ 1777 #define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ 1778 #define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ 1779 #define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1780 #define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1781 #define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ 1782 #define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ 1783 #define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ 1784 #define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1785 #define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1786 #define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ 1787 #define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ 1788 #define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ 1789 #define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1790 #define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1791 #define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ 1792 #define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ 1793 #define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ 1794 #define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1795 #define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1796 #define EMU_EM23PERNORETAINSTATUS_USBLOCKED (0x1UL << 24) /**< Indicates If USB Powered Down During EM23 */ 1797 #define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_SHIFT 24 /**< Shift value for EMU_USBLOCKED */ 1798 #define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_MASK 0x1000000UL /**< Bit mask for EMU_USBLOCKED */ 1799 #define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1800 #define EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 1801 1802 /* Bit fields for EMU EM23PERNORETAINCTRL */ 1803 #define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ 1804 #define _EMU_EM23PERNORETAINCTRL_MASK 0x01B7FFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ 1805 #define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ 1806 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ 1807 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ 1808 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1809 #define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1810 #define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ 1811 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ 1812 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ 1813 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1814 #define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1815 #define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ 1816 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ 1817 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ 1818 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1819 #define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1820 #define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ 1821 #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ 1822 #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ 1823 #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1824 #define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1825 #define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ 1826 #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ 1827 #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ 1828 #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1829 #define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1830 #define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ 1831 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ 1832 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ 1833 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1834 #define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1835 #define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ 1836 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ 1837 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ 1838 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1839 #define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1840 #define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ 1841 #define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ 1842 #define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ 1843 #define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1844 #define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1845 #define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ 1846 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ 1847 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ 1848 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1849 #define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1850 #define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ 1851 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ 1852 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ 1853 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1854 #define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1855 #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ 1856 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ 1857 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ 1858 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1859 #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1860 #define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ 1861 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ 1862 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ 1863 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1864 #define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1865 #define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ 1866 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ 1867 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ 1868 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1869 #define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1870 #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ 1871 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ 1872 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ 1873 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1874 #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1875 #define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ 1876 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ 1877 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ 1878 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1879 #define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1880 #define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ 1881 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ 1882 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ 1883 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1884 #define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1885 #define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ 1886 #define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ 1887 #define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ 1888 #define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1889 #define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1890 #define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ 1891 #define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ 1892 #define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ 1893 #define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1894 #define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1895 #define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ 1896 #define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ 1897 #define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ 1898 #define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1899 #define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1900 #define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ 1901 #define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ 1902 #define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ 1903 #define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1904 #define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1905 #define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ 1906 #define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ 1907 #define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ 1908 #define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1909 #define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1910 #define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ 1911 #define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ 1912 #define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ 1913 #define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1914 #define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1915 #define EMU_EM23PERNORETAINCTRL_USBDIS (0x1UL << 24) /**< Allow Power Down of USB During EM23 */ 1916 #define _EMU_EM23PERNORETAINCTRL_USBDIS_SHIFT 24 /**< Shift value for EMU_USBDIS */ 1917 #define _EMU_EM23PERNORETAINCTRL_USBDIS_MASK 0x1000000UL /**< Bit mask for EMU_USBDIS */ 1918 #define _EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1919 #define EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 1920 1921 /** @} */ 1922 /** @} End of group EFM32GG12B_EMU */ 1923 /** @} End of group Parts */ 1924
