1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG12B_DMAREQ register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 42 /***************************************************************************//** 43 * @addtogroup EFM32GG12B_DMAREQ DMAREQ 44 * @{ 45 * @defgroup EFM32GG12B_DMAREQ_BitFields DMAREQ Bit Fields 46 * @{ 47 ******************************************************************************/ 48 #define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */ 49 #define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */ 50 #define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */ 51 #define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */ 52 #define DMAREQ_ADC1_SINGLE ((9 << 16) + 0) /**< DMA channel select for ADC1_SINGLE */ 53 #define DMAREQ_ADC1_SCAN ((9 << 16) + 1) /**< DMA channel select for ADC1_SCAN */ 54 #define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */ 55 #define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */ 56 #define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */ 57 #define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */ 58 #define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */ 59 #define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */ 60 #define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */ 61 #define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */ 62 #define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */ 63 #define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */ 64 #define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */ 65 #define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */ 66 #define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */ 67 #define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */ 68 #define DMAREQ_USART3_TXBL ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */ 69 #define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */ 70 #define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */ 71 #define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */ 72 #define DMAREQ_USART4_RXDATAV ((16 << 16) + 0) /**< DMA channel select for USART4_RXDATAV */ 73 #define DMAREQ_USART4_TXBL ((16 << 16) + 1) /**< DMA channel select for USART4_TXBL */ 74 #define DMAREQ_USART4_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for USART4_TXEMPTY */ 75 #define DMAREQ_USART4_RXDATAVRIGHT ((16 << 16) + 3) /**< DMA channel select for USART4_RXDATAVRIGHT */ 76 #define DMAREQ_USART4_TXBLRIGHT ((16 << 16) + 4) /**< DMA channel select for USART4_TXBLRIGHT */ 77 #define DMAREQ_UART0_RXDATAV ((18 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */ 78 #define DMAREQ_UART0_TXBL ((18 << 16) + 1) /**< DMA channel select for UART0_TXBL */ 79 #define DMAREQ_UART0_TXEMPTY ((18 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */ 80 #define DMAREQ_UART1_RXDATAV ((19 << 16) + 0) /**< DMA channel select for UART1_RXDATAV */ 81 #define DMAREQ_UART1_TXBL ((19 << 16) + 1) /**< DMA channel select for UART1_TXBL */ 82 #define DMAREQ_UART1_TXEMPTY ((19 << 16) + 2) /**< DMA channel select for UART1_TXEMPTY */ 83 #define DMAREQ_LEUART0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */ 84 #define DMAREQ_LEUART0_TXBL ((20 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */ 85 #define DMAREQ_LEUART0_TXEMPTY ((20 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */ 86 #define DMAREQ_LEUART1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */ 87 #define DMAREQ_LEUART1_TXBL ((21 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */ 88 #define DMAREQ_LEUART1_TXEMPTY ((21 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */ 89 #define DMAREQ_I2C0_RXDATAV ((22 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */ 90 #define DMAREQ_I2C0_TXBL ((22 << 16) + 1) /**< DMA channel select for I2C0_TXBL */ 91 #define DMAREQ_I2C1_RXDATAV ((23 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */ 92 #define DMAREQ_I2C1_TXBL ((23 << 16) + 1) /**< DMA channel select for I2C1_TXBL */ 93 #define DMAREQ_TIMER0_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */ 94 #define DMAREQ_TIMER0_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */ 95 #define DMAREQ_TIMER0_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */ 96 #define DMAREQ_TIMER0_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */ 97 #define DMAREQ_TIMER1_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */ 98 #define DMAREQ_TIMER1_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */ 99 #define DMAREQ_TIMER1_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */ 100 #define DMAREQ_TIMER1_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */ 101 #define DMAREQ_TIMER1_CC3 ((26 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */ 102 #define DMAREQ_TIMER2_UFOF ((27 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */ 103 #define DMAREQ_TIMER2_CC0 ((27 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */ 104 #define DMAREQ_TIMER2_CC1 ((27 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */ 105 #define DMAREQ_TIMER2_CC2 ((27 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */ 106 #define DMAREQ_TIMER3_UFOF ((28 << 16) + 0) /**< DMA channel select for TIMER3_UFOF */ 107 #define DMAREQ_TIMER3_CC0 ((28 << 16) + 1) /**< DMA channel select for TIMER3_CC0 */ 108 #define DMAREQ_TIMER3_CC1 ((28 << 16) + 2) /**< DMA channel select for TIMER3_CC1 */ 109 #define DMAREQ_TIMER3_CC2 ((28 << 16) + 3) /**< DMA channel select for TIMER3_CC2 */ 110 #define DMAREQ_WTIMER0_UFOF ((32 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */ 111 #define DMAREQ_WTIMER0_CC0 ((32 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */ 112 #define DMAREQ_WTIMER0_CC1 ((32 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */ 113 #define DMAREQ_WTIMER0_CC2 ((32 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */ 114 #define DMAREQ_WTIMER1_UFOF ((33 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */ 115 #define DMAREQ_WTIMER1_CC0 ((33 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */ 116 #define DMAREQ_WTIMER1_CC1 ((33 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */ 117 #define DMAREQ_WTIMER1_CC2 ((33 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */ 118 #define DMAREQ_WTIMER1_CC3 ((33 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */ 119 #define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */ 120 #define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */ 121 #define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */ 122 #define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */ 123 #define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */ 124 #define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */ 125 #define DMAREQ_EBI_PXL0EMPTY ((50 << 16) + 0) /**< DMA channel select for EBI_PXL0EMPTY */ 126 #define DMAREQ_EBI_PXL1EMPTY ((50 << 16) + 1) /**< DMA channel select for EBI_PXL1EMPTY */ 127 #define DMAREQ_EBI_PXLFULL ((50 << 16) + 2) /**< DMA channel select for EBI_PXLFULL */ 128 #define DMAREQ_EBI_DDEMPTY ((50 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */ 129 #define DMAREQ_EBI_VSYNC ((50 << 16) + 4) /**< DMA channel select for EBI_VSYNC */ 130 #define DMAREQ_EBI_HSYNC ((50 << 16) + 5) /**< DMA channel select for EBI_HSYNC */ 131 #define DMAREQ_PDM_RXDATAV ((51 << 16) + 0) /**< DMA channel select for PDM_RXDATAV */ 132 #define DMAREQ_CSEN_DATA ((61 << 16) + 0) /**< DMA channel select for CSEN_DATA */ 133 #define DMAREQ_CSEN_BSLN ((61 << 16) + 1) /**< DMA channel select for CSEN_BSLN */ 134 #define DMAREQ_LESENSE_BUFDATAV ((62 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */ 135 136 /** @} */ 137 /** @} End of group EFM32GG12B_DMAREQ */ 138 /** @} End of group Parts */ 139
