1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG12B_CAN register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG12B_CAN CAN 43 * @{ 44 * @brief EFM32GG12B_CAN Register Declaration 45 ******************************************************************************/ 46 /** CAN Register Declaration */ 47 typedef struct { 48 __IOM uint32_t CTRL; /**< Control Register */ 49 __IOM uint32_t STATUS; /**< Status Register */ 50 __IM uint32_t ERRCNT; /**< Error Count Register */ 51 __IOM uint32_t BITTIMING; /**< Bit Timing Register */ 52 __IM uint32_t INTID; /**< Interrupt Identification Register */ 53 __IOM uint32_t TEST; /**< Test Register */ 54 __IOM uint32_t BRPE; /**< BRP Extension Register */ 55 __IM uint32_t TRANSREQ; /**< Transmission Request Register */ 56 __IM uint32_t MESSAGEDATA; /**< New Data Register */ 57 58 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 59 __IM uint32_t MESSAGESTATE; /**< Message Valid Register */ 60 __IOM uint32_t CONFIG; /**< Configuration Register */ 61 __IM uint32_t IF0IF; /**< Message Object Interrupt Flag Register */ 62 __IOM uint32_t IF0IFS; /**< Message Object Interrupt Flag Set Register */ 63 __IOM uint32_t IF0IFC; /**< Message Object Interrupt Flag Clear Register */ 64 __IOM uint32_t IF0IEN; /**< Message Object Interrupt Enable Register */ 65 __IM uint32_t IF1IF; /**< Status Interrupt Flag Register */ 66 __IOM uint32_t IF1IFS; /**< Message Object Interrupt Flag Set Register */ 67 __IOM uint32_t IF1IFC; /**< Message Object Interrupt Flag Clear Register */ 68 __IOM uint32_t IF1IEN; /**< Status Interrupt Enable Register */ 69 __IOM uint32_t ROUTE; /**< I/O Routing Register */ 70 71 uint32_t RESERVED1[3U]; /**< Reserved registers */ 72 CAN_MIR_TypeDef MIR[2U]; /**< Interface Registers */ 73 } CAN_TypeDef; /** @} */ 74 75 /***************************************************************************//** 76 * @addtogroup EFM32GG12B_CAN 77 * @{ 78 * @defgroup EFM32GG12B_CAN_BitFields CAN Bit Fields 79 * @{ 80 ******************************************************************************/ 81 82 /* Bit fields for CAN CTRL */ 83 #define _CAN_CTRL_RESETVALUE 0x00000001UL /**< Default value for CAN_CTRL */ 84 #define _CAN_CTRL_MASK 0x000000EFUL /**< Mask for CAN_CTRL */ 85 #define CAN_CTRL_INIT (0x1UL << 0) /**< Initialize */ 86 #define _CAN_CTRL_INIT_SHIFT 0 /**< Shift value for CAN_INIT */ 87 #define _CAN_CTRL_INIT_MASK 0x1UL /**< Bit mask for CAN_INIT */ 88 #define _CAN_CTRL_INIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_CTRL */ 89 #define CAN_CTRL_INIT_DEFAULT (_CAN_CTRL_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_CTRL */ 90 #define CAN_CTRL_IE (0x1UL << 1) /**< Module Interrupt Enable */ 91 #define _CAN_CTRL_IE_SHIFT 1 /**< Shift value for CAN_IE */ 92 #define _CAN_CTRL_IE_MASK 0x2UL /**< Bit mask for CAN_IE */ 93 #define _CAN_CTRL_IE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */ 94 #define CAN_CTRL_IE_DEFAULT (_CAN_CTRL_IE_DEFAULT << 1) /**< Shifted mode DEFAULT for CAN_CTRL */ 95 #define CAN_CTRL_SIE (0x1UL << 2) /**< Status Change Interrupt Enable */ 96 #define _CAN_CTRL_SIE_SHIFT 2 /**< Shift value for CAN_SIE */ 97 #define _CAN_CTRL_SIE_MASK 0x4UL /**< Bit mask for CAN_SIE */ 98 #define _CAN_CTRL_SIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */ 99 #define CAN_CTRL_SIE_DEFAULT (_CAN_CTRL_SIE_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_CTRL */ 100 #define CAN_CTRL_EIE (0x1UL << 3) /**< Error Interrupt Enable */ 101 #define _CAN_CTRL_EIE_SHIFT 3 /**< Shift value for CAN_EIE */ 102 #define _CAN_CTRL_EIE_MASK 0x8UL /**< Bit mask for CAN_EIE */ 103 #define _CAN_CTRL_EIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */ 104 #define CAN_CTRL_EIE_DEFAULT (_CAN_CTRL_EIE_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_CTRL */ 105 #define CAN_CTRL_DAR (0x1UL << 5) /**< Disable Automatic Retransmission */ 106 #define _CAN_CTRL_DAR_SHIFT 5 /**< Shift value for CAN_DAR */ 107 #define _CAN_CTRL_DAR_MASK 0x20UL /**< Bit mask for CAN_DAR */ 108 #define _CAN_CTRL_DAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */ 109 #define CAN_CTRL_DAR_DEFAULT (_CAN_CTRL_DAR_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_CTRL */ 110 #define CAN_CTRL_CCE (0x1UL << 6) /**< Configuration Change Enable */ 111 #define _CAN_CTRL_CCE_SHIFT 6 /**< Shift value for CAN_CCE */ 112 #define _CAN_CTRL_CCE_MASK 0x40UL /**< Bit mask for CAN_CCE */ 113 #define _CAN_CTRL_CCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */ 114 #define CAN_CTRL_CCE_DEFAULT (_CAN_CTRL_CCE_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_CTRL */ 115 #define CAN_CTRL_TEST (0x1UL << 7) /**< Test Mode Enable Write */ 116 #define _CAN_CTRL_TEST_SHIFT 7 /**< Shift value for CAN_TEST */ 117 #define _CAN_CTRL_TEST_MASK 0x80UL /**< Bit mask for CAN_TEST */ 118 #define _CAN_CTRL_TEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */ 119 #define CAN_CTRL_TEST_DEFAULT (_CAN_CTRL_TEST_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_CTRL */ 120 121 /* Bit fields for CAN STATUS */ 122 #define _CAN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CAN_STATUS */ 123 #define _CAN_STATUS_MASK 0x000000FFUL /**< Mask for CAN_STATUS */ 124 #define _CAN_STATUS_LEC_SHIFT 0 /**< Shift value for CAN_LEC */ 125 #define _CAN_STATUS_LEC_MASK 0x7UL /**< Bit mask for CAN_LEC */ 126 #define _CAN_STATUS_LEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */ 127 #define _CAN_STATUS_LEC_NONE 0x00000000UL /**< Mode NONE for CAN_STATUS */ 128 #define _CAN_STATUS_LEC_STUFF 0x00000001UL /**< Mode STUFF for CAN_STATUS */ 129 #define _CAN_STATUS_LEC_FORM 0x00000002UL /**< Mode FORM for CAN_STATUS */ 130 #define _CAN_STATUS_LEC_ACK 0x00000003UL /**< Mode ACK for CAN_STATUS */ 131 #define _CAN_STATUS_LEC_BIT1 0x00000004UL /**< Mode BIT1 for CAN_STATUS */ 132 #define _CAN_STATUS_LEC_BIT0 0x00000005UL /**< Mode BIT0 for CAN_STATUS */ 133 #define _CAN_STATUS_LEC_CRC 0x00000006UL /**< Mode CRC for CAN_STATUS */ 134 #define _CAN_STATUS_LEC_UNUSED 0x00000007UL /**< Mode UNUSED for CAN_STATUS */ 135 #define CAN_STATUS_LEC_DEFAULT (_CAN_STATUS_LEC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_STATUS */ 136 #define CAN_STATUS_LEC_NONE (_CAN_STATUS_LEC_NONE << 0) /**< Shifted mode NONE for CAN_STATUS */ 137 #define CAN_STATUS_LEC_STUFF (_CAN_STATUS_LEC_STUFF << 0) /**< Shifted mode STUFF for CAN_STATUS */ 138 #define CAN_STATUS_LEC_FORM (_CAN_STATUS_LEC_FORM << 0) /**< Shifted mode FORM for CAN_STATUS */ 139 #define CAN_STATUS_LEC_ACK (_CAN_STATUS_LEC_ACK << 0) /**< Shifted mode ACK for CAN_STATUS */ 140 #define CAN_STATUS_LEC_BIT1 (_CAN_STATUS_LEC_BIT1 << 0) /**< Shifted mode BIT1 for CAN_STATUS */ 141 #define CAN_STATUS_LEC_BIT0 (_CAN_STATUS_LEC_BIT0 << 0) /**< Shifted mode BIT0 for CAN_STATUS */ 142 #define CAN_STATUS_LEC_CRC (_CAN_STATUS_LEC_CRC << 0) /**< Shifted mode CRC for CAN_STATUS */ 143 #define CAN_STATUS_LEC_UNUSED (_CAN_STATUS_LEC_UNUSED << 0) /**< Shifted mode UNUSED for CAN_STATUS */ 144 #define CAN_STATUS_TXOK (0x1UL << 3) /**< Transmitted a Message Successfully */ 145 #define _CAN_STATUS_TXOK_SHIFT 3 /**< Shift value for CAN_TXOK */ 146 #define _CAN_STATUS_TXOK_MASK 0x8UL /**< Bit mask for CAN_TXOK */ 147 #define _CAN_STATUS_TXOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */ 148 #define CAN_STATUS_TXOK_DEFAULT (_CAN_STATUS_TXOK_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_STATUS */ 149 #define CAN_STATUS_RXOK (0x1UL << 4) /**< Received a Message Successfully */ 150 #define _CAN_STATUS_RXOK_SHIFT 4 /**< Shift value for CAN_RXOK */ 151 #define _CAN_STATUS_RXOK_MASK 0x10UL /**< Bit mask for CAN_RXOK */ 152 #define _CAN_STATUS_RXOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */ 153 #define CAN_STATUS_RXOK_DEFAULT (_CAN_STATUS_RXOK_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_STATUS */ 154 #define CAN_STATUS_EPASS (0x1UL << 5) /**< Error Passive */ 155 #define _CAN_STATUS_EPASS_SHIFT 5 /**< Shift value for CAN_EPASS */ 156 #define _CAN_STATUS_EPASS_MASK 0x20UL /**< Bit mask for CAN_EPASS */ 157 #define _CAN_STATUS_EPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */ 158 #define CAN_STATUS_EPASS_DEFAULT (_CAN_STATUS_EPASS_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_STATUS */ 159 #define CAN_STATUS_EWARN (0x1UL << 6) /**< Warning Status */ 160 #define _CAN_STATUS_EWARN_SHIFT 6 /**< Shift value for CAN_EWARN */ 161 #define _CAN_STATUS_EWARN_MASK 0x40UL /**< Bit mask for CAN_EWARN */ 162 #define _CAN_STATUS_EWARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */ 163 #define CAN_STATUS_EWARN_DEFAULT (_CAN_STATUS_EWARN_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_STATUS */ 164 #define CAN_STATUS_BOFF (0x1UL << 7) /**< Bus Off Status */ 165 #define _CAN_STATUS_BOFF_SHIFT 7 /**< Shift value for CAN_BOFF */ 166 #define _CAN_STATUS_BOFF_MASK 0x80UL /**< Bit mask for CAN_BOFF */ 167 #define _CAN_STATUS_BOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */ 168 #define CAN_STATUS_BOFF_DEFAULT (_CAN_STATUS_BOFF_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_STATUS */ 169 170 /* Bit fields for CAN ERRCNT */ 171 #define _CAN_ERRCNT_RESETVALUE 0x00000000UL /**< Default value for CAN_ERRCNT */ 172 #define _CAN_ERRCNT_MASK 0x0000FFFFUL /**< Mask for CAN_ERRCNT */ 173 #define _CAN_ERRCNT_TEC_SHIFT 0 /**< Shift value for CAN_TEC */ 174 #define _CAN_ERRCNT_TEC_MASK 0xFFUL /**< Bit mask for CAN_TEC */ 175 #define _CAN_ERRCNT_TEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */ 176 #define CAN_ERRCNT_TEC_DEFAULT (_CAN_ERRCNT_TEC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_ERRCNT */ 177 #define _CAN_ERRCNT_REC_SHIFT 8 /**< Shift value for CAN_REC */ 178 #define _CAN_ERRCNT_REC_MASK 0x7F00UL /**< Bit mask for CAN_REC */ 179 #define _CAN_ERRCNT_REC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */ 180 #define CAN_ERRCNT_REC_DEFAULT (_CAN_ERRCNT_REC_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_ERRCNT */ 181 #define CAN_ERRCNT_RECERRP (0x1UL << 15) /**< Receive Error Passive */ 182 #define _CAN_ERRCNT_RECERRP_SHIFT 15 /**< Shift value for CAN_RECERRP */ 183 #define _CAN_ERRCNT_RECERRP_MASK 0x8000UL /**< Bit mask for CAN_RECERRP */ 184 #define _CAN_ERRCNT_RECERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */ 185 #define _CAN_ERRCNT_RECERRP_FALSE 0x00000000UL /**< Mode FALSE for CAN_ERRCNT */ 186 #define _CAN_ERRCNT_RECERRP_TRUE 0x00000001UL /**< Mode TRUE for CAN_ERRCNT */ 187 #define CAN_ERRCNT_RECERRP_DEFAULT (_CAN_ERRCNT_RECERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_ERRCNT */ 188 #define CAN_ERRCNT_RECERRP_FALSE (_CAN_ERRCNT_RECERRP_FALSE << 15) /**< Shifted mode FALSE for CAN_ERRCNT */ 189 #define CAN_ERRCNT_RECERRP_TRUE (_CAN_ERRCNT_RECERRP_TRUE << 15) /**< Shifted mode TRUE for CAN_ERRCNT */ 190 191 /* Bit fields for CAN BITTIMING */ 192 #define _CAN_BITTIMING_RESETVALUE 0x00002301UL /**< Default value for CAN_BITTIMING */ 193 #define _CAN_BITTIMING_MASK 0x00007FFFUL /**< Mask for CAN_BITTIMING */ 194 #define _CAN_BITTIMING_BRP_SHIFT 0 /**< Shift value for CAN_BRP */ 195 #define _CAN_BITTIMING_BRP_MASK 0x3FUL /**< Bit mask for CAN_BRP */ 196 #define _CAN_BITTIMING_BRP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_BITTIMING */ 197 #define CAN_BITTIMING_BRP_DEFAULT (_CAN_BITTIMING_BRP_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_BITTIMING */ 198 #define _CAN_BITTIMING_SJW_SHIFT 6 /**< Shift value for CAN_SJW */ 199 #define _CAN_BITTIMING_SJW_MASK 0xC0UL /**< Bit mask for CAN_SJW */ 200 #define _CAN_BITTIMING_SJW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_BITTIMING */ 201 #define CAN_BITTIMING_SJW_DEFAULT (_CAN_BITTIMING_SJW_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_BITTIMING */ 202 #define _CAN_BITTIMING_TSEG1_SHIFT 8 /**< Shift value for CAN_TSEG1 */ 203 #define _CAN_BITTIMING_TSEG1_MASK 0xF00UL /**< Bit mask for CAN_TSEG1 */ 204 #define _CAN_BITTIMING_TSEG1_DEFAULT 0x00000003UL /**< Mode DEFAULT for CAN_BITTIMING */ 205 #define CAN_BITTIMING_TSEG1_DEFAULT (_CAN_BITTIMING_TSEG1_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_BITTIMING */ 206 #define _CAN_BITTIMING_TSEG2_SHIFT 12 /**< Shift value for CAN_TSEG2 */ 207 #define _CAN_BITTIMING_TSEG2_MASK 0x7000UL /**< Bit mask for CAN_TSEG2 */ 208 #define _CAN_BITTIMING_TSEG2_DEFAULT 0x00000002UL /**< Mode DEFAULT for CAN_BITTIMING */ 209 #define CAN_BITTIMING_TSEG2_DEFAULT (_CAN_BITTIMING_TSEG2_DEFAULT << 12) /**< Shifted mode DEFAULT for CAN_BITTIMING */ 210 211 /* Bit fields for CAN INTID */ 212 #define _CAN_INTID_RESETVALUE 0x00000000UL /**< Default value for CAN_INTID */ 213 #define _CAN_INTID_MASK 0x0000803FUL /**< Mask for CAN_INTID */ 214 #define _CAN_INTID_INTID_SHIFT 0 /**< Shift value for CAN_INTID */ 215 #define _CAN_INTID_INTID_MASK 0x3FUL /**< Bit mask for CAN_INTID */ 216 #define _CAN_INTID_INTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_INTID */ 217 #define CAN_INTID_INTID_DEFAULT (_CAN_INTID_INTID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_INTID */ 218 #define CAN_INTID_INTSTAT (0x1UL << 15) /**< Status Interupt */ 219 #define _CAN_INTID_INTSTAT_SHIFT 15 /**< Shift value for CAN_INTSTAT */ 220 #define _CAN_INTID_INTSTAT_MASK 0x8000UL /**< Bit mask for CAN_INTSTAT */ 221 #define _CAN_INTID_INTSTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_INTID */ 222 #define _CAN_INTID_INTSTAT_FALSE 0x00000000UL /**< Mode FALSE for CAN_INTID */ 223 #define _CAN_INTID_INTSTAT_TRUE 0x00000001UL /**< Mode TRUE for CAN_INTID */ 224 #define CAN_INTID_INTSTAT_DEFAULT (_CAN_INTID_INTSTAT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_INTID */ 225 #define CAN_INTID_INTSTAT_FALSE (_CAN_INTID_INTSTAT_FALSE << 15) /**< Shifted mode FALSE for CAN_INTID */ 226 #define CAN_INTID_INTSTAT_TRUE (_CAN_INTID_INTSTAT_TRUE << 15) /**< Shifted mode TRUE for CAN_INTID */ 227 228 /* Bit fields for CAN TEST */ 229 #define _CAN_TEST_RESETVALUE 0x00000000UL /**< Default value for CAN_TEST */ 230 #define _CAN_TEST_MASK 0x000000FCUL /**< Mask for CAN_TEST */ 231 #define CAN_TEST_BASIC (0x1UL << 2) /**< Basic Mode */ 232 #define _CAN_TEST_BASIC_SHIFT 2 /**< Shift value for CAN_BASIC */ 233 #define _CAN_TEST_BASIC_MASK 0x4UL /**< Bit mask for CAN_BASIC */ 234 #define _CAN_TEST_BASIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */ 235 #define CAN_TEST_BASIC_DEFAULT (_CAN_TEST_BASIC_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_TEST */ 236 #define CAN_TEST_SILENT (0x1UL << 3) /**< Silent Mode */ 237 #define _CAN_TEST_SILENT_SHIFT 3 /**< Shift value for CAN_SILENT */ 238 #define _CAN_TEST_SILENT_MASK 0x8UL /**< Bit mask for CAN_SILENT */ 239 #define _CAN_TEST_SILENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */ 240 #define CAN_TEST_SILENT_DEFAULT (_CAN_TEST_SILENT_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_TEST */ 241 #define CAN_TEST_LBACK (0x1UL << 4) /**< Loopback Mode */ 242 #define _CAN_TEST_LBACK_SHIFT 4 /**< Shift value for CAN_LBACK */ 243 #define _CAN_TEST_LBACK_MASK 0x10UL /**< Bit mask for CAN_LBACK */ 244 #define _CAN_TEST_LBACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */ 245 #define CAN_TEST_LBACK_DEFAULT (_CAN_TEST_LBACK_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_TEST */ 246 #define _CAN_TEST_TX_SHIFT 5 /**< Shift value for CAN_TX */ 247 #define _CAN_TEST_TX_MASK 0x60UL /**< Bit mask for CAN_TX */ 248 #define _CAN_TEST_TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */ 249 #define _CAN_TEST_TX_CORE 0x00000000UL /**< Mode CORE for CAN_TEST */ 250 #define _CAN_TEST_TX_SAMPT 0x00000001UL /**< Mode SAMPT for CAN_TEST */ 251 #define _CAN_TEST_TX_LOW 0x00000002UL /**< Mode LOW for CAN_TEST */ 252 #define _CAN_TEST_TX_HIGH 0x00000003UL /**< Mode HIGH for CAN_TEST */ 253 #define CAN_TEST_TX_DEFAULT (_CAN_TEST_TX_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_TEST */ 254 #define CAN_TEST_TX_CORE (_CAN_TEST_TX_CORE << 5) /**< Shifted mode CORE for CAN_TEST */ 255 #define CAN_TEST_TX_SAMPT (_CAN_TEST_TX_SAMPT << 5) /**< Shifted mode SAMPT for CAN_TEST */ 256 #define CAN_TEST_TX_LOW (_CAN_TEST_TX_LOW << 5) /**< Shifted mode LOW for CAN_TEST */ 257 #define CAN_TEST_TX_HIGH (_CAN_TEST_TX_HIGH << 5) /**< Shifted mode HIGH for CAN_TEST */ 258 #define CAN_TEST_RX (0x1UL << 7) /**< Monitors the Actual Value of CAN_RX Pin */ 259 #define _CAN_TEST_RX_SHIFT 7 /**< Shift value for CAN_RX */ 260 #define _CAN_TEST_RX_MASK 0x80UL /**< Bit mask for CAN_RX */ 261 #define _CAN_TEST_RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */ 262 #define _CAN_TEST_RX_LOW 0x00000000UL /**< Mode LOW for CAN_TEST */ 263 #define _CAN_TEST_RX_HIGH 0x00000001UL /**< Mode HIGH for CAN_TEST */ 264 #define CAN_TEST_RX_DEFAULT (_CAN_TEST_RX_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_TEST */ 265 #define CAN_TEST_RX_LOW (_CAN_TEST_RX_LOW << 7) /**< Shifted mode LOW for CAN_TEST */ 266 #define CAN_TEST_RX_HIGH (_CAN_TEST_RX_HIGH << 7) /**< Shifted mode HIGH for CAN_TEST */ 267 268 /* Bit fields for CAN BRPE */ 269 #define _CAN_BRPE_RESETVALUE 0x00000000UL /**< Default value for CAN_BRPE */ 270 #define _CAN_BRPE_MASK 0x0000000FUL /**< Mask for CAN_BRPE */ 271 #define _CAN_BRPE_BRPE_SHIFT 0 /**< Shift value for CAN_BRPE */ 272 #define _CAN_BRPE_BRPE_MASK 0xFUL /**< Bit mask for CAN_BRPE */ 273 #define _CAN_BRPE_BRPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_BRPE */ 274 #define CAN_BRPE_BRPE_DEFAULT (_CAN_BRPE_BRPE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_BRPE */ 275 276 /* Bit fields for CAN TRANSREQ */ 277 #define _CAN_TRANSREQ_RESETVALUE 0x00000000UL /**< Default value for CAN_TRANSREQ */ 278 #define _CAN_TRANSREQ_MASK 0xFFFFFFFFUL /**< Mask for CAN_TRANSREQ */ 279 #define _CAN_TRANSREQ_TXRQSTOUT_SHIFT 0 /**< Shift value for CAN_TXRQSTOUT */ 280 #define _CAN_TRANSREQ_TXRQSTOUT_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_TXRQSTOUT */ 281 #define _CAN_TRANSREQ_TXRQSTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TRANSREQ */ 282 #define _CAN_TRANSREQ_TXRQSTOUT_FALSE 0x00000000UL /**< Mode FALSE for CAN_TRANSREQ */ 283 #define _CAN_TRANSREQ_TXRQSTOUT_TRUE 0x00000001UL /**< Mode TRUE for CAN_TRANSREQ */ 284 #define CAN_TRANSREQ_TXRQSTOUT_DEFAULT (_CAN_TRANSREQ_TXRQSTOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_TRANSREQ */ 285 #define CAN_TRANSREQ_TXRQSTOUT_FALSE (_CAN_TRANSREQ_TXRQSTOUT_FALSE << 0) /**< Shifted mode FALSE for CAN_TRANSREQ */ 286 #define CAN_TRANSREQ_TXRQSTOUT_TRUE (_CAN_TRANSREQ_TXRQSTOUT_TRUE << 0) /**< Shifted mode TRUE for CAN_TRANSREQ */ 287 288 /* Bit fields for CAN MESSAGEDATA */ 289 #define _CAN_MESSAGEDATA_RESETVALUE 0x00000000UL /**< Default value for CAN_MESSAGEDATA */ 290 #define _CAN_MESSAGEDATA_MASK 0xFFFFFFFFUL /**< Mask for CAN_MESSAGEDATA */ 291 #define _CAN_MESSAGEDATA_VALID_SHIFT 0 /**< Shift value for CAN_VALID */ 292 #define _CAN_MESSAGEDATA_VALID_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_VALID */ 293 #define _CAN_MESSAGEDATA_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MESSAGEDATA */ 294 #define CAN_MESSAGEDATA_VALID_DEFAULT (_CAN_MESSAGEDATA_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGEDATA */ 295 296 /* Bit fields for CAN MESSAGESTATE */ 297 #define _CAN_MESSAGESTATE_RESETVALUE 0x00000000UL /**< Default value for CAN_MESSAGESTATE */ 298 #define _CAN_MESSAGESTATE_MASK 0xFFFFFFFFUL /**< Mask for CAN_MESSAGESTATE */ 299 #define _CAN_MESSAGESTATE_VALID_SHIFT 0 /**< Shift value for CAN_VALID */ 300 #define _CAN_MESSAGESTATE_VALID_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_VALID */ 301 #define _CAN_MESSAGESTATE_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MESSAGESTATE */ 302 #define CAN_MESSAGESTATE_VALID_DEFAULT (_CAN_MESSAGESTATE_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGESTATE */ 303 304 /* Bit fields for CAN CONFIG */ 305 #define _CAN_CONFIG_RESETVALUE 0x00000000UL /**< Default value for CAN_CONFIG */ 306 #define _CAN_CONFIG_MASK 0x00008000UL /**< Mask for CAN_CONFIG */ 307 #define CAN_CONFIG_DBGHALT (0x1UL << 15) /**< Debug Halt */ 308 #define _CAN_CONFIG_DBGHALT_SHIFT 15 /**< Shift value for CAN_DBGHALT */ 309 #define _CAN_CONFIG_DBGHALT_MASK 0x8000UL /**< Bit mask for CAN_DBGHALT */ 310 #define _CAN_CONFIG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CONFIG */ 311 #define _CAN_CONFIG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for CAN_CONFIG */ 312 #define _CAN_CONFIG_DBGHALT_STALL 0x00000001UL /**< Mode STALL for CAN_CONFIG */ 313 #define CAN_CONFIG_DBGHALT_DEFAULT (_CAN_CONFIG_DBGHALT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_CONFIG */ 314 #define CAN_CONFIG_DBGHALT_NORMAL (_CAN_CONFIG_DBGHALT_NORMAL << 15) /**< Shifted mode NORMAL for CAN_CONFIG */ 315 #define CAN_CONFIG_DBGHALT_STALL (_CAN_CONFIG_DBGHALT_STALL << 15) /**< Shifted mode STALL for CAN_CONFIG */ 316 317 /* Bit fields for CAN IF0IF */ 318 #define _CAN_IF0IF_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IF */ 319 #define _CAN_IF0IF_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IF */ 320 #define _CAN_IF0IF_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */ 321 #define _CAN_IF0IF_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */ 322 #define _CAN_IF0IF_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IF */ 323 #define CAN_IF0IF_MESSAGE_DEFAULT (_CAN_IF0IF_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IF */ 324 325 /* Bit fields for CAN IF0IFS */ 326 #define _CAN_IF0IFS_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IFS */ 327 #define _CAN_IF0IFS_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IFS */ 328 #define _CAN_IF0IFS_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */ 329 #define _CAN_IF0IFS_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */ 330 #define _CAN_IF0IFS_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IFS */ 331 #define CAN_IF0IFS_MESSAGE_DEFAULT (_CAN_IF0IFS_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFS */ 332 333 /* Bit fields for CAN IF0IFC */ 334 #define _CAN_IF0IFC_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IFC */ 335 #define _CAN_IF0IFC_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IFC */ 336 #define _CAN_IF0IFC_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */ 337 #define _CAN_IF0IFC_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */ 338 #define _CAN_IF0IFC_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IFC */ 339 #define CAN_IF0IFC_MESSAGE_DEFAULT (_CAN_IF0IFC_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFC */ 340 341 /* Bit fields for CAN IF0IEN */ 342 #define _CAN_IF0IEN_RESETVALUE 0xFFFFFFFFUL /**< Default value for CAN_IF0IEN */ 343 #define _CAN_IF0IEN_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IEN */ 344 #define _CAN_IF0IEN_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */ 345 #define _CAN_IF0IEN_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */ 346 #define _CAN_IF0IEN_MESSAGE_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for CAN_IF0IEN */ 347 #define CAN_IF0IEN_MESSAGE_DEFAULT (_CAN_IF0IEN_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IEN */ 348 349 /* Bit fields for CAN IF1IF */ 350 #define _CAN_IF1IF_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IF */ 351 #define _CAN_IF1IF_MASK 0x00000001UL /**< Mask for CAN_IF1IF */ 352 #define CAN_IF1IF_STATUS (0x1UL << 0) /**< Status Interrupt Flag */ 353 #define _CAN_IF1IF_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */ 354 #define _CAN_IF1IF_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */ 355 #define _CAN_IF1IF_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IF */ 356 #define CAN_IF1IF_STATUS_DEFAULT (_CAN_IF1IF_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IF */ 357 358 /* Bit fields for CAN IF1IFS */ 359 #define _CAN_IF1IFS_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IFS */ 360 #define _CAN_IF1IFS_MASK 0x00000001UL /**< Mask for CAN_IF1IFS */ 361 #define CAN_IF1IFS_STATUS (0x1UL << 0) /**< Set STATUS Interrupt Flag */ 362 #define _CAN_IF1IFS_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */ 363 #define _CAN_IF1IFS_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */ 364 #define _CAN_IF1IFS_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IFS */ 365 #define CAN_IF1IFS_STATUS_DEFAULT (_CAN_IF1IFS_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFS */ 366 367 /* Bit fields for CAN IF1IFC */ 368 #define _CAN_IF1IFC_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IFC */ 369 #define _CAN_IF1IFC_MASK 0x00000001UL /**< Mask for CAN_IF1IFC */ 370 #define CAN_IF1IFC_STATUS (0x1UL << 0) /**< Clear STATUS Interrupt Flag */ 371 #define _CAN_IF1IFC_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */ 372 #define _CAN_IF1IFC_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */ 373 #define _CAN_IF1IFC_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IFC */ 374 #define CAN_IF1IFC_STATUS_DEFAULT (_CAN_IF1IFC_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFC */ 375 376 /* Bit fields for CAN IF1IEN */ 377 #define _CAN_IF1IEN_RESETVALUE 0x00000001UL /**< Default value for CAN_IF1IEN */ 378 #define _CAN_IF1IEN_MASK 0x00000001UL /**< Mask for CAN_IF1IEN */ 379 #define CAN_IF1IEN_STATUS (0x1UL << 0) /**< STATUS Interrupt Enable */ 380 #define _CAN_IF1IEN_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */ 381 #define _CAN_IF1IEN_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */ 382 #define _CAN_IF1IEN_STATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_IF1IEN */ 383 #define CAN_IF1IEN_STATUS_DEFAULT (_CAN_IF1IEN_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IEN */ 384 385 /* Bit fields for CAN ROUTE */ 386 #define _CAN_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CAN_ROUTE */ 387 #define _CAN_ROUTE_MASK 0x0000071DUL /**< Mask for CAN_ROUTE */ 388 #define CAN_ROUTE_TXPEN (0x1UL << 0) /**< TX Pin Enable */ 389 #define _CAN_ROUTE_TXPEN_SHIFT 0 /**< Shift value for CAN_TXPEN */ 390 #define _CAN_ROUTE_TXPEN_MASK 0x1UL /**< Bit mask for CAN_TXPEN */ 391 #define _CAN_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */ 392 #define CAN_ROUTE_TXPEN_DEFAULT (_CAN_ROUTE_TXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_ROUTE */ 393 #define _CAN_ROUTE_RXLOC_SHIFT 2 /**< Shift value for CAN_RXLOC */ 394 #define _CAN_ROUTE_RXLOC_MASK 0x1CUL /**< Bit mask for CAN_RXLOC */ 395 #define _CAN_ROUTE_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for CAN_ROUTE */ 396 #define _CAN_ROUTE_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */ 397 #define _CAN_ROUTE_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for CAN_ROUTE */ 398 #define _CAN_ROUTE_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for CAN_ROUTE */ 399 #define _CAN_ROUTE_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for CAN_ROUTE */ 400 #define _CAN_ROUTE_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for CAN_ROUTE */ 401 #define _CAN_ROUTE_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for CAN_ROUTE */ 402 #define _CAN_ROUTE_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for CAN_ROUTE */ 403 #define CAN_ROUTE_RXLOC_LOC0 (_CAN_ROUTE_RXLOC_LOC0 << 2) /**< Shifted mode LOC0 for CAN_ROUTE */ 404 #define CAN_ROUTE_RXLOC_DEFAULT (_CAN_ROUTE_RXLOC_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_ROUTE */ 405 #define CAN_ROUTE_RXLOC_LOC1 (_CAN_ROUTE_RXLOC_LOC1 << 2) /**< Shifted mode LOC1 for CAN_ROUTE */ 406 #define CAN_ROUTE_RXLOC_LOC2 (_CAN_ROUTE_RXLOC_LOC2 << 2) /**< Shifted mode LOC2 for CAN_ROUTE */ 407 #define CAN_ROUTE_RXLOC_LOC3 (_CAN_ROUTE_RXLOC_LOC3 << 2) /**< Shifted mode LOC3 for CAN_ROUTE */ 408 #define CAN_ROUTE_RXLOC_LOC4 (_CAN_ROUTE_RXLOC_LOC4 << 2) /**< Shifted mode LOC4 for CAN_ROUTE */ 409 #define CAN_ROUTE_RXLOC_LOC5 (_CAN_ROUTE_RXLOC_LOC5 << 2) /**< Shifted mode LOC5 for CAN_ROUTE */ 410 #define CAN_ROUTE_RXLOC_LOC6 (_CAN_ROUTE_RXLOC_LOC6 << 2) /**< Shifted mode LOC6 for CAN_ROUTE */ 411 #define _CAN_ROUTE_TXLOC_SHIFT 8 /**< Shift value for CAN_TXLOC */ 412 #define _CAN_ROUTE_TXLOC_MASK 0x700UL /**< Bit mask for CAN_TXLOC */ 413 #define _CAN_ROUTE_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for CAN_ROUTE */ 414 #define _CAN_ROUTE_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */ 415 #define _CAN_ROUTE_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for CAN_ROUTE */ 416 #define _CAN_ROUTE_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for CAN_ROUTE */ 417 #define _CAN_ROUTE_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for CAN_ROUTE */ 418 #define _CAN_ROUTE_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for CAN_ROUTE */ 419 #define _CAN_ROUTE_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for CAN_ROUTE */ 420 #define _CAN_ROUTE_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for CAN_ROUTE */ 421 #define CAN_ROUTE_TXLOC_LOC0 (_CAN_ROUTE_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for CAN_ROUTE */ 422 #define CAN_ROUTE_TXLOC_DEFAULT (_CAN_ROUTE_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_ROUTE */ 423 #define CAN_ROUTE_TXLOC_LOC1 (_CAN_ROUTE_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for CAN_ROUTE */ 424 #define CAN_ROUTE_TXLOC_LOC2 (_CAN_ROUTE_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for CAN_ROUTE */ 425 #define CAN_ROUTE_TXLOC_LOC3 (_CAN_ROUTE_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for CAN_ROUTE */ 426 #define CAN_ROUTE_TXLOC_LOC4 (_CAN_ROUTE_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for CAN_ROUTE */ 427 #define CAN_ROUTE_TXLOC_LOC5 (_CAN_ROUTE_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for CAN_ROUTE */ 428 #define CAN_ROUTE_TXLOC_LOC6 (_CAN_ROUTE_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for CAN_ROUTE */ 429 430 /* Bit fields for CAN MIR_CMDMASK */ 431 #define _CAN_MIR_CMDMASK_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_CMDMASK */ 432 #define _CAN_MIR_CMDMASK_MASK 0x000000FFUL /**< Mask for CAN_MIR_CMDMASK */ 433 #define CAN_MIR_CMDMASK_DATAB (0x1UL << 0) /**< CC Channel Mode */ 434 #define _CAN_MIR_CMDMASK_DATAB_SHIFT 0 /**< Shift value for CAN_DATAB */ 435 #define _CAN_MIR_CMDMASK_DATAB_MASK 0x1UL /**< Bit mask for CAN_DATAB */ 436 #define _CAN_MIR_CMDMASK_DATAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ 437 #define CAN_MIR_CMDMASK_DATAB_DEFAULT (_CAN_MIR_CMDMASK_DATAB_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ 438 #define CAN_MIR_CMDMASK_DATAA (0x1UL << 1) /**< Access Data Bytes 0-3 */ 439 #define _CAN_MIR_CMDMASK_DATAA_SHIFT 1 /**< Shift value for CAN_DATAA */ 440 #define _CAN_MIR_CMDMASK_DATAA_MASK 0x2UL /**< Bit mask for CAN_DATAA */ 441 #define _CAN_MIR_CMDMASK_DATAA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ 442 #define CAN_MIR_CMDMASK_DATAA_DEFAULT (_CAN_MIR_CMDMASK_DATAA_DEFAULT << 1) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ 443 #define CAN_MIR_CMDMASK_TXRQSTNEWDAT (0x1UL << 2) /**< Transmission Request Bit/ New Data Bit */ 444 #define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_SHIFT 2 /**< Shift value for CAN_TXRQSTNEWDAT */ 445 #define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_MASK 0x4UL /**< Bit mask for CAN_TXRQSTNEWDAT */ 446 #define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ 447 #define CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT (_CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ 448 #define CAN_MIR_CMDMASK_CLRINTPND (0x1UL << 3) /**< Clear Interrupt Pending Bit */ 449 #define _CAN_MIR_CMDMASK_CLRINTPND_SHIFT 3 /**< Shift value for CAN_CLRINTPND */ 450 #define _CAN_MIR_CMDMASK_CLRINTPND_MASK 0x8UL /**< Bit mask for CAN_CLRINTPND */ 451 #define _CAN_MIR_CMDMASK_CLRINTPND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ 452 #define CAN_MIR_CMDMASK_CLRINTPND_DEFAULT (_CAN_MIR_CMDMASK_CLRINTPND_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ 453 #define CAN_MIR_CMDMASK_CONTROL (0x1UL << 4) /**< Access Control Bits */ 454 #define _CAN_MIR_CMDMASK_CONTROL_SHIFT 4 /**< Shift value for CAN_CONTROL */ 455 #define _CAN_MIR_CMDMASK_CONTROL_MASK 0x10UL /**< Bit mask for CAN_CONTROL */ 456 #define _CAN_MIR_CMDMASK_CONTROL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ 457 #define CAN_MIR_CMDMASK_CONTROL_DEFAULT (_CAN_MIR_CMDMASK_CONTROL_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ 458 #define CAN_MIR_CMDMASK_ARBACC (0x1UL << 5) /**< Access Arbitration Bits */ 459 #define _CAN_MIR_CMDMASK_ARBACC_SHIFT 5 /**< Shift value for CAN_ARBACC */ 460 #define _CAN_MIR_CMDMASK_ARBACC_MASK 0x20UL /**< Bit mask for CAN_ARBACC */ 461 #define _CAN_MIR_CMDMASK_ARBACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ 462 #define CAN_MIR_CMDMASK_ARBACC_DEFAULT (_CAN_MIR_CMDMASK_ARBACC_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ 463 #define CAN_MIR_CMDMASK_MASKACC (0x1UL << 6) /**< Access Mask Bits */ 464 #define _CAN_MIR_CMDMASK_MASKACC_SHIFT 6 /**< Shift value for CAN_MASKACC */ 465 #define _CAN_MIR_CMDMASK_MASKACC_MASK 0x40UL /**< Bit mask for CAN_MASKACC */ 466 #define _CAN_MIR_CMDMASK_MASKACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ 467 #define CAN_MIR_CMDMASK_MASKACC_DEFAULT (_CAN_MIR_CMDMASK_MASKACC_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ 468 #define CAN_MIR_CMDMASK_WRRD (0x1UL << 7) /**< Write/Read RAM */ 469 #define _CAN_MIR_CMDMASK_WRRD_SHIFT 7 /**< Shift value for CAN_WRRD */ 470 #define _CAN_MIR_CMDMASK_WRRD_MASK 0x80UL /**< Bit mask for CAN_WRRD */ 471 #define _CAN_MIR_CMDMASK_WRRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ 472 #define _CAN_MIR_CMDMASK_WRRD_READ 0x00000000UL /**< Mode READ for CAN_MIR_CMDMASK */ 473 #define _CAN_MIR_CMDMASK_WRRD_WRITE 0x00000001UL /**< Mode WRITE for CAN_MIR_CMDMASK */ 474 #define CAN_MIR_CMDMASK_WRRD_DEFAULT (_CAN_MIR_CMDMASK_WRRD_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ 475 #define CAN_MIR_CMDMASK_WRRD_READ (_CAN_MIR_CMDMASK_WRRD_READ << 7) /**< Shifted mode READ for CAN_MIR_CMDMASK */ 476 #define CAN_MIR_CMDMASK_WRRD_WRITE (_CAN_MIR_CMDMASK_WRRD_WRITE << 7) /**< Shifted mode WRITE for CAN_MIR_CMDMASK */ 477 478 /* Bit fields for CAN MIR_MASK */ 479 #define _CAN_MIR_MASK_RESETVALUE 0xDFFFFFFFUL /**< Default value for CAN_MIR_MASK */ 480 #define _CAN_MIR_MASK_MASK 0xDFFFFFFFUL /**< Mask for CAN_MIR_MASK */ 481 #define _CAN_MIR_MASK_MASK_SHIFT 0 /**< Shift value for CAN_MASK */ 482 #define _CAN_MIR_MASK_MASK_MASK 0x1FFFFFFFUL /**< Bit mask for CAN_MASK */ 483 #define _CAN_MIR_MASK_MASK_DEFAULT 0x1FFFFFFFUL /**< Mode DEFAULT for CAN_MIR_MASK */ 484 #define CAN_MIR_MASK_MASK_DEFAULT (_CAN_MIR_MASK_MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_MASK */ 485 #define CAN_MIR_MASK_MDIR (0x1UL << 30) /**< Mask Message Direction */ 486 #define _CAN_MIR_MASK_MDIR_SHIFT 30 /**< Shift value for CAN_MDIR */ 487 #define _CAN_MIR_MASK_MDIR_MASK 0x40000000UL /**< Bit mask for CAN_MDIR */ 488 #define _CAN_MIR_MASK_MDIR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_MASK */ 489 #define CAN_MIR_MASK_MDIR_DEFAULT (_CAN_MIR_MASK_MDIR_DEFAULT << 30) /**< Shifted mode DEFAULT for CAN_MIR_MASK */ 490 #define CAN_MIR_MASK_MXTD (0x1UL << 31) /**< Mask Extended Identifier */ 491 #define _CAN_MIR_MASK_MXTD_SHIFT 31 /**< Shift value for CAN_MXTD */ 492 #define _CAN_MIR_MASK_MXTD_MASK 0x80000000UL /**< Bit mask for CAN_MXTD */ 493 #define _CAN_MIR_MASK_MXTD_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_MASK */ 494 #define CAN_MIR_MASK_MXTD_DEFAULT (_CAN_MIR_MASK_MXTD_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_MASK */ 495 496 /* Bit fields for CAN MIR_ARB */ 497 #define _CAN_MIR_ARB_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_ARB */ 498 #define _CAN_MIR_ARB_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_ARB */ 499 #define _CAN_MIR_ARB_ID_SHIFT 0 /**< Shift value for CAN_ID */ 500 #define _CAN_MIR_ARB_ID_MASK 0x1FFFFFFFUL /**< Bit mask for CAN_ID */ 501 #define _CAN_MIR_ARB_ID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */ 502 #define CAN_MIR_ARB_ID_DEFAULT (_CAN_MIR_ARB_ID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_ARB */ 503 #define CAN_MIR_ARB_DIR (0x1UL << 29) /**< Message Direction */ 504 #define _CAN_MIR_ARB_DIR_SHIFT 29 /**< Shift value for CAN_DIR */ 505 #define _CAN_MIR_ARB_DIR_MASK 0x20000000UL /**< Bit mask for CAN_DIR */ 506 #define _CAN_MIR_ARB_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */ 507 #define _CAN_MIR_ARB_DIR_RX 0x00000000UL /**< Mode RX for CAN_MIR_ARB */ 508 #define _CAN_MIR_ARB_DIR_TX 0x00000001UL /**< Mode TX for CAN_MIR_ARB */ 509 #define CAN_MIR_ARB_DIR_DEFAULT (_CAN_MIR_ARB_DIR_DEFAULT << 29) /**< Shifted mode DEFAULT for CAN_MIR_ARB */ 510 #define CAN_MIR_ARB_DIR_RX (_CAN_MIR_ARB_DIR_RX << 29) /**< Shifted mode RX for CAN_MIR_ARB */ 511 #define CAN_MIR_ARB_DIR_TX (_CAN_MIR_ARB_DIR_TX << 29) /**< Shifted mode TX for CAN_MIR_ARB */ 512 #define CAN_MIR_ARB_XTD (0x1UL << 30) /**< Extended Identifier */ 513 #define _CAN_MIR_ARB_XTD_SHIFT 30 /**< Shift value for CAN_XTD */ 514 #define _CAN_MIR_ARB_XTD_MASK 0x40000000UL /**< Bit mask for CAN_XTD */ 515 #define _CAN_MIR_ARB_XTD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */ 516 #define _CAN_MIR_ARB_XTD_STD 0x00000000UL /**< Mode STD for CAN_MIR_ARB */ 517 #define _CAN_MIR_ARB_XTD_EXT 0x00000001UL /**< Mode EXT for CAN_MIR_ARB */ 518 #define CAN_MIR_ARB_XTD_DEFAULT (_CAN_MIR_ARB_XTD_DEFAULT << 30) /**< Shifted mode DEFAULT for CAN_MIR_ARB */ 519 #define CAN_MIR_ARB_XTD_STD (_CAN_MIR_ARB_XTD_STD << 30) /**< Shifted mode STD for CAN_MIR_ARB */ 520 #define CAN_MIR_ARB_XTD_EXT (_CAN_MIR_ARB_XTD_EXT << 30) /**< Shifted mode EXT for CAN_MIR_ARB */ 521 #define CAN_MIR_ARB_MSGVAL (0x1UL << 31) /**< Message Valid */ 522 #define _CAN_MIR_ARB_MSGVAL_SHIFT 31 /**< Shift value for CAN_MSGVAL */ 523 #define _CAN_MIR_ARB_MSGVAL_MASK 0x80000000UL /**< Bit mask for CAN_MSGVAL */ 524 #define _CAN_MIR_ARB_MSGVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */ 525 #define CAN_MIR_ARB_MSGVAL_DEFAULT (_CAN_MIR_ARB_MSGVAL_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_ARB */ 526 527 /* Bit fields for CAN MIR_CTRL */ 528 #define _CAN_MIR_CTRL_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_CTRL */ 529 #define _CAN_MIR_CTRL_MASK 0x0000FF8FUL /**< Mask for CAN_MIR_CTRL */ 530 #define _CAN_MIR_CTRL_DLC_SHIFT 0 /**< Shift value for CAN_DLC */ 531 #define _CAN_MIR_CTRL_DLC_MASK 0xFUL /**< Bit mask for CAN_DLC */ 532 #define _CAN_MIR_CTRL_DLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ 533 #define CAN_MIR_CTRL_DLC_DEFAULT (_CAN_MIR_CTRL_DLC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ 534 #define CAN_MIR_CTRL_EOB (0x1UL << 7) /**< End of Buffer */ 535 #define _CAN_MIR_CTRL_EOB_SHIFT 7 /**< Shift value for CAN_EOB */ 536 #define _CAN_MIR_CTRL_EOB_MASK 0x80UL /**< Bit mask for CAN_EOB */ 537 #define _CAN_MIR_CTRL_EOB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ 538 #define CAN_MIR_CTRL_EOB_DEFAULT (_CAN_MIR_CTRL_EOB_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ 539 #define CAN_MIR_CTRL_TXRQST (0x1UL << 8) /**< Transmit Request */ 540 #define _CAN_MIR_CTRL_TXRQST_SHIFT 8 /**< Shift value for CAN_TXRQST */ 541 #define _CAN_MIR_CTRL_TXRQST_MASK 0x100UL /**< Bit mask for CAN_TXRQST */ 542 #define _CAN_MIR_CTRL_TXRQST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ 543 #define CAN_MIR_CTRL_TXRQST_DEFAULT (_CAN_MIR_CTRL_TXRQST_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ 544 #define CAN_MIR_CTRL_RMTEN (0x1UL << 9) /**< Remote Enable */ 545 #define _CAN_MIR_CTRL_RMTEN_SHIFT 9 /**< Shift value for CAN_RMTEN */ 546 #define _CAN_MIR_CTRL_RMTEN_MASK 0x200UL /**< Bit mask for CAN_RMTEN */ 547 #define _CAN_MIR_CTRL_RMTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ 548 #define CAN_MIR_CTRL_RMTEN_DEFAULT (_CAN_MIR_CTRL_RMTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ 549 #define CAN_MIR_CTRL_RXIE (0x1UL << 10) /**< Receive Interrupt Enable */ 550 #define _CAN_MIR_CTRL_RXIE_SHIFT 10 /**< Shift value for CAN_RXIE */ 551 #define _CAN_MIR_CTRL_RXIE_MASK 0x400UL /**< Bit mask for CAN_RXIE */ 552 #define _CAN_MIR_CTRL_RXIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ 553 #define CAN_MIR_CTRL_RXIE_DEFAULT (_CAN_MIR_CTRL_RXIE_DEFAULT << 10) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ 554 #define CAN_MIR_CTRL_TXIE (0x1UL << 11) /**< Transmit Interrupt Enable */ 555 #define _CAN_MIR_CTRL_TXIE_SHIFT 11 /**< Shift value for CAN_TXIE */ 556 #define _CAN_MIR_CTRL_TXIE_MASK 0x800UL /**< Bit mask for CAN_TXIE */ 557 #define _CAN_MIR_CTRL_TXIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ 558 #define CAN_MIR_CTRL_TXIE_DEFAULT (_CAN_MIR_CTRL_TXIE_DEFAULT << 11) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ 559 #define CAN_MIR_CTRL_UMASK (0x1UL << 12) /**< Use Acceptance Mask */ 560 #define _CAN_MIR_CTRL_UMASK_SHIFT 12 /**< Shift value for CAN_UMASK */ 561 #define _CAN_MIR_CTRL_UMASK_MASK 0x1000UL /**< Bit mask for CAN_UMASK */ 562 #define _CAN_MIR_CTRL_UMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ 563 #define CAN_MIR_CTRL_UMASK_DEFAULT (_CAN_MIR_CTRL_UMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ 564 #define CAN_MIR_CTRL_INTPND (0x1UL << 13) /**< Interrupt Pending */ 565 #define _CAN_MIR_CTRL_INTPND_SHIFT 13 /**< Shift value for CAN_INTPND */ 566 #define _CAN_MIR_CTRL_INTPND_MASK 0x2000UL /**< Bit mask for CAN_INTPND */ 567 #define _CAN_MIR_CTRL_INTPND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ 568 #define CAN_MIR_CTRL_INTPND_DEFAULT (_CAN_MIR_CTRL_INTPND_DEFAULT << 13) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ 569 #define CAN_MIR_CTRL_MESSAGEOF (0x1UL << 14) /**< Message Lost (only Valid for Message Objects With Direction = Receive) */ 570 #define _CAN_MIR_CTRL_MESSAGEOF_SHIFT 14 /**< Shift value for CAN_MESSAGEOF */ 571 #define _CAN_MIR_CTRL_MESSAGEOF_MASK 0x4000UL /**< Bit mask for CAN_MESSAGEOF */ 572 #define _CAN_MIR_CTRL_MESSAGEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ 573 #define CAN_MIR_CTRL_MESSAGEOF_DEFAULT (_CAN_MIR_CTRL_MESSAGEOF_DEFAULT << 14) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ 574 #define CAN_MIR_CTRL_DATAVALID (0x1UL << 15) /**< New Data */ 575 #define _CAN_MIR_CTRL_DATAVALID_SHIFT 15 /**< Shift value for CAN_DATAVALID */ 576 #define _CAN_MIR_CTRL_DATAVALID_MASK 0x8000UL /**< Bit mask for CAN_DATAVALID */ 577 #define _CAN_MIR_CTRL_DATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ 578 #define CAN_MIR_CTRL_DATAVALID_DEFAULT (_CAN_MIR_CTRL_DATAVALID_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ 579 580 /* Bit fields for CAN MIR_DATAL */ 581 #define _CAN_MIR_DATAL_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_DATAL */ 582 #define _CAN_MIR_DATAL_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_DATAL */ 583 #define _CAN_MIR_DATAL_DATA0_SHIFT 0 /**< Shift value for CAN_DATA0 */ 584 #define _CAN_MIR_DATAL_DATA0_MASK 0xFFUL /**< Bit mask for CAN_DATA0 */ 585 #define _CAN_MIR_DATAL_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */ 586 #define CAN_MIR_DATAL_DATA0_DEFAULT (_CAN_MIR_DATAL_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */ 587 #define _CAN_MIR_DATAL_DATA1_SHIFT 8 /**< Shift value for CAN_DATA1 */ 588 #define _CAN_MIR_DATAL_DATA1_MASK 0xFF00UL /**< Bit mask for CAN_DATA1 */ 589 #define _CAN_MIR_DATAL_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */ 590 #define CAN_MIR_DATAL_DATA1_DEFAULT (_CAN_MIR_DATAL_DATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */ 591 #define _CAN_MIR_DATAL_DATA2_SHIFT 16 /**< Shift value for CAN_DATA2 */ 592 #define _CAN_MIR_DATAL_DATA2_MASK 0xFF0000UL /**< Bit mask for CAN_DATA2 */ 593 #define _CAN_MIR_DATAL_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */ 594 #define CAN_MIR_DATAL_DATA2_DEFAULT (_CAN_MIR_DATAL_DATA2_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */ 595 #define _CAN_MIR_DATAL_DATA3_SHIFT 24 /**< Shift value for CAN_DATA3 */ 596 #define _CAN_MIR_DATAL_DATA3_MASK 0xFF000000UL /**< Bit mask for CAN_DATA3 */ 597 #define _CAN_MIR_DATAL_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */ 598 #define CAN_MIR_DATAL_DATA3_DEFAULT (_CAN_MIR_DATAL_DATA3_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */ 599 600 /* Bit fields for CAN MIR_DATAH */ 601 #define _CAN_MIR_DATAH_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_DATAH */ 602 #define _CAN_MIR_DATAH_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_DATAH */ 603 #define _CAN_MIR_DATAH_DATA4_SHIFT 0 /**< Shift value for CAN_DATA4 */ 604 #define _CAN_MIR_DATAH_DATA4_MASK 0xFFUL /**< Bit mask for CAN_DATA4 */ 605 #define _CAN_MIR_DATAH_DATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */ 606 #define CAN_MIR_DATAH_DATA4_DEFAULT (_CAN_MIR_DATAH_DATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */ 607 #define _CAN_MIR_DATAH_DATA5_SHIFT 8 /**< Shift value for CAN_DATA5 */ 608 #define _CAN_MIR_DATAH_DATA5_MASK 0xFF00UL /**< Bit mask for CAN_DATA5 */ 609 #define _CAN_MIR_DATAH_DATA5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */ 610 #define CAN_MIR_DATAH_DATA5_DEFAULT (_CAN_MIR_DATAH_DATA5_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */ 611 #define _CAN_MIR_DATAH_DATA6_SHIFT 16 /**< Shift value for CAN_DATA6 */ 612 #define _CAN_MIR_DATAH_DATA6_MASK 0xFF0000UL /**< Bit mask for CAN_DATA6 */ 613 #define _CAN_MIR_DATAH_DATA6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */ 614 #define CAN_MIR_DATAH_DATA6_DEFAULT (_CAN_MIR_DATAH_DATA6_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */ 615 #define _CAN_MIR_DATAH_DATA7_SHIFT 24 /**< Shift value for CAN_DATA7 */ 616 #define _CAN_MIR_DATAH_DATA7_MASK 0xFF000000UL /**< Bit mask for CAN_DATA7 */ 617 #define _CAN_MIR_DATAH_DATA7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */ 618 #define CAN_MIR_DATAH_DATA7_DEFAULT (_CAN_MIR_DATAH_DATA7_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */ 619 620 /* Bit fields for CAN MIR_CMDREQ */ 621 #define _CAN_MIR_CMDREQ_RESETVALUE 0x00000001UL /**< Default value for CAN_MIR_CMDREQ */ 622 #define _CAN_MIR_CMDREQ_MASK 0x0000803FUL /**< Mask for CAN_MIR_CMDREQ */ 623 #define _CAN_MIR_CMDREQ_MSGNUM_SHIFT 0 /**< Shift value for CAN_MSGNUM */ 624 #define _CAN_MIR_CMDREQ_MSGNUM_MASK 0x3FUL /**< Bit mask for CAN_MSGNUM */ 625 #define _CAN_MIR_CMDREQ_MSGNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_CMDREQ */ 626 #define CAN_MIR_CMDREQ_MSGNUM_DEFAULT (_CAN_MIR_CMDREQ_MSGNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */ 627 #define CAN_MIR_CMDREQ_BUSY (0x1UL << 15) /**< Busy Flag */ 628 #define _CAN_MIR_CMDREQ_BUSY_SHIFT 15 /**< Shift value for CAN_BUSY */ 629 #define _CAN_MIR_CMDREQ_BUSY_MASK 0x8000UL /**< Bit mask for CAN_BUSY */ 630 #define _CAN_MIR_CMDREQ_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDREQ */ 631 #define _CAN_MIR_CMDREQ_BUSY_FALSE 0x00000000UL /**< Mode FALSE for CAN_MIR_CMDREQ */ 632 #define _CAN_MIR_CMDREQ_BUSY_TRUE 0x00000001UL /**< Mode TRUE for CAN_MIR_CMDREQ */ 633 #define CAN_MIR_CMDREQ_BUSY_DEFAULT (_CAN_MIR_CMDREQ_BUSY_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */ 634 #define CAN_MIR_CMDREQ_BUSY_FALSE (_CAN_MIR_CMDREQ_BUSY_FALSE << 15) /**< Shifted mode FALSE for CAN_MIR_CMDREQ */ 635 #define CAN_MIR_CMDREQ_BUSY_TRUE (_CAN_MIR_CMDREQ_BUSY_TRUE << 15) /**< Shifted mode TRUE for CAN_MIR_CMDREQ */ 636 637 /** @} */ 638 /** @} End of group EFM32GG12B_CAN */ 639 /** @} End of group Parts */ 640
