1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG11B_DEVINFO register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG11B_DEVINFO Device Information and Calibration 43 * @{ 44 ******************************************************************************/ 45 46 /** DEVINFO Register Declaration */ 47 typedef struct { 48 __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */ 49 __IM uint32_t MODULEINFO; /**< Module trace information */ 50 __IM uint32_t MODXOCAL; /**< Module Crystal Oscillator Calibration */ 51 uint32_t RESERVED0[5U]; /**< Reserved for future use **/ 52 __IM uint32_t EXTINFO; /**< External Component description */ 53 uint32_t RESERVED1[1U]; /**< Reserved for future use **/ 54 __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */ 55 __IM uint32_t EUI48H; /**< OUI */ 56 __IM uint32_t CUSTOMINFO; /**< Custom information */ 57 __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */ 58 uint32_t RESERVED2[2U]; /**< Reserved for future use **/ 59 __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */ 60 __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */ 61 __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */ 62 __IM uint32_t PART; /**< Part description */ 63 __IM uint32_t DEVINFOREV; /**< Device information page revision */ 64 __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */ 65 uint32_t RESERVED3[2U]; /**< Reserved for future use **/ 66 __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */ 67 __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */ 68 __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */ 69 __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */ 70 __IM uint32_t ADC1CAL0; /**< ADC1 calibration register 0 */ 71 __IM uint32_t ADC1CAL1; /**< ADC1 calibration register 1 */ 72 __IM uint32_t ADC1CAL2; /**< ADC1 calibration register 2 */ 73 __IM uint32_t ADC1CAL3; /**< ADC1 calibration register 3 */ 74 __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */ 75 uint32_t RESERVED4[2U]; /**< Reserved for future use **/ 76 __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */ 77 uint32_t RESERVED5[2U]; /**< Reserved for future use **/ 78 __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */ 79 __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */ 80 __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */ 81 uint32_t RESERVED6[1U]; /**< Reserved for future use **/ 82 __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */ 83 __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */ 84 __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */ 85 __IM uint32_t HFRCOCAL13; /**< HFRCO Calibration Register (48 MHz) */ 86 __IM uint32_t HFRCOCAL14; /**< HFRCO Calibration Register (56 MHz) */ 87 __IM uint32_t HFRCOCAL15; /**< HFRCO Calibration Register (64 MHz) */ 88 __IM uint32_t HFRCOCAL16; /**< HFRCO Calibration Register (72 MHz) */ 89 uint32_t RESERVED7[7U]; /**< Reserved for future use **/ 90 __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */ 91 uint32_t RESERVED8[2U]; /**< Reserved for future use **/ 92 __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */ 93 uint32_t RESERVED9[2U]; /**< Reserved for future use **/ 94 __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */ 95 __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */ 96 __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */ 97 uint32_t RESERVED10[1U]; /**< Reserved for future use **/ 98 __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */ 99 __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */ 100 __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */ 101 __IM uint32_t AUXHFRCOCAL13; /**< AUXHFRCO Calibration Register (48 MHz) */ 102 __IM uint32_t AUXHFRCOCAL14; /**< AUXHFRCO Calibration Register (50 MHz) */ 103 uint32_t RESERVED11[9U]; /**< Reserved for future use **/ 104 __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */ 105 __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */ 106 __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */ 107 uint32_t RESERVED12[3U]; /**< Reserved for future use **/ 108 __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */ 109 __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */ 110 uint32_t RESERVED13[2U]; /**< Reserved for future use **/ 111 __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */ 112 __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */ 113 __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */ 114 __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */ 115 __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */ 116 __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */ 117 __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */ 118 __IM uint32_t VDAC0MAINCAL; /**< VDAC0 Cals for Main Path */ 119 __IM uint32_t VDAC0ALTCAL; /**< VDAC0 Cals for Alternate Path */ 120 __IM uint32_t VDAC0CH1CAL; /**< VDAC0 CH1 Error Cal */ 121 __IM uint32_t OPA0CAL0; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ 122 __IM uint32_t OPA0CAL1; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ 123 __IM uint32_t OPA0CAL2; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ 124 __IM uint32_t OPA0CAL3; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ 125 __IM uint32_t OPA0CAL4; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ 126 __IM uint32_t OPA0CAL5; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ 127 __IM uint32_t OPA0CAL6; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ 128 __IM uint32_t OPA0CAL7; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ 129 __IM uint32_t OPA1CAL0; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ 130 __IM uint32_t OPA1CAL1; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ 131 __IM uint32_t OPA1CAL2; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ 132 __IM uint32_t OPA1CAL3; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ 133 __IM uint32_t OPA1CAL4; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ 134 __IM uint32_t OPA1CAL5; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ 135 __IM uint32_t OPA1CAL6; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ 136 __IM uint32_t OPA1CAL7; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ 137 __IM uint32_t OPA2CAL0; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ 138 __IM uint32_t OPA2CAL1; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ 139 __IM uint32_t OPA2CAL2; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ 140 __IM uint32_t OPA2CAL3; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ 141 __IM uint32_t OPA2CAL4; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ 142 __IM uint32_t OPA2CAL5; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ 143 __IM uint32_t OPA2CAL6; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ 144 __IM uint32_t OPA2CAL7; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ 145 __IM uint32_t OPA3CAL0; /**< OPA3 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ 146 __IM uint32_t OPA3CAL1; /**< OPA3 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ 147 __IM uint32_t OPA3CAL2; /**< OPA3 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ 148 __IM uint32_t OPA3CAL3; /**< OPA3 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ 149 __IM uint32_t OPA3CAL4; /**< OPA3 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ 150 __IM uint32_t OPA3CAL5; /**< OPA3 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ 151 __IM uint32_t OPA3CAL6; /**< OPA3 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ 152 __IM uint32_t OPA3CAL7; /**< OPA3 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ 153 __IM uint32_t CSENGAINCAL; /**< Cap Sense Gain Adjustment */ 154 uint32_t RESERVED14[22U]; /**< Reserved for future use **/ 155 __IM uint32_t USHFRCOCAL7; /**< USHFRCO Calibration Register (16 MHz) */ 156 uint32_t RESERVED15[3U]; /**< Reserved for future use **/ 157 __IM uint32_t USHFRCOCAL11; /**< USHFRCO Calibration Register (32 MHz) */ 158 uint32_t RESERVED16[1U]; /**< Reserved for future use **/ 159 __IM uint32_t USHFRCOCAL13; /**< USHFRCO Calibration Register (48 MHz) */ 160 __IM uint32_t USHFRCOCAL14; /**< USHFRCO Calibration Register (50 MHz) */ 161 uint32_t RESERVED17[9U]; /**< Reserved for future use **/ 162 __IM uint32_t CURRMON5V; /**< 5V Current monitor Transconductance */ 163 } DEVINFO_TypeDef; /** @} */ 164 165 /***************************************************************************//** 166 * @addtogroup EFM32GG11B_DEVINFO 167 * @{ 168 * @defgroup EFM32GG11B_DEVINFO_BitFields DEVINFO Bit Fields 169 * @{ 170 ******************************************************************************/ 171 172 /* Bit fields for DEVINFO CAL */ 173 #define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */ 174 #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */ 175 #define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */ 176 #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */ 177 #define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */ 178 179 /* Bit fields for DEVINFO MODULEINFO */ 180 #define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */ 181 #define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for HWREV */ 182 #define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for HWREV */ 183 #define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for ANTENNA */ 184 #define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for ANTENNA */ 185 #define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */ 186 #define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */ 187 #define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */ 188 #define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */ 189 #define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO */ 190 #define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */ 191 #define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for MODNUMBER */ 192 #define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for MODNUMBER */ 193 #define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for TYPE */ 194 #define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for TYPE */ 195 #define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */ 196 #define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */ 197 #define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */ 198 #define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */ 199 #define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for LFXO */ 200 #define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for LFXO */ 201 #define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */ 202 #define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */ 203 #define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ 204 #define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */ 205 #define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for EXPRESS */ 206 #define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for EXPRESS */ 207 #define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */ 208 #define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */ 209 #define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO */ 210 #define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ 211 #define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for LFXOCALVAL */ 212 #define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for LFXOCALVAL */ 213 #define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ 214 #define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ 215 #define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ 216 #define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO */ 217 #define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for HFXOCALVAL */ 218 #define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for HFXOCALVAL */ 219 #define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ 220 #define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ 221 #define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ 222 #define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO */ 223 #define _DEVINFO_MODULEINFO_RESERVED1_SHIFT 20 /**< Shift value for RESERVED1 */ 224 #define _DEVINFO_MODULEINFO_RESERVED1_MASK 0xFFF00000UL /**< Bit mask for RESERVED1 */ 225 226 /* Bit fields for DEVINFO MODXOCAL */ 227 #define _DEVINFO_MODXOCAL_MASK 0x0000FFFFUL /**< Mask for DEVINFO_MODXOCAL */ 228 #define _DEVINFO_MODXOCAL_HFXOCTUNE_SHIFT 0 /**< Shift value for HFXOCTUNE */ 229 #define _DEVINFO_MODXOCAL_HFXOCTUNE_MASK 0x1FFUL /**< Bit mask for HFXOCTUNE */ 230 #define _DEVINFO_MODXOCAL_LFXOTUNING_SHIFT 9 /**< Shift value for LFXOTUNING */ 231 #define _DEVINFO_MODXOCAL_LFXOTUNING_MASK 0xFE00UL /**< Bit mask for LFXOTUNING */ 232 233 /* Bit fields for DEVINFO EXTINFO */ 234 #define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ 235 #define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */ 236 #define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */ 237 #define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */ 238 #define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */ 239 #define _DEVINFO_EXTINFO_TYPE_WF200 0x00000003UL /**< Mode WF200 for DEVINFO_EXTINFO */ 240 #define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ 241 #define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */ 242 #define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */ 243 #define DEVINFO_EXTINFO_TYPE_WF200 (_DEVINFO_EXTINFO_TYPE_WF200 << 0) /**< Shifted mode WF200 for DEVINFO_EXTINFO */ 244 #define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ 245 #define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */ 246 #define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */ 247 #define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */ 248 #define _DEVINFO_EXTINFO_CONNECTION_SDIO 0x00000002UL /**< Mode SDIO for DEVINFO_EXTINFO */ 249 #define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ 250 #define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ 251 #define DEVINFO_EXTINFO_CONNECTION_SDIO (_DEVINFO_EXTINFO_CONNECTION_SDIO << 8) /**< Shifted mode SDIO for DEVINFO_EXTINFO */ 252 #define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ 253 #define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */ 254 #define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */ 255 #define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */ 256 #define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ 257 #define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */ 258 #define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */ 259 260 /* Bit fields for DEVINFO EUI48L */ 261 #define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ 262 #define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */ 263 #define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */ 264 #define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */ 265 #define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */ 266 267 /* Bit fields for DEVINFO EUI48H */ 268 #define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */ 269 #define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */ 270 #define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */ 271 272 /* Bit fields for DEVINFO CUSTOMINFO */ 273 #define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ 274 #define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */ 275 #define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */ 276 277 /* Bit fields for DEVINFO MEMINFO */ 278 #define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ 279 #define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */ 280 #define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */ 281 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */ 282 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */ 283 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */ 284 #define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */ 285 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */ 286 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */ 287 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */ 288 #define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */ 289 #define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */ 290 #define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */ 291 #define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */ 292 #define _DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_MEMINFO */ 293 #define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */ 294 #define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */ 295 #define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */ 296 #define DEVINFO_MEMINFO_PKGTYPE_BGA (_DEVINFO_MEMINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_MEMINFO */ 297 #define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */ 298 #define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */ 299 #define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */ 300 #define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */ 301 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */ 302 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */ 303 304 /* Bit fields for DEVINFO UNIQUEL */ 305 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */ 306 #define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */ 307 #define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */ 308 309 /* Bit fields for DEVINFO UNIQUEH */ 310 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */ 311 #define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */ 312 #define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */ 313 314 /* Bit fields for DEVINFO MSIZE */ 315 #define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */ 316 #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */ 317 #define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */ 318 #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */ 319 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */ 320 321 /* Bit fields for DEVINFO PART */ 322 #define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */ 323 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */ 324 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */ 325 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */ 326 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */ 327 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */ 328 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */ 329 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */ 330 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */ 331 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */ 332 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */ 333 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */ 334 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */ 335 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */ 336 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */ 337 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */ 338 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */ 339 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */ 340 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */ 341 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */ 342 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */ 343 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */ 344 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */ 345 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_PART */ 346 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_PART */ 347 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_PART */ 348 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */ 349 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */ 350 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */ 351 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P 0x0000002EUL /**< Mode EFR32ZG13P for DEVINFO_PART */ 352 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L 0x0000002FUL /**< Mode EFR32ZG13L for DEVINFO_PART */ 353 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S 0x00000030UL /**< Mode EFR32ZG13S for DEVINFO_PART */ 354 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */ 355 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */ 356 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */ 357 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_PART */ 358 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_PART */ 359 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_PART */ 360 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_PART */ 361 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_PART */ 362 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_PART */ 363 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P 0x0000003AUL /**< Mode EFR32ZG14P for DEVINFO_PART */ 364 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_PART */ 365 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_PART */ 366 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_PART */ 367 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */ 368 #define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */ 369 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */ 370 #define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */ 371 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */ 372 #define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */ 373 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */ 374 #define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */ 375 #define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */ 376 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */ 377 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */ 378 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */ 379 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */ 380 #define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */ 381 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */ 382 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */ 383 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */ 384 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */ 385 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_PART */ 386 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_PART */ 387 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B 0x0000006AUL /**< Mode EFM32GG12B for DEVINFO_PART */ 388 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */ 389 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */ 390 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */ 391 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */ 392 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */ 393 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */ 394 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */ 395 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */ 396 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */ 397 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */ 398 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */ 399 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */ 400 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */ 401 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */ 402 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */ 403 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */ 404 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */ 405 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */ 406 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */ 407 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */ 408 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */ 409 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_PART */ 410 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_PART */ 411 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_PART */ 412 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */ 413 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */ 414 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */ 415 #define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P << 16) /**< Shifted mode EFR32ZG13P for DEVINFO_PART */ 416 #define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L << 16) /**< Shifted mode EFR32ZG13L for DEVINFO_PART */ 417 #define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S << 16) /**< Shifted mode EFR32ZG13S for DEVINFO_PART */ 418 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */ 419 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */ 420 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */ 421 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_PART */ 422 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_PART */ 423 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_PART */ 424 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_PART */ 425 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_PART */ 426 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_PART */ 427 #define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P << 16) /**< Shifted mode EFR32ZG14P for DEVINFO_PART */ 428 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_PART */ 429 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_PART */ 430 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_PART */ 431 #define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */ 432 #define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */ 433 #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */ 434 #define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */ 435 #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */ 436 #define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */ 437 #define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */ 438 #define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */ 439 #define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */ 440 #define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */ 441 #define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */ 442 #define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */ 443 #define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */ 444 #define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */ 445 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */ 446 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */ 447 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */ 448 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */ 449 #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_PART */ 450 #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_PART */ 451 #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B << 16) /**< Shifted mode EFM32GG12B for DEVINFO_PART */ 452 #define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */ 453 #define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */ 454 #define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */ 455 #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */ 456 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */ 457 458 /* Bit fields for DEVINFO DEVINFOREV */ 459 #define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */ 460 #define _DEVINFO_DEVINFOREV_MINOR_SHIFT 0 /**< Shift value for MINOR */ 461 #define _DEVINFO_DEVINFOREV_MINOR_MASK 0x1FUL /**< Bit mask for MINOR */ 462 #define _DEVINFO_DEVINFOREV_MAJOR_SHIFT 5 /**< Shift value for MAJOR */ 463 #define _DEVINFO_DEVINFOREV_MAJOR_MASK 0xE0UL /**< Bit mask for MAJOR */ 464 465 /* Bit fields for DEVINFO EMUTEMP */ 466 #define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */ 467 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */ 468 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */ 469 470 /* Bit fields for DEVINFO ADC0CAL0 */ 471 #define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */ 472 #define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */ 473 #define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */ 474 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */ 475 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */ 476 #define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */ 477 #define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */ 478 #define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */ 479 #define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */ 480 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */ 481 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */ 482 #define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */ 483 #define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */ 484 485 /* Bit fields for DEVINFO ADC0CAL1 */ 486 #define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */ 487 #define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */ 488 #define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */ 489 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */ 490 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */ 491 #define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */ 492 #define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */ 493 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */ 494 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */ 495 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */ 496 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */ 497 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */ 498 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */ 499 500 /* Bit fields for DEVINFO ADC0CAL2 */ 501 #define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */ 502 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */ 503 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */ 504 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */ 505 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */ 506 507 /* Bit fields for DEVINFO ADC0CAL3 */ 508 #define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */ 509 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */ 510 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */ 511 512 /* Bit fields for DEVINFO ADC1CAL0 */ 513 #define _DEVINFO_ADC1CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC1CAL0 */ 514 #define _DEVINFO_ADC1CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */ 515 #define _DEVINFO_ADC1CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */ 516 #define _DEVINFO_ADC1CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */ 517 #define _DEVINFO_ADC1CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */ 518 #define _DEVINFO_ADC1CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */ 519 #define _DEVINFO_ADC1CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */ 520 #define _DEVINFO_ADC1CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */ 521 #define _DEVINFO_ADC1CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */ 522 #define _DEVINFO_ADC1CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */ 523 #define _DEVINFO_ADC1CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */ 524 #define _DEVINFO_ADC1CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */ 525 #define _DEVINFO_ADC1CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */ 526 527 /* Bit fields for DEVINFO ADC1CAL1 */ 528 #define _DEVINFO_ADC1CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC1CAL1 */ 529 #define _DEVINFO_ADC1CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */ 530 #define _DEVINFO_ADC1CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */ 531 #define _DEVINFO_ADC1CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */ 532 #define _DEVINFO_ADC1CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */ 533 #define _DEVINFO_ADC1CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */ 534 #define _DEVINFO_ADC1CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */ 535 #define _DEVINFO_ADC1CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */ 536 #define _DEVINFO_ADC1CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */ 537 #define _DEVINFO_ADC1CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */ 538 #define _DEVINFO_ADC1CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */ 539 #define _DEVINFO_ADC1CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */ 540 #define _DEVINFO_ADC1CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */ 541 542 /* Bit fields for DEVINFO ADC1CAL2 */ 543 #define _DEVINFO_ADC1CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC1CAL2 */ 544 #define _DEVINFO_ADC1CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */ 545 #define _DEVINFO_ADC1CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */ 546 #define _DEVINFO_ADC1CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */ 547 #define _DEVINFO_ADC1CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */ 548 549 /* Bit fields for DEVINFO ADC1CAL3 */ 550 #define _DEVINFO_ADC1CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC1CAL3 */ 551 #define _DEVINFO_ADC1CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */ 552 #define _DEVINFO_ADC1CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */ 553 554 /* Bit fields for DEVINFO HFRCOCAL0 */ 555 #define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */ 556 #define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ 557 #define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 558 #define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 559 #define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 560 #define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 561 #define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 562 #define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 563 #define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 564 #define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 565 #define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 566 #define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 567 #define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 568 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 569 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 570 #define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 571 #define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 572 573 /* Bit fields for DEVINFO HFRCOCAL3 */ 574 #define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */ 575 #define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ 576 #define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 577 #define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 578 #define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 579 #define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 580 #define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 581 #define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 582 #define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 583 #define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 584 #define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 585 #define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 586 #define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 587 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 588 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 589 #define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 590 #define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 591 592 /* Bit fields for DEVINFO HFRCOCAL6 */ 593 #define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */ 594 #define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ 595 #define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 596 #define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 597 #define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 598 #define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 599 #define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 600 #define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 601 #define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 602 #define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 603 #define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 604 #define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 605 #define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 606 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 607 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 608 #define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 609 #define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 610 611 /* Bit fields for DEVINFO HFRCOCAL7 */ 612 #define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */ 613 #define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ 614 #define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 615 #define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 616 #define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 617 #define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 618 #define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 619 #define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 620 #define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 621 #define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 622 #define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 623 #define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 624 #define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 625 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 626 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 627 #define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 628 #define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 629 630 /* Bit fields for DEVINFO HFRCOCAL8 */ 631 #define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */ 632 #define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ 633 #define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 634 #define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 635 #define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 636 #define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 637 #define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 638 #define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 639 #define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 640 #define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 641 #define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 642 #define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 643 #define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 644 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 645 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 646 #define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 647 #define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 648 649 /* Bit fields for DEVINFO HFRCOCAL10 */ 650 #define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */ 651 #define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ 652 #define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 653 #define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 654 #define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 655 #define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 656 #define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 657 #define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 658 #define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 659 #define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 660 #define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 661 #define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 662 #define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 663 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 664 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 665 #define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 666 #define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 667 668 /* Bit fields for DEVINFO HFRCOCAL11 */ 669 #define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */ 670 #define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ 671 #define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 672 #define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 673 #define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 674 #define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 675 #define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 676 #define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 677 #define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 678 #define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 679 #define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 680 #define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 681 #define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 682 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 683 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 684 #define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 685 #define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 686 687 /* Bit fields for DEVINFO HFRCOCAL12 */ 688 #define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */ 689 #define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ 690 #define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 691 #define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 692 #define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 693 #define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 694 #define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 695 #define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 696 #define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 697 #define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 698 #define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 699 #define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 700 #define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 701 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 702 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 703 #define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 704 #define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 705 706 /* Bit fields for DEVINFO HFRCOCAL13 */ 707 #define _DEVINFO_HFRCOCAL13_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL13 */ 708 #define _DEVINFO_HFRCOCAL13_TUNING_SHIFT 0 /**< Shift value for TUNING */ 709 #define _DEVINFO_HFRCOCAL13_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 710 #define _DEVINFO_HFRCOCAL13_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 711 #define _DEVINFO_HFRCOCAL13_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 712 #define _DEVINFO_HFRCOCAL13_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 713 #define _DEVINFO_HFRCOCAL13_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 714 #define _DEVINFO_HFRCOCAL13_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 715 #define _DEVINFO_HFRCOCAL13_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 716 #define _DEVINFO_HFRCOCAL13_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 717 #define _DEVINFO_HFRCOCAL13_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 718 #define _DEVINFO_HFRCOCAL13_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 719 #define _DEVINFO_HFRCOCAL13_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 720 #define _DEVINFO_HFRCOCAL13_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 721 #define _DEVINFO_HFRCOCAL13_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 722 #define _DEVINFO_HFRCOCAL13_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 723 #define _DEVINFO_HFRCOCAL13_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 724 725 /* Bit fields for DEVINFO HFRCOCAL14 */ 726 #define _DEVINFO_HFRCOCAL14_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL14 */ 727 #define _DEVINFO_HFRCOCAL14_TUNING_SHIFT 0 /**< Shift value for TUNING */ 728 #define _DEVINFO_HFRCOCAL14_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 729 #define _DEVINFO_HFRCOCAL14_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 730 #define _DEVINFO_HFRCOCAL14_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 731 #define _DEVINFO_HFRCOCAL14_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 732 #define _DEVINFO_HFRCOCAL14_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 733 #define _DEVINFO_HFRCOCAL14_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 734 #define _DEVINFO_HFRCOCAL14_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 735 #define _DEVINFO_HFRCOCAL14_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 736 #define _DEVINFO_HFRCOCAL14_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 737 #define _DEVINFO_HFRCOCAL14_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 738 #define _DEVINFO_HFRCOCAL14_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 739 #define _DEVINFO_HFRCOCAL14_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 740 #define _DEVINFO_HFRCOCAL14_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 741 #define _DEVINFO_HFRCOCAL14_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 742 #define _DEVINFO_HFRCOCAL14_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 743 744 /* Bit fields for DEVINFO HFRCOCAL15 */ 745 #define _DEVINFO_HFRCOCAL15_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL15 */ 746 #define _DEVINFO_HFRCOCAL15_TUNING_SHIFT 0 /**< Shift value for TUNING */ 747 #define _DEVINFO_HFRCOCAL15_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 748 #define _DEVINFO_HFRCOCAL15_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 749 #define _DEVINFO_HFRCOCAL15_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 750 #define _DEVINFO_HFRCOCAL15_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 751 #define _DEVINFO_HFRCOCAL15_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 752 #define _DEVINFO_HFRCOCAL15_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 753 #define _DEVINFO_HFRCOCAL15_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 754 #define _DEVINFO_HFRCOCAL15_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 755 #define _DEVINFO_HFRCOCAL15_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 756 #define _DEVINFO_HFRCOCAL15_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 757 #define _DEVINFO_HFRCOCAL15_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 758 #define _DEVINFO_HFRCOCAL15_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 759 #define _DEVINFO_HFRCOCAL15_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 760 #define _DEVINFO_HFRCOCAL15_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 761 #define _DEVINFO_HFRCOCAL15_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 762 763 /* Bit fields for DEVINFO HFRCOCAL16 */ 764 #define _DEVINFO_HFRCOCAL16_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL16 */ 765 #define _DEVINFO_HFRCOCAL16_TUNING_SHIFT 0 /**< Shift value for TUNING */ 766 #define _DEVINFO_HFRCOCAL16_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 767 #define _DEVINFO_HFRCOCAL16_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 768 #define _DEVINFO_HFRCOCAL16_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 769 #define _DEVINFO_HFRCOCAL16_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 770 #define _DEVINFO_HFRCOCAL16_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 771 #define _DEVINFO_HFRCOCAL16_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 772 #define _DEVINFO_HFRCOCAL16_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 773 #define _DEVINFO_HFRCOCAL16_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 774 #define _DEVINFO_HFRCOCAL16_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 775 #define _DEVINFO_HFRCOCAL16_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 776 #define _DEVINFO_HFRCOCAL16_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 777 #define _DEVINFO_HFRCOCAL16_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 778 #define _DEVINFO_HFRCOCAL16_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 779 #define _DEVINFO_HFRCOCAL16_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 780 #define _DEVINFO_HFRCOCAL16_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 781 782 /* Bit fields for DEVINFO AUXHFRCOCAL0 */ 783 #define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */ 784 #define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ 785 #define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 786 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 787 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 788 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 789 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 790 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 791 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 792 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 793 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 794 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 795 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 796 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 797 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 798 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 799 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 800 801 /* Bit fields for DEVINFO AUXHFRCOCAL3 */ 802 #define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */ 803 #define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ 804 #define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 805 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 806 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 807 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 808 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 809 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 810 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 811 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 812 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 813 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 814 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 815 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 816 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 817 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 818 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 819 820 /* Bit fields for DEVINFO AUXHFRCOCAL6 */ 821 #define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */ 822 #define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ 823 #define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 824 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 825 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 826 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 827 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 828 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 829 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 830 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 831 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 832 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 833 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 834 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 835 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 836 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 837 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 838 839 /* Bit fields for DEVINFO AUXHFRCOCAL7 */ 840 #define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */ 841 #define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ 842 #define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 843 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 844 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 845 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 846 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 847 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 848 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 849 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 850 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 851 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 852 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 853 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 854 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 855 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 856 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 857 858 /* Bit fields for DEVINFO AUXHFRCOCAL8 */ 859 #define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */ 860 #define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ 861 #define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 862 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 863 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 864 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 865 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 866 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 867 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 868 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 869 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 870 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 871 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 872 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 873 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 874 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 875 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 876 877 /* Bit fields for DEVINFO AUXHFRCOCAL10 */ 878 #define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */ 879 #define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ 880 #define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 881 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 882 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 883 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 884 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 885 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 886 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 887 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 888 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 889 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 890 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 891 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 892 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 893 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 894 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 895 896 /* Bit fields for DEVINFO AUXHFRCOCAL11 */ 897 #define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */ 898 #define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ 899 #define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 900 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 901 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 902 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 903 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 904 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 905 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 906 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 907 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 908 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 909 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 910 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 911 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 912 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 913 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 914 915 /* Bit fields for DEVINFO AUXHFRCOCAL12 */ 916 #define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */ 917 #define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ 918 #define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 919 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 920 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 921 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 922 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 923 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 924 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 925 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 926 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 927 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 928 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 929 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 930 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 931 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 932 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 933 934 /* Bit fields for DEVINFO AUXHFRCOCAL13 */ 935 #define _DEVINFO_AUXHFRCOCAL13_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL13 */ 936 #define _DEVINFO_AUXHFRCOCAL13_TUNING_SHIFT 0 /**< Shift value for TUNING */ 937 #define _DEVINFO_AUXHFRCOCAL13_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 938 #define _DEVINFO_AUXHFRCOCAL13_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 939 #define _DEVINFO_AUXHFRCOCAL13_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 940 #define _DEVINFO_AUXHFRCOCAL13_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 941 #define _DEVINFO_AUXHFRCOCAL13_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 942 #define _DEVINFO_AUXHFRCOCAL13_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 943 #define _DEVINFO_AUXHFRCOCAL13_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 944 #define _DEVINFO_AUXHFRCOCAL13_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 945 #define _DEVINFO_AUXHFRCOCAL13_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 946 #define _DEVINFO_AUXHFRCOCAL13_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 947 #define _DEVINFO_AUXHFRCOCAL13_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 948 #define _DEVINFO_AUXHFRCOCAL13_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 949 #define _DEVINFO_AUXHFRCOCAL13_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 950 #define _DEVINFO_AUXHFRCOCAL13_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 951 #define _DEVINFO_AUXHFRCOCAL13_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 952 953 /* Bit fields for DEVINFO AUXHFRCOCAL14 */ 954 #define _DEVINFO_AUXHFRCOCAL14_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL14 */ 955 #define _DEVINFO_AUXHFRCOCAL14_TUNING_SHIFT 0 /**< Shift value for TUNING */ 956 #define _DEVINFO_AUXHFRCOCAL14_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 957 #define _DEVINFO_AUXHFRCOCAL14_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 958 #define _DEVINFO_AUXHFRCOCAL14_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 959 #define _DEVINFO_AUXHFRCOCAL14_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 960 #define _DEVINFO_AUXHFRCOCAL14_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 961 #define _DEVINFO_AUXHFRCOCAL14_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 962 #define _DEVINFO_AUXHFRCOCAL14_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 963 #define _DEVINFO_AUXHFRCOCAL14_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 964 #define _DEVINFO_AUXHFRCOCAL14_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 965 #define _DEVINFO_AUXHFRCOCAL14_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 966 #define _DEVINFO_AUXHFRCOCAL14_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 967 #define _DEVINFO_AUXHFRCOCAL14_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 968 #define _DEVINFO_AUXHFRCOCAL14_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 969 #define _DEVINFO_AUXHFRCOCAL14_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 970 #define _DEVINFO_AUXHFRCOCAL14_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 971 972 /* Bit fields for DEVINFO VMONCAL0 */ 973 #define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */ 974 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */ 975 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */ 976 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */ 977 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */ 978 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */ 979 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */ 980 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */ 981 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */ 982 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */ 983 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */ 984 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */ 985 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */ 986 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */ 987 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */ 988 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */ 989 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */ 990 991 /* Bit fields for DEVINFO VMONCAL1 */ 992 #define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */ 993 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */ 994 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */ 995 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */ 996 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */ 997 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */ 998 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */ 999 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */ 1000 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */ 1001 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */ 1002 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */ 1003 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */ 1004 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */ 1005 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */ 1006 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */ 1007 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */ 1008 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */ 1009 1010 /* Bit fields for DEVINFO VMONCAL2 */ 1011 #define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */ 1012 #define _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_SHIFT 0 /**< Shift value for BUVDD1V86THRESFINE */ 1013 #define _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for BUVDD1V86THRESFINE */ 1014 #define _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for BUVDD1V86THRESCOARSE */ 1015 #define _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for BUVDD1V86THRESCOARSE */ 1016 #define _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_SHIFT 8 /**< Shift value for BUVDD2V98THRESFINE */ 1017 #define _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for BUVDD2V98THRESFINE */ 1018 #define _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for BUVDD2V98THRESCOARSE */ 1019 #define _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for BUVDD2V98THRESCOARSE */ 1020 #define _DEVINFO_VMONCAL2_IO11V86THRESFINE_SHIFT 16 /**< Shift value for IO11V86THRESFINE */ 1021 #define _DEVINFO_VMONCAL2_IO11V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO11V86THRESFINE */ 1022 #define _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_SHIFT 20 /**< Shift value for IO11V86THRESCOARSE */ 1023 #define _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO11V86THRESCOARSE */ 1024 #define _DEVINFO_VMONCAL2_IO12V98THRESFINE_SHIFT 24 /**< Shift value for IO12V98THRESFINE */ 1025 #define _DEVINFO_VMONCAL2_IO12V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO12V98THRESFINE */ 1026 #define _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_SHIFT 28 /**< Shift value for IO12V98THRESCOARSE */ 1027 #define _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO12V98THRESCOARSE */ 1028 1029 /* Bit fields for DEVINFO IDAC0CAL0 */ 1030 #define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */ 1031 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */ 1032 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */ 1033 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */ 1034 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */ 1035 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */ 1036 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */ 1037 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */ 1038 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */ 1039 1040 /* Bit fields for DEVINFO IDAC0CAL1 */ 1041 #define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */ 1042 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */ 1043 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */ 1044 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */ 1045 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */ 1046 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */ 1047 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */ 1048 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */ 1049 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */ 1050 1051 /* Bit fields for DEVINFO DCDCLNVCTRL0 */ 1052 #define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */ 1053 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */ 1054 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */ 1055 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */ 1056 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */ 1057 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */ 1058 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */ 1059 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */ 1060 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */ 1061 1062 /* Bit fields for DEVINFO DCDCLPVCTRL0 */ 1063 #define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */ 1064 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */ 1065 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */ 1066 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */ 1067 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */ 1068 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */ 1069 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */ 1070 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */ 1071 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */ 1072 1073 /* Bit fields for DEVINFO DCDCLPVCTRL1 */ 1074 #define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */ 1075 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */ 1076 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */ 1077 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */ 1078 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */ 1079 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */ 1080 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */ 1081 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */ 1082 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */ 1083 1084 /* Bit fields for DEVINFO DCDCLPVCTRL2 */ 1085 #define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */ 1086 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */ 1087 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */ 1088 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */ 1089 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */ 1090 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */ 1091 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */ 1092 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */ 1093 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */ 1094 1095 /* Bit fields for DEVINFO DCDCLPVCTRL3 */ 1096 #define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */ 1097 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */ 1098 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */ 1099 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */ 1100 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */ 1101 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */ 1102 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */ 1103 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */ 1104 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */ 1105 1106 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */ 1107 #define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */ 1108 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */ 1109 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */ 1110 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */ 1111 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */ 1112 1113 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */ 1114 #define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */ 1115 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */ 1116 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */ 1117 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */ 1118 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */ 1119 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */ 1120 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */ 1121 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */ 1122 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */ 1123 1124 /* Bit fields for DEVINFO VDAC0MAINCAL */ 1125 #define _DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0MAINCAL */ 1126 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LN */ 1127 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LN */ 1128 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LN */ 1129 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LN */ 1130 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12 /**< Shift value for GAINERRTRIM1V25 */ 1131 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25 */ 1132 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18 /**< Shift value for GAINERRTRIM2V5 */ 1133 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5 */ 1134 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPIN */ 1135 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPIN */ 1136 1137 /* Bit fields for DEVINFO VDAC0ALTCAL */ 1138 #define _DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0ALTCAL */ 1139 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LNALT */ 1140 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LNALT */ 1141 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LNALT */ 1142 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LNALT */ 1143 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12 /**< Shift value for GAINERRTRIM1V25ALT */ 1144 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25ALT */ 1145 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18 /**< Shift value for GAINERRTRIM2V5ALT */ 1146 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5ALT */ 1147 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPINALT */ 1148 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPINALT */ 1149 1150 /* Bit fields for DEVINFO VDAC0CH1CAL */ 1151 #define _DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL /**< Mask for DEVINFO_VDAC0CH1CAL */ 1152 #define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for OFFSETTRIM */ 1153 #define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for OFFSETTRIM */ 1154 #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4 /**< Shift value for GAINERRTRIMCH1A */ 1155 #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL /**< Bit mask for GAINERRTRIMCH1A */ 1156 #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8 /**< Shift value for GAINERRTRIMCH1B */ 1157 #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL /**< Bit mask for GAINERRTRIMCH1B */ 1158 1159 /* Bit fields for DEVINFO OPA0CAL0 */ 1160 #define _DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL0 */ 1161 #define _DEVINFO_OPA0CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ 1162 #define _DEVINFO_OPA0CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1163 #define _DEVINFO_OPA0CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ 1164 #define _DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1165 #define _DEVINFO_OPA0CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ 1166 #define _DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1167 #define _DEVINFO_OPA0CAL0_GM_SHIFT 13 /**< Shift value for GM */ 1168 #define _DEVINFO_OPA0CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ 1169 #define _DEVINFO_OPA0CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ 1170 #define _DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1171 #define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1172 #define _DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1173 #define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1174 #define _DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1175 1176 /* Bit fields for DEVINFO OPA0CAL1 */ 1177 #define _DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL1 */ 1178 #define _DEVINFO_OPA0CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ 1179 #define _DEVINFO_OPA0CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1180 #define _DEVINFO_OPA0CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ 1181 #define _DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1182 #define _DEVINFO_OPA0CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ 1183 #define _DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1184 #define _DEVINFO_OPA0CAL1_GM_SHIFT 13 /**< Shift value for GM */ 1185 #define _DEVINFO_OPA0CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ 1186 #define _DEVINFO_OPA0CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ 1187 #define _DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1188 #define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1189 #define _DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1190 #define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1191 #define _DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1192 1193 /* Bit fields for DEVINFO OPA0CAL2 */ 1194 #define _DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL2 */ 1195 #define _DEVINFO_OPA0CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ 1196 #define _DEVINFO_OPA0CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1197 #define _DEVINFO_OPA0CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ 1198 #define _DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1199 #define _DEVINFO_OPA0CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ 1200 #define _DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1201 #define _DEVINFO_OPA0CAL2_GM_SHIFT 13 /**< Shift value for GM */ 1202 #define _DEVINFO_OPA0CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ 1203 #define _DEVINFO_OPA0CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ 1204 #define _DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1205 #define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1206 #define _DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1207 #define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1208 #define _DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1209 1210 /* Bit fields for DEVINFO OPA0CAL3 */ 1211 #define _DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL3 */ 1212 #define _DEVINFO_OPA0CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ 1213 #define _DEVINFO_OPA0CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1214 #define _DEVINFO_OPA0CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ 1215 #define _DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1216 #define _DEVINFO_OPA0CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ 1217 #define _DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1218 #define _DEVINFO_OPA0CAL3_GM_SHIFT 13 /**< Shift value for GM */ 1219 #define _DEVINFO_OPA0CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ 1220 #define _DEVINFO_OPA0CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ 1221 #define _DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1222 #define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1223 #define _DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1224 #define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1225 #define _DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1226 1227 /* Bit fields for DEVINFO OPA0CAL4 */ 1228 #define _DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL4 */ 1229 #define _DEVINFO_OPA0CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ 1230 #define _DEVINFO_OPA0CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1231 #define _DEVINFO_OPA0CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ 1232 #define _DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1233 #define _DEVINFO_OPA0CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ 1234 #define _DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1235 #define _DEVINFO_OPA0CAL4_GM_SHIFT 13 /**< Shift value for GM */ 1236 #define _DEVINFO_OPA0CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ 1237 #define _DEVINFO_OPA0CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ 1238 #define _DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1239 #define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1240 #define _DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1241 #define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1242 #define _DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1243 1244 /* Bit fields for DEVINFO OPA0CAL5 */ 1245 #define _DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL5 */ 1246 #define _DEVINFO_OPA0CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ 1247 #define _DEVINFO_OPA0CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1248 #define _DEVINFO_OPA0CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ 1249 #define _DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1250 #define _DEVINFO_OPA0CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ 1251 #define _DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1252 #define _DEVINFO_OPA0CAL5_GM_SHIFT 13 /**< Shift value for GM */ 1253 #define _DEVINFO_OPA0CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ 1254 #define _DEVINFO_OPA0CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ 1255 #define _DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1256 #define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1257 #define _DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1258 #define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1259 #define _DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1260 1261 /* Bit fields for DEVINFO OPA0CAL6 */ 1262 #define _DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL6 */ 1263 #define _DEVINFO_OPA0CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ 1264 #define _DEVINFO_OPA0CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1265 #define _DEVINFO_OPA0CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ 1266 #define _DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1267 #define _DEVINFO_OPA0CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ 1268 #define _DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1269 #define _DEVINFO_OPA0CAL6_GM_SHIFT 13 /**< Shift value for GM */ 1270 #define _DEVINFO_OPA0CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ 1271 #define _DEVINFO_OPA0CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ 1272 #define _DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1273 #define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1274 #define _DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1275 #define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1276 #define _DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1277 1278 /* Bit fields for DEVINFO OPA0CAL7 */ 1279 #define _DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL7 */ 1280 #define _DEVINFO_OPA0CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ 1281 #define _DEVINFO_OPA0CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1282 #define _DEVINFO_OPA0CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ 1283 #define _DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1284 #define _DEVINFO_OPA0CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ 1285 #define _DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1286 #define _DEVINFO_OPA0CAL7_GM_SHIFT 13 /**< Shift value for GM */ 1287 #define _DEVINFO_OPA0CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ 1288 #define _DEVINFO_OPA0CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ 1289 #define _DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1290 #define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1291 #define _DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1292 #define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1293 #define _DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1294 1295 /* Bit fields for DEVINFO OPA1CAL0 */ 1296 #define _DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL0 */ 1297 #define _DEVINFO_OPA1CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ 1298 #define _DEVINFO_OPA1CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1299 #define _DEVINFO_OPA1CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ 1300 #define _DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1301 #define _DEVINFO_OPA1CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ 1302 #define _DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1303 #define _DEVINFO_OPA1CAL0_GM_SHIFT 13 /**< Shift value for GM */ 1304 #define _DEVINFO_OPA1CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ 1305 #define _DEVINFO_OPA1CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ 1306 #define _DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1307 #define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1308 #define _DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1309 #define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1310 #define _DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1311 1312 /* Bit fields for DEVINFO OPA1CAL1 */ 1313 #define _DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL1 */ 1314 #define _DEVINFO_OPA1CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ 1315 #define _DEVINFO_OPA1CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1316 #define _DEVINFO_OPA1CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ 1317 #define _DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1318 #define _DEVINFO_OPA1CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ 1319 #define _DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1320 #define _DEVINFO_OPA1CAL1_GM_SHIFT 13 /**< Shift value for GM */ 1321 #define _DEVINFO_OPA1CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ 1322 #define _DEVINFO_OPA1CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ 1323 #define _DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1324 #define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1325 #define _DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1326 #define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1327 #define _DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1328 1329 /* Bit fields for DEVINFO OPA1CAL2 */ 1330 #define _DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL2 */ 1331 #define _DEVINFO_OPA1CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ 1332 #define _DEVINFO_OPA1CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1333 #define _DEVINFO_OPA1CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ 1334 #define _DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1335 #define _DEVINFO_OPA1CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ 1336 #define _DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1337 #define _DEVINFO_OPA1CAL2_GM_SHIFT 13 /**< Shift value for GM */ 1338 #define _DEVINFO_OPA1CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ 1339 #define _DEVINFO_OPA1CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ 1340 #define _DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1341 #define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1342 #define _DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1343 #define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1344 #define _DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1345 1346 /* Bit fields for DEVINFO OPA1CAL3 */ 1347 #define _DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL3 */ 1348 #define _DEVINFO_OPA1CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ 1349 #define _DEVINFO_OPA1CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1350 #define _DEVINFO_OPA1CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ 1351 #define _DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1352 #define _DEVINFO_OPA1CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ 1353 #define _DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1354 #define _DEVINFO_OPA1CAL3_GM_SHIFT 13 /**< Shift value for GM */ 1355 #define _DEVINFO_OPA1CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ 1356 #define _DEVINFO_OPA1CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ 1357 #define _DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1358 #define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1359 #define _DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1360 #define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1361 #define _DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1362 1363 /* Bit fields for DEVINFO OPA1CAL4 */ 1364 #define _DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL4 */ 1365 #define _DEVINFO_OPA1CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ 1366 #define _DEVINFO_OPA1CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1367 #define _DEVINFO_OPA1CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ 1368 #define _DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1369 #define _DEVINFO_OPA1CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ 1370 #define _DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1371 #define _DEVINFO_OPA1CAL4_GM_SHIFT 13 /**< Shift value for GM */ 1372 #define _DEVINFO_OPA1CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ 1373 #define _DEVINFO_OPA1CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ 1374 #define _DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1375 #define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1376 #define _DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1377 #define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1378 #define _DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1379 1380 /* Bit fields for DEVINFO OPA1CAL5 */ 1381 #define _DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL5 */ 1382 #define _DEVINFO_OPA1CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ 1383 #define _DEVINFO_OPA1CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1384 #define _DEVINFO_OPA1CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ 1385 #define _DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1386 #define _DEVINFO_OPA1CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ 1387 #define _DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1388 #define _DEVINFO_OPA1CAL5_GM_SHIFT 13 /**< Shift value for GM */ 1389 #define _DEVINFO_OPA1CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ 1390 #define _DEVINFO_OPA1CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ 1391 #define _DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1392 #define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1393 #define _DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1394 #define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1395 #define _DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1396 1397 /* Bit fields for DEVINFO OPA1CAL6 */ 1398 #define _DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL6 */ 1399 #define _DEVINFO_OPA1CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ 1400 #define _DEVINFO_OPA1CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1401 #define _DEVINFO_OPA1CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ 1402 #define _DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1403 #define _DEVINFO_OPA1CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ 1404 #define _DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1405 #define _DEVINFO_OPA1CAL6_GM_SHIFT 13 /**< Shift value for GM */ 1406 #define _DEVINFO_OPA1CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ 1407 #define _DEVINFO_OPA1CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ 1408 #define _DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1409 #define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1410 #define _DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1411 #define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1412 #define _DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1413 1414 /* Bit fields for DEVINFO OPA1CAL7 */ 1415 #define _DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL7 */ 1416 #define _DEVINFO_OPA1CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ 1417 #define _DEVINFO_OPA1CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1418 #define _DEVINFO_OPA1CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ 1419 #define _DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1420 #define _DEVINFO_OPA1CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ 1421 #define _DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1422 #define _DEVINFO_OPA1CAL7_GM_SHIFT 13 /**< Shift value for GM */ 1423 #define _DEVINFO_OPA1CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ 1424 #define _DEVINFO_OPA1CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ 1425 #define _DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1426 #define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1427 #define _DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1428 #define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1429 #define _DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1430 1431 /* Bit fields for DEVINFO OPA2CAL0 */ 1432 #define _DEVINFO_OPA2CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL0 */ 1433 #define _DEVINFO_OPA2CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ 1434 #define _DEVINFO_OPA2CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1435 #define _DEVINFO_OPA2CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ 1436 #define _DEVINFO_OPA2CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1437 #define _DEVINFO_OPA2CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ 1438 #define _DEVINFO_OPA2CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1439 #define _DEVINFO_OPA2CAL0_GM_SHIFT 13 /**< Shift value for GM */ 1440 #define _DEVINFO_OPA2CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ 1441 #define _DEVINFO_OPA2CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ 1442 #define _DEVINFO_OPA2CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1443 #define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1444 #define _DEVINFO_OPA2CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1445 #define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1446 #define _DEVINFO_OPA2CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1447 1448 /* Bit fields for DEVINFO OPA2CAL1 */ 1449 #define _DEVINFO_OPA2CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL1 */ 1450 #define _DEVINFO_OPA2CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ 1451 #define _DEVINFO_OPA2CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1452 #define _DEVINFO_OPA2CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ 1453 #define _DEVINFO_OPA2CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1454 #define _DEVINFO_OPA2CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ 1455 #define _DEVINFO_OPA2CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1456 #define _DEVINFO_OPA2CAL1_GM_SHIFT 13 /**< Shift value for GM */ 1457 #define _DEVINFO_OPA2CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ 1458 #define _DEVINFO_OPA2CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ 1459 #define _DEVINFO_OPA2CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1460 #define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1461 #define _DEVINFO_OPA2CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1462 #define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1463 #define _DEVINFO_OPA2CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1464 1465 /* Bit fields for DEVINFO OPA2CAL2 */ 1466 #define _DEVINFO_OPA2CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL2 */ 1467 #define _DEVINFO_OPA2CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ 1468 #define _DEVINFO_OPA2CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1469 #define _DEVINFO_OPA2CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ 1470 #define _DEVINFO_OPA2CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1471 #define _DEVINFO_OPA2CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ 1472 #define _DEVINFO_OPA2CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1473 #define _DEVINFO_OPA2CAL2_GM_SHIFT 13 /**< Shift value for GM */ 1474 #define _DEVINFO_OPA2CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ 1475 #define _DEVINFO_OPA2CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ 1476 #define _DEVINFO_OPA2CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1477 #define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1478 #define _DEVINFO_OPA2CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1479 #define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1480 #define _DEVINFO_OPA2CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1481 1482 /* Bit fields for DEVINFO OPA2CAL3 */ 1483 #define _DEVINFO_OPA2CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL3 */ 1484 #define _DEVINFO_OPA2CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ 1485 #define _DEVINFO_OPA2CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1486 #define _DEVINFO_OPA2CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ 1487 #define _DEVINFO_OPA2CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1488 #define _DEVINFO_OPA2CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ 1489 #define _DEVINFO_OPA2CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1490 #define _DEVINFO_OPA2CAL3_GM_SHIFT 13 /**< Shift value for GM */ 1491 #define _DEVINFO_OPA2CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ 1492 #define _DEVINFO_OPA2CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ 1493 #define _DEVINFO_OPA2CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1494 #define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1495 #define _DEVINFO_OPA2CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1496 #define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1497 #define _DEVINFO_OPA2CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1498 1499 /* Bit fields for DEVINFO OPA2CAL4 */ 1500 #define _DEVINFO_OPA2CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL4 */ 1501 #define _DEVINFO_OPA2CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ 1502 #define _DEVINFO_OPA2CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1503 #define _DEVINFO_OPA2CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ 1504 #define _DEVINFO_OPA2CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1505 #define _DEVINFO_OPA2CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ 1506 #define _DEVINFO_OPA2CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1507 #define _DEVINFO_OPA2CAL4_GM_SHIFT 13 /**< Shift value for GM */ 1508 #define _DEVINFO_OPA2CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ 1509 #define _DEVINFO_OPA2CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ 1510 #define _DEVINFO_OPA2CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1511 #define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1512 #define _DEVINFO_OPA2CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1513 #define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1514 #define _DEVINFO_OPA2CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1515 1516 /* Bit fields for DEVINFO OPA2CAL5 */ 1517 #define _DEVINFO_OPA2CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL5 */ 1518 #define _DEVINFO_OPA2CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ 1519 #define _DEVINFO_OPA2CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1520 #define _DEVINFO_OPA2CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ 1521 #define _DEVINFO_OPA2CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1522 #define _DEVINFO_OPA2CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ 1523 #define _DEVINFO_OPA2CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1524 #define _DEVINFO_OPA2CAL5_GM_SHIFT 13 /**< Shift value for GM */ 1525 #define _DEVINFO_OPA2CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ 1526 #define _DEVINFO_OPA2CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ 1527 #define _DEVINFO_OPA2CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1528 #define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1529 #define _DEVINFO_OPA2CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1530 #define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1531 #define _DEVINFO_OPA2CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1532 1533 /* Bit fields for DEVINFO OPA2CAL6 */ 1534 #define _DEVINFO_OPA2CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL6 */ 1535 #define _DEVINFO_OPA2CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ 1536 #define _DEVINFO_OPA2CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1537 #define _DEVINFO_OPA2CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ 1538 #define _DEVINFO_OPA2CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1539 #define _DEVINFO_OPA2CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ 1540 #define _DEVINFO_OPA2CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1541 #define _DEVINFO_OPA2CAL6_GM_SHIFT 13 /**< Shift value for GM */ 1542 #define _DEVINFO_OPA2CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ 1543 #define _DEVINFO_OPA2CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ 1544 #define _DEVINFO_OPA2CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1545 #define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1546 #define _DEVINFO_OPA2CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1547 #define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1548 #define _DEVINFO_OPA2CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1549 1550 /* Bit fields for DEVINFO OPA2CAL7 */ 1551 #define _DEVINFO_OPA2CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL7 */ 1552 #define _DEVINFO_OPA2CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ 1553 #define _DEVINFO_OPA2CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1554 #define _DEVINFO_OPA2CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ 1555 #define _DEVINFO_OPA2CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1556 #define _DEVINFO_OPA2CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ 1557 #define _DEVINFO_OPA2CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1558 #define _DEVINFO_OPA2CAL7_GM_SHIFT 13 /**< Shift value for GM */ 1559 #define _DEVINFO_OPA2CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ 1560 #define _DEVINFO_OPA2CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ 1561 #define _DEVINFO_OPA2CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1562 #define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1563 #define _DEVINFO_OPA2CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1564 #define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1565 #define _DEVINFO_OPA2CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1566 1567 /* Bit fields for DEVINFO OPA3CAL0 */ 1568 #define _DEVINFO_OPA3CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL0 */ 1569 #define _DEVINFO_OPA3CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ 1570 #define _DEVINFO_OPA3CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1571 #define _DEVINFO_OPA3CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ 1572 #define _DEVINFO_OPA3CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1573 #define _DEVINFO_OPA3CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ 1574 #define _DEVINFO_OPA3CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1575 #define _DEVINFO_OPA3CAL0_GM_SHIFT 13 /**< Shift value for GM */ 1576 #define _DEVINFO_OPA3CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ 1577 #define _DEVINFO_OPA3CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ 1578 #define _DEVINFO_OPA3CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1579 #define _DEVINFO_OPA3CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1580 #define _DEVINFO_OPA3CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1581 #define _DEVINFO_OPA3CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1582 #define _DEVINFO_OPA3CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1583 1584 /* Bit fields for DEVINFO OPA3CAL1 */ 1585 #define _DEVINFO_OPA3CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL1 */ 1586 #define _DEVINFO_OPA3CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ 1587 #define _DEVINFO_OPA3CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1588 #define _DEVINFO_OPA3CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ 1589 #define _DEVINFO_OPA3CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1590 #define _DEVINFO_OPA3CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ 1591 #define _DEVINFO_OPA3CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1592 #define _DEVINFO_OPA3CAL1_GM_SHIFT 13 /**< Shift value for GM */ 1593 #define _DEVINFO_OPA3CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ 1594 #define _DEVINFO_OPA3CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ 1595 #define _DEVINFO_OPA3CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1596 #define _DEVINFO_OPA3CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1597 #define _DEVINFO_OPA3CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1598 #define _DEVINFO_OPA3CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1599 #define _DEVINFO_OPA3CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1600 1601 /* Bit fields for DEVINFO OPA3CAL2 */ 1602 #define _DEVINFO_OPA3CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL2 */ 1603 #define _DEVINFO_OPA3CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ 1604 #define _DEVINFO_OPA3CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1605 #define _DEVINFO_OPA3CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ 1606 #define _DEVINFO_OPA3CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1607 #define _DEVINFO_OPA3CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ 1608 #define _DEVINFO_OPA3CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1609 #define _DEVINFO_OPA3CAL2_GM_SHIFT 13 /**< Shift value for GM */ 1610 #define _DEVINFO_OPA3CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ 1611 #define _DEVINFO_OPA3CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ 1612 #define _DEVINFO_OPA3CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1613 #define _DEVINFO_OPA3CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1614 #define _DEVINFO_OPA3CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1615 #define _DEVINFO_OPA3CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1616 #define _DEVINFO_OPA3CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1617 1618 /* Bit fields for DEVINFO OPA3CAL3 */ 1619 #define _DEVINFO_OPA3CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL3 */ 1620 #define _DEVINFO_OPA3CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ 1621 #define _DEVINFO_OPA3CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1622 #define _DEVINFO_OPA3CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ 1623 #define _DEVINFO_OPA3CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1624 #define _DEVINFO_OPA3CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ 1625 #define _DEVINFO_OPA3CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1626 #define _DEVINFO_OPA3CAL3_GM_SHIFT 13 /**< Shift value for GM */ 1627 #define _DEVINFO_OPA3CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ 1628 #define _DEVINFO_OPA3CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ 1629 #define _DEVINFO_OPA3CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1630 #define _DEVINFO_OPA3CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1631 #define _DEVINFO_OPA3CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1632 #define _DEVINFO_OPA3CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1633 #define _DEVINFO_OPA3CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1634 1635 /* Bit fields for DEVINFO OPA3CAL4 */ 1636 #define _DEVINFO_OPA3CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL4 */ 1637 #define _DEVINFO_OPA3CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ 1638 #define _DEVINFO_OPA3CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1639 #define _DEVINFO_OPA3CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ 1640 #define _DEVINFO_OPA3CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1641 #define _DEVINFO_OPA3CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ 1642 #define _DEVINFO_OPA3CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1643 #define _DEVINFO_OPA3CAL4_GM_SHIFT 13 /**< Shift value for GM */ 1644 #define _DEVINFO_OPA3CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ 1645 #define _DEVINFO_OPA3CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ 1646 #define _DEVINFO_OPA3CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1647 #define _DEVINFO_OPA3CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1648 #define _DEVINFO_OPA3CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1649 #define _DEVINFO_OPA3CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1650 #define _DEVINFO_OPA3CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1651 1652 /* Bit fields for DEVINFO OPA3CAL5 */ 1653 #define _DEVINFO_OPA3CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL5 */ 1654 #define _DEVINFO_OPA3CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ 1655 #define _DEVINFO_OPA3CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1656 #define _DEVINFO_OPA3CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ 1657 #define _DEVINFO_OPA3CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1658 #define _DEVINFO_OPA3CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ 1659 #define _DEVINFO_OPA3CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1660 #define _DEVINFO_OPA3CAL5_GM_SHIFT 13 /**< Shift value for GM */ 1661 #define _DEVINFO_OPA3CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ 1662 #define _DEVINFO_OPA3CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ 1663 #define _DEVINFO_OPA3CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1664 #define _DEVINFO_OPA3CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1665 #define _DEVINFO_OPA3CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1666 #define _DEVINFO_OPA3CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1667 #define _DEVINFO_OPA3CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1668 1669 /* Bit fields for DEVINFO OPA3CAL6 */ 1670 #define _DEVINFO_OPA3CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL6 */ 1671 #define _DEVINFO_OPA3CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ 1672 #define _DEVINFO_OPA3CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1673 #define _DEVINFO_OPA3CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ 1674 #define _DEVINFO_OPA3CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1675 #define _DEVINFO_OPA3CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ 1676 #define _DEVINFO_OPA3CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1677 #define _DEVINFO_OPA3CAL6_GM_SHIFT 13 /**< Shift value for GM */ 1678 #define _DEVINFO_OPA3CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ 1679 #define _DEVINFO_OPA3CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ 1680 #define _DEVINFO_OPA3CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1681 #define _DEVINFO_OPA3CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1682 #define _DEVINFO_OPA3CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1683 #define _DEVINFO_OPA3CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1684 #define _DEVINFO_OPA3CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1685 1686 /* Bit fields for DEVINFO OPA3CAL7 */ 1687 #define _DEVINFO_OPA3CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL7 */ 1688 #define _DEVINFO_OPA3CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ 1689 #define _DEVINFO_OPA3CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ 1690 #define _DEVINFO_OPA3CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ 1691 #define _DEVINFO_OPA3CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ 1692 #define _DEVINFO_OPA3CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ 1693 #define _DEVINFO_OPA3CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ 1694 #define _DEVINFO_OPA3CAL7_GM_SHIFT 13 /**< Shift value for GM */ 1695 #define _DEVINFO_OPA3CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ 1696 #define _DEVINFO_OPA3CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ 1697 #define _DEVINFO_OPA3CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ 1698 #define _DEVINFO_OPA3CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ 1699 #define _DEVINFO_OPA3CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ 1700 #define _DEVINFO_OPA3CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ 1701 #define _DEVINFO_OPA3CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ 1702 1703 /* Bit fields for DEVINFO CSENGAINCAL */ 1704 #define _DEVINFO_CSENGAINCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_CSENGAINCAL */ 1705 #define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT 0 /**< Shift value for GAINCAL */ 1706 #define _DEVINFO_CSENGAINCAL_GAINCAL_MASK 0xFFUL /**< Bit mask for GAINCAL */ 1707 1708 /* Bit fields for DEVINFO USHFRCOCAL7 */ 1709 #define _DEVINFO_USHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_USHFRCOCAL7 */ 1710 #define _DEVINFO_USHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ 1711 #define _DEVINFO_USHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 1712 #define _DEVINFO_USHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 1713 #define _DEVINFO_USHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 1714 #define _DEVINFO_USHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 1715 #define _DEVINFO_USHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 1716 #define _DEVINFO_USHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 1717 #define _DEVINFO_USHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 1718 #define _DEVINFO_USHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 1719 #define _DEVINFO_USHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 1720 #define _DEVINFO_USHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 1721 #define _DEVINFO_USHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 1722 #define _DEVINFO_USHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 1723 #define _DEVINFO_USHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 1724 #define _DEVINFO_USHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 1725 #define _DEVINFO_USHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 1726 1727 /* Bit fields for DEVINFO USHFRCOCAL11 */ 1728 #define _DEVINFO_USHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_USHFRCOCAL11 */ 1729 #define _DEVINFO_USHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ 1730 #define _DEVINFO_USHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 1731 #define _DEVINFO_USHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 1732 #define _DEVINFO_USHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 1733 #define _DEVINFO_USHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 1734 #define _DEVINFO_USHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 1735 #define _DEVINFO_USHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 1736 #define _DEVINFO_USHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 1737 #define _DEVINFO_USHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 1738 #define _DEVINFO_USHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 1739 #define _DEVINFO_USHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 1740 #define _DEVINFO_USHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 1741 #define _DEVINFO_USHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 1742 #define _DEVINFO_USHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 1743 #define _DEVINFO_USHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 1744 #define _DEVINFO_USHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 1745 1746 /* Bit fields for DEVINFO USHFRCOCAL13 */ 1747 #define _DEVINFO_USHFRCOCAL13_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_USHFRCOCAL13 */ 1748 #define _DEVINFO_USHFRCOCAL13_TUNING_SHIFT 0 /**< Shift value for TUNING */ 1749 #define _DEVINFO_USHFRCOCAL13_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 1750 #define _DEVINFO_USHFRCOCAL13_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 1751 #define _DEVINFO_USHFRCOCAL13_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 1752 #define _DEVINFO_USHFRCOCAL13_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 1753 #define _DEVINFO_USHFRCOCAL13_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 1754 #define _DEVINFO_USHFRCOCAL13_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 1755 #define _DEVINFO_USHFRCOCAL13_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 1756 #define _DEVINFO_USHFRCOCAL13_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 1757 #define _DEVINFO_USHFRCOCAL13_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 1758 #define _DEVINFO_USHFRCOCAL13_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 1759 #define _DEVINFO_USHFRCOCAL13_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 1760 #define _DEVINFO_USHFRCOCAL13_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 1761 #define _DEVINFO_USHFRCOCAL13_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 1762 #define _DEVINFO_USHFRCOCAL13_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 1763 #define _DEVINFO_USHFRCOCAL13_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 1764 1765 /* Bit fields for DEVINFO USHFRCOCAL14 */ 1766 #define _DEVINFO_USHFRCOCAL14_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_USHFRCOCAL14 */ 1767 #define _DEVINFO_USHFRCOCAL14_TUNING_SHIFT 0 /**< Shift value for TUNING */ 1768 #define _DEVINFO_USHFRCOCAL14_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ 1769 #define _DEVINFO_USHFRCOCAL14_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ 1770 #define _DEVINFO_USHFRCOCAL14_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ 1771 #define _DEVINFO_USHFRCOCAL14_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ 1772 #define _DEVINFO_USHFRCOCAL14_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ 1773 #define _DEVINFO_USHFRCOCAL14_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ 1774 #define _DEVINFO_USHFRCOCAL14_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ 1775 #define _DEVINFO_USHFRCOCAL14_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ 1776 #define _DEVINFO_USHFRCOCAL14_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ 1777 #define _DEVINFO_USHFRCOCAL14_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ 1778 #define _DEVINFO_USHFRCOCAL14_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ 1779 #define _DEVINFO_USHFRCOCAL14_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ 1780 #define _DEVINFO_USHFRCOCAL14_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ 1781 #define _DEVINFO_USHFRCOCAL14_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ 1782 #define _DEVINFO_USHFRCOCAL14_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ 1783 1784 /* Bit fields for DEVINFO CURRMON5V */ 1785 #define _DEVINFO_CURRMON5V_MASK 0x00000000UL /**< Mask for DEVINFO_CURRMON5V */ 1786 1787 /** @} */ 1788 /** @} End of group EFM32GG11B_DEVINFO */ 1789 /** @} End of group Parts */ 1790
