1/*
2 * Copyright (c) 2023 Efinix Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <zephyr/dt-bindings/gpio/gpio.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13	model = "efinix,sapphire";
14	compatible = "efinix,sapphire";
15
16	chosen {
17		zephyr,sram = &ram0;
18	};
19
20	ram0: memory@F9000000 {
21		device_type = "memory";
22		reg = <0xF9000000 DT_SIZE_K(192)>;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28		cpu@0 {
29			clock-frequency = <100000000>;
30			compatible = "riscv";
31			device_type = "cpu";
32			reg = <0>;
33			riscv,isa = "rv32ima_zicsr_zifencei";
34			status = "okay";
35			timebase-frequency = <100000000>;
36
37			hlic: interrupt-controller {
38				compatible = "riscv,cpu-intc";
39				#address-cells = <0>;
40				#interrupt-cells = <1>;
41				interrupt-controller;
42			};
43		};
44	};
45
46	soc {
47		#address-cells = <1>;
48		#size-cells = <1>;
49		compatible = "efinix,sapphire";
50		ranges;
51
52		plic0: interrupt-controller@f8c00000 {
53			compatible = "sifive,plic-1.0.0";
54			#address-cells = <0>;
55			#interrupt-cells = <2>;
56			interrupt-controller;
57			interrupts-extended = <&hlic 11>;
58			reg = <0xf8c00000 0x04000000>;
59			riscv,max-priority = <3>;
60			riscv,ndev = <32>;
61		};
62
63		clint: clint@f8b00000 {
64			compatible = "sifive,clint0";
65			interrupts-extended = <&hlic 3 &hlic 7>;
66			reg = <0xf8b00000 0x10000>;
67		};
68
69		timer0: timer@e0002800 {
70			compatible = "efinix,sapphire-timer0";
71			reg = <0xe0002800 0x40>;
72			interrupt-parent = <&plic0>;
73			interrupts = <19 0>;
74			status = "disabled";
75		};
76
77		gpio0: gpio@f8015000 {
78			compatible = "efinix,sapphire-gpio";
79			reg = <0xf8015000 0x100>;
80			reg-names = "base";
81			ngpios = <4>;
82			gpio-controller;
83			#gpio-cells = <2>;
84			#address-cells = <1>;
85			#size-cells = <1>;
86			status = "disabled";
87		};
88
89		uart0: uart@f8010000 {
90			compatible = "efinix,sapphire-uart0";
91			interrupt-parent = <&plic0>;
92			interrupts = <1 1>;
93			reg = <0xf8010000 0x40>;
94			reg-names = "base";
95			current-speed = <115200>;
96			status = "disabled";
97		};
98
99	};
100};
101