1 /**************************************************************************//** 2 * @file ebi_reg.h 3 * @version V1.00 4 * @brief EBI register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EBI_REG_H__ 10 #define __EBI_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 19 /*---------------------- External Bus Interface Controller -------------------------*/ 20 /** 21 @addtogroup EBI External Bus Interface Controller(EBI) 22 Memory Mapped Structure for EBI Controller 23 @{ 24 */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var EBI_T::CTL0 32 * Offset: 0x00 External Bus Interface Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |EN |EBI Enable Bit 37 * | | |This bit is the functional enable bit for EBI. 38 * | | |0 = EBI function Disabled. 39 * | | |1 = EBI function Enabled. 40 * |[1] |DW16 |EBI Data Width 16-bit Select 41 * | | |This bit defines if the EBI data width is 8-bit or 16-bit. 42 * | | |0 = EBI data width is 8-bit. 43 * | | |1 = EBI data width is 16-bit. 44 * |[2] |CSPOLINV |Chip Select Pin Polar Inverse 45 * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). 46 * | | |0 = Chip select pin (EBI_nCS) is active low. 47 * | | |1 = Chip select pin (EBI_nCS) is active high. 48 * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit 49 * | | |0 = Address/Data Bus Separating Mode Disabled. 50 * | | |1 = Address/Data Bus Separating Mode Enabled. 51 * |[4] |CACCESS |Continuous Data Access Mode 52 * | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. 53 * | | |0 = Continuous data access mode Disabled. 54 * | | |1 = Continuous data access mode Enabled. 55 * |[10:8] |MCLKDIV |External Output Clock Divider 56 * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: 57 * | | |000 = HCLK/1. 58 * | | |001 = HCLK/2. 59 * | | |010 = HCLK/4. 60 * | | |011 = HCLK/8. 61 * | | |100 = HCLK/16. 62 * | | |101 = HCLK/32. 63 * | | |110 = HCLK/64. 64 * | | |111 = HCLK/128. 65 * |[18:16] |TALE |Extend Time of ALE 66 * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. 67 * | | |tALE = (TALE+1)*EBI_MCLK. 68 * | | |Note: This field only available in EBI_CTL0 register 69 * |[24] |WBUFEN |EBI Write Buffer Enable Bit 70 * | | |0 = EBI write buffer Disabled. 71 * | | |1 = EBI write buffer Enabled. 72 * | | |Note: This bit only available in EBI_CTL0 register 73 * @var EBI_T::TCTL0 74 * Offset: 0x04 External Bus Interface Timing Control Register 75 * --------------------------------------------------------------------------------------------------- 76 * |Bits |Field |Descriptions 77 * | :----: | :----: | :---- | 78 * |[7:3] |TACC |EBI Data Access Time 79 * | | |TACC define data access time (tACC). 80 * | | |tACC = (TACC+1) * EBI_MCLK. 81 * |[10:8] |TAHD |EBI Data Access Hold Time 82 * | | |TAHD define data access hold time (tAHD). 83 * | | |tAHD = (TAHD+1) * EBI_MCLK. 84 * |[15:12] |W2X |Idle Cycle After Write 85 * | | |This field defines the number of W2X idle cycle. 86 * | | |W2X idle cycle = (W2X * EBI_MCLK). 87 * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. 88 * |[22] |RAHDOFF |Access Hold Time Disable Control When Read 89 * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. 90 * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. 91 * |[23] |WAHDOFF |Access Hold Time Disable Control When Write 92 * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. 93 * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. 94 * |[27:24] |R2R |Idle Cycle Between Read-to-read 95 * | | |This field defines the number of R2R idle cycle. 96 * | | |R2R idle cycle = (R2R * EBI_MCLK). 97 * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. 98 */ 99 __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */ 100 __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */ 101 __I uint32_t RESERVE0[2]; 102 __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */ 103 __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */ 104 __I uint32_t RESERVE1[2]; 105 __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */ 106 __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */ 107 108 } EBI_T; 109 110 /** 111 @addtogroup EBI_CONST EBI Bit Field Definition 112 Constant Definitions for EBI Controller 113 @{ 114 */ 115 116 #define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */ 117 #define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL0: EN Mask */ 118 119 #define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */ 120 #define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */ 121 122 #define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */ 123 #define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */ 124 125 #define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */ 126 #define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */ 127 128 #define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */ 129 #define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */ 130 131 #define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */ 132 #define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */ 133 134 #define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */ 135 #define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */ 136 137 #define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */ 138 #define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */ 139 140 #define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */ 141 #define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */ 142 143 #define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */ 144 #define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */ 145 146 #define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */ 147 #define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */ 148 149 #define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */ 150 #define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */ 151 152 #define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */ 153 #define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */ 154 155 #define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */ 156 #define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */ 157 158 /**@}*/ /* EBI_CONST */ 159 /**@}*/ /* end of EBI register group */ 160 /**@}*/ /* end of REGISTER group */ 161 162 163 #endif /* __EBI_REG_H__ */ 164
