1 /* 2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __DX_NVM_H__ 8 #define __DX_NVM_H__ 9 10 // -------------------------------------- 11 // BLOCK: NVM 12 // -------------------------------------- 13 #define DX_AIB_FUSE_PROG_COMPLETED_REG_OFFSET 0x1F04UL 14 #define DX_AIB_FUSE_PROG_COMPLETED_VALUE_BIT_SHIFT 0x0UL 15 #define DX_AIB_FUSE_PROG_COMPLETED_VALUE_BIT_SIZE 0x1UL 16 #define DX_NVM_DEBUG_STATUS_REG_OFFSET 0x1F08UL 17 #define DX_NVM_DEBUG_STATUS_VALUE_BIT_SHIFT 0x1UL 18 #define DX_NVM_DEBUG_STATUS_VALUE_BIT_SIZE 0x3UL 19 #define DX_LCS_IS_VALID_REG_OFFSET 0x1F0CUL 20 #define DX_LCS_IS_VALID_VALUE_BIT_SHIFT 0x0UL 21 #define DX_LCS_IS_VALID_VALUE_BIT_SIZE 0x1UL 22 #define DX_NVM_IS_IDLE_REG_OFFSET 0x1F10UL 23 #define DX_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL 24 #define DX_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL 25 #define DX_LCS_REG_REG_OFFSET 0x1F14UL 26 #define DX_LCS_REG_LCS_REG_BIT_SHIFT 0x0UL 27 #define DX_LCS_REG_LCS_REG_BIT_SIZE 0x3UL 28 #define DX_LCS_REG_ERROR_KDR_ZERO_CNT_BIT_SHIFT 0x8UL 29 #define DX_LCS_REG_ERROR_KDR_ZERO_CNT_BIT_SIZE 0x1UL 30 #define DX_LCS_REG_ERROR_PROV_ZERO_CNT_BIT_SHIFT 0x9UL 31 #define DX_LCS_REG_ERROR_PROV_ZERO_CNT_BIT_SIZE 0x1UL 32 #define DX_LCS_REG_ERROR_KCE_ZERO_CNT_BIT_SHIFT 0xAUL 33 #define DX_LCS_REG_ERROR_KCE_ZERO_CNT_BIT_SIZE 0x1UL 34 #define DX_LCS_REG_ERROR_KPICV_ZERO_CNT_BIT_SHIFT 0xBUL 35 #define DX_LCS_REG_ERROR_KPICV_ZERO_CNT_BIT_SIZE 0x1UL 36 #define DX_LCS_REG_ERROR_KCEICV_ZERO_CNT_BIT_SHIFT 0xCUL 37 #define DX_LCS_REG_ERROR_KCEICV_ZERO_CNT_BIT_SIZE 0x1UL 38 #define DX_HOST_SHADOW_KDR_REG_REG_OFFSET 0x1F18UL 39 #define DX_HOST_SHADOW_KDR_REG_VALUE_BIT_SHIFT 0x0UL 40 #define DX_HOST_SHADOW_KDR_REG_VALUE_BIT_SIZE 0x1UL 41 #define DX_HOST_SHADOW_KCP_REG_REG_OFFSET 0x1F1CUL 42 #define DX_HOST_SHADOW_KCP_REG_VALUE_BIT_SHIFT 0x0UL 43 #define DX_HOST_SHADOW_KCP_REG_VALUE_BIT_SIZE 0x1UL 44 #define DX_HOST_SHADOW_KCE_REG_REG_OFFSET 0x1F20UL 45 #define DX_HOST_SHADOW_KCE_REG_VALUE_BIT_SHIFT 0x0UL 46 #define DX_HOST_SHADOW_KCE_REG_VALUE_BIT_SIZE 0x1UL 47 #define DX_HOST_SHADOW_KPICV_REG_REG_OFFSET 0x1F24UL 48 #define DX_HOST_SHADOW_KPICV_REG_VALUE_BIT_SHIFT 0x0UL 49 #define DX_HOST_SHADOW_KPICV_REG_VALUE_BIT_SIZE 0x1UL 50 #define DX_HOST_SHADOW_KCEICV_REG_REG_OFFSET 0x1F28UL 51 #define DX_HOST_SHADOW_KCEICV_REG_VALUE_BIT_SHIFT 0x0UL 52 #define DX_HOST_SHADOW_KCEICV_REG_VALUE_BIT_SIZE 0x1UL 53 #define DX_OTP_ADDR_WIDTH_DEF_REG_OFFSET 0x1F2CUL 54 #define DX_OTP_ADDR_WIDTH_DEF_VALUE_BIT_SHIFT 0x0UL 55 #define DX_OTP_ADDR_WIDTH_DEF_VALUE_BIT_SIZE 0x4UL 56 57 #endif //__DX_NVM_H__ 58 59
