1 /* 2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __DX_HOST_H__ 8 #define __DX_HOST_H__ 9 10 // -------------------------------------- 11 // BLOCK: HOST 12 // -------------------------------------- 13 #define DX_HOST_IRR_REG_OFFSET 0x0A00UL 14 #define DX_HOST_IRR_SRAM_TO_DIN_INT_BIT_SHIFT 0x4UL 15 #define DX_HOST_IRR_SRAM_TO_DIN_INT_BIT_SIZE 0x1UL 16 #define DX_HOST_IRR_DOUT_TO_SRAM_INT_BIT_SHIFT 0x5UL 17 #define DX_HOST_IRR_DOUT_TO_SRAM_INT_BIT_SIZE 0x1UL 18 #define DX_HOST_IRR_MEM_TO_DIN_INT_BIT_SHIFT 0x6UL 19 #define DX_HOST_IRR_MEM_TO_DIN_INT_BIT_SIZE 0x1UL 20 #define DX_HOST_IRR_DOUT_TO_MEM_INT_BIT_SHIFT 0x7UL 21 #define DX_HOST_IRR_DOUT_TO_MEM_INT_BIT_SIZE 0x1UL 22 #define DX_HOST_IRR_AHB_ERR_INT_BIT_SHIFT 0x8UL 23 #define DX_HOST_IRR_AHB_ERR_INT_BIT_SIZE 0x1UL 24 #define DX_HOST_IRR_PKA_EXP_INT_BIT_SHIFT 0x9UL 25 #define DX_HOST_IRR_PKA_EXP_INT_BIT_SIZE 0x1UL 26 #define DX_HOST_IRR_RNG_INT_BIT_SHIFT 0xAUL 27 #define DX_HOST_IRR_RNG_INT_BIT_SIZE 0x1UL 28 #define DX_HOST_IRR_SYM_DMA_COMPLETED_BIT_SHIFT 0xBUL 29 #define DX_HOST_IRR_SYM_DMA_COMPLETED_BIT_SIZE 0x1UL 30 #define DX_HOST_IMR_REG_OFFSET 0x0A04UL 31 #define DX_HOST_IMR_SRAM_TO_DIN_MASK_BIT_SHIFT 0x4UL 32 #define DX_HOST_IMR_SRAM_TO_DIN_MASK_BIT_SIZE 0x1UL 33 #define DX_HOST_IMR_DOUT_TO_SRAM_MASK_BIT_SHIFT 0x5UL 34 #define DX_HOST_IMR_DOUT_TO_SRAM_MASK_BIT_SIZE 0x1UL 35 #define DX_HOST_IMR_MEM_TO_DIN_MASK_BIT_SHIFT 0x6UL 36 #define DX_HOST_IMR_MEM_TO_DIN_MASK_BIT_SIZE 0x1UL 37 #define DX_HOST_IMR_DOUT_TO_MEM_MASK_BIT_SHIFT 0x7UL 38 #define DX_HOST_IMR_DOUT_TO_MEM_MASK_BIT_SIZE 0x1UL 39 #define DX_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL 40 #define DX_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL 41 #define DX_HOST_IMR_PKA_EXP_MASK_BIT_SHIFT 0x9UL 42 #define DX_HOST_IMR_PKA_EXP_MASK_BIT_SIZE 0x1UL 43 #define DX_HOST_IMR_RNG_INT_MASK_BIT_SHIFT 0xAUL 44 #define DX_HOST_IMR_RNG_INT_MASK_BIT_SIZE 0x1UL 45 #define DX_HOST_IMR_SYM_DMA_COMPLETED_MASK_BIT_SHIFT 0xBUL 46 #define DX_HOST_IMR_SYM_DMA_COMPLETED_MASK_BIT_SIZE 0x1UL 47 #define DX_HOST_ICR_REG_OFFSET 0x0A08UL 48 #define DX_HOST_ICR_SRAM_TO_DIN_CLEAR_BIT_SHIFT 0x4UL 49 #define DX_HOST_ICR_SRAM_TO_DIN_CLEAR_BIT_SIZE 0x1UL 50 #define DX_HOST_ICR_DOUT_TO_SRAM_CLEAR_BIT_SHIFT 0x5UL 51 #define DX_HOST_ICR_DOUT_TO_SRAM_CLEAR_BIT_SIZE 0x1UL 52 #define DX_HOST_ICR_MEM_TO_DIN_CLEAR_BIT_SHIFT 0x6UL 53 #define DX_HOST_ICR_MEM_TO_DIN_CLEAR_BIT_SIZE 0x1UL 54 #define DX_HOST_ICR_DOUT_TO_MEM_CLEAR_BIT_SHIFT 0x7UL 55 #define DX_HOST_ICR_DOUT_TO_MEM_CLEAR_BIT_SIZE 0x1UL 56 #define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL 57 #define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE 0x1UL 58 #define DX_HOST_ICR_PKA_EXP_CLEAR_BIT_SHIFT 0x9UL 59 #define DX_HOST_ICR_PKA_EXP_CLEAR_BIT_SIZE 0x1UL 60 #define DX_HOST_ICR_RNG_INT_CLEAR_BIT_SHIFT 0xAUL 61 #define DX_HOST_ICR_RNG_INT_CLEAR_BIT_SIZE 0x1UL 62 #define DX_HOST_ICR_SYM_DMA_COMPLETED_CLEAR_BIT_SHIFT 0xBUL 63 #define DX_HOST_ICR_SYM_DMA_COMPLETED_CLEAR_BIT_SIZE 0x1UL 64 #define DX_HOST_ENDIAN_REG_OFFSET 0x0A0CUL 65 #define DX_HOST_ENDIAN_DOUT_WR_BG_BIT_SHIFT 0x3UL 66 #define DX_HOST_ENDIAN_DOUT_WR_BG_BIT_SIZE 0x1UL 67 #define DX_HOST_ENDIAN_DIN_RD_BG_BIT_SHIFT 0x7UL 68 #define DX_HOST_ENDIAN_DIN_RD_BG_BIT_SIZE 0x1UL 69 #define DX_HOST_ENDIAN_DOUT_WR_WBG_BIT_SHIFT 0xBUL 70 #define DX_HOST_ENDIAN_DOUT_WR_WBG_BIT_SIZE 0x1UL 71 #define DX_HOST_ENDIAN_DIN_RD_WBG_BIT_SHIFT 0xFUL 72 #define DX_HOST_ENDIAN_DIN_RD_WBG_BIT_SIZE 0x1UL 73 #define DX_HOST_SIGNATURE_REG_OFFSET 0x0A24UL 74 #define DX_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL 75 #define DX_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL 76 #define DX_HOST_BOOT_REG_OFFSET 0x0A28UL 77 #define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0x0UL 78 #define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL 79 #define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL 80 #define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL 81 #define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT 0x2UL 82 #define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE 0x1UL 83 #define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT 0x3UL 84 #define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE 0x1UL 85 #define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT 0x5UL 86 #define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE 0x1UL 87 #define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL 88 #define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE 0x3UL 89 #define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT 0x9UL 90 #define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE 0x1UL 91 #define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT 0xAUL 92 #define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL 93 #define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT 0xBUL 94 #define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE 0x1UL 95 #define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT 0xCUL 96 #define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL 97 #define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT 0xDUL 98 #define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE 0x1UL 99 #define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT 0xEUL 100 #define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE 0x1UL 101 #define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT 0xFUL 102 #define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE 0x1UL 103 #define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT 0x10UL 104 #define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE 0x1UL 105 #define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT 0x11UL 106 #define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE 0x1UL 107 #define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT 0x12UL 108 #define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE 0x1UL 109 #define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT 0x13UL 110 #define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE 0x1UL 111 #define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT 0x14UL 112 #define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE 0x1UL 113 #define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT 0x15UL 114 #define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE 0x1UL 115 #define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT 0x16UL 116 #define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE 0x1UL 117 #define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL 118 #define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE 0x1UL 119 #define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT 0x18UL 120 #define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE 0x1UL 121 #define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT 0x19UL 122 #define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE 0x1UL 123 #define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT 0x1AUL 124 #define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE 0x1UL 125 #define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT 0x1BUL 126 #define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE 0x1UL 127 #define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT 0x1CUL 128 #define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE 0x1UL 129 #define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT 0x1DUL 130 #define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL 131 #define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL 132 #define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL 133 #define DX_HOST_CRYPTOKEY_SEL_REG_OFFSET 0x0A38UL 134 #define DX_HOST_CRYPTOKEY_SEL_VALUE_BIT_SHIFT 0x0UL 135 #define DX_HOST_CRYPTOKEY_SEL_VALUE_BIT_SIZE 0x3UL 136 #define DX_HOST_CORE_CLK_GATING_ENABLE_REG_OFFSET 0x0A78UL 137 #define DX_HOST_CORE_CLK_GATING_ENABLE_VALUE_BIT_SHIFT 0x0UL 138 #define DX_HOST_CORE_CLK_GATING_ENABLE_VALUE_BIT_SIZE 0x1UL 139 #define DX_HOST_CC_IS_IDLE_REG_OFFSET 0x0A7CUL 140 #define DX_HOST_CC_IS_IDLE_HOST_CC_IS_IDLE_BIT_SHIFT 0x0UL 141 #define DX_HOST_CC_IS_IDLE_HOST_CC_IS_IDLE_BIT_SIZE 0x1UL 142 #define DX_HOST_CC_IS_IDLE_HOST_CC_IS_IDLE_EVENT_BIT_SHIFT 0x1UL 143 #define DX_HOST_CC_IS_IDLE_HOST_CC_IS_IDLE_EVENT_BIT_SIZE 0x1UL 144 #define DX_HOST_CC_IS_IDLE_SYM_IS_BUSY_BIT_SHIFT 0x2UL 145 #define DX_HOST_CC_IS_IDLE_SYM_IS_BUSY_BIT_SIZE 0x1UL 146 #define DX_HOST_CC_IS_IDLE_AHB_IS_IDLE_BIT_SHIFT 0x3UL 147 #define DX_HOST_CC_IS_IDLE_AHB_IS_IDLE_BIT_SIZE 0x1UL 148 #define DX_HOST_CC_IS_IDLE_NVM_ARB_IS_IDLE_BIT_SHIFT 0x4UL 149 #define DX_HOST_CC_IS_IDLE_NVM_ARB_IS_IDLE_BIT_SIZE 0x1UL 150 #define DX_HOST_CC_IS_IDLE_NVM_IS_IDLE_BIT_SHIFT 0x5UL 151 #define DX_HOST_CC_IS_IDLE_NVM_IS_IDLE_BIT_SIZE 0x1UL 152 #define DX_HOST_CC_IS_IDLE_FATAL_WR_BIT_SHIFT 0x6UL 153 #define DX_HOST_CC_IS_IDLE_FATAL_WR_BIT_SIZE 0x1UL 154 #define DX_HOST_CC_IS_IDLE_RNG_IS_IDLE_BIT_SHIFT 0x7UL 155 #define DX_HOST_CC_IS_IDLE_RNG_IS_IDLE_BIT_SIZE 0x1UL 156 #define DX_HOST_CC_IS_IDLE_PKA_IS_IDLE_BIT_SHIFT 0x8UL 157 #define DX_HOST_CC_IS_IDLE_PKA_IS_IDLE_BIT_SIZE 0x1UL 158 #define DX_HOST_CC_IS_IDLE_CRYPTO_IS_IDLE_BIT_SHIFT 0x9UL 159 #define DX_HOST_CC_IS_IDLE_CRYPTO_IS_IDLE_BIT_SIZE 0x1UL 160 #define DX_HOST_POWERDOWN_REG_OFFSET 0x0A80UL 161 #define DX_HOST_POWERDOWN_VALUE_BIT_SHIFT 0x0UL 162 #define DX_HOST_POWERDOWN_VALUE_BIT_SIZE 0x1UL 163 #define DX_HOST_REMOVE_GHASH_ENGINE_REG_OFFSET 0x0A84UL 164 #define DX_HOST_REMOVE_GHASH_ENGINE_VALUE_BIT_SHIFT 0x0UL 165 #define DX_HOST_REMOVE_GHASH_ENGINE_VALUE_BIT_SIZE 0x1UL 166 #define DX_HOST_REMOVE_CHACHA_ENGINE_REG_OFFSET 0x0A88UL 167 #define DX_HOST_REMOVE_CHACHA_ENGINE_VALUE_BIT_SHIFT 0x0UL 168 #define DX_HOST_REMOVE_CHACHA_ENGINE_VALUE_BIT_SIZE 0x1UL 169 // -------------------------------------- 170 // BLOCK: HOST_SRAM 171 // -------------------------------------- 172 #define DX_SRAM_DATA_REG_OFFSET 0x0F00UL 173 #define DX_SRAM_DATA_VALUE_BIT_SHIFT 0x0UL 174 #define DX_SRAM_DATA_VALUE_BIT_SIZE 0x20UL 175 #define DX_SRAM_ADDR_REG_OFFSET 0x0F04UL 176 #define DX_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL 177 #define DX_SRAM_ADDR_VALUE_BIT_SIZE 0xFUL 178 #define DX_SRAM_DATA_READY_REG_OFFSET 0x0F08UL 179 #define DX_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL 180 #define DX_SRAM_DATA_READY_VALUE_BIT_SIZE 0x1UL 181 #endif //__DX_HOST_H__ 182
