1 /* 2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __DX_ENV_H__ 8 #define __DX_ENV_H__ 9 10 // -------------------------------------- 11 // BLOCK: FPGA_ENV_REGS 12 // -------------------------------------- 13 #define DX_ENV_PKA_DEBUG_MODE_REG_OFFSET 0x024UL 14 #define DX_ENV_PKA_DEBUG_MODE_VALUE_BIT_SHIFT 0x0UL 15 #define DX_ENV_PKA_DEBUG_MODE_VALUE_BIT_SIZE 0x1UL 16 #define DX_ENV_SCAN_MODE_REG_OFFSET 0x030UL 17 #define DX_ENV_SCAN_MODE_VALUE_BIT_SHIFT 0x0UL 18 #define DX_ENV_SCAN_MODE_VALUE_BIT_SIZE 0x1UL 19 #define DX_ENV_CC_ALLOW_SCAN_REG_OFFSET 0x034UL 20 #define DX_ENV_CC_ALLOW_SCAN_VALUE_BIT_SHIFT 0x0UL 21 #define DX_ENV_CC_ALLOW_SCAN_VALUE_BIT_SIZE 0x1UL 22 #define DX_ENV_CC_HOST_INT_REG_OFFSET 0x0A0UL 23 #define DX_ENV_CC_HOST_INT_VALUE_BIT_SHIFT 0x0UL 24 #define DX_ENV_CC_HOST_INT_VALUE_BIT_SIZE 0x1UL 25 #define DX_ENV_CC_PUB_HOST_INT_REG_OFFSET 0x0A4UL 26 #define DX_ENV_CC_PUB_HOST_INT_VALUE_BIT_SHIFT 0x0UL 27 #define DX_ENV_CC_PUB_HOST_INT_VALUE_BIT_SIZE 0x1UL 28 #define DX_ENV_CC_RST_N_REG_OFFSET 0x0A8UL 29 #define DX_ENV_CC_RST_N_VALUE_BIT_SHIFT 0x0UL 30 #define DX_ENV_CC_RST_N_VALUE_BIT_SIZE 0x1UL 31 #define DX_ENV_RST_OVERRIDE_REG_OFFSET 0x0ACUL 32 #define DX_ENV_RST_OVERRIDE_VALUE_BIT_SHIFT 0x0UL 33 #define DX_ENV_RST_OVERRIDE_VALUE_BIT_SIZE 0x1UL 34 #define DX_ENV_CC_POR_N_ADDR_REG_OFFSET 0x0E0UL 35 #define DX_ENV_CC_POR_N_ADDR_VALUE_BIT_SHIFT 0x0UL 36 #define DX_ENV_CC_POR_N_ADDR_VALUE_BIT_SIZE 0x1UL 37 #define DX_ENV_CC_COLD_RST_REG_OFFSET 0x0FCUL 38 #define DX_ENV_CC_COLD_RST_VALUE_BIT_SHIFT 0x0UL 39 #define DX_ENV_CC_COLD_RST_VALUE_BIT_SIZE 0x1UL 40 #define DX_ENV_DUMMY_ADDR_REG_OFFSET 0x108UL 41 #define DX_ENV_DUMMY_ADDR_VALUE_BIT_SHIFT 0x0UL 42 #define DX_ENV_DUMMY_ADDR_VALUE_BIT_SIZE 0x20UL 43 #define DX_ENV_COUNTER_CLR_REG_OFFSET 0x118UL 44 #define DX_ENV_COUNTER_CLR_VALUE_BIT_SHIFT 0x0UL 45 #define DX_ENV_COUNTER_CLR_VALUE_BIT_SIZE 0x1UL 46 #define DX_ENV_COUNTER_RD_REG_OFFSET 0x11CUL 47 #define DX_ENV_COUNTER_RD_VALUE_BIT_SHIFT 0x0UL 48 #define DX_ENV_COUNTER_RD_VALUE_BIT_SIZE 0x20UL 49 #define DX_ENV_RNG_DEBUG_ENABLE_REG_OFFSET 0x430UL 50 #define DX_ENV_RNG_DEBUG_ENABLE_VALUE_BIT_SHIFT 0x0UL 51 #define DX_ENV_RNG_DEBUG_ENABLE_VALUE_BIT_SIZE 0x1UL 52 #define DX_ENV_CC_LCS_REG_OFFSET 0x43CUL 53 #define DX_ENV_CC_LCS_VALUE_BIT_SHIFT 0x0UL 54 #define DX_ENV_CC_LCS_VALUE_BIT_SIZE 0x8UL 55 #define DX_ENV_CC_IS_CM_DM_SECURE_RMA_REG_OFFSET 0x440UL 56 #define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_CM_BIT_SHIFT 0x0UL 57 #define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_CM_BIT_SIZE 0x1UL 58 #define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_DM_BIT_SHIFT 0x1UL 59 #define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_DM_BIT_SIZE 0x1UL 60 #define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_SECURE_BIT_SHIFT 0x2UL 61 #define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_SECURE_BIT_SIZE 0x1UL 62 #define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_RMA_BIT_SHIFT 0x3UL 63 #define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_RMA_BIT_SIZE 0x1UL 64 #define DX_ENV_DCU_EN_REG_OFFSET 0x444UL 65 #define DX_ENV_DCU_EN_VALUE_BIT_SHIFT 0x0UL 66 #define DX_ENV_DCU_EN_VALUE_BIT_SIZE 0x20UL 67 #define DX_ENV_CC_LCS_IS_VALID_REG_OFFSET 0x448UL 68 #define DX_ENV_CC_LCS_IS_VALID_VALUE_BIT_SHIFT 0x0UL 69 #define DX_ENV_CC_LCS_IS_VALID_VALUE_BIT_SIZE 0x1UL 70 #define DX_ENV_POWER_DOWN_REG_OFFSET 0x478UL 71 #define DX_ENV_POWER_DOWN_VALUE_BIT_SHIFT 0x0UL 72 #define DX_ENV_POWER_DOWN_VALUE_BIT_SIZE 0x20UL 73 #define DX_ENV_DCU_H_EN_REG_OFFSET 0x484UL 74 #define DX_ENV_DCU_H_EN_VALUE_BIT_SHIFT 0x0UL 75 #define DX_ENV_DCU_H_EN_VALUE_BIT_SIZE 0x20UL 76 #define DX_ENV_VERSION_REG_OFFSET 0x488UL 77 #define DX_ENV_VERSION_VALUE_BIT_SHIFT 0x0UL 78 #define DX_ENV_VERSION_VALUE_BIT_SIZE 0x20UL 79 #define DX_ENV_ROSC_WRITE_REG_OFFSET 0x48CUL 80 #define DX_ENV_ROSC_WRITE_VALUE_BIT_SHIFT 0x0UL 81 #define DX_ENV_ROSC_WRITE_VALUE_BIT_SIZE 0x1UL 82 #define DX_ENV_ROSC_ADDR_REG_OFFSET 0x490UL 83 #define DX_ENV_ROSC_ADDR_VALUE_BIT_SHIFT 0x0UL 84 #define DX_ENV_ROSC_ADDR_VALUE_BIT_SIZE 0x8UL 85 #define DX_ENV_RESET_SESSION_KEY_REG_OFFSET 0x494UL 86 #define DX_ENV_RESET_SESSION_KEY_VALUE_BIT_SHIFT 0x0UL 87 #define DX_ENV_RESET_SESSION_KEY_VALUE_BIT_SIZE 0x1UL 88 #define DX_ENV_SESSION_KEY_0_REG_OFFSET 0x4A0UL 89 #define DX_ENV_SESSION_KEY_0_VALUE_BIT_SHIFT 0x0UL 90 #define DX_ENV_SESSION_KEY_0_VALUE_BIT_SIZE 0x20UL 91 #define DX_ENV_SESSION_KEY_1_REG_OFFSET 0x4A4UL 92 #define DX_ENV_SESSION_KEY_1_VALUE_BIT_SHIFT 0x0UL 93 #define DX_ENV_SESSION_KEY_1_VALUE_BIT_SIZE 0x20UL 94 #define DX_ENV_SESSION_KEY_2_REG_OFFSET 0x4A8UL 95 #define DX_ENV_SESSION_KEY_2_VALUE_BIT_SHIFT 0x0UL 96 #define DX_ENV_SESSION_KEY_2_VALUE_BIT_SIZE 0x20UL 97 #define DX_ENV_SESSION_KEY_3_REG_OFFSET 0x4ACUL 98 #define DX_ENV_SESSION_KEY_3_VALUE_BIT_SHIFT 0x0UL 99 #define DX_ENV_SESSION_KEY_3_VALUE_BIT_SIZE 0x20UL 100 #define DX_ENV_SESSION_KEY_VALID_REG_OFFSET 0x4B0UL 101 #define DX_ENV_SESSION_KEY_VALID_VALUE_BIT_SHIFT 0x0UL 102 #define DX_ENV_SESSION_KEY_VALID_VALUE_BIT_SIZE 0x1UL 103 #define DX_ENV_SPIDEN_REG_OFFSET 0x4D0UL 104 #define DX_ENV_SPIDEN_VALUE_BIT_SHIFT 0x0UL 105 #define DX_ENV_SPIDEN_VALUE_BIT_SIZE 0x1UL 106 #define DX_ENV_AXIM_USER_PARAMS_REG_OFFSET 0x600UL 107 #define DX_ENV_AXIM_USER_PARAMS_ARUSER_BIT_SHIFT 0x0UL 108 #define DX_ENV_AXIM_USER_PARAMS_ARUSER_BIT_SIZE 0x5UL 109 #define DX_ENV_AXIM_USER_PARAMS_AWUSER_BIT_SHIFT 0x5UL 110 #define DX_ENV_AXIM_USER_PARAMS_AWUSER_BIT_SIZE 0x5UL 111 #define DX_ENV_SECURITY_MODE_OVERRIDE_REG_OFFSET 0x604UL 112 #define DX_ENV_SECURITY_MODE_OVERRIDE_AWPROT_NS_BIT_BIT_SHIFT 0x0UL 113 #define DX_ENV_SECURITY_MODE_OVERRIDE_AWPROT_NS_BIT_BIT_SIZE 0x1UL 114 #define DX_ENV_SECURITY_MODE_OVERRIDE_AWPROT_NS_OVERRIDE_BIT_SHIFT 0x1UL 115 #define DX_ENV_SECURITY_MODE_OVERRIDE_AWPROT_NS_OVERRIDE_BIT_SIZE 0x1UL 116 #define DX_ENV_SECURITY_MODE_OVERRIDE_ARPROT_NS_BIT_BIT_SHIFT 0x2UL 117 #define DX_ENV_SECURITY_MODE_OVERRIDE_ARPROT_NS_BIT_BIT_SIZE 0x1UL 118 #define DX_ENV_SECURITY_MODE_OVERRIDE_ARPROT_NS_OVERRIDE_BIT_SHIFT 0x3UL 119 #define DX_ENV_SECURITY_MODE_OVERRIDE_ARPROT_NS_OVERRIDE_BIT_SIZE 0x1UL 120 #define DX_ENV_SRAM_ENABLE_REG_OFFSET 0x608UL 121 #define DX_ENV_SRAM_ENABLE_VALUE_BIT_SHIFT 0x0UL 122 #define DX_ENV_SRAM_ENABLE_VALUE_BIT_SIZE 0x1UL 123 #define DX_ENV_APB_FIPS_ADDR_REG_OFFSET 0x650UL 124 #define DX_ENV_APB_FIPS_ADDR_VALUE_BIT_SHIFT 0x0UL 125 #define DX_ENV_APB_FIPS_ADDR_VALUE_BIT_SIZE 0xCUL 126 #define DX_ENV_APB_FIPS_VAL_REG_OFFSET 0x654UL 127 #define DX_ENV_APB_FIPS_VAL_VALUE_BIT_SHIFT 0x0UL 128 #define DX_ENV_APB_FIPS_VAL_VALUE_BIT_SIZE 0x20UL 129 #define DX_ENV_APB_FIPS_MASK_REG_OFFSET 0x658UL 130 #define DX_ENV_APB_FIPS_MASK_VALUE_BIT_SHIFT 0x0UL 131 #define DX_ENV_APB_FIPS_MASK_VALUE_BIT_SIZE 0x20UL 132 #define DX_ENV_APB_FIPS_CNT_REG_OFFSET 0x65CUL 133 #define DX_ENV_APB_FIPS_CNT_VALUE_BIT_SHIFT 0x0UL 134 #define DX_ENV_APB_FIPS_CNT_VALUE_BIT_SIZE 0x20UL 135 #define DX_ENV_APB_FIPS_NEW_ADDR_REG_OFFSET 0x660UL 136 #define DX_ENV_APB_FIPS_NEW_ADDR_VALUE_BIT_SHIFT 0x0UL 137 #define DX_ENV_APB_FIPS_NEW_ADDR_VALUE_BIT_SIZE 0xCUL 138 #define DX_ENV_APB_FIPS_NEW_VAL_REG_OFFSET 0x664UL 139 #define DX_ENV_APB_FIPS_NEW_VAL_VALUE_BIT_SHIFT 0x0UL 140 #define DX_ENV_APB_FIPS_NEW_VAL_VALUE_BIT_SIZE 0x20UL 141 #define DX_ENV_APB_PPROT_OVERRIDE_REG_OFFSET 0x668UL 142 #define DX_ENV_APB_PPROT_OVERRIDE_PPROT_OVERRIDE_VAL_BIT_SHIFT 0x0UL 143 #define DX_ENV_APB_PPROT_OVERRIDE_PPROT_OVERRIDE_VAL_BIT_SIZE 0x3UL 144 #define DX_ENV_APB_PPROT_OVERRIDE_PPROT_OVERRIDE_CNTL_BIT_SHIFT 0x3UL 145 #define DX_ENV_APB_PPROT_OVERRIDE_PPROT_OVERRIDE_CNTL_BIT_SIZE 0x1UL 146 #define DX_ENV_APBSC_FIPS_ADDR_REG_OFFSET 0x670UL 147 #define DX_ENV_APBSC_FIPS_ADDR_VALUE_BIT_SHIFT 0x0UL 148 #define DX_ENV_APBSC_FIPS_ADDR_VALUE_BIT_SIZE 0xCUL 149 #define DX_ENV_APBSC_FIPS_VAL_REG_OFFSET 0x674UL 150 #define DX_ENV_APBSC_FIPS_VAL_VALUE_BIT_SHIFT 0x0UL 151 #define DX_ENV_APBSC_FIPS_VAL_VALUE_BIT_SIZE 0x20UL 152 #define DX_ENV_APBSC_FIPS_MASK_REG_OFFSET 0x678UL 153 #define DX_ENV_APBSC_FIPS_MASK_VALUE_BIT_SHIFT 0x0UL 154 #define DX_ENV_APBSC_FIPS_MASK_VALUE_BIT_SIZE 0x20UL 155 #define DX_ENV_APBSC_FIPS_CNT_REG_OFFSET 0x67CUL 156 #define DX_ENV_APBSC_FIPS_CNT_VALUE_BIT_SHIFT 0x0UL 157 #define DX_ENV_APBSC_FIPS_CNT_VALUE_BIT_SIZE 0x20UL 158 #define DX_ENV_APBSC_FIPS_NEW_ADDR_REG_OFFSET 0x680UL 159 #define DX_ENV_APBSC_FIPS_NEW_ADDR_VALUE_BIT_SHIFT 0x0UL 160 #define DX_ENV_APBSC_FIPS_NEW_ADDR_VALUE_BIT_SIZE 0xCUL 161 #define DX_ENV_APBSC_FIPS_NEW_VAL_REG_OFFSET 0x684UL 162 #define DX_ENV_APBSC_FIPS_NEW_VAL_VALUE_BIT_SHIFT 0x0UL 163 #define DX_ENV_APBSC_FIPS_NEW_VAL_VALUE_BIT_SIZE 0x20UL 164 #define DX_ENV_APBSC_PPROT_OVERRIDE_REG_OFFSET 0x688UL 165 #define DX_ENV_APBSC_PPROT_OVERRIDE_PPROT_OVERRIDE_VAL_BIT_SHIFT 0x0UL 166 #define DX_ENV_APBSC_PPROT_OVERRIDE_PPROT_OVERRIDE_VAL_BIT_SIZE 0x3UL 167 #define DX_ENV_APBSC_PPROT_OVERRIDE_PPROT_OVERRIDE_CNTL_BIT_SHIFT 0x3UL 168 #define DX_ENV_APBSC_PPROT_OVERRIDE_PPROT_OVERRIDE_CNTL_BIT_SIZE 0x1UL 169 #define DX_ENV_AO_CC_GPPC_REG_OFFSET 0x700UL 170 #define DX_ENV_AO_CC_GPPC_VALUE_BIT_SHIFT 0x0UL 171 #define DX_ENV_AO_CC_GPPC_VALUE_BIT_SIZE 0x8UL 172 #define DX_ENV_AHBM_HPROT_OVERRIDE_REG_OFFSET 0x704UL 173 #define DX_ENV_AHBM_HPROT_OVERRIDE_PPROT_OVERRIDE_VAL_BIT_SHIFT 0x0UL 174 #define DX_ENV_AHBM_HPROT_OVERRIDE_PPROT_OVERRIDE_VAL_BIT_SIZE 0x3UL 175 #define DX_ENV_AHBM_HPROT_OVERRIDE_PPROT_OVERRIDE_CNTL_BIT_SHIFT 0x3UL 176 #define DX_ENV_AHBM_HPROT_OVERRIDE_PPROT_OVERRIDE_CNTL_BIT_SIZE 0x1UL 177 #define DX_ENV_CC_IS_IDLE_REG_OFFSET 0x708UL 178 #define DX_ENV_CC_IS_IDLE_VALUE_BIT_SHIFT 0x0UL 179 #define DX_ENV_CC_IS_IDLE_VALUE_BIT_SIZE 0x1UL 180 #define DX_ENV_CC_POWERDOWN_RDY_REG_OFFSET 0x70CUL 181 #define DX_ENV_CC_POWERDOWN_RDY_VALUE_BIT_SHIFT 0x0UL 182 #define DX_ENV_CC_POWERDOWN_RDY_VALUE_BIT_SIZE 0x1UL 183 #define DX_ENV_CC_STATIC_CFG_REG_OFFSET 0x710UL 184 #define DX_ENV_CC_STATIC_CFG_USER_OTP_FILTERING_DISABLE_BIT_SHIFT 0x0UL 185 #define DX_ENV_CC_STATIC_CFG_USER_OTP_FILTERING_DISABLE_BIT_SIZE 0x1UL 186 #define DX_ENV_CC_STATIC_CFG_REMOVE_GHASH_ENGINE_BIT_SHIFT 0x1UL 187 #define DX_ENV_CC_STATIC_CFG_REMOVE_GHASH_ENGINE_BIT_SIZE 0x1UL 188 #define DX_ENV_CC_STATIC_CFG_REMOVE_CHACHA_ENGINE_BIT_SHIFT 0x2UL 189 #define DX_ENV_CC_STATIC_CFG_REMOVE_CHACHA_ENGINE_BIT_SIZE 0x1UL 190 #define DX_ENV_FUSE_AIB_1K_OFFSET_REG_OFFSET 0x714UL 191 #define DX_ENV_FUSE_AIB_1K_OFFSET_VALUE_BIT_SHIFT 0x0UL 192 #define DX_ENV_FUSE_AIB_1K_OFFSET_VALUE_BIT_SIZE 0x2UL 193 #define DX_ENV_CC_IS_IDLE_CNTR_REG_OFFSET 0x720UL 194 #define DX_ENV_CC_IS_IDLE_CNTR_VALUE_BIT_SHIFT 0x0UL 195 #define DX_ENV_CC_IS_IDLE_CNTR_VALUE_BIT_SIZE 0x20UL 196 197 // -------------------------------------- 198 // BLOCK: ENV_CC_MEMORIES 199 // -------------------------------------- 200 #define DX_ENV_FUSE_READY_REG_OFFSET 0x0000UL 201 #define DX_ENV_FUSE_READY_VALUE_BIT_SHIFT 0x0UL 202 #define DX_ENV_FUSE_READY_VALUE_BIT_SIZE 0x1UL 203 #define DX_ENV_PERF_RAM_MASTER_REG_OFFSET 0x00ECUL 204 #define DX_ENV_PERF_RAM_MASTER_VALUE_BIT_SHIFT 0x0UL 205 #define DX_ENV_PERF_RAM_MASTER_VALUE_BIT_SIZE 0x1UL 206 #define DX_ENV_PERF_RAM_ADDR_HIGH4_REG_OFFSET 0x00F0UL 207 #define DX_ENV_PERF_RAM_ADDR_HIGH4_VALUE_BIT_SHIFT 0x0UL 208 #define DX_ENV_PERF_RAM_ADDR_HIGH4_VALUE_BIT_SIZE 0x2UL 209 #define DX_ENV_FUSES_RAM_REG_OFFSET 0x03ECUL 210 #define DX_ENV_FUSES_RAM_VALUE_BIT_SHIFT 0x0UL 211 #define DX_ENV_FUSES_RAM_VALUE_BIT_SIZE 0x20UL 212 // -------------------------------------- 213 // BLOCK: ENV_PERF_RAM_BASE 214 // -------------------------------------- 215 #define DX_ENV_PERF_RAM_BASE_REG_OFFSET 0x0000UL 216 #define DX_ENV_PERF_RAM_BASE_VALUE_BIT_SHIFT 0x0UL 217 #define DX_ENV_PERF_RAM_BASE_VALUE_BIT_SIZE 0x20UL 218 219 #endif /*__DX_ENV_H__*/ 220 221
