1 /*
2  * Copyright 2023 NXP
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_
9 
10 #define NXP_S32_FIRC_CLK                           1U
11 #define NXP_S32_FXOSC_CLK                          2U
12 #define NXP_S32_SIRC_CLK                           3U
13 #define NXP_S32_COREPLL_CLK                        4U
14 #define NXP_S32_PERIPHPLL_CLK                      5U
15 #define NXP_S32_DDRPLL_CLK                         6U
16 #define NXP_S32_LFAST0_PLL_CLK                     7U
17 #define NXP_S32_LFAST1_PLL_CLK                     8U
18 #define NXP_S32_COREPLL_PHI0_CLK                   9U
19 #define NXP_S32_COREPLL_DFS0_CLK                   10U
20 #define NXP_S32_COREPLL_DFS1_CLK                   11U
21 #define NXP_S32_COREPLL_DFS2_CLK                   12U
22 #define NXP_S32_COREPLL_DFS3_CLK                   13U
23 #define NXP_S32_COREPLL_DFS4_CLK                   14U
24 #define NXP_S32_COREPLL_DFS5_CLK                   15U
25 #define NXP_S32_PERIPHPLL_PHI0_CLK                 16U
26 #define NXP_S32_PERIPHPLL_PHI1_CLK                 17U
27 #define NXP_S32_PERIPHPLL_PHI2_CLK                 18U
28 #define NXP_S32_PERIPHPLL_PHI3_CLK                 19U
29 #define NXP_S32_PERIPHPLL_PHI4_CLK                 20U
30 #define NXP_S32_PERIPHPLL_PHI5_CLK                 21U
31 #define NXP_S32_PERIPHPLL_PHI6_CLK                 22U
32 #define NXP_S32_PERIPHPLL_DFS0_CLK                 23U
33 #define NXP_S32_PERIPHPLL_DFS1_CLK                 24U
34 #define NXP_S32_PERIPHPLL_DFS2_CLK                 25U
35 #define NXP_S32_PERIPHPLL_DFS3_CLK                 26U
36 #define NXP_S32_PERIPHPLL_DFS4_CLK                 27U
37 #define NXP_S32_PERIPHPLL_DFS5_CLK                 28U
38 #define NXP_S32_DDRPLL_PHI0_CLK                    29U
39 #define NXP_S32_LFAST0_PLL_PH0_CLK                 30U
40 #define NXP_S32_LFAST1_PLL_PH0_CLK                 31U
41 #define NXP_S32_ETH_RGMII_REF_CLK                  32U
42 #define NXP_S32_ETH_EXT_TS_CLK                     33U
43 #define NXP_S32_ETH0_EXT_RX_CLK                    34U
44 #define NXP_S32_ETH0_EXT_TX_CLK                    35U
45 #define NXP_S32_ETH1_EXT_RX_CLK                    36U
46 #define NXP_S32_ETH1_EXT_TX_CLK                    37U
47 #define NXP_S32_LFAST0_EXT_REF_CLK                 38U
48 #define NXP_S32_LFAST1_EXT_REF_CLK                 39U
49 #define NXP_S32_DDR_CLK                            40U
50 #define NXP_S32_P0_SYS_CLK                         41U
51 #define NXP_S32_P1_SYS_CLK                         42U
52 #define NXP_S32_P1_SYS_DIV2_CLK                    43U
53 #define NXP_S32_P1_SYS_DIV4_CLK                    44U
54 #define NXP_S32_P2_SYS_CLK                         45U
55 #define NXP_S32_CORE_M33_CLK                       46U
56 #define NXP_S32_P2_SYS_DIV2_CLK                    47U
57 #define NXP_S32_P2_SYS_DIV4_CLK                    48U
58 #define NXP_S32_P3_SYS_CLK                         49U
59 #define NXP_S32_CE_SYS_DIV2_CLK                    50U
60 #define NXP_S32_CE_SYS_DIV4_CLK                    51U
61 #define NXP_S32_P3_SYS_DIV2_NOC_CLK                52U
62 #define NXP_S32_P3_SYS_DIV4_CLK                    53U
63 #define NXP_S32_P4_SYS_CLK                         54U
64 #define NXP_S32_P4_SYS_DIV2_CLK                    55U
65 #define NXP_S32_HSE_SYS_DIV2_CLK                   56U
66 #define NXP_S32_P5_SYS_CLK                         57U
67 #define NXP_S32_P5_SYS_DIV2_CLK                    58U
68 #define NXP_S32_P5_SYS_DIV4_CLK                    59U
69 #define NXP_S32_P2_MATH_CLK                        60U
70 #define NXP_S32_P2_MATH_DIV3_CLK                   61U
71 #define NXP_S32_GLB_LBIST_CLK                      62U
72 #define NXP_S32_RTU0_CORE_CLK                      63U
73 #define NXP_S32_RTU0_CORE_DIV2_CLK                 64U
74 #define NXP_S32_RTU1_CORE_CLK                      65U
75 #define NXP_S32_RTU1_CORE_DIV2_CLK                 66U
76 #define NXP_S32_P0_PSI5_S_UTIL_CLK                 67U
77 #define NXP_S32_P4_PSI5_S_UTIL_CLK                 68U
78 #define NXP_S32_ADC0_CLK                           70U
79 #define NXP_S32_ADC1_CLK                           71U
80 #define NXP_S32_CE_EDMA_CLK                        72U
81 #define NXP_S32_CE_PIT0_CLK                        73U
82 #define NXP_S32_CE_PIT1_CLK                        74U
83 #define NXP_S32_CE_PIT2_CLK                        75U
84 #define NXP_S32_CE_PIT3_CLK                        76U
85 #define NXP_S32_CE_PIT4_CLK                        77U
86 #define NXP_S32_CE_PIT5_CLK                        78U
87 #define NXP_S32_CLKOUT0_CLK                        79U
88 #define NXP_S32_CLKOUT1_CLK                        80U
89 #define NXP_S32_CLKOUT2_CLK                        81U
90 #define NXP_S32_CLKOUT3_CLK                        82U
91 #define NXP_S32_CLKOUT4_CLK                        83U
92 #define NXP_S32_CTU_CLK                            84U
93 #define NXP_S32_DMACRC0_CLK                        85U
94 #define NXP_S32_DMACRC1_CLK                        86U
95 #define NXP_S32_DMACRC4_CLK                        87U
96 #define NXP_S32_DMACRC5_CLK                        88U
97 #define NXP_S32_DMAMUX0_CLK                        89U
98 #define NXP_S32_DMAMUX1_CLK                        90U
99 #define NXP_S32_DMAMUX4_CLK                        91U
100 #define NXP_S32_DMAMUX5_CLK                        92U
101 #define NXP_S32_EDMA0_CLK                          93U
102 #define NXP_S32_EDMA1_CLK                          94U
103 #define NXP_S32_EDMA3_CLK                          95U
104 #define NXP_S32_EDMA4_CLK                          96U
105 #define NXP_S32_EDMA5_CLK                          97U
106 #define NXP_S32_ETH0_TX_MII_CLK                    98U
107 #define NXP_S32_ENET0_CLK                          99U
108 #define NXP_S32_P3_CAN_PE_CLK                      100U
109 #define NXP_S32_FLEXCAN0_CLK                       101U
110 #define NXP_S32_FLEXCAN1_CLK                       102U
111 #define NXP_S32_FLEXCAN2_CLK                       103U
112 #define NXP_S32_FLEXCAN3_CLK                       104U
113 #define NXP_S32_FLEXCAN4_CLK                       105U
114 #define NXP_S32_FLEXCAN5_CLK                       106U
115 #define NXP_S32_FLEXCAN6_CLK                       107U
116 #define NXP_S32_FLEXCAN7_CLK                       108U
117 #define NXP_S32_FLEXCAN8_CLK                       109U
118 #define NXP_S32_FLEXCAN9_CLK                       110U
119 #define NXP_S32_FLEXCAN10_CLK                      111U
120 #define NXP_S32_FLEXCAN11_CLK                      112U
121 #define NXP_S32_FLEXCAN12_CLK                      113U
122 #define NXP_S32_FLEXCAN13_CLK                      114U
123 #define NXP_S32_FLEXCAN14_CLK                      115U
124 #define NXP_S32_FLEXCAN15_CLK                      116U
125 #define NXP_S32_FLEXCAN16_CLK                      117U
126 #define NXP_S32_FLEXCAN17_CLK                      118U
127 #define NXP_S32_FLEXCAN18_CLK                      119U
128 #define NXP_S32_FLEXCAN19_CLK                      120U
129 #define NXP_S32_FLEXCAN20_CLK                      121U
130 #define NXP_S32_FLEXCAN21_CLK                      122U
131 #define NXP_S32_FLEXCAN22_CLK                      123U
132 #define NXP_S32_FLEXCAN23_CLK                      124U
133 #define NXP_S32_P0_FR_PE_CLK                       125U
134 #define NXP_S32_FRAY0_CLK                          126U
135 #define NXP_S32_FRAY1_CLK                          127U
136 #define NXP_S32_GTM_CLK                            128U
137 #define NXP_S32_IIIC0_CLK                          129U
138 #define NXP_S32_IIIC1_CLK                          130U
139 #define NXP_S32_IIIC2_CLK                          131U
140 #define NXP_S32_P0_LIN_BAUD_CLK                    132U
141 #define NXP_S32_LIN0_CLK                           133U
142 #define NXP_S32_LIN1_CLK                           134U
143 #define NXP_S32_LIN2_CLK                           135U
144 #define NXP_S32_P1_LIN_BAUD_CLK                    136U
145 #define NXP_S32_LIN3_CLK                           137U
146 #define NXP_S32_LIN4_CLK                           138U
147 #define NXP_S32_LIN5_CLK                           139U
148 #define NXP_S32_P4_LIN_BAUD_CLK                    140U
149 #define NXP_S32_LIN6_CLK                           141U
150 #define NXP_S32_LIN7_CLK                           142U
151 #define NXP_S32_LIN8_CLK                           143U
152 #define NXP_S32_P5_LIN_BAUD_CLK                    144U
153 #define NXP_S32_LIN9_CLK                           145U
154 #define NXP_S32_LIN10_CLK                          146U
155 #define NXP_S32_LIN11_CLK                          147U
156 #define NXP_S32_MSCDSPI_CLK                        148U
157 #define NXP_S32_MSCLIN_CLK                         149U
158 #define NXP_S32_NANO_CLK                           150U
159 #define NXP_S32_P0_CLKOUT_SRC_CLK                  151U
160 #define NXP_S32_P0_CTU_PER_CLK                     152U
161 #define NXP_S32_P0_DSPI_MSC_CLK                    153U
162 #define NXP_S32_P0_EMIOS_LCU_CLK                   154U
163 #define NXP_S32_P0_GTM_CLK                         155U
164 #define NXP_S32_P0_GTM_NOC_CLK                     156U
165 #define NXP_S32_P0_GTM_TS_CLK                      157U
166 #define NXP_S32_P0_LIN_CLK                         158U
167 #define NXP_S32_P0_NANO_CLK                        159U
168 #define NXP_S32_P0_PSI5_125K_CLK                   160U
169 #define NXP_S32_P0_PSI5_189K_CLK                   161U
170 #define NXP_S32_P0_PSI5_S_BAUD_CLK                 162U
171 #define NXP_S32_P0_PSI5_S_CORE_CLK                 163U
172 #define NXP_S32_P0_PSI5_S_TRIG0_CLK                164U
173 #define NXP_S32_P0_PSI5_S_TRIG1_CLK                165U
174 #define NXP_S32_P0_PSI5_S_TRIG2_CLK                166U
175 #define NXP_S32_P0_PSI5_S_TRIG3_CLK                167U
176 #define NXP_S32_P0_PSI5_S_UART_CLK                 168U
177 #define NXP_S32_P0_PSI5_S_WDOG0_CLK                169U
178 #define NXP_S32_P0_PSI5_S_WDOG1_CLK                170U
179 #define NXP_S32_P0_PSI5_S_WDOG2_CLK                171U
180 #define NXP_S32_P0_PSI5_S_WDOG3_CLK                172U
181 #define NXP_S32_P0_REG_INTF_2X_CLK                 173U
182 #define NXP_S32_P0_REG_INTF_CLK                    174U
183 #define NXP_S32_P1_CLKOUT_SRC_CLK                  175U
184 #define NXP_S32_P1_DSPI60_CLK                      176U
185 #define NXP_S32_ETH_TS_CLK                         177U
186 #define NXP_S32_ETH_TS_DIV4_CLK                    178U
187 #define NXP_S32_ETH0_REF_RMII_CLK                  179U
188 #define NXP_S32_ETH0_RX_MII_CLK                    180U
189 #define NXP_S32_ETH0_RX_RGMII_CLK                  181U
190 #define NXP_S32_ETH0_TX_RGMII_CLK                  182U
191 #define NXP_S32_ETH0_TX_RGMII_LPBK_CLK             183U
192 #define NXP_S32_ETH1_REF_RMII_CLK                  184U
193 #define NXP_S32_ETH1_RX_MII_CLK                    185U
194 #define NXP_S32_ETH1_RX_RGMII_CLK                  186U
195 #define NXP_S32_ETH1_TX_MII_CLK                    187U
196 #define NXP_S32_ETH1_TX_RGMII_CLK                  188U
197 #define NXP_S32_ETH1_TX_RGMII_LPBK_CLK             189U
198 #define NXP_S32_P1_LFAST0_REF_CLK                  190U
199 #define NXP_S32_P1_LFAST1_REF_CLK                  191U
200 #define NXP_S32_P1_LFAST_DFT_CLK                   192U
201 #define NXP_S32_P1_NETC_AXI_CLK                    193U
202 #define NXP_S32_P1_LIN_CLK                         194U
203 #define NXP_S32_P1_REG_INTF_CLK                    195U
204 #define NXP_S32_P2_DBG_ATB_CLK                     196U
205 #define NXP_S32_P2_REG_INTF_CLK                    197U
206 #define NXP_S32_P3_AES_CLK                         198U
207 #define NXP_S32_P3_CLKOUT_SRC_CLK                  199U
208 #define NXP_S32_P3_DBG_TS_CLK                      200U
209 #define NXP_S32_P3_REG_INTF_CLK                    201U
210 #define NXP_S32_P3_SYS_MON1_CLK                    202U
211 #define NXP_S32_P3_SYS_MON2_CLK                    203U
212 #define NXP_S32_P3_SYS_MON3_CLK                    204U
213 #define NXP_S32_P4_CLKOUT_SRC_CLK                  205U
214 #define NXP_S32_P4_DSPI60_CLK                      206U
215 #define NXP_S32_P4_EMIOS_LCU_CLK                   207U
216 #define NXP_S32_P4_LIN_CLK                         208U
217 #define NXP_S32_P4_PSI5_125K_CLK                   209U
218 #define NXP_S32_P4_PSI5_189K_CLK                   210U
219 #define NXP_S32_P4_PSI5_S_BAUD_CLK                 211U
220 #define NXP_S32_P4_PSI5_S_CORE_CLK                 212U
221 #define NXP_S32_P4_PSI5_S_TRIG0_CLK                213U
222 #define NXP_S32_P4_PSI5_S_TRIG1_CLK                214U
223 #define NXP_S32_P4_PSI5_S_TRIG2_CLK                215U
224 #define NXP_S32_P4_PSI5_S_TRIG3_CLK                216U
225 #define NXP_S32_P4_PSI5_S_UART_CLK                 217U
226 #define NXP_S32_P4_PSI5_S_WDOG0_CLK                218U
227 #define NXP_S32_P4_PSI5_S_WDOG1_CLK                219U
228 #define NXP_S32_P4_PSI5_S_WDOG2_CLK                220U
229 #define NXP_S32_P4_PSI5_S_WDOG3_CLK                221U
230 #define NXP_S32_P4_QSPI0_2X_CLK                    222U
231 #define NXP_S32_P4_QSPI0_1X_CLK                    223U
232 #define NXP_S32_P4_QSPI1_2X_CLK                    224U
233 #define NXP_S32_P4_QSPI1_1X_CLK                    225U
234 #define NXP_S32_P4_REG_INTF_2X_CLK                 226U
235 #define NXP_S32_P4_REG_INTF_CLK                    227U
236 #define NXP_S32_P4_SDHC_IP_CLK                     228U
237 #define NXP_S32_P4_SDHC_IP_DIV2_CLK                229U
238 #define NXP_S32_P5_DIPORT_CLK                      230U
239 #define NXP_S32_P5_AE_CLK                          231U
240 #define NXP_S32_P5_CANXL_PE_CLK                    232U
241 #define NXP_S32_P5_CANXL_CHI_CLK                   233U
242 #define NXP_S32_P5_CLKOUT_SRC_CLK                  234U
243 #define NXP_S32_P5_LIN_CLK                         235U
244 #define NXP_S32_P5_REG_INTF_CLK                    236U
245 #define NXP_S32_P6_REG_INTF_CLK                    237U
246 #define NXP_S32_PIT0_CLK                           238U
247 #define NXP_S32_PIT1_CLK                           239U
248 #define NXP_S32_PIT4_CLK                           240U
249 #define NXP_S32_PIT5_CLK                           241U
250 #define NXP_S32_P0_PSI5_1US_CLK                    242U
251 #define NXP_S32_PSI5_0_CLK                         243U
252 #define NXP_S32_P4_PSI5_1US_CLK                    244U
253 #define NXP_S32_PSI5_1_CLK                         245U
254 #define NXP_S32_PSI5S_0_CLK                        246U
255 #define NXP_S32_PSI5S_1_CLK                        247U
256 #define NXP_S32_QSPI0_CLK                          248U
257 #define NXP_S32_QSPI1_CLK                          249U
258 #define NXP_S32_RTU0_CORE_MON1_CLK                 250U
259 #define NXP_S32_RTU0_CORE_MON2_CLK                 251U
260 #define NXP_S32_RTU0_CORE_DIV2_MON1_CLK            252U
261 #define NXP_S32_RTU0_CORE_DIV2_MON2_CLK            253U
262 #define NXP_S32_RTU0_CORE_DIV2_MON3_CLK            254U
263 #define NXP_S32_RTU0_REG_INTF_CLK                  255U
264 #define NXP_S32_RTU1_CORE_MON1_CLK                 256U
265 #define NXP_S32_RTU1_CORE_MON2_CLK                 257U
266 #define NXP_S32_RTU1_CORE_DIV2_MON1_CLK            258U
267 #define NXP_S32_RTU1_CORE_DIV2_MON2_CLK            259U
268 #define NXP_S32_RTU1_CORE_DIV2_MON3_CLK            260U
269 #define NXP_S32_RTU1_REG_INTF_CLK                  261U
270 #define NXP_S32_P4_SDHC_CLK                        262U
271 #define NXP_S32_RXLUT_CLK                          263U
272 #define NXP_S32_SDHC0_CLK                          264U
273 #define NXP_S32_SINC_CLK                           265U
274 #define NXP_S32_SIPI0_CLK                          266U
275 #define NXP_S32_SIPI1_CLK                          267U
276 #define NXP_S32_SIUL2_0_CLK                        268U
277 #define NXP_S32_SIUL2_1_CLK                        269U
278 #define NXP_S32_SIUL2_4_CLK                        270U
279 #define NXP_S32_SIUL2_5_CLK                        271U
280 #define NXP_S32_P0_DSPI_CLK                        272U
281 #define NXP_S32_SPI0_CLK                           273U
282 #define NXP_S32_SPI1_CLK                           274U
283 #define NXP_S32_P1_DSPI_CLK                        275U
284 #define NXP_S32_SPI2_CLK                           276U
285 #define NXP_S32_SPI3_CLK                           277U
286 #define NXP_S32_SPI4_CLK                           278U
287 #define NXP_S32_P4_DSPI_CLK                        279U
288 #define NXP_S32_SPI5_CLK                           280U
289 #define NXP_S32_SPI6_CLK                           281U
290 #define NXP_S32_SPI7_CLK                           282U
291 #define NXP_S32_P5_DSPI_CLK                        283U
292 #define NXP_S32_SPI8_CLK                           284U
293 #define NXP_S32_SPI9_CLK                           285U
294 #define NXP_S32_SRX0_CLK                           286U
295 #define NXP_S32_SRX1_CLK                           287U
296 
297 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_ */
298