1# Copyright (c) 2014-2015 Wind River Systems, Inc.
2# Copyright (c) 2016 Cadence Design Systems, Inc.
3# Copyright (c) 2019-2023 Intel Corp.
4# SPDX-License-Identifier: Apache-2.0
5
6choice
7	prompt "Default System Timer"
8	default HPET_TIMER if SOC_FAMILY_INTEL_ISH || SOC_ATOM || SOC_LAKEMONT
9	default APIC_TSC_DEADLINE_TIMER
10	depends on X86
11	help
12	  Select Default System Timer.
13
14config HPET_TIMER
15	bool "HPET timer"
16	depends on DT_HAS_INTEL_HPET_ENABLED
17	select IOAPIC
18	select LOAPIC
19	imply TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
20	select TICKLESS_CAPABLE
21	select TIMER_HAS_64BIT_CYCLE_COUNTER
22	help
23	  This option selects High Precision Event Timer (HPET) as a
24	  system timer.
25
26config APIC_TIMER
27	bool "Local APIC timer"
28	select LOAPIC
29	select TIMER_HAS_64BIT_CYCLE_COUNTER
30	select SYSTEM_CLOCK_LOCK_FREE_COUNT
31	help
32	  Use the x86 local APIC in periodic mode as the system time
33	  source.  NOTE: this probably isn't what you want except on
34	  older or idiosyncratic hardware (or environments like qemu
35	  without complete APIC emulation).  Modern hardware will work
36	  better with CONFIG_APIC_TSC_DEADLINE_TIMER.
37
38config APIC_TSC_DEADLINE_TIMER
39	bool "Local APIC timer using TSC deadline mode"
40	select LOAPIC
41	select TICKLESS_CAPABLE
42	select TIMER_HAS_64BIT_CYCLE_COUNTER
43	help
44	  Extremely simple timer driver based the local APIC TSC
45	  deadline capability.  The use of a free-running 64 bit
46	  counter with comparator eliminates almost all edge cases
47	  from the handling, and the near-instruction-cycle resolution
48	  permits effectively unlimited precision where needed (the
49	  limit becomes the CPU time taken to execute the timing
50	  logic). SMP-safe and very fast, this should be the obvious
51	  choice for any x86 device with invariant TSC and TSC
52	  deadline capability.
53
54config APIC_TIMER_TSC
55	bool "Local APIC timer using TSC time source"
56	depends on !SMP
57	select LOAPIC
58	select TICKLESS_CAPABLE
59	select TIMER_HAS_64BIT_CYCLE_COUNTER
60	help
61	  If your CPU supports invariant TSC but no TSC deadline capability
62	  then this choice will rely on the TSC as time source and the
63	  local APIC in one-shot mode as the timeout event source.
64	  You must know the ratio of the TSC frequency to the local APIC
65	  timer frequency.
66
67endchoice
68
69if APIC_TIMER
70
71config APIC_TIMER_IRQ
72	int "Local APIC timer IRQ"
73	default 24
74	help
75	  This option specifies the IRQ used by the local APIC timer.
76	  Note: this MUST be set to the index immediately after the
77	  last IO-APIC IRQ (the timer is the first entry in the APIC
78	  local vector table).  This footgun is not intended to be
79	  user-configurable and almost certainly should be managed via
80	  a different mechanism.
81
82endif # APIC_TIMER
83
84if APIC_TIMER_TSC
85
86config APIC_TIMER_TSC_N
87	int "TSC to local APIC timer frequency multiplier (N)"
88	default 1
89
90config APIC_TIMER_TSC_M
91	int "TSC to local APIC timer frequency divisor (M)"
92	default 1
93
94endif # APIC_TIMER_TSC
95
96config APIC_TIMER_IRQ_PRIORITY
97	int "Local APIC timer interrupt priority"
98	depends on APIC_TIMER || APIC_TSC_DEADLINE_TIMER || APIC_TIMER_TSC
99	default 4
100	help
101	  This option specifies the interrupt priority used by the
102	  local APIC timer.
103