1 /**
2 ******************************************************************************
3 * @file stm32wlxx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extended peripheral:
8 * + Extended Peripheral Control functions
9 * + Extended Clock management functions
10 * + Extended Clock Recovery System Control functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2020 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32wlxx_hal.h"
27
28 /** @addtogroup STM32WLxx_HAL_Driver
29 * @{
30 */
31
32 /** @defgroup RCCEx RCCEx
33 * @brief RCC Extended HAL module driver
34 * @{
35 */
36
37 #ifdef HAL_RCC_MODULE_ENABLED
38
39 /* Private typedef -----------------------------------------------------------*/
40 /* Private defines -----------------------------------------------------------*/
41 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
42 * @{
43 */
44 #define __LSCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
45 #define LSCO1_GPIO_PORT GPIOA
46 #define LSCO1_PIN GPIO_PIN_2
47 /**
48 * @}
49 */
50
51 /* Private macros ------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53 /* Private function prototypes -----------------------------------------------*/
54 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
55 * @{
56 */
57 static uint32_t RCC_PLL_GetFreqDomain_P(void);
58 static uint32_t RCC_PLL_GetFreqDomain_Q(void);
59 /**
60 * @}
61 */
62
63 /* Exported functions --------------------------------------------------------*/
64
65 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
66 * @{
67 */
68
69 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
70 * @brief Extended Peripheral Control functions
71 *
72 @verbatim
73 ===============================================================================
74 ##### Extended Peripheral Control functions #####
75 ===============================================================================
76 [..]
77 This subsection provides a set of functions allowing to control the RCC Clocks
78 frequencies.
79 [..]
80 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
81 select the RTC clock source; in this case the Backup domain will be reset in
82 order to modify the RTC Clock source, as consequence RTC registers (including
83 the backup registers) and RCC_BDCR register are set to their reset values.
84
85 @endverbatim
86 * @{
87 */
88
89 /**
90 * @brief Initialize the RCC extended peripherals clocks according to the specified
91 * parameters in the @ref RCC_PeriphCLKInitTypeDef.
92 * @param PeriphClkInit pointer to a @ref RCC_PeriphCLKInitTypeDef structure that
93 * contains a field PeriphClockSelection which can be a combination of the following values:
94 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
95 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
96 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
97 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
98 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
99 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
100 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
101 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
102 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
103 * @arg @ref RCC_PERIPHCLK_LPTIM3 LPTIM3 peripheral clock
104 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
105 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
106 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
107 *
108 * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
109 * the RTC clock source: in this case the access to Backup domain is enabled.
110 *
111 * @retval HAL status
112 */
HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef * PeriphClkInit)113 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
114 {
115 uint32_t tmpregister = 0;
116 uint32_t tickstart;
117 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
118 HAL_StatusTypeDef status = HAL_OK; /* Final status */
119
120 /* Check the parameters */
121 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
122
123 /*-------------------------- RTC clock source configuration ----------------------*/
124 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
125 {
126
127 /* Check for RTC Parameters used to output RTCCLK */
128 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
129
130
131 /* Enable write access to Backup domain */
132 HAL_PWR_EnableBkUpAccess();
133
134 /* Wait for Backup domain Write protection disable */
135 tickstart = HAL_GetTick();
136
137 while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)))
138 {
139 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
140 {
141 ret = HAL_TIMEOUT;
142 break;
143 }
144 }
145
146 if (ret == HAL_OK)
147 {
148 /* Reset the Backup domain only if the RTC Clock source selection is modified */
149 if (LL_RCC_GetRTCClockSource() != PeriphClkInit->RTCClockSelection)
150 {
151 /* Store the content of BDCR register before the reset of Backup Domain */
152 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
153
154 /* RTC Clock selection can be changed only if the Backup Domain is reset */
155 __HAL_RCC_BACKUPRESET_FORCE();
156 __HAL_RCC_BACKUPRESET_RELEASE();
157
158 /* Restore the Content of BDCR register */
159 RCC->BDCR = tmpregister;
160 }
161
162 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
163 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSERDY))
164 {
165 /* Get Start Tick*/
166 tickstart = HAL_GetTick();
167
168 /* Wait till LSE is ready */
169 while (LL_RCC_LSE_IsReady() != 1U)
170 {
171 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
172 {
173 ret = HAL_TIMEOUT;
174 break;
175 }
176 }
177 }
178
179 if (ret == HAL_OK)
180 {
181 /* Apply new RTC clock source selection */
182 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
183 }
184 else
185 {
186 /* set overall return value */
187 status = ret;
188 }
189 }
190 else
191 {
192 /* set overall return value */
193 status = ret;
194 }
195
196 }
197
198 /*-------------------- USART1 clock source configuration -------------------*/
199 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
200 {
201 /* Check the parameters */
202 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
203
204 /* Configure the USART1 clock source */
205 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
206 }
207
208 /*-------------------- USART2 clock source configuration -------------------*/
209 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
210 {
211 /* Check the parameters */
212 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
213
214 /* Configure the USART2 clock source */
215 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
216 }
217
218 /*-------------------- LPUART1 clock source configuration ------------------*/
219 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
220 {
221 /* Check the parameters */
222 assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
223
224 /* Configure the LPUAR1 clock source */
225 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
226 }
227
228 /*-------------------- LPTIM1 clock source configuration -------------------*/
229 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
230 {
231 /* Check the parameters */
232 assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
233
234 /* Configure the LPTIM1 clock source */
235 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
236 }
237
238 /*-------------------- LPTIM2 clock source configuration -------------------*/
239 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
240 {
241 /* Check the parameters */
242 assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection));
243
244 /* Configure the LPTIM2 clock source */
245 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
246 }
247
248 /*-------------------- LPTIM3 clock source configuration -------------------*/
249 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM3) == (RCC_PERIPHCLK_LPTIM3))
250 {
251 /* Check the parameters */
252 assert_param(IS_RCC_LPTIM3CLKSOURCE(PeriphClkInit->Lptim3ClockSelection));
253
254 /* Configure the LPTIM3 clock source */
255 __HAL_RCC_LPTIM3_CONFIG(PeriphClkInit->Lptim3ClockSelection);
256 }
257
258 /*-------------------- I2C1 clock source configuration ---------------------*/
259 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
260 {
261 /* Check the parameters */
262 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
263
264 /* Configure the I2C1 clock source */
265 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
266 }
267
268 /*-------------------- I2C2 clock source configuration ---------------------*/
269 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
270 {
271 /* Check the parameters */
272 assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
273
274 /* Configure the I2C2 clock source */
275 __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
276 }
277
278 /*-------------------- I2C3 clock source configuration ---------------------*/
279 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
280 {
281 /* Check the parameters */
282 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
283
284 /* Configure the I2C3 clock source */
285 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
286 }
287
288 /*-------------------- I2S2 clock source configuration ---------------------*/
289 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == (RCC_PERIPHCLK_I2S2))
290 {
291 /* Check the parameters */
292 assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
293
294 /* Configure the I2S2 clock source */
295 __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
296
297 if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL)
298 {
299 /* Enable RCC_PLL_I2S2CLK output */
300 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2S2CLK);
301 }
302 }
303
304 /*-------------------- RNG clock source configuration ----------------------*/
305 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
306 {
307 assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
308 __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
309
310 if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
311 {
312 /* Enable RCC_PLL_RNGCLK output */
313 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK);
314 }
315 }
316
317 /*-------------------- ADC clock source configuration ----------------------*/
318 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
319 {
320 /* Check the parameters */
321 assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
322
323 /* Configure the ADC interface clock source */
324 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
325
326 if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL)
327 {
328 /* Enable RCC_PLL_RNGCLK output */
329 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
330 }
331 }
332
333 return status;
334 }
335
336
337 /**
338 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
339 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
340 * returns the configuration information for the Extended Peripherals
341 * clocks(LPTIM1, LPTIM2, LPTIM3, I2C1, I2C2, I2C3, I2S2, LPUART1,
342 * USART1, USART2, RTC, ADC, RNG).
343 * @retval None
344 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * PeriphClkInit)345 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
346 {
347 /* Set all possible values for the extended clock type parameter------------*/
348 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2S2 | \
349 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
350 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM3 | \
351 RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \
352 RCC_PERIPHCLK_LPUART1;
353
354 /* Get the USART1 clock source ---------------------------------------------*/
355 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
356
357 /* Get the USART2 clock source ---------------------------------------------*/
358 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
359
360 /* Get the I2S2 clock source -----------------------------------------------*/
361 PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
362
363 /* Get the LPUART1 clock source --------------------------------------------*/
364 PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
365
366 /* Get the I2C1 clock source -----------------------------------------------*/
367 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
368
369 /* Get the I2C2 clock source -----------------------------------------------*/
370 PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
371
372 /* Get the I2C3 clock source -----------------------------------------------*/
373 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
374
375 /* Get the LPTIM1 clock source ---------------------------------------------*/
376 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
377
378 /* Get the LPTIM2 clock source ---------------------------------------------*/
379 PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
380
381 /* Get the LPTIM3 clock source ---------------------------------------------*/
382 PeriphClkInit->Lptim3ClockSelection = __HAL_RCC_GET_LPTIM3_SOURCE();
383
384 /* Get the RTC clock source ------------------------------------------------*/
385 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
386
387 /* Get the RNG clock source ------------------------------------------------*/
388 PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
389
390 /* Get the ADC clock source ------------------------------------------------*/
391 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
392
393 }
394
395 /**
396 * @brief Return the peripheral clock frequency for peripherals with clock source
397 * @note Return 0 if peripheral clock identifier not managed by this API
398 * @param PeriphClk Peripheral clock identifier
399 * This parameter can be one of the following values:
400 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
401 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
402 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
403 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
404 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
405 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
406 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
407 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
408 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
409 * @arg @ref RCC_PERIPHCLK_LPTIM3 LPTIM3 peripheral clock
410 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
411 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
412 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
413 *
414 * @retval Frequency in Hz
415 */
HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)416 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
417 {
418 uint32_t frequency = 0U;
419 uint32_t srcclk;
420
421 /* Check the parameters */
422 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
423
424 switch (PeriphClk)
425 {
426 case RCC_PERIPHCLK_RTC:
427
428 /* Get the current RTC source */
429 srcclk = LL_RCC_GetRTCClockSource();
430
431 switch (srcclk)
432 {
433 case LL_RCC_RTC_CLKSOURCE_LSE: /* LSE clock used as RTC clock source */
434 if (LL_RCC_LSE_IsReady() == 1U)
435 {
436 frequency = LSE_VALUE;
437 }
438 break;
439
440 case LL_RCC_RTC_CLKSOURCE_LSI: /* LSI clock used as RTC clock source */
441 if (LL_RCC_LSI_IsReady() == 1U)
442 {
443 if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
444 {
445 frequency = LSI_VALUE / 128U;
446 }
447 else
448 {
449 frequency = LSI_VALUE;
450 }
451 }
452 break;
453
454 case LL_RCC_RTC_CLKSOURCE_HSE_DIV32: /* HSE/32 clock used as RTC clock source */
455 frequency = HSE_VALUE / 32U;
456 break;
457
458 case LL_RCC_RTC_CLKSOURCE_NONE: /* No clock used as RTC clock source */
459 default:
460 /* No clock source, frequency default init at 0 */
461 break;
462 }
463 break;
464
465 case RCC_PERIPHCLK_RNG:
466
467 /* Get the current RTC source */
468 srcclk = LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE);
469
470 switch (srcclk)
471 {
472 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
473 if (LL_RCC_PLL_IsReady() == 1U)
474 {
475 frequency = RCC_PLL_GetFreqDomain_Q();
476 }
477 break;
478
479 case LL_RCC_RNG_CLKSOURCE_LSI: /* LSI clock used as RNG clock source */
480 if (LL_RCC_LSI_IsReady() == 1U)
481 {
482 if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
483 {
484 frequency = LSI_VALUE / 128U;
485 }
486 else
487 {
488 frequency = LSI_VALUE;
489 }
490 }
491 break;
492
493 case LL_RCC_RNG_CLKSOURCE_LSE: /* LSE clock used as RNG clock source */
494 if (LL_RCC_LSE_IsReady() == 1U)
495 {
496 frequency = LSE_VALUE;
497 }
498 break;
499
500 case LL_RCC_RNG_CLKSOURCE_MSI: /* MSI clock used as RNG clock source */
501 default:
502 if (LL_RCC_MSI_IsReady() == 1U)
503 {
504 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
505 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
506 LL_RCC_MSI_GetRange() :
507 LL_RCC_MSI_GetRangeAfterStandby()));
508 }
509 break;
510 }
511 break;
512
513 case RCC_PERIPHCLK_USART1:
514
515 /* Get the current USART1 source */
516 srcclk = LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE);
517
518 switch (srcclk)
519 {
520 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
521 frequency = HAL_RCC_GetSysClockFreq();
522 break;
523
524 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
525 if (LL_RCC_HSI_IsReady() == 1U)
526 {
527 frequency = HSI_VALUE;
528 }
529 break;
530
531 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
532 if (LL_RCC_LSE_IsReady() == 1U)
533 {
534 frequency = LSE_VALUE;
535 }
536 break;
537
538 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
539 default:
540 frequency = __LL_RCC_CALC_PCLK2_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
541 LL_RCC_GetAHBPrescaler()), \
542 LL_RCC_GetAPB2Prescaler());
543 break;
544 }
545 break;
546
547 case RCC_PERIPHCLK_USART2:
548
549 /* Get the current USART2 source */
550 srcclk = LL_RCC_GetUSARTClockSource(LL_RCC_USART2_CLKSOURCE);
551
552 switch (srcclk)
553 {
554 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
555 frequency = HAL_RCC_GetSysClockFreq();
556 break;
557
558 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
559 if (LL_RCC_HSI_IsReady() == 1U)
560 {
561 frequency = HSI_VALUE;
562 }
563 break;
564
565 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
566 if (LL_RCC_LSE_IsReady() == 1U)
567 {
568 frequency = LSE_VALUE;
569 }
570 break;
571
572 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
573 default:
574 frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
575 LL_RCC_GetAHBPrescaler()), \
576 LL_RCC_GetAPB1Prescaler());
577 break;
578 }
579 break;
580
581 case RCC_PERIPHCLK_LPUART1:
582
583 /* Get the current LPUART1 source */
584 srcclk = LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE);
585
586 switch (srcclk)
587 {
588 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
589 frequency = HAL_RCC_GetSysClockFreq();
590 break;
591
592 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
593 if (LL_RCC_HSI_IsReady() == 1U)
594 {
595 frequency = HSI_VALUE;
596 }
597 break;
598
599 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
600 if (LL_RCC_LSE_IsReady() == 1U)
601 {
602 frequency = LSE_VALUE;
603 }
604 break;
605
606 case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
607 default:
608 frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
609 LL_RCC_GetAHBPrescaler()), \
610 LL_RCC_GetAPB1Prescaler());
611 break;
612 }
613
614 break;
615
616 case RCC_PERIPHCLK_ADC:
617
618 /* Get the current ADC source */
619 srcclk = LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE);
620
621 switch (srcclk)
622 {
623 case LL_RCC_ADC_CLKSOURCE_HSI: /* HSI Osc. used as ADC clock source */
624 if (LL_RCC_HSI_IsReady() == 1U)
625 {
626 frequency = HSI_VALUE;
627 }
628 break;
629
630
631 case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
632 frequency = HAL_RCC_GetSysClockFreq();
633 break;
634
635 case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as ADC clock source */
636 if (LL_RCC_PLL_IsReady() == 1U)
637 {
638 frequency = RCC_PLL_GetFreqDomain_P();
639 }
640 break;
641
642 case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */
643 default:
644 /* No clock source, frequency default init at 0 */
645 break;
646 }
647 break;
648
649 case RCC_PERIPHCLK_I2C1:
650
651 /* Get the current I2C1 source */
652 srcclk = LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE);
653
654 switch (srcclk)
655 {
656 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
657 frequency = HAL_RCC_GetSysClockFreq();
658 break;
659
660 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
661 if (LL_RCC_HSI_IsReady() == 1U)
662 {
663 frequency = HSI_VALUE;
664 }
665 break;
666
667 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
668 default:
669 frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
670 LL_RCC_GetAHBPrescaler()), \
671 LL_RCC_GetAPB1Prescaler());
672 break;
673 }
674 break;
675
676 case RCC_PERIPHCLK_I2C2:
677
678 /* Get the current I2C2 source */
679 srcclk = LL_RCC_GetI2CClockSource(LL_RCC_I2C2_CLKSOURCE);
680
681 switch (srcclk)
682 {
683 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
684 frequency = HAL_RCC_GetSysClockFreq();
685 break;
686
687 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
688 if (LL_RCC_HSI_IsReady() == 1U)
689 {
690 frequency = HSI_VALUE;
691 }
692 break;
693
694 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
695 default:
696 frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
697 LL_RCC_GetAHBPrescaler()), \
698 LL_RCC_GetAPB1Prescaler());
699 break;
700 }
701 break;
702
703 case RCC_PERIPHCLK_I2C3:
704
705 /* Get the current I2C3 source */
706 srcclk = LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE);
707
708 switch (srcclk)
709 {
710 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
711 frequency = HAL_RCC_GetSysClockFreq();
712 break;
713
714 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
715 if (LL_RCC_HSI_IsReady() == 1U)
716 {
717 frequency = HSI_VALUE;
718 }
719 break;
720
721 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
722 default:
723 frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
724 LL_RCC_GetAHBPrescaler()), \
725 LL_RCC_GetAPB1Prescaler());
726 break;
727 }
728 break;
729
730 case RCC_PERIPHCLK_I2S2:
731
732 /* Get the current I2S2 source */
733 srcclk = LL_RCC_GetI2SClockSource(LL_RCC_I2S2_CLKSOURCE);
734
735 switch (srcclk)
736 {
737 case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
738 frequency = EXTERNAL_CLOCK_VALUE;
739 break;
740
741 case LL_RCC_I2S2_CLKSOURCE_HSI: /* I2S2 Clock is HSI Osc. */
742 if (LL_RCC_HSI_IsReady() == 1U)
743 {
744 frequency = HSI_VALUE;
745 }
746 break;
747
748 case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL */
749 default:
750 frequency = RCC_PLL_GetFreqDomain_Q();
751 break;
752 }
753 break;
754
755 case RCC_PERIPHCLK_LPTIM1:
756
757 /* Get the current LPTIM1 source */
758 srcclk = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
759
760 switch (srcclk)
761 {
762 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
763 if (LL_RCC_LSI_IsReady() == 1U)
764 {
765 if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
766 {
767 frequency = LSI_VALUE / 128U;
768 }
769 else
770 {
771 frequency = LSI_VALUE;
772 }
773 }
774 break;
775
776 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
777 if (LL_RCC_HSI_IsReady() == 1U)
778 {
779 frequency = HSI_VALUE;
780 }
781 break;
782
783 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
784 if (LL_RCC_LSE_IsReady() == 1U)
785 {
786 frequency = LSE_VALUE;
787 }
788 break;
789
790 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
791 default:
792 frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
793 LL_RCC_GetAHBPrescaler()), \
794 LL_RCC_GetAPB1Prescaler());
795 break;
796 }
797 break;
798
799 case RCC_PERIPHCLK_LPTIM2:
800
801 /* Get the current LPTIM2 source */
802 srcclk = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
803
804 switch (srcclk)
805 {
806 case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
807 if (LL_RCC_LSI_IsReady() == 1U)
808 {
809 if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
810 {
811 frequency = LSI_VALUE / 128U;
812 }
813 else
814 {
815 frequency = LSI_VALUE;
816 }
817 }
818 break;
819
820 case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */
821 if (LL_RCC_HSI_IsReady() == 1U)
822 {
823 frequency = HSI_VALUE;
824 }
825 break;
826
827 case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
828 if (LL_RCC_LSE_IsReady() == 1U)
829 {
830 frequency = LSE_VALUE;
831 }
832 break;
833
834 case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */
835 default:
836 frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
837 LL_RCC_GetAHBPrescaler()), \
838 LL_RCC_GetAPB1Prescaler());
839 break;
840 }
841
842 break;
843
844 case RCC_PERIPHCLK_LPTIM3:
845
846 /* Get the current LPTIM3 source */
847 srcclk = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE);
848
849 switch (srcclk)
850 {
851 case LL_RCC_LPTIM3_CLKSOURCE_LSI: /* LPTIM3 Clock is LSI Osc. */
852 if (LL_RCC_LSI_IsReady() == 1U)
853 {
854 if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
855 {
856 frequency = LSI_VALUE / 128U;
857 }
858 else
859 {
860 frequency = LSI_VALUE;
861 }
862 }
863 break;
864
865 case LL_RCC_LPTIM3_CLKSOURCE_HSI: /* LPTIM3 Clock is HSI Osc. */
866 if (LL_RCC_HSI_IsReady() == 1U)
867 {
868 frequency = HSI_VALUE;
869 }
870 break;
871
872 case LL_RCC_LPTIM3_CLKSOURCE_LSE: /* LPTIM3 Clock is LSE Osc. */
873 if (LL_RCC_LSE_IsReady() == 1U)
874 {
875 frequency = LSE_VALUE;
876 }
877 break;
878
879 case LL_RCC_LPTIM3_CLKSOURCE_PCLK1: /* LPTIM3 Clock is PCLK1 */
880 default:
881 frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
882 LL_RCC_GetAHBPrescaler()), \
883 LL_RCC_GetAPB1Prescaler());
884 break;
885 }
886
887 break;
888
889 default:
890 /* Unknown periphclk, frequency default init at 0 */
891 break;
892 }
893
894 return (frequency);
895 }
896
897 /**
898 * @}
899 */
900
901 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
902 * @brief Extended Clock management functions
903 *
904 @verbatim
905 ===============================================================================
906 ##### Extended clock management functions #####
907 ===============================================================================
908 [..]
909 This subsection provides a set of functions allowing to control the
910 activation or deactivation of MSI PLL-mode, LSE CSS,
911 Low speed clock output and clock after wake-up from STOP mode.
912 @endverbatim
913 * @{
914 */
915
916 /******************************************************************************/
917
918 /**
919 * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
920 * @param WakeUpClk Wakeup clock
921 * This parameter can be one of the following values:
922 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection
923 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection
924 * @note This function shall not be called after the Clock Security System on HSE has been
925 * enabled.
926 * @retval None
927 */
HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)928 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
929 {
930 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
931
932 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
933 }
934
935 /**
936 * @brief Enable the LSE Clock Security System.
937 * @note Prior to enable the LSE Clock Security System, LSE oscillator has to be enabled
938 * with HAL_RCC_OscConfig() and the LSE oscillator clock has to be selected as RTC
939 * clock with HAL_RCCEx_PeriphCLKConfig().
940 * @retval None
941 */
HAL_RCCEx_EnableLSECSS(void)942 void HAL_RCCEx_EnableLSECSS(void)
943 {
944 LL_RCC_LSE_EnableCSS();
945 }
946
947 /**
948 * @brief Disable the LSE Clock Security System.
949 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
950 * @retval None
951 */
HAL_RCCEx_DisableLSECSS(void)952 void HAL_RCCEx_DisableLSECSS(void)
953 {
954 LL_RCC_LSE_DisableCSS();
955
956 /* Disable LSE CSS IT if any */
957 __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
958 }
959
960 /**
961 * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
962 * @note Prior to enable the LSE Clock Security System, LSE oscillator has to be enabled
963 * with HAL_RCC_OscConfig() and the LSE oscillator clock has to be selected as RTC
964 * clock with HAL_RCCEx_PeriphCLKConfig().
965 * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
966 * @retval None
967 */
HAL_RCCEx_EnableLSECSS_IT(void)968 void HAL_RCCEx_EnableLSECSS_IT(void)
969 {
970 /* Enable LSE CSS */
971 LL_RCC_LSE_EnableCSS();
972
973 /* Enable LSE CSS IT */
974 __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
975
976 /* Enable IT on EXTI Line 19 */
977 __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
978
979 }
980
981 /**
982 * @brief Handle the RCC LSE Clock Security System interrupt request.
983 * @note Clearing the interrupt flag is under aplication's responsibility.
984 * This should be part of clock recovery strategy when waking up the
985 * system.
986 * @retval None
987 */
HAL_RCCEx_LSECSS_IRQHandler(void)988 void HAL_RCCEx_LSECSS_IRQHandler(void)
989 {
990 /* Check RCC LSE CSSF flag */
991 if (__HAL_RCC_GET_IT(RCC_IT_LSECSS))
992 {
993
994 /* RCC LSE Clock Security System interrupt user callback */
995 HAL_RCCEx_LSECSS_Callback();
996 }
997 }
998
999 /**
1000 * @brief RCCEx LSE Clock Security System interrupt callback.
1001 * @retval none
1002 */
HAL_RCCEx_LSECSS_Callback(void)1003 __weak void HAL_RCCEx_LSECSS_Callback(void)
1004 {
1005 /* NOTE : This function should not be modified, when the callback is needed,
1006 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
1007 */
1008 }
1009
1010 /**
1011 * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
1012 * @param LSCOSource specifies the Low Speed clock source to output.
1013 * This parameter can be one of the following values:
1014 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
1015 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
1016 * @retval None
1017 */
HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)1018 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
1019 {
1020 /* Check the parameters */
1021 assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
1022
1023 /* Update LSCO selection according to parameter and enable LSCO */
1024 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
1025 }
1026
1027 /**
1028 * @brief Disable the Low Speed clock output.
1029 * @retval None
1030 */
HAL_RCCEx_DisableLSCO(void)1031 void HAL_RCCEx_DisableLSCO(void)
1032 {
1033 /* Clear LSCOEN in BDCR register */
1034 LL_RCC_LSCO_Disable();
1035 }
1036
1037 /**
1038 * @brief Enable the PLL-mode of the MSI.
1039 * @note Prior to enable the PLL-mode of the MSI for automatic hardware
1040 * calibration LSE oscillator has to be enabled with @ref HAL_RCC_OscConfig().
1041 * @retval None
1042 */
HAL_RCCEx_EnableMSIPLLMode(void)1043 void HAL_RCCEx_EnableMSIPLLMode(void)
1044 {
1045 LL_RCC_MSI_EnablePLLMode() ;
1046 }
1047
1048 /**
1049 * @brief Disable the PLL-mode of the MSI.
1050 * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
1051 * @retval None
1052 */
HAL_RCCEx_DisableMSIPLLMode(void)1053 void HAL_RCCEx_DisableMSIPLLMode(void)
1054 {
1055 LL_RCC_MSI_DisablePLLMode() ;
1056 }
1057
1058 /**
1059 * @}
1060 */
1061
1062
1063 /**
1064 * @}
1065 */
1066
1067 /** @addtogroup RCCEx_Private_Functions
1068 * @{
1069 */
1070
1071 /**
1072 * @brief Return PLL clock (PLLPCLK) frequency used for ADC domain
1073 * @retval PLLPCLK clock frequency (in Hz)
1074 */
RCC_PLL_GetFreqDomain_P(void)1075 static uint32_t RCC_PLL_GetFreqDomain_P(void)
1076 {
1077 uint32_t pllinputfreq;
1078 uint32_t pllsource;
1079
1080 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value / PLLM) * PLLN
1081 * ADC Domain clock = PLL_VCO / PLLP
1082 */
1083 pllsource = LL_RCC_PLL_GetMainSource();
1084
1085 switch (pllsource)
1086 {
1087 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1088 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1089 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1090 LL_RCC_MSI_GetRange() :
1091 LL_RCC_MSI_GetRangeAfterStandby()));
1092 break;
1093
1094 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1095 pllinputfreq = HSI_VALUE;
1096 break;
1097
1098 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1099 if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
1100 {
1101 pllinputfreq = HSE_VALUE / 2U;
1102 }
1103 else
1104 {
1105 pllinputfreq = HSE_VALUE;
1106 }
1107 break;
1108
1109 default:
1110 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1111 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1112 LL_RCC_MSI_GetRange() :
1113 LL_RCC_MSI_GetRangeAfterStandby()));
1114 break;
1115 }
1116 return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1117 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1118 }
1119
1120
1121 /**
1122 * @brief Return PLL clock (PLLQCLK) frequency used for 48 MHz domain
1123 * @retval PLLQCLK clock frequency (in Hz)
1124 */
RCC_PLL_GetFreqDomain_Q(void)1125 static uint32_t RCC_PLL_GetFreqDomain_Q(void)
1126 {
1127 uint32_t pllinputfreq;
1128 uint32_t pllsource;
1129
1130 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLN
1131 * 48M Domain clock = PLL_VCO / PLLQ
1132 */
1133 pllsource = LL_RCC_PLL_GetMainSource();
1134
1135 switch (pllsource)
1136 {
1137 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1138 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1139 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1140 LL_RCC_MSI_GetRange() :
1141 LL_RCC_MSI_GetRangeAfterStandby()));
1142 break;
1143
1144 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1145 pllinputfreq = HSI_VALUE;
1146 break;
1147
1148 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1149 if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
1150 {
1151 pllinputfreq = HSE_VALUE / 2U;
1152 }
1153 else
1154 {
1155 pllinputfreq = HSE_VALUE;
1156 }
1157 break;
1158
1159 default:
1160 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1161 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1162 LL_RCC_MSI_GetRange() :
1163 LL_RCC_MSI_GetRangeAfterStandby()));
1164 break;
1165 }
1166 return __LL_RCC_CALC_PLLCLK_RNG_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1167 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1168 }
1169
1170
1171 /**
1172 * @}
1173 */
1174
1175 #endif /* HAL_RCC_MODULE_ENABLED */
1176 /**
1177 * @}
1178 */
1179
1180 /**
1181 * @}
1182 */
1183
