1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 #if defined (USE_FULL_LL_DRIVER)
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32wbaxx_ll_dma.h"
43 #include "stm32wbaxx_ll_bus.h"
44 #ifdef USE_FULL_ASSERT
45 #include "stm32_assert.h"
46 #else
47 #define assert_param(expr) ((void)0U)
48 #endif /* USE_FULL_ASSERT */
49
50 /** @addtogroup STM32WBAxx_LL_Driver
51 * @{
52 */
53
54 #if defined (GPDMA1)
55 /** @addtogroup DMA_LL
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private constants ---------------------------------------------------------*/
62 /* Private macros ------------------------------------------------------------*/
63
64 /** @addtogroup DMA_LL_Private_Macros
65 * @{
66 */
67 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \
68 (((Channel) == LL_DMA_CHANNEL_0) || \
69 ((Channel) == LL_DMA_CHANNEL_1) || \
70 ((Channel) == LL_DMA_CHANNEL_2) || \
71 ((Channel) == LL_DMA_CHANNEL_3) || \
72 ((Channel) == LL_DMA_CHANNEL_4) || \
73 ((Channel) == LL_DMA_CHANNEL_5) || \
74 ((Channel) == LL_DMA_CHANNEL_6) || \
75 ((Channel) == LL_DMA_CHANNEL_7) || \
76 ((Channel) == LL_DMA_CHANNEL_ALL)))
77
78 #define IS_LL_GPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \
79 (((Channel) == LL_DMA_CHANNEL_0) || \
80 ((Channel) == LL_DMA_CHANNEL_1) || \
81 ((Channel) == LL_DMA_CHANNEL_2) || \
82 ((Channel) == LL_DMA_CHANNEL_3) || \
83 ((Channel) == LL_DMA_CHANNEL_4) || \
84 ((Channel) == LL_DMA_CHANNEL_5) || \
85 ((Channel) == LL_DMA_CHANNEL_6) || \
86 ((Channel) == LL_DMA_CHANNEL_7)))
87
88 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \
89 ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
90 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH))
91
92 #define IS_LL_DMA_DATA_ALIGNMENT(__VALUE__) (((__VALUE__) == LL_DMA_DATA_ALIGN_ZEROPADD) || \
93 ((__VALUE__) == LL_DMA_DATA_ALIGN_SIGNEXTPADD) || \
94 ((__VALUE__) == LL_DMA_DATA_PACK_UNPACK))
95
96 #define IS_LL_DMA_BURST_LENGTH(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= 64U))
97
98 #define IS_LL_DMA_SRC_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_SRC_DATAWIDTH_BYTE) || \
99 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_HALFWORD) || \
100 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_WORD))
101
102 #define IS_LL_DMA_DEST_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_DEST_DATAWIDTH_BYTE) || \
103 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_HALFWORD) || \
104 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_WORD))
105
106 #define IS_LL_DMA_SRC_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_FIXED) || \
107 ((__VALUE__) == LL_DMA_SRC_INCREMENT))
108
109 #define IS_LL_DMA_DEST_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_FIXED) || \
110 ((__VALUE__) == LL_DMA_DEST_INCREMENT))
111
112 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_LOW_PRIORITY_LOW_WEIGHT) || \
113 ((__VALUE__) == LL_DMA_LOW_PRIORITY_MID_WEIGHT) || \
114 ((__VALUE__) == LL_DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
115 ((__VALUE__) == LL_DMA_HIGH_PRIORITY))
116
117 #define IS_LL_DMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0xFFFFU)
118
119 #define IS_LL_DMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x0EFFU)
120
121 #define IS_LL_DMA_TRIGGER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TRIGM_BLK_TRANSFER) || \
122 ((__VALUE__) == LL_DMA_TRIGM_RPT_BLK_TRANSFER) || \
123 ((__VALUE__) == LL_DMA_TRIGM_LLI_LINK_TRANSFER) || \
124 ((__VALUE__) == LL_DMA_TRIGM_SINGLBURST_TRANSFER ))
125
126 #define IS_LL_DMA_TRIGGER_POLARITY(__VALUE__) (((__VALUE__) == LL_DMA_TRIG_POLARITY_MASKED) || \
127 ((__VALUE__) == LL_DMA_TRIG_POLARITY_RISING) || \
128 ((__VALUE__) == LL_DMA_TRIG_POLARITY_FALLING))
129
130 #define IS_LL_DMA_BLKHW_REQUEST(__VALUE__) (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \
131 ((__VALUE__) == LL_DMA_HWREQUEST_BLK))
132
133 #if defined (TIM3)
134 #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_TIM3_TRGO)
135 #else
136 #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_ADC4_AWD1)
137 #endif /* TIM3 */
138
139
140 #if defined (LPTIM2)
141 #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM2_UE)
142 #else
143 #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM1_UE)
144 #endif /* LPTIM2 */
145
146
147 #define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \
148 ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \
149 ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \
150 ((__VALUE__) == LL_DMA_TCEM_LAST_LLITEM_TRANSFER))
151
152 #define IS_LL_DMA_DEST_HALFWORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_HALFWORD_PRESERVE) || \
153 ((__VALUE__) == LL_DMA_DEST_HALFWORD_EXCHANGE))
154
155 #define IS_LL_DMA_DEST_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_BYTE_PRESERVE) || \
156 ((__VALUE__) == LL_DMA_DEST_BYTE_EXCHANGE))
157
158 #define IS_LL_DMA_SRC_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_BYTE_PRESERVE) || \
159 ((__VALUE__) == LL_DMA_SRC_BYTE_EXCHANGE))
160
161 #define IS_LL_DMA_LINK_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT0) || \
162 ((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT1))
163
164 #define IS_LL_DMA_SRC_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT0) || \
165 ((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT1))
166
167 #define IS_LL_DMA_DEST_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT0) || \
168 ((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT1))
169
170 #define IS_LL_DMA_LINK_STEP_MODE(__VALUE__) (((__VALUE__) == LL_DMA_LSM_FULL_EXECUTION) || \
171 ((__VALUE__) == LL_DMA_LSM_1LINK_EXECUTION))
172
173 #define IS_LL_DMA_BURST_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_SRC_ADDR_INCREMENT) || \
174 ((__VALUE__) == LL_DMA_BURST_SRC_ADDR_DECREMENT))
175
176 #define IS_LL_DMA_BURST_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_DEST_ADDR_INCREMENT) || \
177 ((__VALUE__) == LL_DMA_BURST_DEST_ADDR_DECREMENT))
178
179 #define IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
180
181 #define IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_INCREMENT) || \
182 ((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_DECREMENT))
183
184 #define IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_INCREMENT) || \
185 ((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_DECREMENT))
186
187 #define IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0xFFFFU)
188
189 #define IS_LL_DMA_LINK_BASEADDR(__VALUE__) (((__VALUE__) & 0xFFFFU) == 0U)
190
191 #define IS_LL_DMA_LINK_ADDR_OFFSET(__VALUE__) (((__VALUE__) & 0x03U) == 0U)
192
193 #define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__) ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U))
194
195 #define IS_LL_DMA_LINK_NODETYPE(TYPE) \
196 ((TYPE) == LL_DMA_GPDMA_LINEAR_NODE)
197
198 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
199 #define IS_LL_DMA_CHANNEL_SRC_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_SRC_NSEC) || \
200 ((__VALUE__) == LL_DMA_CHANNEL_SRC_SEC))
201
202 #define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \
203 ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC))
204
205 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
206 /**
207 * @}
208 */
209
210 /* Private function prototypes -----------------------------------------------*/
211 /* Exported functions --------------------------------------------------------*/
212
213 /** @addtogroup DMA_LL_Exported_Functions
214 * @{
215 */
216
217 /** @addtogroup DMA_LL_EF_Init
218 * @{
219 */
220
221 /**
222 * @brief De-initialize the DMA registers to their default reset values.
223 * @note This API is used for all available DMA channels.
224 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
225 * helper macros :
226 * @arg @ref LL_DMA_GET_INSTANCE
227 * @arg @ref LL_DMA_GET_CHANNEL
228 * @param DMAx DMAx Instance
229 * @param Channel This parameter can be one of the following values:
230 * @arg @ref LL_DMA_CHANNEL_0
231 * @arg @ref LL_DMA_CHANNEL_1
232 * @arg @ref LL_DMA_CHANNEL_2
233 * @arg @ref LL_DMA_CHANNEL_3
234 * @arg @ref LL_DMA_CHANNEL_4
235 * @arg @ref LL_DMA_CHANNEL_5
236 * @arg @ref LL_DMA_CHANNEL_6
237 * @arg @ref LL_DMA_CHANNEL_7
238 * @retval An ErrorStatus enumeration value:
239 * - SUCCESS : DMA registers are de-initialized.
240 * - ERROR : DMA registers are not de-initialized.
241 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)242 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
243 {
244 DMA_Channel_TypeDef *tmp;
245 ErrorStatus status = SUCCESS;
246
247 /* Check the DMA Instance DMAx and Channel parameters */
248 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
249
250 if (Channel == LL_DMA_CHANNEL_ALL)
251 {
252 /* Force reset of DMA clock */
253 LL_AHB2_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
254
255 /* Release reset of DMA clock */
256 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
257 }
258 else
259 {
260 /* Get the DMA Channel Instance */
261 tmp = (DMA_Channel_TypeDef *)(LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
262
263 /* Suspend DMA channel */
264 LL_DMA_SuspendChannel(DMAx, Channel);
265
266 /* Disable the selected Channel */
267 LL_DMA_ResetChannel(DMAx, Channel);
268
269 /* Reset DMAx_Channely control register */
270 LL_DMA_WriteReg(tmp, CLBAR, 0U);
271
272 /* Reset DMAx_Channely control register */
273 LL_DMA_WriteReg(tmp, CCR, 0U);
274
275 /* Reset DMAx_Channely Configuration register */
276 LL_DMA_WriteReg(tmp, CTR1, 0U);
277
278 /* Reset DMAx_Channely transfer register 2 */
279 LL_DMA_WriteReg(tmp, CTR2, 0U);
280
281 /* Reset DMAx_Channely block number of data register */
282 LL_DMA_WriteReg(tmp, CBR1, 0U);
283
284 /* Reset DMAx_Channely source address register */
285 LL_DMA_WriteReg(tmp, CSAR, 0U);
286
287 /* Reset DMAx_Channely destination address register */
288 LL_DMA_WriteReg(tmp, CDAR, 0U);
289
290
291 /* Reset DMAx_Channely Linked list address register */
292 LL_DMA_WriteReg(tmp, CLLR, 0U);
293
294 /* Reset DMAx_Channely pending flags */
295 LL_DMA_WriteReg(tmp, CFCR, 0x00003F00U);
296 #if defined (DMA_PRIVCFGR_PRIV0)
297 /* Reset DMAx_Channely attribute */
298 LL_DMA_DisableChannelPrivilege(DMAx, Channel);
299 #endif /* DMA_PRIVCFGR_PRIV0 */
300 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
301 LL_DMA_DisableChannelSecure(DMAx, Channel);
302 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
303 }
304
305 return (uint32_t)status;
306 }
307
308 /**
309 * @brief Initialize the DMA registers according to the specified parameters
310 * in DMA_InitStruct.
311 * @note This API is used for all available DMA channels.
312 * @note A software request transfer can be done once programming the direction
313 * field in memory to memory value.
314 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
315 * helper macros :
316 * @arg @ref LL_DMA_GET_INSTANCE
317 * @arg @ref LL_DMA_GET_CHANNEL
318 * @param DMAx DMAx Instance
319 * @param Channel This parameter can be one of the following values:
320 * @arg @ref LL_DMA_CHANNEL_0
321 * @arg @ref LL_DMA_CHANNEL_1
322 * @arg @ref LL_DMA_CHANNEL_2
323 * @arg @ref LL_DMA_CHANNEL_3
324 * @arg @ref LL_DMA_CHANNEL_4
325 * @arg @ref LL_DMA_CHANNEL_5
326 * @arg @ref LL_DMA_CHANNEL_6
327 * @arg @ref LL_DMA_CHANNEL_7
328 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
329 * @retval An ErrorStatus enumeration value:
330 * - SUCCESS : DMA registers are initialized.
331 * - ERROR : Not applicable.
332 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)333 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
334 {
335 /* Check the DMA Instance DMAx and Channel parameters*/
336 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
337
338 /* Check the DMA parameters from DMA_InitStruct */
339 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
340
341 /* Check direction */
342 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
343 {
344 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitStruct->Request));
345 }
346
347 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitStruct->DataAlignment));
348 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitStruct->SrcDataWidth));
349 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitStruct->DestDataWidth));
350 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitStruct->SrcIncMode));
351 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitStruct->DestIncMode));
352 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
353 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitStruct->BlkDataLength));
354 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitStruct->TriggerPolarity));
355 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitStruct->BlkHWRequest));
356 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitStruct->TransferEventMode));
357 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitStruct->LinkStepMode));
358 assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr));
359 assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset));
360
361 /* Check DMA instance */
362 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
363 {
364 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->SrcBurstLength));
365 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->DestBurstLength));
366 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitStruct->DestHWordExchange));
367 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitStruct->DestByteExchange));
368 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitStruct->SrcByteExchange));
369 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitStruct->LinkAllocatedPort));
370 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitStruct->SrcAllocatedPort));
371 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitStruct->DestAllocatedPort));
372 }
373
374 /* Check trigger polarity */
375 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
376 {
377 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitStruct->TriggerMode));
378 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitStruct->TriggerSelection));
379 }
380
381
382 /*-------------------------- DMAx CLBAR Configuration ------------------------
383 * Configure the Transfer linked list address with parameter :
384 * - LinkedListBaseAdd: DMA_CLBAR_LBA[31:16] bits
385 */
386 LL_DMA_SetLinkedListBaseAddr(DMAx, Channel, DMA_InitStruct->LinkedListBaseAddr);
387
388 /*-------------------------- DMAx CCR Configuration --------------------------
389 * Configure the control parameter :
390 * - LinkAllocatedPort: DMA_CCR_LAP bit
391 * - LinkStepMode: DMA_CCR_LSM bit
392 * - Priority: DMA_CCR_PRIO [23:22] bits
393 */
394 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitStruct->Priority | \
395 DMA_InitStruct->LinkAllocatedPort | \
396 DMA_InitStruct->LinkStepMode);
397
398 /*-------------------------- DMAx CTR1 Configuration -------------------------
399 * Configure the Data transfer parameter :
400 * - DestAllocatedPort: DMA_CTR1_DAP bit
401 * - DestHWordExchange: DMA_CTR1_DHX bit
402 * - DestByteExchange: DMA_CTR1_DBX bit
403 * - DestIncMode: DMA_CTR1_DINC bit
404 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
405 * - SrcAllocatedPort: DMA_CTR1_SAP bit
406 * - SrcByteExchange: DMA_CTR1_SBX bit
407 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
408 * - SrcIncMode: DMA_CTR1_SINC bit
409 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
410 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
411 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
412 */
413 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->DestAllocatedPort | \
414 DMA_InitStruct->DestHWordExchange | \
415 DMA_InitStruct->DestByteExchange | \
416 DMA_InitStruct->DestIncMode | \
417 DMA_InitStruct->DestDataWidth | \
418 DMA_InitStruct->SrcAllocatedPort | \
419 DMA_InitStruct->SrcByteExchange | \
420 DMA_InitStruct->DataAlignment | \
421 DMA_InitStruct->SrcIncMode | \
422 DMA_InitStruct->SrcDataWidth);
423 /* Check DMA instance */
424 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
425 {
426 LL_DMA_ConfigBurstLength(DMAx, Channel, DMA_InitStruct->SrcBurstLength,
427 DMA_InitStruct->DestBurstLength);
428 }
429 /*-------------------------- DMAx CTR2 Configuration -------------------------
430 * Configure the channel transfer parameter :
431 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
432 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
433 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
434 * - BlkHWRequest: DMA_CTR2_BREQ bit
435 * - Direction: DMA_CTR2_DREQ bit
436 * - Direction: DMA_CTR2_SWREQ bit
437 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
438 * - Request: DMA_CTR2_REQSEL [6:0] bits
439 */
440 LL_DMA_ConfigChannelTransfer(DMAx, Channel, DMA_InitStruct->TransferEventMode | \
441 DMA_InitStruct->TriggerPolarity | \
442 DMA_InitStruct->BlkHWRequest | \
443 DMA_InitStruct->Direction);
444
445 /* Check direction */
446 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
447 {
448 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->Request);
449 }
450
451 /* Check trigger polarity */
452 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
453 {
454 LL_DMA_SetHWTrigger(DMAx, Channel, DMA_InitStruct->TriggerSelection);
455 LL_DMA_SetTriggerMode(DMAx, Channel, DMA_InitStruct->TriggerMode);
456 }
457
458 /*-------------------------- DMAx CBR1 Configuration -------------------------
459 * Configure the Transfer Block counters and update mode with parameter :
460 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
461 */
462 LL_DMA_SetBlkDataLength(DMAx, Channel, DMA_InitStruct->BlkDataLength);
463
464 /*-------------------------- DMAx CSAR and CDAR Configuration ----------------
465 * Configure the Transfer source address with parameter :
466 * - SrcAddress: DMA_CSAR_SA[31:0] bits
467 * - DestAddress: DMA_CDAR_DA[31:0] bits
468 */
469 LL_DMA_ConfigAddresses(DMAx, Channel, DMA_InitStruct->SrcAddress, DMA_InitStruct->DestAddress);
470
471 /*-------------------------- DMAx CLLR Configuration -------------------------
472 * Configure the Transfer linked list address with parameter :
473 * - DestAddrOffset: DMA_CLLR_LA[15:2] bits
474 */
475 LL_DMA_SetLinkedListAddrOffset(DMAx, Channel, DMA_InitStruct->LinkedListAddrOffset);
476
477 return (uint32_t)SUCCESS;
478 }
479
480 /**
481 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
482 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
483 * @retval None.
484 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)485 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
486 {
487 /* Set DMA_InitStruct fields to default values */
488 DMA_InitStruct->SrcAddress = 0x00000000U;
489 DMA_InitStruct->DestAddress = 0x00000000U;
490 DMA_InitStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
491 DMA_InitStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
492 DMA_InitStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
493 DMA_InitStruct->SrcBurstLength = 1U;
494 DMA_InitStruct->DestBurstLength = 1U;
495 DMA_InitStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
496 DMA_InitStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
497 DMA_InitStruct->SrcIncMode = LL_DMA_SRC_FIXED;
498 DMA_InitStruct->DestIncMode = LL_DMA_DEST_FIXED;
499 DMA_InitStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
500 DMA_InitStruct->BlkDataLength = 0x00000000U;
501 DMA_InitStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
502 DMA_InitStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
503 DMA_InitStruct->TriggerSelection = 0x00000000U;
504 DMA_InitStruct->Request = 0x00000000U;
505 DMA_InitStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
506 DMA_InitStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
507 DMA_InitStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
508 DMA_InitStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
509 DMA_InitStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
510 DMA_InitStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
511 DMA_InitStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
512 DMA_InitStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
513 DMA_InitStruct->LinkedListBaseAddr = 0x00000000U;
514 DMA_InitStruct->LinkedListAddrOffset = 0x00000000U;
515 }
516
517 /**
518 * @brief Set each @ref LL_DMA_InitLinkedListTypeDef field to default value.
519 * @param DMA_InitLinkedListStruct Pointer to
520 * a @ref LL_DMA_InitLinkedListTypeDef structure.
521 * @retval None.
522 */
LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)523 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
524 {
525 /* Set LL_DMA_InitLinkedListTypeDef fields to default values */
526 DMA_InitLinkedListStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
527 DMA_InitLinkedListStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
528 DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER;
529 DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
530 }
531
532 /**
533 * @brief De-initialize the DMA linked list.
534 * @note This API is used for all available DMA channels.
535 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
536 * helper macros :
537 * @arg @ref LL_DMA_GET_INSTANCE
538 * @arg @ref LL_DMA_GET_CHANNEL
539 * @param DMAx DMAx Instance
540 * @param Channel This parameter can be one of the following values:
541 * @arg @ref LL_DMA_CHANNEL_0
542 * @arg @ref LL_DMA_CHANNEL_1
543 * @arg @ref LL_DMA_CHANNEL_2
544 * @arg @ref LL_DMA_CHANNEL_3
545 * @arg @ref LL_DMA_CHANNEL_4
546 * @arg @ref LL_DMA_CHANNEL_5
547 * @arg @ref LL_DMA_CHANNEL_6
548 * @arg @ref LL_DMA_CHANNEL_7
549 * @retval An ErrorStatus enumeration value:
550 * - SUCCESS : DMA registers are de-initialized.
551 * - ERROR : DMA registers are not de-initialized.
552 */
LL_DMA_List_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)553 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
554 {
555 return LL_DMA_DeInit(DMAx, Channel);
556 }
557
558 /**
559 * @brief Initialize the DMA linked list according to the specified parameters
560 * in LL_DMA_InitLinkedListTypeDef.
561 * @note This API is used for all available DMA channels.
562 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
563 * helper macros :
564 * @arg @ref LL_DMA_GET_INSTANCE
565 * @arg @ref LL_DMA_GET_CHANNEL
566 * @param DMAx DMAx Instance
567 * @param Channel This parameter can be one of the following values:
568 * @arg @ref LL_DMA_CHANNEL_0
569 * @arg @ref LL_DMA_CHANNEL_1
570 * @arg @ref LL_DMA_CHANNEL_2
571 * @arg @ref LL_DMA_CHANNEL_3
572 * @arg @ref LL_DMA_CHANNEL_4
573 * @arg @ref LL_DMA_CHANNEL_5
574 * @arg @ref LL_DMA_CHANNEL_6
575 * @arg @ref LL_DMA_CHANNEL_7
576 * @param DMA_InitLinkedListStruct pointer to
577 * a @ref LL_DMA_InitLinkedListTypeDef structure.
578 * @retval An ErrorStatus enumeration value:
579 * - SUCCESS : DMA registers are initialized.
580 * - ERROR : Not applicable.
581 */
LL_DMA_List_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)582 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
583 {
584 /* Check the DMA Instance DMAx and Channel parameters*/
585 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
586
587 /* Check the DMA parameters from DMA_InitLinkedListStruct */
588 assert_param(IS_LL_DMA_PRIORITY(DMA_InitLinkedListStruct->Priority));
589 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitLinkedListStruct->LinkStepMode));
590 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitLinkedListStruct->TransferEventMode));
591 /* Check DMA instance */
592 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
593 {
594 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitLinkedListStruct->LinkAllocatedPort));
595 }
596
597 /*-------------------------- DMAx CCR Configuration --------------------------
598 * Configure the control parameter :
599 * - LinkAllocatedPort: DMA_CCR_LAP bit
600 * LinkAllocatedPort field is supported only by GPDMA channels.
601 * - LinkStepMode: DMA_CCR_LSM bit
602 * - Priority: DMA_CCR_PRIO [23:22] bits
603 */
604 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \
605 DMA_InitLinkedListStruct->LinkAllocatedPort | \
606 DMA_InitLinkedListStruct->LinkStepMode);
607 /*-------------------------- DMAx CTR2 Configuration -------------------------
608 * Configure the channel transfer parameter :
609 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
610 */
611 LL_DMA_SetTransferEventMode(DMAx, Channel, DMA_InitLinkedListStruct->TransferEventMode);
612
613 return (uint32_t)SUCCESS;
614 }
615
616 /**
617 * @brief Set each @ref LL_DMA_InitNodeTypeDef field to default value.
618 * @param DMA_InitNodeStruct Pointer to a @ref LL_DMA_InitNodeTypeDef
619 * structure.
620 * @retval None.
621 */
LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct)622 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct)
623 {
624 /* Set DMA_InitNodeStruct fields to default values */
625 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
626 DMA_InitNodeStruct->DestSecure = LL_DMA_CHANNEL_DEST_NSEC;
627 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
628 DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
629 DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
630 DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
631 DMA_InitNodeStruct->DestBurstLength = 1U;
632 DMA_InitNodeStruct->DestIncMode = LL_DMA_DEST_FIXED;
633 DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
634 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
635 DMA_InitNodeStruct->SrcSecure = LL_DMA_CHANNEL_SRC_NSEC;
636 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
637 DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
638 DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
639 DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
640 DMA_InitNodeStruct->SrcBurstLength = 1U;
641 DMA_InitNodeStruct->SrcIncMode = LL_DMA_SRC_FIXED;
642 DMA_InitNodeStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
643 DMA_InitNodeStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
644 DMA_InitNodeStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
645 DMA_InitNodeStruct->TriggerSelection = 0x00000000U;
646 DMA_InitNodeStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
647 DMA_InitNodeStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
648 DMA_InitNodeStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
649 DMA_InitNodeStruct->Request = 0x00000000U;
650 DMA_InitNodeStruct->BlkDataLength = 0x00000000U;
651 DMA_InitNodeStruct->SrcAddress = 0x00000000U;
652 DMA_InitNodeStruct->DestAddress = 0x00000000U;
653 DMA_InitNodeStruct->UpdateRegisters = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | \
654 LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | \
655 LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CLLR);
656 DMA_InitNodeStruct->NodeType = LL_DMA_GPDMA_LINEAR_NODE;
657 }
658
659 /**
660 * @brief Initializes DMA linked list node according to the specified
661 * parameters in the DMA_InitNodeStruct.
662 * @param DMA_InitNodeStruct Pointer to a LL_DMA_InitNodeTypeDef structure
663 * that contains linked list node
664 * registers configurations.
665 * @param pNode Pointer to linked list node to fill according to
666 * LL_DMA_LinkNodeTypeDef parameters.
667 * @retval None
668 */
LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct,LL_DMA_LinkNodeTypeDef * pNode)669 uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode)
670 {
671 uint32_t reg_counter = 0U;
672
673 /* Check the DMA Node type */
674 assert_param(IS_LL_DMA_LINK_NODETYPE(DMA_InitNodeStruct->NodeType));
675
676 /* Check the DMA parameters from DMA_InitNodeStruct */
677 assert_param(IS_LL_DMA_DIRECTION(DMA_InitNodeStruct->Direction));
678
679 /* Check direction */
680 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
681 {
682 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitNodeStruct->Request));
683 }
684
685 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitNodeStruct->DataAlignment));
686 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitNodeStruct->SrcDataWidth));
687 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitNodeStruct->DestDataWidth));
688 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitNodeStruct->SrcIncMode));
689 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitNodeStruct->DestIncMode));
690 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitNodeStruct->BlkDataLength));
691 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitNodeStruct->TriggerPolarity));
692 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitNodeStruct->BlkHWRequest));
693 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitNodeStruct->TransferEventMode));
694 assert_param(IS_LL_DMA_LINK_UPDATE_REGISTERS(DMA_InitNodeStruct->UpdateRegisters));
695
696 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
697 assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure));
698 assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure));
699 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
700
701 /* Check trigger polarity */
702 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
703 {
704 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode));
705 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection));
706 }
707
708 /* Check node type */
709 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE)
710 {
711 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitNodeStruct->DestHWordExchange));
712 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitNodeStruct->DestByteExchange));
713 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitNodeStruct->SrcByteExchange));
714 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitNodeStruct->SrcAllocatedPort));
715 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitNodeStruct->DestAllocatedPort));
716 }
717
718
719 /* Check if CTR1 register update is enabled */
720 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR1) == LL_DMA_UPDATE_CTR1)
721 {
722 /*-------------------------- DMAx CTR1 Configuration -----------------------
723 * Configure the Data transfer parameter :
724 * - DestAllocatedPort: DMA_CTR1_DAP bit
725 * - DestHWordExchange: DMA_CTR1_DHX bit
726 * - DestByteExchange: DMA_CTR1_DBX bit
727 * - DestIncMode: DMA_CTR1_DINC bit
728 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
729 * - SrcAllocatedPort: DMA_CTR1_SAP bit
730 * - SrcByteExchange: DMA_CTR1_SBX bit
731 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
732 * - SrcIncMode: DMA_CTR1_SINC bit
733 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
734 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
735 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
736 */
737
738 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->DestIncMode | \
739 DMA_InitNodeStruct->DestDataWidth | \
740 DMA_InitNodeStruct->DataAlignment | \
741 DMA_InitNodeStruct->SrcIncMode | \
742 DMA_InitNodeStruct->SrcDataWidth);
743
744 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
745 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \
746 DMA_InitNodeStruct->SrcSecure);
747 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
748
749
750 /* Update CTR1 register fields */
751 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \
752 DMA_InitNodeStruct->DestHWordExchange | \
753 DMA_InitNodeStruct->DestByteExchange | \
754 ((DMA_InitNodeStruct->DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) | \
755 DMA_InitNodeStruct->SrcAllocatedPort | \
756 DMA_InitNodeStruct->SrcByteExchange | \
757 ((DMA_InitNodeStruct->SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos));
758
759 /* Increment counter for the next register */
760 reg_counter++;
761 }
762
763
764 /* Check if CTR2 register update is enabled */
765 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR2) == LL_DMA_UPDATE_CTR2)
766 {
767 /*-------------------------- DMAx CTR2 Configuration -----------------------
768 * Configure the channel transfer parameter :
769 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
770 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
771 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
772 * - BlkHWRequest: DMA_CTR2_BREQ bit
773 * - Direction: DMA_CTR2_DREQ bit
774 * - Direction: DMA_CTR2_SWREQ bit
775 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
776 * - Request: DMA_CTR2_REQSEL [6:0] bits
777 */
778 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->TransferEventMode | \
779 DMA_InitNodeStruct->TriggerPolarity | \
780 DMA_InitNodeStruct->BlkHWRequest | \
781 DMA_InitNodeStruct->Direction);
782
783 /* Check direction */
784 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
785 {
786 pNode->LinkRegisters[reg_counter] |= DMA_InitNodeStruct->Request & DMA_CTR2_REQSEL;
787 }
788
789 /* Check trigger polarity */
790 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
791 {
792 pNode->LinkRegisters[reg_counter] |= (((DMA_InitNodeStruct->TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & \
793 DMA_CTR2_TRIGSEL) | DMA_InitNodeStruct->TriggerMode);
794 }
795
796
797 /* Increment counter for the next register */
798 reg_counter++;
799 }
800 /* Check if CBR1 register update is enabled */
801 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR1) == LL_DMA_UPDATE_CBR1)
802 {
803 /*-------------------------- DMAx CBR1 Configuration -----------------------
804 * Configure the Transfer Block counters and update mode with parameter :
805 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
806 */
807 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->BlkDataLength;
808
809 /* Increment counter for the next register */
810 reg_counter++;
811 }
812 /* Check if CSAR register update is enabled */
813 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CSAR) == LL_DMA_UPDATE_CSAR)
814 {
815 /*-------------------------- DMAx CSAR Configuration -----------------------
816 * Configure the Transfer Block counters and update mode with parameter :
817 * - SrcAddress: DMA_CSAR_SA[31:0] bits
818 */
819 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->SrcAddress;
820
821 /* Increment counter for the next register */
822 reg_counter++;
823 }
824
825
826 /* Check if CDAR register update is enabled */
827 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CDAR) == LL_DMA_UPDATE_CDAR)
828 {
829 /*-------------------------- DMAx CDAR Configuration -----------------------
830 * Configure the Transfer Block counters and update mode with parameter :
831 * - DestAddress: DMA_CDAR_DA[31:0] bits
832 */
833 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->DestAddress;
834
835 /* Increment counter for the next register */
836 reg_counter++;
837 }
838
839
840 /* Check if CLLR register update is enabled */
841 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR)
842 {
843 /*-------------------------- DMAx CLLR Configuration -----------------------
844 * Configure the Transfer Block counters and update mode with parameter :
845 * - UpdateRegisters DMA_CLLR_UT1 bit
846 * - UpdateRegisters DMA_CLLR_UT2 bit
847 * - UpdateRegisters DMA_CLLR_UB1 bit
848 * - UpdateRegisters DMA_CLLR_USA bit
849 * - UpdateRegisters DMA_CLLR_UDA bit
850 * - UpdateRegisters DMA_CLLR_ULL bit
851 */
852 pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CLLR_UT2 | \
853 DMA_CLLR_UB1 | DMA_CLLR_USA | \
854 DMA_CLLR_UDA | DMA_CLLR_ULL)));
855
856 }
857 else
858 {
859 /* Reset of the CLLR of the node being created */
860 pNode->LinkRegisters[reg_counter] = 0U;
861 }
862
863 return (uint32_t)SUCCESS;
864 }
865
866 /**
867 * @brief Connect Linked list Nodes.
868 * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Linked list node.
869 * @param PrevNodeCLLRIdx Offset of Previous Node CLLR register.
870 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
871 * @param pNewLinkNode Pointer to new Linked list.
872 * @param NewNodeCLLRIdx Offset of New Node CLLR register.
873 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
874 * @retval None
875 */
LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef * pPrevLinkNode,uint32_t PrevNodeCLLRIdx,LL_DMA_LinkNodeTypeDef * pNewLinkNode,uint32_t NewNodeCLLRIdx)876 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
877 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx)
878 {
879 pPrevLinkNode->LinkRegisters[PrevNodeCLLRIdx] = (((uint32_t)pNewLinkNode & DMA_CLLR_LA) | \
880 (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \
881 DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \
882 DMA_CLLR_ULL)));
883 }
884
885 /**
886 * @brief Disconnect the next linked list node.
887 * @param pLinkNode Pointer to linked list node to be disconnected from the next one.
888 * @param LinkNodeCLLRIdx Offset of Link Node CLLR register.
889 * @retval None.
890 */
LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef * pLinkNode,uint32_t LinkNodeCLLRIdx)891 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx)
892 {
893 pLinkNode->LinkRegisters[LinkNodeCLLRIdx] = 0;
894 }
895
896 /**
897 * @}
898 */
899
900 /**
901 * @}
902 */
903
904 /**
905 * @}
906 */
907
908 #endif /* GPDMA1 */
909
910 /**
911 * @}
912 */
913
914 #endif /* USE_FULL_LL_DRIVER */
915
916
