1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_hal_tim_ex.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer Extended peripheral:
8 * + Time Hall Sensor Interface Initialization
9 * + Time Hall Sensor Interface Start
10 * + Time Complementary signal break and dead time configuration
11 * + Time Master and Slave synchronization configuration
12 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
13 * + Time OCRef clear configuration
14 * + Timer remapping capabilities configuration
15 * + Timer encoder index configuration
16 ******************************************************************************
17 * @attention
18 *
19 * Copyright (c) 2022 STMicroelectronics.
20 * All rights reserved.
21 *
22 * This software is licensed under terms that can be found in the LICENSE file
23 * in the root directory of this software component.
24 * If no LICENSE file comes with this software, it is provided AS-IS.
25 *
26 ******************************************************************************
27 @verbatim
28 ==============================================================================
29 ##### TIMER Extended features #####
30 ==============================================================================
31 [..]
32 The Timer Extended features include:
33 (#) Complementary outputs with programmable dead-time for :
34 (++) Output Compare
35 (++) PWM generation (Edge and Center-aligned Mode)
36 (++) One-pulse mode output
37 (#) Synchronization circuit to control the timer with external signals and to
38 interconnect several timers together.
39 (#) Break input to put the timer output signals in reset state or in a known state.
40 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
41 positioning purposes
42 (#) In case of Pulse on compare, configure pulse length and delay
43 (#) Encoder index configuration
44
45 ##### How to use this driver #####
46 ==============================================================================
47 [..]
48 (#) Initialize the TIM low level resources by implementing the following functions
49 depending on the selected feature:
50 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
51
52 (#) Initialize the TIM low level resources :
53 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
54 (##) TIM pins configuration
55 (+++) Enable the clock for the TIM GPIOs using the following function:
56 __HAL_RCC_GPIOx_CLK_ENABLE();
57 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
58
59 (#) The external Clock can be configured, if needed (the default clock is the
60 internal clock from the APBx), using the following function:
61 HAL_TIM_ConfigClockSource, the clock configuration should be done before
62 any start function.
63
64 (#) Configure the TIM in the desired functioning mode using one of the
65 initialization function of this driver:
66 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
67 Timer Hall Sensor Interface and the commutation event with the corresponding
68 Interrupt and DMA request if needed (Note that One Timer is used to interface
69 with the Hall sensor Interface and another Timer should be used to use
70 the commutation event).
71 (#) In case of Pulse On Compare:
72 (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler
73
74
75 (#) Activate the TIM peripheral using one of the start functions:
76 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
77 HAL_TIMEx_OCN_Start_IT()
78 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
79 HAL_TIMEx_PWMN_Start_IT()
80 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
81 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
82 HAL_TIMEx_HallSensor_Start_IT().
83
84 @endverbatim
85 ******************************************************************************
86 */
87
88 /* Includes ------------------------------------------------------------------*/
89 #include "stm32wbaxx_hal.h"
90
91 /** @addtogroup STM32WBAxx_HAL_Driver
92 * @{
93 */
94
95 /** @defgroup TIMEx TIMEx
96 * @brief TIM Extended HAL module driver
97 * @{
98 */
99
100 #ifdef HAL_TIM_MODULE_ENABLED
101
102 /* Private typedef -----------------------------------------------------------*/
103 /* Private define ------------------------------------------------------------*/
104 /* Private constants ---------------------------------------------------------*/
105 /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
106 * @{
107 */
108 /* Timeout for break input rearm */
109 #define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
110 /**
111 * @}
112 */
113 /* End of private constants --------------------------------------------------*/
114
115 /* Private macros ------------------------------------------------------------*/
116 /* Private variables ---------------------------------------------------------*/
117 /* Private function prototypes -----------------------------------------------*/
118 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
119 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
120 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
121
122 /* Exported functions --------------------------------------------------------*/
123 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
124 * @{
125 */
126
127 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
128 * @brief Timer Hall Sensor functions
129 *
130 @verbatim
131 ==============================================================================
132 ##### Timer Hall Sensor functions #####
133 ==============================================================================
134 [..]
135 This section provides functions allowing to:
136 (+) Initialize and configure TIM HAL Sensor.
137 (+) De-initialize TIM HAL Sensor.
138 (+) Start the Hall Sensor Interface.
139 (+) Stop the Hall Sensor Interface.
140 (+) Start the Hall Sensor Interface and enable interrupts.
141 (+) Stop the Hall Sensor Interface and disable interrupts.
142 (+) Start the Hall Sensor Interface and enable DMA transfers.
143 (+) Stop the Hall Sensor Interface and disable DMA transfers.
144
145 @endverbatim
146 * @{
147 */
148 /**
149 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
150 * @note When the timer instance is initialized in Hall Sensor Interface mode,
151 * timer channels 1 and channel 2 are reserved and cannot be used for
152 * other purpose.
153 * @param htim TIM Hall Sensor Interface handle
154 * @param sConfig TIM Hall Sensor configuration structure
155 * @retval HAL status
156 */
HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef * htim,const TIM_HallSensor_InitTypeDef * sConfig)157 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
158 {
159 TIM_OC_InitTypeDef OC_Config;
160
161 /* Check the TIM handle allocation */
162 if (htim == NULL)
163 {
164 return HAL_ERROR;
165 }
166
167 /* Check the parameters */
168 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
169 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
170 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
171 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
172 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
173 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
174 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
175 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
176
177 if (htim->State == HAL_TIM_STATE_RESET)
178 {
179 /* Allocate lock resource and initialize it */
180 htim->Lock = HAL_UNLOCKED;
181
182 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
183 /* Reset interrupt callbacks to legacy week callbacks */
184 TIM_ResetCallback(htim);
185
186 if (htim->HallSensor_MspInitCallback == NULL)
187 {
188 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
189 }
190 /* Init the low level hardware : GPIO, CLOCK, NVIC */
191 htim->HallSensor_MspInitCallback(htim);
192 #else
193 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
194 HAL_TIMEx_HallSensor_MspInit(htim);
195 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
196 }
197
198 /* Set the TIM state */
199 htim->State = HAL_TIM_STATE_BUSY;
200
201 /* Configure the Time base in the Encoder Mode */
202 TIM_Base_SetConfig(htim->Instance, &htim->Init);
203
204 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
205 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
206
207 /* Reset the IC1PSC Bits */
208 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
209 /* Set the IC1PSC value */
210 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
211
212 /* Enable the Hall sensor interface (XOR function of the three inputs) */
213 htim->Instance->CR2 |= TIM_CR2_TI1S;
214
215 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
216 htim->Instance->SMCR &= ~TIM_SMCR_TS;
217 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
218
219 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
220 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
221 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
222
223 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
224 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
225 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
226 OC_Config.OCMode = TIM_OCMODE_PWM2;
227 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
228 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
229 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
230 OC_Config.Pulse = sConfig->Commutation_Delay;
231
232 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
233
234 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
235 register to 101 */
236 htim->Instance->CR2 &= ~TIM_CR2_MMS;
237 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
238
239 /* Initialize the DMA burst operation state */
240 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
241
242 /* Initialize the TIM channels state */
243 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
244 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
245 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
246 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
247
248 /* Initialize the TIM state*/
249 htim->State = HAL_TIM_STATE_READY;
250
251 return HAL_OK;
252 }
253
254 /**
255 * @brief DeInitializes the TIM Hall Sensor interface
256 * @param htim TIM Hall Sensor Interface handle
257 * @retval HAL status
258 */
HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef * htim)259 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
260 {
261 /* Check the parameters */
262 assert_param(IS_TIM_INSTANCE(htim->Instance));
263
264 htim->State = HAL_TIM_STATE_BUSY;
265
266 /* Disable the TIM Peripheral Clock */
267 __HAL_TIM_DISABLE(htim);
268
269 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
270 if (htim->HallSensor_MspDeInitCallback == NULL)
271 {
272 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
273 }
274 /* DeInit the low level hardware */
275 htim->HallSensor_MspDeInitCallback(htim);
276 #else
277 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
278 HAL_TIMEx_HallSensor_MspDeInit(htim);
279 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
280
281 /* Change the DMA burst operation state */
282 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
283
284 /* Change the TIM channels state */
285 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
286 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
287 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
288 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
289
290 /* Change TIM state */
291 htim->State = HAL_TIM_STATE_RESET;
292
293 /* Release Lock */
294 __HAL_UNLOCK(htim);
295
296 return HAL_OK;
297 }
298
299 /**
300 * @brief Initializes the TIM Hall Sensor MSP.
301 * @param htim TIM Hall Sensor Interface handle
302 * @retval None
303 */
HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef * htim)304 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
305 {
306 /* Prevent unused argument(s) compilation warning */
307 UNUSED(htim);
308
309 /* NOTE : This function should not be modified, when the callback is needed,
310 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
311 */
312 }
313
314 /**
315 * @brief DeInitializes TIM Hall Sensor MSP.
316 * @param htim TIM Hall Sensor Interface handle
317 * @retval None
318 */
HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef * htim)319 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
320 {
321 /* Prevent unused argument(s) compilation warning */
322 UNUSED(htim);
323
324 /* NOTE : This function should not be modified, when the callback is needed,
325 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
326 */
327 }
328
329 /**
330 * @brief Starts the TIM Hall Sensor Interface.
331 * @param htim TIM Hall Sensor Interface handle
332 * @retval HAL status
333 */
HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef * htim)334 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
335 {
336 uint32_t tmpsmcr;
337 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
338 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
339 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
340 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
341
342 /* Check the parameters */
343 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
344
345 /* Check the TIM channels state */
346 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
347 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
348 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
349 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
350 {
351 return HAL_ERROR;
352 }
353
354 /* Set the TIM channels state */
355 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
356 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
357 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
358 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
359
360 /* Enable the Input Capture channel 1
361 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
362 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
363 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
364
365 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
366 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
367 {
368 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
369 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
370 {
371 __HAL_TIM_ENABLE(htim);
372 }
373 }
374 else
375 {
376 __HAL_TIM_ENABLE(htim);
377 }
378
379 /* Return function status */
380 return HAL_OK;
381 }
382
383 /**
384 * @brief Stops the TIM Hall sensor Interface.
385 * @param htim TIM Hall Sensor Interface handle
386 * @retval HAL status
387 */
HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef * htim)388 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
389 {
390 /* Check the parameters */
391 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
392
393 /* Disable the Input Capture channels 1, 2 and 3
394 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
395 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
396 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
397
398 /* Disable the Peripheral */
399 __HAL_TIM_DISABLE(htim);
400
401 /* Set the TIM channels state */
402 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
403 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
404 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
405 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
406
407 /* Return function status */
408 return HAL_OK;
409 }
410
411 /**
412 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
413 * @param htim TIM Hall Sensor Interface handle
414 * @retval HAL status
415 */
HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef * htim)416 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
417 {
418 uint32_t tmpsmcr;
419 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
420 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
421 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
422 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
423
424 /* Check the parameters */
425 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
426
427 /* Check the TIM channels state */
428 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
429 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
430 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
431 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
432 {
433 return HAL_ERROR;
434 }
435
436 /* Set the TIM channels state */
437 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
438 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
439 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
440 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
441
442 /* Enable the capture compare Interrupts 1 event */
443 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
444
445 /* Enable the Input Capture channel 1
446 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
447 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
448 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
449
450 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
451 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
452 {
453 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
454 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
455 {
456 __HAL_TIM_ENABLE(htim);
457 }
458 }
459 else
460 {
461 __HAL_TIM_ENABLE(htim);
462 }
463
464 /* Return function status */
465 return HAL_OK;
466 }
467
468 /**
469 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
470 * @param htim TIM Hall Sensor Interface handle
471 * @retval HAL status
472 */
HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef * htim)473 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
474 {
475 /* Check the parameters */
476 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
477
478 /* Disable the Input Capture channel 1
479 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
480 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
481 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
482
483 /* Disable the capture compare Interrupts event */
484 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
485
486 /* Disable the Peripheral */
487 __HAL_TIM_DISABLE(htim);
488
489 /* Set the TIM channels state */
490 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
491 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
492 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
493 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
494
495 /* Return function status */
496 return HAL_OK;
497 }
498
499 /**
500 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
501 * @param htim TIM Hall Sensor Interface handle
502 * @param pData The destination Buffer address.
503 * @param Length The length of data to be transferred from TIM peripheral to memory.
504 * @retval HAL status
505 */
HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)506 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
507 {
508 uint32_t tmpsmcr;
509 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
510 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
511
512 /* Check the parameters */
513 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
514
515 /* Set the TIM channel state */
516 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
517 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
518 {
519 return HAL_BUSY;
520 }
521 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
522 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
523 {
524 if ((pData == NULL) || (Length == 0U))
525 {
526 return HAL_ERROR;
527 }
528 else
529 {
530 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
531 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
532 }
533 }
534 else
535 {
536 return HAL_ERROR;
537 }
538
539 /* Enable the Input Capture channel 1
540 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
541 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
542 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
543
544 /* Set the DMA Input Capture 1 Callbacks */
545 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
546 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
547 /* Set the DMA error callback */
548 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
549
550 /* Enable the DMA channel for Capture 1*/
551 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
552 {
553 /* Return error status */
554 return HAL_ERROR;
555 }
556 /* Enable the capture compare 1 Interrupt */
557 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
558
559 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
560 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
561 {
562 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
563 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
564 {
565 __HAL_TIM_ENABLE(htim);
566 }
567 }
568 else
569 {
570 __HAL_TIM_ENABLE(htim);
571 }
572
573 /* Return function status */
574 return HAL_OK;
575 }
576
577 /**
578 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
579 * @param htim TIM Hall Sensor Interface handle
580 * @retval HAL status
581 */
HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef * htim)582 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
583 {
584 /* Check the parameters */
585 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
586
587 /* Disable the Input Capture channel 1
588 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
589 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
590 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
591
592
593 /* Disable the capture compare Interrupts 1 event */
594 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
595
596 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
597
598 /* Disable the Peripheral */
599 __HAL_TIM_DISABLE(htim);
600
601 /* Set the TIM channel state */
602 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
603 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
604
605 /* Return function status */
606 return HAL_OK;
607 }
608
609 /**
610 * @}
611 */
612
613 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
614 * @brief Timer Complementary Output Compare functions
615 *
616 @verbatim
617 ==============================================================================
618 ##### Timer Complementary Output Compare functions #####
619 ==============================================================================
620 [..]
621 This section provides functions allowing to:
622 (+) Start the Complementary Output Compare/PWM.
623 (+) Stop the Complementary Output Compare/PWM.
624 (+) Start the Complementary Output Compare/PWM and enable interrupts.
625 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
626 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
627 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
628
629 @endverbatim
630 * @{
631 */
632
633 /**
634 * @brief Starts the TIM Output Compare signal generation on the complementary
635 * output.
636 * @param htim TIM Output Compare handle
637 * @param Channel TIM Channel to be enabled
638 * This parameter can be one of the following values:
639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
643 * @retval HAL status
644 */
HAL_TIMEx_OCN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)645 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
646 {
647 uint32_t tmpsmcr;
648
649 /* Check the parameters */
650 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
651
652 /* Check the TIM complementary channel state */
653 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
654 {
655 return HAL_ERROR;
656 }
657
658 /* Set the TIM complementary channel state */
659 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
660
661 /* Enable the Capture compare channel N */
662 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
663
664 /* Enable the Main Output */
665 __HAL_TIM_MOE_ENABLE(htim);
666
667 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
668 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
669 {
670 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
671 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
672 {
673 __HAL_TIM_ENABLE(htim);
674 }
675 }
676 else
677 {
678 __HAL_TIM_ENABLE(htim);
679 }
680
681 /* Return function status */
682 return HAL_OK;
683 }
684
685 /**
686 * @brief Stops the TIM Output Compare signal generation on the complementary
687 * output.
688 * @param htim TIM handle
689 * @param Channel TIM Channel to be disabled
690 * This parameter can be one of the following values:
691 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
692 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
693 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
694 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
695 * @retval HAL status
696 */
HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)697 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
698 {
699 /* Check the parameters */
700 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
701
702 /* Disable the Capture compare channel N */
703 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
704
705 /* Disable the Main Output */
706 __HAL_TIM_MOE_DISABLE(htim);
707
708 /* Disable the Peripheral */
709 __HAL_TIM_DISABLE(htim);
710
711 /* Set the TIM complementary channel state */
712 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
713
714 /* Return function status */
715 return HAL_OK;
716 }
717
718 /**
719 * @brief Starts the TIM Output Compare signal generation in interrupt mode
720 * on the complementary output.
721 * @param htim TIM OC handle
722 * @param Channel TIM Channel to be enabled
723 * This parameter can be one of the following values:
724 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
725 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
726 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
727 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
728 * @retval HAL status
729 */
HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)730 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
731 {
732 HAL_StatusTypeDef status = HAL_OK;
733 uint32_t tmpsmcr;
734
735 /* Check the parameters */
736 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
737
738 /* Check the TIM complementary channel state */
739 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
740 {
741 return HAL_ERROR;
742 }
743
744 /* Set the TIM complementary channel state */
745 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
746
747 switch (Channel)
748 {
749 case TIM_CHANNEL_1:
750 {
751 /* Enable the TIM Output Compare interrupt */
752 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
753 break;
754 }
755
756 case TIM_CHANNEL_2:
757 {
758 /* Enable the TIM Output Compare interrupt */
759 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
760 break;
761 }
762
763 case TIM_CHANNEL_3:
764 {
765 /* Enable the TIM Output Compare interrupt */
766 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
767 break;
768 }
769
770
771 case TIM_CHANNEL_4:
772 {
773 /* Enable the TIM Output Compare interrupt */
774 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
775 break;
776 }
777
778 default:
779 status = HAL_ERROR;
780 break;
781 }
782
783 if (status == HAL_OK)
784 {
785 /* Enable the TIM Break interrupt */
786 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
787
788 /* Enable the Capture compare channel N */
789 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
790
791 /* Enable the Main Output */
792 __HAL_TIM_MOE_ENABLE(htim);
793
794 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
795 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
796 {
797 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
798 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
799 {
800 __HAL_TIM_ENABLE(htim);
801 }
802 }
803 else
804 {
805 __HAL_TIM_ENABLE(htim);
806 }
807 }
808
809 /* Return function status */
810 return status;
811 }
812
813 /**
814 * @brief Stops the TIM Output Compare signal generation in interrupt mode
815 * on the complementary output.
816 * @param htim TIM Output Compare handle
817 * @param Channel TIM Channel to be disabled
818 * This parameter can be one of the following values:
819 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
820 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
821 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
822 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
823 * @retval HAL status
824 */
HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)825 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
826 {
827 HAL_StatusTypeDef status = HAL_OK;
828 uint32_t tmpccer;
829
830 /* Check the parameters */
831 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
832
833 switch (Channel)
834 {
835 case TIM_CHANNEL_1:
836 {
837 /* Disable the TIM Output Compare interrupt */
838 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
839 break;
840 }
841
842 case TIM_CHANNEL_2:
843 {
844 /* Disable the TIM Output Compare interrupt */
845 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
846 break;
847 }
848
849 case TIM_CHANNEL_3:
850 {
851 /* Disable the TIM Output Compare interrupt */
852 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
853 break;
854 }
855
856 case TIM_CHANNEL_4:
857 {
858 /* Disable the TIM Output Compare interrupt */
859 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
860 break;
861 }
862
863 default:
864 status = HAL_ERROR;
865 break;
866 }
867
868 if (status == HAL_OK)
869 {
870 /* Disable the Capture compare channel N */
871 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
872
873 /* Disable the TIM Break interrupt (only if no more channel is active) */
874 tmpccer = htim->Instance->CCER;
875 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
876 {
877 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
878 }
879
880 /* Disable the Main Output */
881 __HAL_TIM_MOE_DISABLE(htim);
882
883 /* Disable the Peripheral */
884 __HAL_TIM_DISABLE(htim);
885
886 /* Set the TIM complementary channel state */
887 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
888 }
889
890 /* Return function status */
891 return status;
892 }
893
894 /**
895 * @brief Starts the TIM Output Compare signal generation in DMA mode
896 * on the complementary output.
897 * @param htim TIM Output Compare handle
898 * @param Channel TIM Channel to be enabled
899 * This parameter can be one of the following values:
900 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
901 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
902 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
903 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
904 * @param pData The source Buffer address.
905 * @param Length The length of data to be transferred from memory to TIM peripheral
906 * @retval HAL status
907 */
HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)908 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
909 uint16_t Length)
910 {
911 HAL_StatusTypeDef status = HAL_OK;
912 uint32_t tmpsmcr;
913
914 /* Check the parameters */
915 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
916
917 /* Set the TIM complementary channel state */
918 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
919 {
920 return HAL_BUSY;
921 }
922 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
923 {
924 if ((pData == NULL) || (Length == 0U))
925 {
926 return HAL_ERROR;
927 }
928 else
929 {
930 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
931 }
932 }
933 else
934 {
935 return HAL_ERROR;
936 }
937
938 switch (Channel)
939 {
940 case TIM_CHANNEL_1:
941 {
942 /* Set the DMA compare callbacks */
943 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
944 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
945
946 /* Set the DMA error callback */
947 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
948
949 /* Enable the DMA channel */
950 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
951 Length) != HAL_OK)
952 {
953 /* Return error status */
954 return HAL_ERROR;
955 }
956 /* Enable the TIM Output Compare DMA request */
957 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
958 break;
959 }
960
961 case TIM_CHANNEL_2:
962 {
963 /* Set the DMA compare callbacks */
964 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
965 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
966
967 /* Set the DMA error callback */
968 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
969
970 /* Enable the DMA channel */
971 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
972 Length) != HAL_OK)
973 {
974 /* Return error status */
975 return HAL_ERROR;
976 }
977 /* Enable the TIM Output Compare DMA request */
978 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
979 break;
980 }
981
982 case TIM_CHANNEL_3:
983 {
984 /* Set the DMA compare callbacks */
985 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
986 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
987
988 /* Set the DMA error callback */
989 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
990
991 /* Enable the DMA channel */
992 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
993 Length) != HAL_OK)
994 {
995 /* Return error status */
996 return HAL_ERROR;
997 }
998 /* Enable the TIM Output Compare DMA request */
999 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1000 break;
1001 }
1002
1003 case TIM_CHANNEL_4:
1004 {
1005 /* Set the DMA compare callbacks */
1006 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1007 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1008
1009 /* Set the DMA error callback */
1010 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
1011
1012 /* Enable the DMA channel */
1013 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1014 Length) != HAL_OK)
1015 {
1016 /* Return error status */
1017 return HAL_ERROR;
1018 }
1019 /* Enable the TIM Output Compare DMA request */
1020 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1021 break;
1022 }
1023
1024 default:
1025 status = HAL_ERROR;
1026 break;
1027 }
1028
1029 if (status == HAL_OK)
1030 {
1031 /* Enable the Capture compare channel N */
1032 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1033
1034 /* Enable the Main Output */
1035 __HAL_TIM_MOE_ENABLE(htim);
1036
1037 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1038 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1039 {
1040 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1041 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1042 {
1043 __HAL_TIM_ENABLE(htim);
1044 }
1045 }
1046 else
1047 {
1048 __HAL_TIM_ENABLE(htim);
1049 }
1050 }
1051
1052 /* Return function status */
1053 return status;
1054 }
1055
1056 /**
1057 * @brief Stops the TIM Output Compare signal generation in DMA mode
1058 * on the complementary output.
1059 * @param htim TIM Output Compare handle
1060 * @param Channel TIM Channel to be disabled
1061 * This parameter can be one of the following values:
1062 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1063 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1064 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1065 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1066 * @retval HAL status
1067 */
HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1068 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1069 {
1070 HAL_StatusTypeDef status = HAL_OK;
1071
1072 /* Check the parameters */
1073 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1074
1075 switch (Channel)
1076 {
1077 case TIM_CHANNEL_1:
1078 {
1079 /* Disable the TIM Output Compare DMA request */
1080 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1081 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1082 break;
1083 }
1084
1085 case TIM_CHANNEL_2:
1086 {
1087 /* Disable the TIM Output Compare DMA request */
1088 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1089 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1090 break;
1091 }
1092
1093 case TIM_CHANNEL_3:
1094 {
1095 /* Disable the TIM Output Compare DMA request */
1096 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1097 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1098 break;
1099 }
1100
1101 case TIM_CHANNEL_4:
1102 {
1103 /* Disable the TIM Output Compare interrupt */
1104 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1105 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1106 break;
1107 }
1108
1109 default:
1110 status = HAL_ERROR;
1111 break;
1112 }
1113
1114 if (status == HAL_OK)
1115 {
1116 /* Disable the Capture compare channel N */
1117 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1118
1119 /* Disable the Main Output */
1120 __HAL_TIM_MOE_DISABLE(htim);
1121
1122 /* Disable the Peripheral */
1123 __HAL_TIM_DISABLE(htim);
1124
1125 /* Set the TIM complementary channel state */
1126 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1127 }
1128
1129 /* Return function status */
1130 return status;
1131 }
1132
1133 /**
1134 * @}
1135 */
1136
1137 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
1138 * @brief Timer Complementary PWM functions
1139 *
1140 @verbatim
1141 ==============================================================================
1142 ##### Timer Complementary PWM functions #####
1143 ==============================================================================
1144 [..]
1145 This section provides functions allowing to:
1146 (+) Start the Complementary PWM.
1147 (+) Stop the Complementary PWM.
1148 (+) Start the Complementary PWM and enable interrupts.
1149 (+) Stop the Complementary PWM and disable interrupts.
1150 (+) Start the Complementary PWM and enable DMA transfers.
1151 (+) Stop the Complementary PWM and disable DMA transfers.
1152 @endverbatim
1153 * @{
1154 */
1155
1156 /**
1157 * @brief Starts the PWM signal generation on the complementary output.
1158 * @param htim TIM handle
1159 * @param Channel TIM Channel to be enabled
1160 * This parameter can be one of the following values:
1161 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1162 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1163 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1164 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1165 * @retval HAL status
1166 */
HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1167 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1168 {
1169 uint32_t tmpsmcr;
1170
1171 /* Check the parameters */
1172 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1173
1174 /* Check the TIM complementary channel state */
1175 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1176 {
1177 return HAL_ERROR;
1178 }
1179
1180 /* Set the TIM complementary channel state */
1181 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1182
1183 /* Enable the complementary PWM output */
1184 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1185
1186 /* Enable the Main Output */
1187 __HAL_TIM_MOE_ENABLE(htim);
1188
1189 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1190 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1191 {
1192 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1193 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1194 {
1195 __HAL_TIM_ENABLE(htim);
1196 }
1197 }
1198 else
1199 {
1200 __HAL_TIM_ENABLE(htim);
1201 }
1202
1203 /* Return function status */
1204 return HAL_OK;
1205 }
1206
1207 /**
1208 * @brief Stops the PWM signal generation on the complementary output.
1209 * @param htim TIM handle
1210 * @param Channel TIM Channel to be disabled
1211 * This parameter can be one of the following values:
1212 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1213 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1214 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1215 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1216 * @retval HAL status
1217 */
HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1218 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1219 {
1220 /* Check the parameters */
1221 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1222
1223 /* Disable the complementary PWM output */
1224 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1225
1226 /* Disable the Main Output */
1227 __HAL_TIM_MOE_DISABLE(htim);
1228
1229 /* Disable the Peripheral */
1230 __HAL_TIM_DISABLE(htim);
1231
1232 /* Set the TIM complementary channel state */
1233 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1234
1235 /* Return function status */
1236 return HAL_OK;
1237 }
1238
1239 /**
1240 * @brief Starts the PWM signal generation in interrupt mode on the
1241 * complementary output.
1242 * @param htim TIM handle
1243 * @param Channel TIM Channel to be disabled
1244 * This parameter can be one of the following values:
1245 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1246 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1247 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1248 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1249 * @retval HAL status
1250 */
HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1251 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1252 {
1253 HAL_StatusTypeDef status = HAL_OK;
1254 uint32_t tmpsmcr;
1255
1256 /* Check the parameters */
1257 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1258
1259 /* Check the TIM complementary channel state */
1260 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1261 {
1262 return HAL_ERROR;
1263 }
1264
1265 /* Set the TIM complementary channel state */
1266 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1267
1268 switch (Channel)
1269 {
1270 case TIM_CHANNEL_1:
1271 {
1272 /* Enable the TIM Capture/Compare 1 interrupt */
1273 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1274 break;
1275 }
1276
1277 case TIM_CHANNEL_2:
1278 {
1279 /* Enable the TIM Capture/Compare 2 interrupt */
1280 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1281 break;
1282 }
1283
1284 case TIM_CHANNEL_3:
1285 {
1286 /* Enable the TIM Capture/Compare 3 interrupt */
1287 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1288 break;
1289 }
1290
1291 case TIM_CHANNEL_4:
1292 {
1293 /* Enable the TIM Capture/Compare 4 interrupt */
1294 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1295 break;
1296 }
1297
1298 default:
1299 status = HAL_ERROR;
1300 break;
1301 }
1302
1303 if (status == HAL_OK)
1304 {
1305 /* Enable the TIM Break interrupt */
1306 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1307
1308 /* Enable the complementary PWM output */
1309 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1310
1311 /* Enable the Main Output */
1312 __HAL_TIM_MOE_ENABLE(htim);
1313
1314 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1315 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1316 {
1317 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1318 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1319 {
1320 __HAL_TIM_ENABLE(htim);
1321 }
1322 }
1323 else
1324 {
1325 __HAL_TIM_ENABLE(htim);
1326 }
1327 }
1328
1329 /* Return function status */
1330 return status;
1331 }
1332
1333 /**
1334 * @brief Stops the PWM signal generation in interrupt mode on the
1335 * complementary output.
1336 * @param htim TIM handle
1337 * @param Channel TIM Channel to be disabled
1338 * This parameter can be one of the following values:
1339 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1340 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1341 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1342 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1343 * @retval HAL status
1344 */
HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1345 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1346 {
1347 HAL_StatusTypeDef status = HAL_OK;
1348 uint32_t tmpccer;
1349
1350 /* Check the parameters */
1351 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1352
1353 switch (Channel)
1354 {
1355 case TIM_CHANNEL_1:
1356 {
1357 /* Disable the TIM Capture/Compare 1 interrupt */
1358 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1359 break;
1360 }
1361
1362 case TIM_CHANNEL_2:
1363 {
1364 /* Disable the TIM Capture/Compare 2 interrupt */
1365 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1366 break;
1367 }
1368
1369 case TIM_CHANNEL_3:
1370 {
1371 /* Disable the TIM Capture/Compare 3 interrupt */
1372 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1373 break;
1374 }
1375
1376 case TIM_CHANNEL_4:
1377 {
1378 /* Disable the TIM Capture/Compare 4 interrupt */
1379 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1380 break;
1381 }
1382
1383 default:
1384 status = HAL_ERROR;
1385 break;
1386 }
1387
1388 if (status == HAL_OK)
1389 {
1390 /* Disable the complementary PWM output */
1391 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1392
1393 /* Disable the TIM Break interrupt (only if no more channel is active) */
1394 tmpccer = htim->Instance->CCER;
1395 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
1396 {
1397 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1398 }
1399
1400 /* Disable the Main Output */
1401 __HAL_TIM_MOE_DISABLE(htim);
1402
1403 /* Disable the Peripheral */
1404 __HAL_TIM_DISABLE(htim);
1405
1406 /* Set the TIM complementary channel state */
1407 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1408 }
1409
1410 /* Return function status */
1411 return status;
1412 }
1413
1414 /**
1415 * @brief Starts the TIM PWM signal generation in DMA mode on the
1416 * complementary output
1417 * @param htim TIM handle
1418 * @param Channel TIM Channel to be enabled
1419 * This parameter can be one of the following values:
1420 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1421 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1422 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1423 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1424 * @param pData The source Buffer address.
1425 * @param Length The length of data to be transferred from memory to TIM peripheral
1426 * @retval HAL status
1427 */
HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1428 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1429 uint16_t Length)
1430 {
1431 HAL_StatusTypeDef status = HAL_OK;
1432 uint32_t tmpsmcr;
1433
1434 /* Check the parameters */
1435 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1436
1437 /* Set the TIM complementary channel state */
1438 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1439 {
1440 return HAL_BUSY;
1441 }
1442 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1443 {
1444 if ((pData == NULL) || (Length == 0U))
1445 {
1446 return HAL_ERROR;
1447 }
1448 else
1449 {
1450 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1451 }
1452 }
1453 else
1454 {
1455 return HAL_ERROR;
1456 }
1457
1458 switch (Channel)
1459 {
1460 case TIM_CHANNEL_1:
1461 {
1462 /* Set the DMA compare callbacks */
1463 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1464 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1465
1466 /* Set the DMA error callback */
1467 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
1468
1469 /* Enable the DMA channel */
1470 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1471 Length) != HAL_OK)
1472 {
1473 /* Return error status */
1474 return HAL_ERROR;
1475 }
1476 /* Enable the TIM Capture/Compare 1 DMA request */
1477 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1478 break;
1479 }
1480
1481 case TIM_CHANNEL_2:
1482 {
1483 /* Set the DMA compare callbacks */
1484 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1485 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1486
1487 /* Set the DMA error callback */
1488 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
1489
1490 /* Enable the DMA channel */
1491 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1492 Length) != HAL_OK)
1493 {
1494 /* Return error status */
1495 return HAL_ERROR;
1496 }
1497 /* Enable the TIM Capture/Compare 2 DMA request */
1498 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1499 break;
1500 }
1501
1502 case TIM_CHANNEL_3:
1503 {
1504 /* Set the DMA compare callbacks */
1505 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1506 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1507
1508 /* Set the DMA error callback */
1509 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
1510
1511 /* Enable the DMA channel */
1512 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1513 Length) != HAL_OK)
1514 {
1515 /* Return error status */
1516 return HAL_ERROR;
1517 }
1518 /* Enable the TIM Capture/Compare 3 DMA request */
1519 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1520 break;
1521 }
1522
1523 case TIM_CHANNEL_4:
1524 {
1525 /* Set the DMA compare callbacks */
1526 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1527 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1528
1529 /* Set the DMA error callback */
1530 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
1531
1532 /* Enable the DMA channel */
1533 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1534 Length) != HAL_OK)
1535 {
1536 /* Return error status */
1537 return HAL_ERROR;
1538 }
1539 /* Enable the TIM Capture/Compare 4 DMA request */
1540 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1541 break;
1542 }
1543
1544 default:
1545 status = HAL_ERROR;
1546 break;
1547 }
1548
1549 if (status == HAL_OK)
1550 {
1551 /* Enable the complementary PWM output */
1552 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1553
1554 /* Enable the Main Output */
1555 __HAL_TIM_MOE_ENABLE(htim);
1556
1557 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1558 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1559 {
1560 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1561 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1562 {
1563 __HAL_TIM_ENABLE(htim);
1564 }
1565 }
1566 else
1567 {
1568 __HAL_TIM_ENABLE(htim);
1569 }
1570 }
1571
1572 /* Return function status */
1573 return status;
1574 }
1575
1576 /**
1577 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1578 * output
1579 * @param htim TIM handle
1580 * @param Channel TIM Channel to be disabled
1581 * This parameter can be one of the following values:
1582 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1583 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1584 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1585 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1586 * @retval HAL status
1587 */
HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1588 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1589 {
1590 HAL_StatusTypeDef status = HAL_OK;
1591
1592 /* Check the parameters */
1593 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1594
1595 switch (Channel)
1596 {
1597 case TIM_CHANNEL_1:
1598 {
1599 /* Disable the TIM Capture/Compare 1 DMA request */
1600 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1601 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1602 break;
1603 }
1604
1605 case TIM_CHANNEL_2:
1606 {
1607 /* Disable the TIM Capture/Compare 2 DMA request */
1608 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1609 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1610 break;
1611 }
1612
1613 case TIM_CHANNEL_3:
1614 {
1615 /* Disable the TIM Capture/Compare 3 DMA request */
1616 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1617 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1618 break;
1619 }
1620
1621 case TIM_CHANNEL_4:
1622 {
1623 /* Disable the TIM Capture/Compare 4 DMA request */
1624 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1625 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1626 break;
1627 }
1628
1629 default:
1630 status = HAL_ERROR;
1631 break;
1632 }
1633
1634 if (status == HAL_OK)
1635 {
1636 /* Disable the complementary PWM output */
1637 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1638
1639 /* Disable the Main Output */
1640 __HAL_TIM_MOE_DISABLE(htim);
1641
1642 /* Disable the Peripheral */
1643 __HAL_TIM_DISABLE(htim);
1644
1645 /* Set the TIM complementary channel state */
1646 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1647 }
1648
1649 /* Return function status */
1650 return status;
1651 }
1652
1653 /**
1654 * @}
1655 */
1656
1657 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1658 * @brief Timer Complementary One Pulse functions
1659 *
1660 @verbatim
1661 ==============================================================================
1662 ##### Timer Complementary One Pulse functions #####
1663 ==============================================================================
1664 [..]
1665 This section provides functions allowing to:
1666 (+) Start the Complementary One Pulse generation.
1667 (+) Stop the Complementary One Pulse.
1668 (+) Start the Complementary One Pulse and enable interrupts.
1669 (+) Stop the Complementary One Pulse and disable interrupts.
1670
1671 @endverbatim
1672 * @{
1673 */
1674
1675 /**
1676 * @brief Starts the TIM One Pulse signal generation on the complementary
1677 * output.
1678 * @note OutputChannel must match the pulse output channel chosen when calling
1679 * @ref HAL_TIM_OnePulse_ConfigChannel().
1680 * @param htim TIM One Pulse handle
1681 * @param OutputChannel pulse output channel to enable
1682 * This parameter can be one of the following values:
1683 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1684 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1685 * @retval HAL status
1686 */
HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1687 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1688 {
1689 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1690 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1691 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1692 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1693 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1694
1695 /* Check the parameters */
1696 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1697
1698 /* Check the TIM channels state */
1699 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1700 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1701 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1702 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1703 {
1704 return HAL_ERROR;
1705 }
1706
1707 /* Set the TIM channels state */
1708 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1709 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1710 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1711 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1712
1713 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1714 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1715 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1716
1717 /* Enable the Main Output */
1718 __HAL_TIM_MOE_ENABLE(htim);
1719
1720 /* Return function status */
1721 return HAL_OK;
1722 }
1723
1724 /**
1725 * @brief Stops the TIM One Pulse signal generation on the complementary
1726 * output.
1727 * @note OutputChannel must match the pulse output channel chosen when calling
1728 * @ref HAL_TIM_OnePulse_ConfigChannel().
1729 * @param htim TIM One Pulse handle
1730 * @param OutputChannel pulse output channel to disable
1731 * This parameter can be one of the following values:
1732 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1733 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1734 * @retval HAL status
1735 */
HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1736 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1737 {
1738 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1739
1740 /* Check the parameters */
1741 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1742
1743 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1744 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1745 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1746
1747 /* Disable the Main Output */
1748 __HAL_TIM_MOE_DISABLE(htim);
1749
1750 /* Disable the Peripheral */
1751 __HAL_TIM_DISABLE(htim);
1752
1753 /* Set the TIM channels state */
1754 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1755 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1756 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1757 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1758
1759 /* Return function status */
1760 return HAL_OK;
1761 }
1762
1763 /**
1764 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1765 * complementary channel.
1766 * @note OutputChannel must match the pulse output channel chosen when calling
1767 * @ref HAL_TIM_OnePulse_ConfigChannel().
1768 * @param htim TIM One Pulse handle
1769 * @param OutputChannel pulse output channel to enable
1770 * This parameter can be one of the following values:
1771 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1772 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1773 * @retval HAL status
1774 */
HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1775 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1776 {
1777 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1778 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1779 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1780 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1781 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1782
1783 /* Check the parameters */
1784 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1785
1786 /* Check the TIM channels state */
1787 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1788 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1789 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1790 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1791 {
1792 return HAL_ERROR;
1793 }
1794
1795 /* Set the TIM channels state */
1796 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1797 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1798 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1799 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1800
1801 /* Enable the TIM Capture/Compare 1 interrupt */
1802 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1803
1804 /* Enable the TIM Capture/Compare 2 interrupt */
1805 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1806
1807 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1808 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1809 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1810
1811 /* Enable the Main Output */
1812 __HAL_TIM_MOE_ENABLE(htim);
1813
1814 /* Return function status */
1815 return HAL_OK;
1816 }
1817
1818 /**
1819 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1820 * complementary channel.
1821 * @note OutputChannel must match the pulse output channel chosen when calling
1822 * @ref HAL_TIM_OnePulse_ConfigChannel().
1823 * @param htim TIM One Pulse handle
1824 * @param OutputChannel pulse output channel to disable
1825 * This parameter can be one of the following values:
1826 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1827 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1828 * @retval HAL status
1829 */
HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1830 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1831 {
1832 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1833
1834 /* Check the parameters */
1835 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1836
1837 /* Disable the TIM Capture/Compare 1 interrupt */
1838 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1839
1840 /* Disable the TIM Capture/Compare 2 interrupt */
1841 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1842
1843 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1844 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1845 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1846
1847 /* Disable the Main Output */
1848 __HAL_TIM_MOE_DISABLE(htim);
1849
1850 /* Disable the Peripheral */
1851 __HAL_TIM_DISABLE(htim);
1852
1853 /* Set the TIM channels state */
1854 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1855 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1856 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1857 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1858
1859 /* Return function status */
1860 return HAL_OK;
1861 }
1862
1863 /**
1864 * @}
1865 */
1866
1867 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1868 * @brief Peripheral Control functions
1869 *
1870 @verbatim
1871 ==============================================================================
1872 ##### Peripheral Control functions #####
1873 ==============================================================================
1874 [..]
1875 This section provides functions allowing to:
1876 (+) Configure the commutation event in case of use of the Hall sensor interface.
1877 (+) Configure Output channels for OC and PWM mode.
1878
1879 (+) Configure Complementary channels, break features and dead time.
1880 (+) Configure Master synchronization.
1881 (+) Configure timer remapping capabilities.
1882 (+) Select timer input source.
1883 (+) Enable or disable channel grouping.
1884 (+) Configure Pulse on compare.
1885 (+) Configure Encoder index.
1886
1887 @endverbatim
1888 * @{
1889 */
1890
1891 /**
1892 * @brief Configure the TIM commutation event sequence.
1893 * @note This function is mandatory to use the commutation event in order to
1894 * update the configuration at each commutation detection on the TRGI input of the Timer,
1895 * the typical use of this feature is with the use of another Timer(interface Timer)
1896 * configured in Hall sensor interface, this interface Timer will generate the
1897 * commutation at its TRGO output (connected to Timer used in this function) each time
1898 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1899 * @param htim TIM handle
1900 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1901 * This parameter can be one of the following values:
1902 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1903 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1904 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1905 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1906 * @arg TIM_TS_ITR8: Internal trigger 8 selected
1907 * @arg TIM_TS_NONE: No trigger is needed
1908 * @param CommutationSource the Commutation Event source
1909 * This parameter can be one of the following values:
1910 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1911 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1912 * @retval HAL status
1913 */
HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1914 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1915 uint32_t CommutationSource)
1916 {
1917 /* Check the parameters */
1918 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1919 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
1920
1921 __HAL_LOCK(htim);
1922
1923 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1924 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR7) ||
1925 (InputTrigger == TIM_TS_ITR8))
1926 {
1927 /* Select the Input trigger */
1928 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1929 htim->Instance->SMCR |= InputTrigger;
1930 }
1931
1932 /* Select the Capture Compare preload feature */
1933 htim->Instance->CR2 |= TIM_CR2_CCPC;
1934 /* Select the Commutation event source */
1935 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1936 htim->Instance->CR2 |= CommutationSource;
1937
1938 /* Disable Commutation Interrupt */
1939 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1940
1941 /* Disable Commutation DMA request */
1942 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1943
1944 __HAL_UNLOCK(htim);
1945
1946 return HAL_OK;
1947 }
1948
1949 /**
1950 * @brief Configure the TIM commutation event sequence with interrupt.
1951 * @note This function is mandatory to use the commutation event in order to
1952 * update the configuration at each commutation detection on the TRGI input of the Timer,
1953 * the typical use of this feature is with the use of another Timer(interface Timer)
1954 * configured in Hall sensor interface, this interface Timer will generate the
1955 * commutation at its TRGO output (connected to Timer used in this function) each time
1956 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1957 * @param htim TIM handle
1958 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1959 * This parameter can be one of the following values:
1960 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1961 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1962 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1963 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1964 * @arg TIM_TS_ITR8: Internal trigger 8 selected
1965 * @arg TIM_TS_NONE: No trigger is needed
1966 * @param CommutationSource the Commutation Event source
1967 * This parameter can be one of the following values:
1968 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1969 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1970 * @retval HAL status
1971 */
HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1972 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1973 uint32_t CommutationSource)
1974 {
1975 /* Check the parameters */
1976 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1977 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
1978
1979 __HAL_LOCK(htim);
1980
1981 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1982 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR7) ||
1983 (InputTrigger == TIM_TS_ITR8))
1984 {
1985 /* Select the Input trigger */
1986 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1987 htim->Instance->SMCR |= InputTrigger;
1988 }
1989
1990 /* Select the Capture Compare preload feature */
1991 htim->Instance->CR2 |= TIM_CR2_CCPC;
1992 /* Select the Commutation event source */
1993 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1994 htim->Instance->CR2 |= CommutationSource;
1995
1996 /* Disable Commutation DMA request */
1997 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1998
1999 /* Enable the Commutation Interrupt */
2000 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
2001
2002 __HAL_UNLOCK(htim);
2003
2004 return HAL_OK;
2005 }
2006
2007 /**
2008 * @brief Configure the TIM commutation event sequence with DMA.
2009 * @note This function is mandatory to use the commutation event in order to
2010 * update the configuration at each commutation detection on the TRGI input of the Timer,
2011 * the typical use of this feature is with the use of another Timer(interface Timer)
2012 * configured in Hall sensor interface, this interface Timer will generate the
2013 * commutation at its TRGO output (connected to Timer used in this function) each time
2014 * the TI1 of the Interface Timer detect a commutation at its input TI1.
2015 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
2016 * @param htim TIM handle
2017 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
2018 * This parameter can be one of the following values:
2019 * @arg TIM_TS_ITR0: Internal trigger 0 selected
2020 * @arg TIM_TS_ITR1: Internal trigger 1 selected
2021 * @arg TIM_TS_ITR2: Internal trigger 2 selected
2022 * @arg TIM_TS_ITR7: Internal trigger 7 selected
2023 * @arg TIM_TS_ITR8: Internal trigger 8 selected
2024 * @arg TIM_TS_NONE: No trigger is needed
2025 * @param CommutationSource the Commutation Event source
2026 * This parameter can be one of the following values:
2027 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
2028 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
2029 * @retval HAL status
2030 */
HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)2031 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
2032 uint32_t CommutationSource)
2033 {
2034 /* Check the parameters */
2035 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
2036 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
2037
2038 __HAL_LOCK(htim);
2039
2040 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2041 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR7) ||
2042 (InputTrigger == TIM_TS_ITR8))
2043 {
2044 /* Select the Input trigger */
2045 htim->Instance->SMCR &= ~TIM_SMCR_TS;
2046 htim->Instance->SMCR |= InputTrigger;
2047 }
2048
2049 /* Select the Capture Compare preload feature */
2050 htim->Instance->CR2 |= TIM_CR2_CCPC;
2051 /* Select the Commutation event source */
2052 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
2053 htim->Instance->CR2 |= CommutationSource;
2054
2055 /* Enable the Commutation DMA Request */
2056 /* Set the DMA Commutation Callback */
2057 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
2058 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
2059 /* Set the DMA error callback */
2060 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
2061
2062 /* Disable Commutation Interrupt */
2063 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
2064
2065 /* Enable the Commutation DMA Request */
2066 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
2067
2068 __HAL_UNLOCK(htim);
2069
2070 return HAL_OK;
2071 }
2072
2073 /**
2074 * @brief Configures the TIM in master mode.
2075 * @param htim TIM handle.
2076 * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
2077 * contains the selected trigger output (TRGO) and the Master/Slave
2078 * mode.
2079 * @retval HAL status
2080 */
HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef * htim,const TIM_MasterConfigTypeDef * sMasterConfig)2081 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
2082 const TIM_MasterConfigTypeDef *sMasterConfig)
2083 {
2084 uint32_t tmpcr2;
2085 uint32_t tmpsmcr;
2086
2087 /* Check the parameters */
2088 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
2089 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
2090 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
2091
2092 /* Check input state */
2093 __HAL_LOCK(htim);
2094
2095 /* Change the handler state */
2096 htim->State = HAL_TIM_STATE_BUSY;
2097
2098 /* Get the TIMx CR2 register value */
2099 tmpcr2 = htim->Instance->CR2;
2100
2101 /* Get the TIMx SMCR register value */
2102 tmpsmcr = htim->Instance->SMCR;
2103
2104 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
2105 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
2106 {
2107 /* Check the parameters */
2108 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
2109
2110 /* Clear the MMS2 bits */
2111 tmpcr2 &= ~TIM_CR2_MMS2;
2112 /* Select the TRGO2 source*/
2113 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
2114 }
2115
2116 /* Reset the MMS Bits */
2117 tmpcr2 &= ~TIM_CR2_MMS;
2118 /* Select the TRGO source */
2119 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
2120
2121 /* Update TIMx CR2 */
2122 htim->Instance->CR2 = tmpcr2;
2123
2124 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2125 {
2126 /* Reset the MSM Bit */
2127 tmpsmcr &= ~TIM_SMCR_MSM;
2128 /* Set master mode */
2129 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2130
2131 /* Update TIMx SMCR */
2132 htim->Instance->SMCR = tmpsmcr;
2133 }
2134
2135 /* Change the htim state */
2136 htim->State = HAL_TIM_STATE_READY;
2137
2138 __HAL_UNLOCK(htim);
2139
2140 return HAL_OK;
2141 }
2142
2143 /**
2144 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2145 * and the AOE(automatic output enable).
2146 * @param htim TIM handle
2147 * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2148 * contains the BDTR Register configuration information for the TIM peripheral.
2149 * @note Interrupts can be generated when an active level is detected on the
2150 * break input, the break 2 input or the system break input. Break
2151 * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
2152 * @retval HAL status
2153 */
HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef * htim,const TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)2154 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2155 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
2156 {
2157 /* Keep this variable initialized to 0 as it is used to configure BDTR register */
2158 uint32_t tmpbdtr = 0U;
2159
2160 /* Check the parameters */
2161 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2162 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2163 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2164 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2165 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2166 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2167 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2168 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2169 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2170 assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
2171
2172 /* Check input state */
2173 __HAL_LOCK(htim);
2174
2175 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2176 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2177
2178 /* Set the BDTR bits */
2179 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
2180 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
2181 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
2182 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
2183 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
2184 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
2185 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
2186 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
2187 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
2188
2189 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
2190 {
2191 /* Check the parameters */
2192 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2193 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2194 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2195 assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
2196
2197 /* Set the BREAK2 input related BDTR bits */
2198 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
2199 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
2200 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
2201 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
2202 }
2203
2204 /* Set TIMx_BDTR */
2205 htim->Instance->BDTR = tmpbdtr;
2206
2207 __HAL_UNLOCK(htim);
2208
2209 return HAL_OK;
2210 }
2211
2212 /**
2213 * @brief Configures the break input source.
2214 * @param htim TIM handle.
2215 * @param BreakInput Break input to configure
2216 * This parameter can be one of the following values:
2217 * @arg TIM_BREAKINPUT_BRK: Timer break input
2218 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2219 * @param sBreakInputConfig Break input source configuration
2220 * @retval HAL status
2221 */
HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput,const TIMEx_BreakInputConfigTypeDef * sBreakInputConfig)2222 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
2223 uint32_t BreakInput,
2224 const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
2225 {
2226 HAL_StatusTypeDef status = HAL_OK;
2227 uint32_t tmporx;
2228 uint32_t bkin_enable_mask;
2229 uint32_t bkin_polarity_mask;
2230 uint32_t bkin_enable_bitpos;
2231 uint32_t bkin_polarity_bitpos;
2232
2233 /* Check the parameters */
2234 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2235 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2236 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
2237 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
2238 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
2239
2240 /* Check input state */
2241 __HAL_LOCK(htim);
2242
2243 switch (sBreakInputConfig->Source)
2244 {
2245 case TIM_BREAKINPUTSOURCE_BKIN:
2246 {
2247 bkin_enable_mask = TIM_AF1_BKINE;
2248 bkin_enable_bitpos = TIM_AF1_BKINE_Pos;
2249 bkin_polarity_mask = TIM_AF1_BKINP;
2250 bkin_polarity_bitpos = TIM_AF1_BKINP_Pos;
2251 break;
2252 }
2253 case TIM_BREAKINPUTSOURCE_COMP1:
2254 {
2255 bkin_enable_mask = TIM_AF1_BKCMP1E;
2256 bkin_enable_bitpos = TIM_AF1_BKCMP1E_Pos;
2257 bkin_polarity_mask = TIM_AF1_BKCMP1P;
2258 bkin_polarity_bitpos = TIM_AF1_BKCMP1P_Pos;
2259 break;
2260 }
2261 case TIM_BREAKINPUTSOURCE_COMP2:
2262 {
2263 bkin_enable_mask = TIM_AF1_BKCMP2E;
2264 bkin_enable_bitpos = TIM_AF1_BKCMP2E_Pos;
2265 bkin_polarity_mask = TIM_AF1_BKCMP2P;
2266 bkin_polarity_bitpos = TIM_AF1_BKCMP2P_Pos;
2267 break;
2268 }
2269
2270 default:
2271 {
2272 bkin_enable_mask = 0U;
2273 bkin_polarity_mask = 0U;
2274 bkin_enable_bitpos = 0U;
2275 bkin_polarity_bitpos = 0U;
2276 break;
2277 }
2278 }
2279
2280 switch (BreakInput)
2281 {
2282 case TIM_BREAKINPUT_BRK:
2283 {
2284 /* Get the TIMx_AF1 register value */
2285 tmporx = htim->Instance->AF1;
2286
2287 /* Enable the break input */
2288 tmporx &= ~bkin_enable_mask;
2289 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2290
2291 /* Set the break input polarity */
2292 tmporx &= ~bkin_polarity_mask;
2293 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2294
2295 /* Set TIMx_AF1 */
2296 htim->Instance->AF1 = tmporx;
2297 break;
2298 }
2299 case TIM_BREAKINPUT_BRK2:
2300 {
2301 /* Get the TIMx_AF2 register value */
2302 tmporx = htim->Instance->AF2;
2303
2304 /* Enable the break input */
2305 tmporx &= ~bkin_enable_mask;
2306 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2307
2308 /* Set the break input polarity */
2309 tmporx &= ~bkin_polarity_mask;
2310 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2311
2312 /* Set TIMx_AF2 */
2313 htim->Instance->AF2 = tmporx;
2314 break;
2315 }
2316 default:
2317 status = HAL_ERROR;
2318 break;
2319 }
2320
2321 __HAL_UNLOCK(htim);
2322
2323 return status;
2324 }
2325
2326 /**
2327 * @brief Configures the TIMx Remapping input capabilities.
2328 * @param htim TIM handle.
2329 * @param Remap specifies the TIM remapping source.
2330 * For TIM1, the parameter can take one of the following values:
2331 * @arg TIM_TIM1_ETR_GPIO TIM1_ETR is not connected to I/O
2332 * @arg TIM_TIM1_ETR_COMP1 TIM1_ETR is connected to COMP1 output
2333 * @arg TIM_TIM1_ETR_COMP2 TIM1_ETR is connected to COMP2 output
2334 * @arg TIM_TIM1_ETR_HSI TIM1_ETR is connected to HSI
2335 * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1_ETR is connected to ADC4 AWD1
2336 * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1_ETR is connected to ADC4 AWD2
2337 * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1_ETR is connected to ADC4 AWD3
2338 *
2339 * For TIM2, the parameter can take one of the following values:
2340 * @arg TIM_TIM2_ETR_GPIO TIM2_ETR is not connected to I/O
2341 * @arg TIM_TIM2_ETR_COMP1 TIM2_ETR is connected to COMP1 output
2342 * @arg TIM_TIM2_ETR_COMP2 TIM2_ETR is connected to COMP2 output
2343 * @arg TIM_TIM2_ETR_HSI TIM2_ETR is connected to HSI
2344 * @arg TIM_TIM2_ETR_TIM3_ETR TIM2_ETR is connected to TIM3 ETR
2345 * @arg TIM_TIM2_ETR_LSE TIM2_ETR is connected to LSE
2346 *
2347 * For TIM3, the parameter can take one of the following values:
2348 * @arg TIM_TIM3_ETR_GPIO TIM3_ETR is not connected to I/O
2349 * @arg TIM_TIM3_ETR_COMP1 TIM3_ETR is connected to COMP1 output
2350 * @arg TIM_TIM3_ETR_COMP2 TIM3_ETR is connected to COMP2 output
2351 * @arg TIM_TIM3_ETR_HSI TIM3_ETR is connected to HSI
2352 * @arg TIM_TIM3_ETR_TIM2_ETR TIM3_ETR is connected to TIM2 ETR
2353 * @arg TIM_TIM3_ETR_ADC4_AWD2 TIM3_ETR is connected to ADC4 AWD2
2354 * @arg TIM_TIM3_ETR_ADC4_AWD3 TIM3_ETR is connected to ADC4 AWD3
2355 *
2356 * @retval HAL status
2357 */
HAL_TIMEx_RemapConfig(TIM_HandleTypeDef * htim,uint32_t Remap)2358 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2359 {
2360 /* Check parameters */
2361 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2362 assert_param(IS_TIM_REMAP(Remap));
2363
2364 __HAL_LOCK(htim);
2365
2366 MODIFY_REG(htim->Instance->AF1, TIM_AF1_ETRSEL_Msk, Remap);
2367
2368 __HAL_UNLOCK(htim);
2369
2370 return HAL_OK;
2371 }
2372
2373 /**
2374 * @brief Select the timer input source
2375 * @param htim TIM handle.
2376 * @param Channel specifies the TIM Channel
2377 * This parameter can be one of the following values:
2378 * @arg TIM_CHANNEL_1: TI1 input channel
2379 * @arg TIM_CHANNEL_2: TI2 input channel
2380 * @arg TIM_CHANNEL_4: TI4 input channel
2381 * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
2382 * For TIM1, the parameter is one of the following values:
2383 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
2384 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
2385 * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output
2386 *
2387 * For TIM2, the parameter is one of the following values:
2388 * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO
2389 * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output
2390 * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP1 output
2391 * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO
2392 * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output
2393 * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP1 output
2394 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
2395 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
2396 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
2397 *
2398 * For TIM3, the parameter is one of the following values:
2399 * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
2400 * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
2401 * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
2402 * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO
2403 * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output
2404 * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP1 output
2405 *
2406 * For TIM16, the parameter can have the following values:
2407 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
2408 * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO
2409 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
2410 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
2411 * @arg TIM_TIM16_TI1_RTC_WKUP: TIM16 TI1 is connected to RTC wakeup interrupt
2412 * @arg TIM_TIM16_TI1_HSE_DIV32: TIM16 TI1 is connected to HSE/32
2413 *
2414 * For TIM17, the parameter can have the following values:
2415 * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
2416 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
2417 * @arg TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to LSI
2418 * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to LSE
2419 * @arg TIM_TIM17_TI1_RTC_WKUP: TIM17 TI1 is connected to RTC wakeup interrupt
2420 * @arg TIM_TIM17_TI1_HSE_DIV32: TIM17 TI1 is connected to HSE/32
2421 * @retval HAL status
2422 */
HAL_TIMEx_TISelection(TIM_HandleTypeDef * htim,uint32_t TISelection,uint32_t Channel)2423 HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
2424 {
2425 HAL_StatusTypeDef status = HAL_OK;
2426
2427 /* Check parameters */
2428 assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
2429 assert_param(IS_TIM_TISEL(TISelection));
2430
2431 __HAL_LOCK(htim);
2432
2433 switch (Channel)
2434 {
2435 case TIM_CHANNEL_1:
2436 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
2437
2438 /* If required, set OR bit to request HSE/32 clock */
2439 if (IS_TIM_HSE32_INSTANCE(htim->Instance))
2440 {
2441 SET_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
2442 }
2443 else
2444 {
2445 CLEAR_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
2446 }
2447 break;
2448 case TIM_CHANNEL_2:
2449 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
2450 break;
2451 case TIM_CHANNEL_4:
2452 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
2453 break;
2454 default:
2455 status = HAL_ERROR;
2456 break;
2457 }
2458
2459 __HAL_UNLOCK(htim);
2460
2461 return status;
2462 }
2463
2464 /**
2465 * @brief Group channel 5 and channel 1, 2 or 3
2466 * @param htim TIM handle.
2467 * @param Channels specifies the reference signal(s) the OC5REF is combined with.
2468 * This parameter can be any combination of the following values:
2469 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2470 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2471 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2472 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2473 * @retval HAL status
2474 */
HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef * htim,uint32_t Channels)2475 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
2476 {
2477 /* Check parameters */
2478 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2479 assert_param(IS_TIM_GROUPCH5(Channels));
2480
2481 /* Process Locked */
2482 __HAL_LOCK(htim);
2483
2484 htim->State = HAL_TIM_STATE_BUSY;
2485
2486 /* Clear GC5Cx bit fields */
2487 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
2488
2489 /* Set GC5Cx bit fields */
2490 htim->Instance->CCR5 |= Channels;
2491
2492 /* Change the htim state */
2493 htim->State = HAL_TIM_STATE_READY;
2494
2495 __HAL_UNLOCK(htim);
2496
2497 return HAL_OK;
2498 }
2499
2500 /**
2501 * @brief Disarm the designated break input (when it operates in bidirectional mode).
2502 * @param htim TIM handle.
2503 * @param BreakInput Break input to disarm
2504 * This parameter can be one of the following values:
2505 * @arg TIM_BREAKINPUT_BRK: Timer break input
2506 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2507 * @note The break input can be disarmed only when it is configured in
2508 * bidirectional mode and when when MOE is reset.
2509 * @note Purpose is to be able to have the input voltage back to high-state,
2510 * whatever the time constant on the output .
2511 * @retval HAL status
2512 */
HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput)2513 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
2514 {
2515 HAL_StatusTypeDef status = HAL_OK;
2516 uint32_t tmpbdtr;
2517
2518 /* Check the parameters */
2519 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2520 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2521
2522 switch (BreakInput)
2523 {
2524 case TIM_BREAKINPUT_BRK:
2525 {
2526 /* Check initial conditions */
2527 tmpbdtr = READ_REG(htim->Instance->BDTR);
2528 if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
2529 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2530 {
2531 /* Break input BRK is disarmed */
2532 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
2533 }
2534 break;
2535 }
2536 case TIM_BREAKINPUT_BRK2:
2537 {
2538 /* Check initial conditions */
2539 tmpbdtr = READ_REG(htim->Instance->BDTR);
2540 if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
2541 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2542 {
2543 /* Break input BRK is disarmed */
2544 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
2545 }
2546 break;
2547 }
2548 default:
2549 status = HAL_ERROR;
2550 break;
2551 }
2552
2553 return status;
2554 }
2555
2556 /**
2557 * @brief Arm the designated break input (when it operates in bidirectional mode).
2558 * @param htim TIM handle.
2559 * @param BreakInput Break input to arm
2560 * This parameter can be one of the following values:
2561 * @arg TIM_BREAKINPUT_BRK: Timer break input
2562 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2563 * @note Arming is possible at anytime, even if fault is present.
2564 * @note Break input is automatically armed as soon as MOE bit is set.
2565 * @retval HAL status
2566 */
HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef * htim,uint32_t BreakInput)2567 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
2568 {
2569 HAL_StatusTypeDef status = HAL_OK;
2570 uint32_t tickstart;
2571
2572 /* Check the parameters */
2573 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2574 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2575
2576 switch (BreakInput)
2577 {
2578 case TIM_BREAKINPUT_BRK:
2579 {
2580 /* Check initial conditions */
2581 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
2582 {
2583 /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2584 /* Init tickstart for timeout management */
2585 tickstart = HAL_GetTick();
2586 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2587 {
2588 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2589 {
2590 /* New check to avoid false timeout detection in case of preemption */
2591 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2592 {
2593 return HAL_TIMEOUT;
2594 }
2595 }
2596 }
2597 }
2598 break;
2599 }
2600
2601 case TIM_BREAKINPUT_BRK2:
2602 {
2603 /* Check initial conditions */
2604 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
2605 {
2606 /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2607 /* Init tickstart for timeout management */
2608 tickstart = HAL_GetTick();
2609 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2610 {
2611 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2612 {
2613 /* New check to avoid false timeout detection in case of preemption */
2614 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2615 {
2616 return HAL_TIMEOUT;
2617 }
2618 }
2619 }
2620 }
2621 break;
2622 }
2623 default:
2624 status = HAL_ERROR;
2625 break;
2626 }
2627
2628 return status;
2629 }
2630
2631 /**
2632 * @brief Enable dithering
2633 * @param htim TIM handle
2634 * @note Main usage is PWM mode
2635 * @note This function must be called when timer is stopped or disabled (CEN =0)
2636 * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
2637 * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
2638 * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
2639 * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
2640 * - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers
2641 * (corresponds to 4094 for the integer part and 15 for the dithered part).
2642 * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER()
2643 * can be used to calculate period (ARR) and delay (CCRx) value.
2644 * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2645 * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2646 * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
2647 * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
2648 * @retval HAL status
2649 */
HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef * htim)2650 HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim)
2651 {
2652 /* Check the parameters */
2653 assert_param(IS_TIM_INSTANCE(htim->Instance));
2654
2655 SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
2656 return HAL_OK;
2657 }
2658
2659 /**
2660 * @brief Disable dithering
2661 * @param htim TIM handle
2662 * @note This function must be called when timer is stopped or disabled (CEN =0)
2663 * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
2664 * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
2665 * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
2666 * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
2667 * - ARR and CCRx values are limited to 0xFFEF in dithering mode
2668 * (corresponds to 4094 for the integer part and 15 for the dithered part).
2669 * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2670 * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
2671 * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
2672 * @retval HAL status
2673 */
HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef * htim)2674 HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim)
2675 {
2676 /* Check the parameters */
2677 assert_param(IS_TIM_INSTANCE(htim->Instance));
2678
2679 CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
2680 return HAL_OK;
2681 }
2682
2683 /**
2684 * @brief Initializes the pulse on compare pulse width and pulse prescaler
2685 * @param htim TIM Output Compare handle
2686 * @param PulseWidthPrescaler Pulse width prescaler
2687 * This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7
2688 * @param PulseWidth Pulse width
2689 * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
2690 * @retval HAL status
2691 */
HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef * htim,uint32_t PulseWidthPrescaler,uint32_t PulseWidth)2692 HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim,
2693 uint32_t PulseWidthPrescaler,
2694 uint32_t PulseWidth)
2695 {
2696 uint32_t tmpecr;
2697
2698 /* Check the parameters */
2699 assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
2700 assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
2701 assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
2702
2703 /* Process Locked */
2704 __HAL_LOCK(htim);
2705
2706 /* Set the TIM state */
2707 htim->State = HAL_TIM_STATE_BUSY;
2708
2709 /* Get the TIMx ECR register value */
2710 tmpecr = htim->Instance->ECR;
2711 /* Reset the Pulse width prescaler and the Pulse width */
2712 tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
2713 /* Set the Pulse width prescaler and Pulse width*/
2714 tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
2715 tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
2716 /* Write to TIMx ECR */
2717 htim->Instance->ECR = tmpecr;
2718
2719 /* Change the TIM state */
2720 htim->State = HAL_TIM_STATE_READY;
2721
2722 /* Release Lock */
2723 __HAL_UNLOCK(htim);
2724
2725 return HAL_OK;
2726 }
2727
2728 /**
2729 * @brief Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
2730 * @param htim TIM handle
2731 * @param Source Source of slave mode selection preload
2732 * This parameter can be one of the following values:
2733 * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload
2734 * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload
2735 * @retval HAL status
2736 */
HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef * htim,uint32_t Source)2737 HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source)
2738 {
2739 /* Check the parameters */
2740 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
2741 assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
2742
2743 MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
2744 return HAL_OK;
2745 }
2746
2747 /**
2748 * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
2749 * @param htim TIM handle
2750 * @retval HAL status
2751 */
HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef * htim)2752 HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim)
2753 {
2754 /* Check the parameters */
2755 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
2756
2757 SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
2758 return HAL_OK;
2759 }
2760
2761 /**
2762 * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
2763 * @param htim TIM handle
2764 * @retval HAL status
2765 */
HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef * htim)2766 HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim)
2767 {
2768 /* Check the parameters */
2769 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
2770
2771 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
2772 return HAL_OK;
2773 }
2774
2775 /**
2776 * @brief Enable deadtime preload
2777 * @param htim TIM handle
2778 * @retval HAL status
2779 */
HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef * htim)2780 HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim)
2781 {
2782 /* Check the parameters */
2783 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2784
2785 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
2786 return HAL_OK;
2787 }
2788
2789 /**
2790 * @brief Disable deadtime preload
2791 * @param htim TIM handle
2792 * @retval HAL status
2793 */
HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef * htim)2794 HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim)
2795 {
2796 /* Check the parameters */
2797 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2798
2799 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
2800 return HAL_OK;
2801 }
2802
2803 /**
2804 * @brief Configure deadtime
2805 * @param htim TIM handle
2806 * @param Deadtime Deadtime value
2807 * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
2808 * @retval HAL status
2809 */
HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef * htim,uint32_t Deadtime)2810 HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime)
2811 {
2812 /* Check the parameters */
2813 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2814 assert_param(IS_TIM_DEADTIME(Deadtime));
2815
2816 MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
2817 return HAL_OK;
2818 }
2819
2820 /**
2821 * @brief Configure asymmetrical deadtime
2822 * @param htim TIM handle
2823 * @param FallingDeadtime Falling edge deadtime value
2824 * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
2825 * @retval HAL status
2826 */
HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef * htim,uint32_t FallingDeadtime)2827 HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
2828 {
2829 /* Check the parameters */
2830 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2831 assert_param(IS_TIM_DEADTIME(FallingDeadtime));
2832
2833 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
2834 return HAL_OK;
2835 }
2836
2837 /**
2838 * @brief Enable asymmetrical deadtime
2839 * @param htim TIM handle
2840 * @retval HAL status
2841 */
HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef * htim)2842 HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
2843 {
2844 /* Check the parameters */
2845 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2846
2847 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
2848 return HAL_OK;
2849 }
2850
2851 /**
2852 * @brief Disable asymmetrical deadtime
2853 * @param htim TIM handle
2854 * @retval HAL status
2855 */
HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef * htim)2856 HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
2857 {
2858 /* Check the parameters */
2859 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2860
2861 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
2862 return HAL_OK;
2863 }
2864
2865 /**
2866 * @brief Configures the encoder index.
2867 * @note warning in case of encoder mode clock plus direction
2868 * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
2869 * Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN
2870 * @param htim TIM handle.
2871 * @param sEncoderIndexConfig Encoder index configuration
2872 * @retval HAL status
2873 */
HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef * htim,TIMEx_EncoderIndexConfigTypeDef * sEncoderIndexConfig)2874 HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
2875 TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
2876 {
2877 /* Check the parameters */
2878 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2879 assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
2880 assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
2881 assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
2882 assert_param(IS_TIM_ENCODERINDEX_BLANKING(sEncoderIndexConfig->Blanking));
2883 assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
2884 assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
2885 assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
2886
2887 /* Process Locked */
2888 __HAL_LOCK(htim);
2889
2890 /* Configures the TIMx External Trigger (ETR) which is used as Index input */
2891 TIM_ETR_SetConfig(htim->Instance,
2892 sEncoderIndexConfig->Prescaler,
2893 sEncoderIndexConfig->Polarity,
2894 sEncoderIndexConfig->Filter);
2895
2896 /* Configures the encoder index */
2897 MODIFY_REG(htim->Instance->ECR,
2898 TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
2899 (sEncoderIndexConfig->Direction |
2900 (sEncoderIndexConfig->Blanking) |
2901 ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
2902 sEncoderIndexConfig->Position |
2903 TIM_ECR_IE));
2904
2905 __HAL_UNLOCK(htim);
2906
2907 return HAL_OK;
2908 }
2909
2910 /**
2911 * @brief Enable encoder index
2912 * @param htim TIM handle
2913 * @retval HAL status
2914 */
HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef * htim)2915 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim)
2916 {
2917 /* Check the parameters */
2918 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2919
2920 SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
2921 return HAL_OK;
2922 }
2923
2924 /**
2925 * @brief Disable encoder index
2926 * @param htim TIM handle
2927 * @retval HAL status
2928 */
HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef * htim)2929 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim)
2930 {
2931 /* Check the parameters */
2932 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2933
2934 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
2935 return HAL_OK;
2936 }
2937
2938 /**
2939 * @brief Enable encoder first index
2940 * @param htim TIM handle
2941 * @retval HAL status
2942 */
HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef * htim)2943 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim)
2944 {
2945 /* Check the parameters */
2946 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2947
2948 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
2949 return HAL_OK;
2950 }
2951
2952 /**
2953 * @brief Disable encoder first index
2954 * @param htim TIM handle
2955 * @retval HAL status
2956 */
HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef * htim)2957 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim)
2958 {
2959 /* Check the parameters */
2960 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2961
2962 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
2963 return HAL_OK;
2964 }
2965
2966 /**
2967 * @}
2968 */
2969
2970 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
2971 * @brief Extended Callbacks functions
2972 *
2973 @verbatim
2974 ==============================================================================
2975 ##### Extended Callbacks functions #####
2976 ==============================================================================
2977 [..]
2978 This section provides Extended TIM callback functions:
2979 (+) Timer Commutation callback
2980 (+) Timer Break callback
2981
2982 @endverbatim
2983 * @{
2984 */
2985
2986 /**
2987 * @brief Commutation callback in non-blocking mode
2988 * @param htim TIM handle
2989 * @retval None
2990 */
HAL_TIMEx_CommutCallback(TIM_HandleTypeDef * htim)2991 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
2992 {
2993 /* Prevent unused argument(s) compilation warning */
2994 UNUSED(htim);
2995
2996 /* NOTE : This function should not be modified, when the callback is needed,
2997 the HAL_TIMEx_CommutCallback could be implemented in the user file
2998 */
2999 }
3000 /**
3001 * @brief Commutation half complete callback in non-blocking mode
3002 * @param htim TIM handle
3003 * @retval None
3004 */
HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef * htim)3005 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
3006 {
3007 /* Prevent unused argument(s) compilation warning */
3008 UNUSED(htim);
3009
3010 /* NOTE : This function should not be modified, when the callback is needed,
3011 the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
3012 */
3013 }
3014
3015 /**
3016 * @brief Break detection callback in non-blocking mode
3017 * @param htim TIM handle
3018 * @retval None
3019 */
HAL_TIMEx_BreakCallback(TIM_HandleTypeDef * htim)3020 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
3021 {
3022 /* Prevent unused argument(s) compilation warning */
3023 UNUSED(htim);
3024
3025 /* NOTE : This function should not be modified, when the callback is needed,
3026 the HAL_TIMEx_BreakCallback could be implemented in the user file
3027 */
3028 }
3029
3030 /**
3031 * @brief Break2 detection callback in non blocking mode
3032 * @param htim: TIM handle
3033 * @retval None
3034 */
HAL_TIMEx_Break2Callback(TIM_HandleTypeDef * htim)3035 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
3036 {
3037 /* Prevent unused argument(s) compilation warning */
3038 UNUSED(htim);
3039
3040 /* NOTE : This function Should not be modified, when the callback is needed,
3041 the HAL_TIMEx_Break2Callback could be implemented in the user file
3042 */
3043 }
3044
3045 /**
3046 * @brief Encoder index callback in non-blocking mode
3047 * @param htim TIM handle
3048 * @retval None
3049 */
HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef * htim)3050 __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
3051 {
3052 /* Prevent unused argument(s) compilation warning */
3053 UNUSED(htim);
3054
3055 /* NOTE : This function should not be modified, when the callback is needed,
3056 the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
3057 */
3058 }
3059
3060 /**
3061 * @brief Direction change callback in non-blocking mode
3062 * @param htim TIM handle
3063 * @retval None
3064 */
HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef * htim)3065 __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
3066 {
3067 /* Prevent unused argument(s) compilation warning */
3068 UNUSED(htim);
3069
3070 /* NOTE : This function should not be modified, when the callback is needed,
3071 the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
3072 */
3073 }
3074
3075 /**
3076 * @brief Index error callback in non-blocking mode
3077 * @param htim TIM handle
3078 * @retval None
3079 */
HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef * htim)3080 __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
3081 {
3082 /* Prevent unused argument(s) compilation warning */
3083 UNUSED(htim);
3084
3085 /* NOTE : This function should not be modified, when the callback is needed,
3086 the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
3087 */
3088 }
3089
3090 /**
3091 * @brief Transition error callback in non-blocking mode
3092 * @param htim TIM handle
3093 * @retval None
3094 */
HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef * htim)3095 __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
3096 {
3097 /* Prevent unused argument(s) compilation warning */
3098 UNUSED(htim);
3099
3100 /* NOTE : This function should not be modified, when the callback is needed,
3101 the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
3102 */
3103 }
3104
3105 /**
3106 * @}
3107 */
3108
3109 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
3110 * @brief Extended Peripheral State functions
3111 *
3112 @verbatim
3113 ==============================================================================
3114 ##### Extended Peripheral State functions #####
3115 ==============================================================================
3116 [..]
3117 This subsection permits to get in run-time the status of the peripheral
3118 and the data flow.
3119
3120 @endverbatim
3121 * @{
3122 */
3123
3124 /**
3125 * @brief Return the TIM Hall Sensor interface handle state.
3126 * @param htim TIM Hall Sensor handle
3127 * @retval HAL state
3128 */
HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef * htim)3129 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
3130 {
3131 return htim->State;
3132 }
3133
3134 /**
3135 * @brief Return actual state of the TIM complementary channel.
3136 * @param htim TIM handle
3137 * @param ChannelN TIM Complementary channel
3138 * This parameter can be one of the following values:
3139 * @arg TIM_CHANNEL_1: TIM Channel 1
3140 * @arg TIM_CHANNEL_2: TIM Channel 2
3141 * @arg TIM_CHANNEL_3: TIM Channel 3
3142 * @arg TIM_CHANNEL_4: TIM Channel 4
3143 * @retval TIM Complementary channel state
3144 */
HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef * htim,uint32_t ChannelN)3145 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN)
3146 {
3147 HAL_TIM_ChannelStateTypeDef channel_state;
3148
3149 /* Check the parameters */
3150 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
3151
3152 channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
3153
3154 return channel_state;
3155 }
3156 /**
3157 * @}
3158 */
3159
3160 /**
3161 * @}
3162 */
3163
3164 /* Private functions ---------------------------------------------------------*/
3165 /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
3166 * @{
3167 */
3168
3169 /**
3170 * @brief TIM DMA Commutation callback.
3171 * @param hdma pointer to DMA handle.
3172 * @retval None
3173 */
TIMEx_DMACommutationCplt(DMA_HandleTypeDef * hdma)3174 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
3175 {
3176 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3177
3178 /* Change the htim state */
3179 htim->State = HAL_TIM_STATE_READY;
3180
3181 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3182 htim->CommutationCallback(htim);
3183 #else
3184 HAL_TIMEx_CommutCallback(htim);
3185 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3186 }
3187
3188 /**
3189 * @brief TIM DMA Commutation half complete callback.
3190 * @param hdma pointer to DMA handle.
3191 * @retval None
3192 */
TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef * hdma)3193 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
3194 {
3195 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3196
3197 /* Change the htim state */
3198 htim->State = HAL_TIM_STATE_READY;
3199
3200 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3201 htim->CommutationHalfCpltCallback(htim);
3202 #else
3203 HAL_TIMEx_CommutHalfCpltCallback(htim);
3204 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3205 }
3206
3207
3208 /**
3209 * @brief TIM DMA Delay Pulse complete callback (complementary channel).
3210 * @param hdma pointer to DMA handle.
3211 * @retval None
3212 */
TIM_DMADelayPulseNCplt(DMA_HandleTypeDef * hdma)3213 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
3214 {
3215 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3216
3217 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
3218 {
3219 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3220 }
3221 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
3222 {
3223 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3224 }
3225 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
3226 {
3227 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3228 }
3229 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
3230 {
3231 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3232 }
3233 else
3234 {
3235 /* nothing to do */
3236 }
3237
3238 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3239 htim->PWM_PulseFinishedCallback(htim);
3240 #else
3241 HAL_TIM_PWM_PulseFinishedCallback(htim);
3242 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3243
3244 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3245 }
3246
3247 /**
3248 * @brief TIM DMA error callback (complementary channel)
3249 * @param hdma pointer to DMA handle.
3250 * @retval None
3251 */
TIM_DMAErrorCCxN(DMA_HandleTypeDef * hdma)3252 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
3253 {
3254 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3255
3256 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
3257 {
3258 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3259 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3260 }
3261 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
3262 {
3263 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3264 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3265 }
3266 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
3267 {
3268 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3269 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
3270 }
3271 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
3272 {
3273 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3274 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
3275 }
3276 else
3277 {
3278 /* nothing to do */
3279 }
3280
3281 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3282 htim->ErrorCallback(htim);
3283 #else
3284 HAL_TIM_ErrorCallback(htim);
3285 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3286
3287 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3288 }
3289
3290 /**
3291 * @brief Enables or disables the TIM Capture Compare Channel xN.
3292 * @param TIMx to select the TIM peripheral
3293 * @param Channel specifies the TIM Channel
3294 * This parameter can be one of the following values:
3295 * @arg TIM_CHANNEL_1: TIM Channel 1
3296 * @arg TIM_CHANNEL_2: TIM Channel 2
3297 * @arg TIM_CHANNEL_3: TIM Channel 3
3298 * @arg TIM_CHANNEL_4: TIM Channel 4
3299 * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
3300 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
3301 * @retval None
3302 */
TIM_CCxNChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelNState)3303 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
3304 {
3305 uint32_t tmp;
3306
3307 tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
3308
3309 /* Reset the CCxNE Bit */
3310 TIMx->CCER &= ~tmp;
3311
3312 /* Set or reset the CCxNE Bit */
3313 TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
3314 }
3315 /**
3316 * @}
3317 */
3318
3319 #endif /* HAL_TIM_MODULE_ENABLED */
3320 /**
3321 * @}
3322 */
3323
3324 /**
3325 * @}
3326 */
3327
