1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extended peripheral:
8 * + Extended Peripheral Control functions
9 * + Extended Clock management functions
10 * + Extended Clock Recovery System Control functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2022 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32wbaxx_hal.h"
27
28 /** @addtogroup STM32WBAxx_HAL_Driver
29 * @{
30 */
31
32 /** @defgroup RCCEx RCCEx
33 * @brief RCC Extended HAL module driver
34 * @{
35 */
36
37 #ifdef HAL_RCC_MODULE_ENABLED
38
39 /* Private typedef -----------------------------------------------------------*/
40 /* Private defines -----------------------------------------------------------*/
41 /* Private macros ------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private function prototypes -----------------------------------------------*/
44 /* Exported functions --------------------------------------------------------*/
45
46 /** @addtogroup RCCEx_Exported_Functions
47 * @{
48 */
49
50 /** @addtogroup RCCEx_Exported_Functions_Group1
51 * @brief Extended Peripheral Control functions
52 *
53 @verbatim
54 ===============================================================================
55 ##### Extended Peripheral Control functions #####
56 ===============================================================================
57 [..]
58 This subsection provides a set of functions allowing to control the RCC Clocks
59 frequencies.
60 [..]
61 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
62 select the RTC clock source; in this case the Backup domain will be reset in
63 order to modify the RTC Clock source, as consequence RTC registers (including
64 the backup registers) are set to their reset values.
65
66 @endverbatim
67 * @{
68 */
69
70 /**
71 * @brief Initialize the RCC extended peripherals clocks according to the specified
72 * parameters in the RCC_PeriphCLKInitTypeDef.
73 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
74 * contains a field PeriphClockSelection which can be a combination of the following values:
75 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
76 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (*)
77 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock (*)
78 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (*)
79 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock (*)
80 * @arg @ref RCC_PERIPHCLK_SYSTICK SYSTICK peripheral clock
81 * @arg @ref RCC_PERIPHCLK_TIMIC TIMIC peripheral clock
82 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*)
83 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
84 * @arg @ref RCC_PERIPHCLK_AUDIOSYNC AUDIOSYNC peripheral clock (*)
85 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
86 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
87 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
88 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
89 * @arg @ref RCC_PERIPHCLK_ADC ADC4 peripheral clock
90 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
91 * @arg @ref RCC_PERIPHCLK_RADIOST RADIO sleep timer clock (**)
92 * @note (*) Peripherals are not available on all devices
93 * @note (**) This requires the Backup domain access to be enabled
94 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
95 * the RTC clock source: in this case the access to Backup domain is enabled.
96 * @retval HAL status
97 */
HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef * PeriphClkInit)98 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit)
99 {
100 uint32_t tmpreg1;
101 uint32_t tmpreg2;
102 uint32_t tickstart;
103
104 /* Check the parameters */
105 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
106
107 /*-------------------------- USART1 clock source configuration -------------------*/
108 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
109 {
110 /* Check the parameters */
111 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
112
113 /* Configure the USART1 clock source */
114 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
115 }
116
117 #if defined (USART2)
118 /*-------------------------- USART2 clock source configuration -------------------*/
119 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
120 {
121 /* Check the parameters */
122 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
123
124 /* Configure the USART2 clock source */
125 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
126 }
127 #endif
128
129
130 #if defined (I2C1)
131 /*-------------------------- I2C1 clock source configuration ---------------------*/
132 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
133 {
134 /* Check the parameters */
135 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
136
137 /* Configure the I2C1 clock source */
138 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
139 }
140 #endif
141
142
143
144
145 #if defined (LPTIM2)
146 /*-------------------------- LPTIM2 clock source configuration -------------------*/
147 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
148 {
149 /* Check the parameters */
150 assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection));
151
152 /* Configure the LPTIM2 clock source */
153 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
154 }
155 #endif
156
157 #if defined (SPI1)
158 /*-------------------------- SPI1 clock source configuration ----------------*/
159 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
160 {
161 /* Check the parameters */
162 assert_param(IS_RCC_SPI1CLKSOURCE(PeriphClkInit->Spi1ClockSelection));
163
164 /* Configure the SPI1 clock source */
165 __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection);
166 }
167 #endif
168
169 /*-------------------------- SYSTICK clock source configuration ----------------*/
170 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SYSTICK) == RCC_PERIPHCLK_SYSTICK)
171 {
172 /* Check the parameters */
173 assert_param(IS_RCC_SYSTICKCLKSOURCE(PeriphClkInit->SystickClockSelection));
174
175 /* Configure the SYSTICK clock source */
176 __HAL_RCC_SYSTICK_CONFIG(PeriphClkInit->SystickClockSelection);
177 }
178
179 /*-------------------------- TIMIC clock source configuration ----------------*/
180 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIMIC) == RCC_PERIPHCLK_TIMIC)
181 {
182 /* Check the parameters */
183 assert_param(IS_RCC_TIMICCLKSOURCE(PeriphClkInit->TimIcClockSelection));
184
185 /* Configure the TIMIC clock source */
186 __HAL_RCC_TIMIC_CONFIG(PeriphClkInit->TimIcClockSelection);
187 }
188
189 #if defined (SAI1)
190 /*-------------------------- SAI1 clock source configuration ---------------------*/
191 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
192 {
193 /* Check the parameters */
194 assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
195
196 /* Set the source of SAI1 clock*/
197 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
198
199 if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL1P)
200 {
201 /* Enable PLL1 PCLK output */
202 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_PCLK);
203 }
204 else if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL1Q)
205 {
206 /* Enable PLL1 QCLK output */
207 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_QCLK);
208 }
209 else
210 {
211 /* Do nothing ; for misra 15.7 error only */
212 }
213 }
214 #endif
215
216 /*------------------------------ RNG Configuration -------------------------*/
217 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
218 {
219 /* Check the parameters */
220 assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
221
222 /* Set the source of RNG clock*/
223 __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
224
225 if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL1Q)
226 {
227 /* Enable PLL1 QCLK output */
228 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_QCLK);
229 }
230 }
231
232
233 #if defined (RCC_CCIPR2_ASSEL)
234 /*-------------------------- AS clock source configuration -------------------*/
235 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_AUDIOSYNC) == RCC_PERIPHCLK_AUDIOSYNC)
236 {
237 /* Check the parameters */
238 assert_param(IS_RCC_ASCLKSOURCE(PeriphClkInit->AudioSyncClockSelection));
239
240 /* Configure the AS clock source */
241 __HAL_RCC_AUDIOSYNC_CONFIG(PeriphClkInit->AudioSyncClockSelection);
242
243 if (PeriphClkInit->AudioSyncClockSelection == RCC_ASCLKSOURCE_PLL1P)
244 {
245 /* Enable PLL1 PCLK output */
246 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_PCLK);
247 }
248 else if (PeriphClkInit->AudioSyncClockSelection == RCC_ASCLKSOURCE_PLL1Q)
249 {
250 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_QCLK);
251 }
252 else
253 {
254 /* Do nothing ; for misra 15.7 error only */
255 }
256 }
257 #endif
258
259 /*-------------------------- LPUART1 clock source configuration ------------------*/
260 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
261 {
262 /* Check the parameters */
263 assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
264
265 /* Configure the LPUART1 clock source */
266 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
267 }
268
269 /*-------------------------- SPI3 clock source configuration ----------------*/
270 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3)
271 {
272 /* Check the parameters */
273 assert_param(IS_RCC_SPI3CLKSOURCE(PeriphClkInit->Spi3ClockSelection));
274
275 /* Configure the SPI3 clock source */
276 __HAL_RCC_SPI3_CONFIG(PeriphClkInit->Spi3ClockSelection);
277 }
278
279
280 /*-------------------------- I2C3 clock source configuration ---------------------*/
281 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
282 {
283 /* Check the parameters */
284 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
285
286 /* Configure the I2C3 clock source */
287 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
288 }
289
290 /*-------------------------- LPTIM1 clock source configuration -------------------*/
291 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
292 {
293 /* Check the parameters */
294 assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
295
296 /* Configure the I2C3 clock source */
297 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
298 }
299
300 /*-------------------------- ADC clock source configuration ----------------------*/
301 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
302 {
303 /* Check the parameters */
304 assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
305
306 /* Configure the ADC4 interface clock source */
307 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
308
309 if (PeriphClkInit->AdcClockSelection == RCC_PERIPHCLK_ADC)
310 {
311 /* Enable PLL1 PCLK output */
312 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_PCLK);
313 }
314 }
315
316 /*-------------------------- RTC clock source configuration ----------------------*/
317 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
318 {
319 FlagStatus pwrclkchanged = RESET;
320
321 /* Check for RTC Parameters used to output RTCCLK */
322 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
323
324 /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
325 tmpreg2 = __HAL_RCC_GET_RTC_SOURCE();
326
327 /* Check if RTC clock source needs to be changed */
328 if (tmpreg2 != PeriphClkInit->RTCClockSelection)
329 {
330 /* Enable Power Clock */
331 if (__HAL_RCC_PWR_IS_CLK_ENABLED() != 0x01u)
332 {
333 __HAL_RCC_PWR_CLK_ENABLE();
334 pwrclkchanged = SET;
335 }
336
337 /* Enable write access to Backup domain */
338 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
339
340 /* Wait for Backup domain Write protection disable */
341 tickstart = HAL_GetTick();
342
343 while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
344 {
345 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
346 {
347 return HAL_TIMEOUT;
348 }
349 }
350
351 /* Save BDCR1 content */
352 tmpreg1 = (RCC->BDCR1 & ~RCC_BDCR1_RTCSEL);
353
354 /* Check if a backup domain reset is required */
355 if (tmpreg2 != RCC_RTCCLKSOURCE_DISABLE)
356 {
357 #if defined(RCC_LSI2_SUPPORT)
358 /* Save BDCR2 content */
359 tmpreg2 = RCC->BDCR2;
360 #endif /* RCC_LSI2_SUPPORT */
361 /* RTC Clock selection can be changed only if the Backup Domain is reset */
362 __HAL_RCC_BACKUPRESET_FORCE();
363 __HAL_RCC_BACKUPRESET_RELEASE();
364 #if defined(RCC_LSI2_SUPPORT)
365 /* Restore previously saved BDCR2 */
366 RCC->BDCR2 = tmpreg2;
367 #endif /* RCC_LSI2_SUPPORT */
368 }
369
370 /* Apply new RTC clock source selection */
371 RCC->BDCR1 = (tmpreg1 | PeriphClkInit->RTCClockSelection);
372
373 /* mask all ON bits */
374 tmpreg2 = (RCC_BDCR1_LSEON | RCC_BDCR1_LSI1ON);
375 #if defined(RCC_LSI2_SUPPORT)
376 tmpreg2 |= RCC_BDCR1_LSI2ON;
377 #endif
378
379 /* Check which oscillators were enable */
380 tmpreg2 &= tmpreg1;
381
382 if (tmpreg2 != 0x00u)
383 {
384 /* Get Start Tick*/
385 tickstart = HAL_GetTick();
386
387 /* Wait till all oscillators are enabled : RDY bit position is ON shifted by 1 */
388 while (READ_BIT(RCC->BDCR1, (tmpreg2 << 1)) == 0x00u)
389 {
390 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
391 {
392 return HAL_TIMEOUT;
393 }
394 }
395 }
396 /* Restore clock configuration if changed */
397 if (pwrclkchanged == SET)
398 {
399 __HAL_RCC_PWR_CLK_DISABLE();
400 }
401 }
402 }
403
404 /*-------------------------- RADIO Sleep Timer clock source configuration --*/
405 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RADIOST) == RCC_PERIPHCLK_RADIOST)
406 {
407 /* Check the parameters */
408 assert_param(IS_RCC_RADIOSLEEPTIMERSOURCE(PeriphClkInit->RadioSlpTimClockSelection));
409
410 /* Configure the RADIO Sleep Timer clock source */
411 __HAL_RCC_RADIOSLPTIM_CONFIG(PeriphClkInit->RadioSlpTimClockSelection);
412
413 /* Check configuration validity as under Backup domain access control */
414 if (__HAL_RCC_GET_RADIOSLPTIM_SOURCE() != PeriphClkInit->RadioSlpTimClockSelection)
415 {
416 return HAL_ERROR;
417 }
418 }
419
420 return HAL_OK;
421 }
422
423
424 /**
425 * @brief Get the peripheral kernel clock configuration.
426 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
427 * returns the configuration information for all existing peripheral kernel clocks. (*)
428 * @note (*) Peripherals are not available on all devices
429 * @retval None
430 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * PeriphClkInit)431 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
432 {
433 uint32_t tmpreg;
434
435 /* Check the parameters */
436 assert_param(PeriphClkInit != NULL);
437
438 /* Set all possible values for the extended clock type parameter------------*/
439 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLOCK_ALL;
440
441 /* Get CCIPR1 register value */
442 tmpreg = RCC->CCIPR1;
443
444 /* Get the USART1 clock source ---------------------------------------------*/
445 PeriphClkInit->Usart1ClockSelection = (tmpreg & RCC_CCIPR1_USART1SEL);
446
447 #if defined (USART2)
448 /* Get the USART2 clock source ---------------------------------------------*/
449 PeriphClkInit->Usart2ClockSelection = (tmpreg & RCC_CCIPR1_USART2SEL);
450 #endif
451
452
453
454
455
456 #if defined (I2C1)
457 /* Get the I2C1 clock source -----------------------------------------------*/
458 PeriphClkInit->I2c1ClockSelection = (tmpreg & RCC_CCIPR1_I2C1SEL);
459 #endif
460
461 #if defined (LPTIM2)
462 /* Get the LPTIM2 clock source ---------------------------------------------*/
463 PeriphClkInit->Lptim2ClockSelection = (tmpreg & RCC_CCIPR1_LPTIM2SEL);
464 #endif
465
466 #if defined (SPI1)
467 /* Get the SPI1 clock source -----------------------------------------------*/
468 PeriphClkInit->Spi1ClockSelection = (tmpreg & RCC_CCIPR1_SPI1SEL);
469 #endif
470
471 /* Get the SYSTICK clock source --------------------------------------------*/
472 PeriphClkInit->SystickClockSelection = (tmpreg & RCC_CCIPR1_SYSTICKSEL);
473
474 /* Get the TIMIC clock source ----------------------------------------------*/
475 PeriphClkInit->TimIcClockSelection = (tmpreg & RCC_CCIPR1_TIMICSEL);
476
477 /* Get CCIPR2 register value */
478 tmpreg = RCC->CCIPR2;
479
480 #if defined (SAI1)
481 /* Get the SAI1 clock source -----------------------------------------------*/
482 PeriphClkInit->Sai1ClockSelection = (tmpreg & RCC_CCIPR2_SAI1SEL);
483 #endif
484
485 /* Get the RNG clock source ------------------------------------------------*/
486 PeriphClkInit->RngClockSelection = (tmpreg & RCC_CCIPR2_RNGSEL);
487
488
489 #if defined (RCC_CCIPR2_ASSEL)
490 /* Get the Audio sync clock source -----------------------------------------*/
491 PeriphClkInit->AudioSyncClockSelection = (tmpreg & RCC_CCIPR2_ASSEL);
492 #endif
493
494 /* Get CCIPR3 register value */
495 tmpreg = RCC->CCIPR3;
496
497 /* Get the LPUART1 clock source --------------------------------------------*/
498 PeriphClkInit->Lpuart1ClockSelection = (tmpreg & RCC_CCIPR3_LPUART1SEL);
499
500 /* Get the SPI3 clock source -----------------------------------------------*/
501 PeriphClkInit->Spi3ClockSelection = (tmpreg & RCC_CCIPR3_SPI3SEL);
502
503 /* Get the I2C3 clock source -----------------------------------------------*/
504 PeriphClkInit->I2c3ClockSelection = (tmpreg & RCC_CCIPR3_I2C3SEL);
505
506 /* Get the LPTIM1 clock source ---------------------------------------------*/
507 PeriphClkInit->Lptim1ClockSelection = (tmpreg & RCC_CCIPR3_LPTIM1SEL);
508
509 /* Get the ADC clock source ------------------------------------------------*/
510 PeriphClkInit->AdcClockSelection = (tmpreg & RCC_CCIPR3_ADCSEL);
511
512 /* Get BDCR1 register value */
513 tmpreg = RCC->BDCR1;
514
515 /* Get the RTC clock source ------------------------------------------------*/
516 PeriphClkInit->RTCClockSelection = (tmpreg & RCC_BDCR1_RTCSEL);
517
518 /* Get the Radio Sleep Timer clock source ----------------------------------*/
519 PeriphClkInit->RadioSlpTimClockSelection = (tmpreg & RCC_BDCR1_RADIOSTSEL);
520 }
521
522
523 /**
524 * @brief Return the peripheral clock frequency for peripherals
525 * @note Return 0 if peripheral clock identifier not managed by this API
526 * @param PeriphClk Peripheral clock identifier
527 * This parameter can be one of the following values:
528 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
529 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (*)
530 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock (*)
531 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (*)
532 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock (*)
533 * @arg @ref RCC_PERIPHCLK_SYSTICK SYSTICK peripheral clock
534 * @arg @ref RCC_PERIPHCLK_TIMIC TIMIC peripheral clock
535 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*)
536 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
537 * @arg @ref RCC_PERIPHCLK_AUDIOSYNC AUDIOSYNC peripheral clock (*)
538 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
539 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
540 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
541 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
542 * @arg @ref RCC_PERIPHCLK_ADC ADC4 peripheral clock
543 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
544 * @arg @ref RCC_PERIPHCLK_RADIOST RADIO sleep timer clock
545 * @note (*) Peripherals are not available on all devices
546 * @retval Frequency in Hz
547 */
HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)548 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
549 {
550 uint32_t frequency = 0;
551 uint32_t srcclk;
552
553 /* Check the parameters */
554 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
555
556 switch (PeriphClk)
557 {
558 case RCC_PERIPHCLK_USART1:
559 /* Get the current USART1 source */
560 srcclk = __HAL_RCC_GET_USART1_SOURCE();
561
562 if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
563 {
564 frequency = HAL_RCC_GetPCLK2Freq();
565 }
566 else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
567 {
568 frequency = HAL_RCC_GetSysClockFreq();
569 }
570 else if (srcclk == RCC_USART1CLKSOURCE_HSI)
571 {
572 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
573 {
574 frequency = HSI_VALUE;
575 }
576 }
577 else
578 {
579 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
580 {
581 frequency = LSE_VALUE;
582 }
583 }
584 break;
585
586 #if defined (USART2)
587 case RCC_PERIPHCLK_USART2:
588 /* Get the current USART2 source */
589 srcclk = __HAL_RCC_GET_USART2_SOURCE();
590
591 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
592 {
593 frequency = HAL_RCC_GetPCLK1Freq();
594 }
595 else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
596 {
597 frequency = HAL_RCC_GetSysClockFreq();
598 }
599 else if (srcclk == RCC_USART2CLKSOURCE_HSI)
600 {
601 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
602 {
603 frequency = HSI_VALUE;
604 }
605 }
606 else
607 {
608 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
609 {
610 frequency = LSE_VALUE;
611 }
612 }
613 break;
614 #endif
615
616
617 #if defined(I2C1)
618 case RCC_PERIPHCLK_I2C1:
619 /* Get the current I2C1 source */
620 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
621
622 if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
623 {
624 frequency = HAL_RCC_GetPCLK1Freq();
625 }
626 else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
627 {
628 frequency = HAL_RCC_GetSysClockFreq();
629 }
630 else if (srcclk == RCC_I2C1CLKSOURCE_HSI)
631 {
632 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
633 {
634 frequency = HSI_VALUE;
635 }
636 }
637 else
638 {
639 /* Do nothing ; for misra 15.7 error only */
640 }
641 break;
642 #endif
643
644
645
646
647 #if defined(LPTIM2)
648 case RCC_PERIPHCLK_LPTIM2:
649 /* Get the current LPTIM2 source */
650 srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
651
652 if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1)
653 {
654 frequency = HAL_RCC_GetPCLK1Freq();
655 }
656 /* Check if LSI1 or LIS2 is ready and if LPTIM2 clock selection is LSI */
657 else if (srcclk == RCC_LPTIM2CLKSOURCE_LSI)
658 {
659 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY))
660 {
661 /* LSI Frequency */
662 frequency = LSI_VALUE;
663
664 /* Check is LSI1 is divided */
665 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV))
666 {
667 frequency /= 128U;
668 }
669 }
670 #if defined(RCC_LSI2_SUPPORT)
671 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY))
672 {
673 frequency = LSI2_VALUE;
674 }
675 else
676 {
677 /* Do nothing ; for misra 15.7 error only */
678 }
679 #endif
680 }
681 else if (srcclk == RCC_LPTIM2CLKSOURCE_HSI)
682 {
683 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
684 {
685 frequency = HSI_VALUE;
686 }
687 }
688 else
689 {
690 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
691 {
692 frequency = LSE_VALUE;
693 }
694 }
695 break;
696 #endif
697
698 #if defined(SPI1)
699 case RCC_PERIPHCLK_SPI1:
700 /* Get the current SPI1 kernel source */
701 srcclk = __HAL_RCC_GET_SPI1_SOURCE();
702
703 if (srcclk == RCC_SPI1CLKSOURCE_PCLK2)
704 {
705 frequency = HAL_RCC_GetPCLK2Freq();
706 }
707 else if (srcclk == RCC_SPI1CLKSOURCE_SYSCLK)
708 {
709 frequency = HAL_RCC_GetSysClockFreq();
710 }
711 else if (srcclk == RCC_SPI1CLKSOURCE_HSI)
712 {
713 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
714 {
715 frequency = HSI_VALUE;
716 }
717 }
718 else
719 {
720 /* Do nothing ; for misra 15.7 error only */
721 }
722 break;
723 #endif
724
725 case RCC_PERIPHCLK_SYSTICK:
726 /* Get the current SYSTICK kernel source */
727 srcclk = __HAL_RCC_GET_SYSTICK_SOURCE();
728
729 if (srcclk == RCC_SYSTICKCLKSOURCE_HCLK_DIV8)
730 {
731 frequency = (HAL_RCC_GetHCLKFreq() / 8U);
732 }
733 else if (srcclk == RCC_SYSTICKCLKSOURCE_LSE)
734 {
735 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
736 {
737 frequency = LSE_VALUE;
738 }
739 }
740 else if (srcclk == RCC_SYSTICKCLKSOURCE_LSI)
741 {
742 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY))
743 {
744 /* LSI Frequency */
745 frequency = LSI_VALUE;
746
747 /* Check is LSI1 is divided */
748 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV))
749 {
750 frequency /= 128U;
751 }
752 }
753 #if defined(RCC_LSI2_SUPPORT)
754 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY))
755 {
756 frequency = LSI2_VALUE;
757 }
758 else
759 {
760 /* Do nothing ; for misra 15.7 error only */
761 }
762 #endif
763 }
764 else
765 {
766 /* Do nothing ; for misra 15.7 error only */
767 }
768 break;
769
770 case RCC_PERIPHCLK_TIMIC:
771 /* Get the current TIMIC source */
772 srcclk = __HAL_RCC_GET_TIMIC_SOURCE();
773
774 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
775 {
776 frequency = HSI_VALUE;
777 if (srcclk == RCC_TIMICCLKSOURCE_HSI_DIV256)
778 {
779 frequency /= 256U;
780 }
781 }
782 break;
783
784 #if defined (SAI1)
785 case RCC_PERIPHCLK_SAI1:
786 /* Get the current SAI1 source */
787 srcclk = __HAL_RCC_GET_SAI1_SOURCE();
788
789 if (srcclk == RCC_SAI1CLKSOURCE_PLL1P)
790 {
791 frequency = HAL_RCC_GetPLL1PFreq();
792 }
793 else if (srcclk == RCC_SAI1CLKSOURCE_PLL1Q)
794 {
795 frequency = HAL_RCC_GetPLL1QFreq();
796 }
797 else if (srcclk == RCC_SAI1CLKSOURCE_SYSCLK)
798 {
799 frequency = HAL_RCC_GetSysClockFreq();
800 }
801 else if (srcclk == RCC_SAI1CLKSOURCE_PIN)
802 {
803 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
804 }
805 else if (srcclk == RCC_SAI1CLKSOURCE_HSI)
806 {
807 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
808 {
809 frequency = HSI_VALUE;
810 }
811 }
812 else
813 {
814 /* Do nothing ; for misra 15.7 error only */
815 }
816 break;
817 #endif
818
819 case RCC_PERIPHCLK_RNG:
820 /* Get the current RNG source */
821 srcclk = __HAL_RCC_GET_RNG_SOURCE();
822
823 if (srcclk == RCC_RNGCLKSOURCE_LSE)
824 {
825 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
826 {
827 frequency = LSE_VALUE;
828 }
829 }
830 else if (srcclk == RCC_RNGCLKSOURCE_LSI)
831 {
832 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY))
833 {
834 /* LSI Frequency */
835 frequency = LSI_VALUE;
836
837 /* Check is LSI1 is divided */
838 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV))
839 {
840 frequency /= 128U;
841 }
842 }
843 #if defined(RCC_LSI2_SUPPORT)
844 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY))
845 {
846 frequency = LSI2_VALUE;
847 }
848 else
849 {
850 /* Do nothing ; for misra 15.7 error only */
851 }
852 #endif
853 }
854 else if (srcclk == RCC_RNGCLKSOURCE_HSI)
855 {
856 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
857 {
858 frequency = HSI_VALUE;
859 }
860 }
861 else
862 {
863 frequency = HAL_RCC_GetPLL1QFreq();
864 }
865 break;
866
867
868 #if defined (RCC_CCIPR2_ASSEL)
869 case RCC_PERIPHCLK_AUDIOSYNC:
870 /* Get the current Audio Sync source */
871 srcclk = __HAL_RCC_GET_AUDIOSYNC_SOURCE();
872
873 if (srcclk == RCC_ASCLKSOURCE_PLL1P)
874 {
875 frequency = HAL_RCC_GetPLL1PFreq();
876 }
877 else
878 {
879 frequency = HAL_RCC_GetPLL1QFreq();
880 }
881 break;
882 #endif
883
884 case RCC_PERIPHCLK_LPUART1:
885 /* Get the current LPUART1 source */
886 srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
887
888 if (srcclk == RCC_LPUART1CLKSOURCE_PCLK7)
889 {
890 frequency = HAL_RCC_GetPCLK7Freq();
891 }
892 else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
893 {
894 frequency = HAL_RCC_GetSysClockFreq();
895 }
896 else if (srcclk == RCC_LPUART1CLKSOURCE_HSI)
897 {
898 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
899 {
900 frequency = HSI_VALUE;
901 }
902 }
903 else
904 {
905 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
906 {
907 frequency = LSE_VALUE;
908 }
909 }
910 break;
911
912 case RCC_PERIPHCLK_SPI3:
913 /* Get the current SPI3 kernel source */
914 srcclk = __HAL_RCC_GET_SPI3_SOURCE();
915
916 if (srcclk == RCC_SPI3CLKSOURCE_PCLK7)
917 {
918 frequency = HAL_RCC_GetPCLK7Freq();
919 }
920 else if (srcclk == RCC_SPI3CLKSOURCE_SYSCLK)
921 {
922 frequency = HAL_RCC_GetSysClockFreq();
923 }
924 else if (srcclk == RCC_SPI3CLKSOURCE_HSI)
925 {
926 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
927 {
928 frequency = HSI_VALUE;
929 }
930 }
931 else
932 {
933 /* Do nothing ; for misra 15.7 error only */
934 }
935 break;
936
937 case RCC_PERIPHCLK_I2C3:
938 /* Get the current I2C3 source */
939 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
940
941 if (srcclk == RCC_I2C3CLKSOURCE_PCLK7)
942 {
943 frequency = HAL_RCC_GetPCLK7Freq();
944 }
945 else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
946 {
947 frequency = HAL_RCC_GetSysClockFreq();
948 }
949 else if (srcclk == RCC_I2C3CLKSOURCE_HSI)
950 {
951 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
952 {
953 frequency = HSI_VALUE;
954 }
955 }
956 else
957 {
958 /* Do nothing ; for misra 15.7 error only */
959 }
960 break;
961
962 case RCC_PERIPHCLK_LPTIM1:
963 /* Get the current LPTIM1 source */
964 srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
965
966 if (srcclk == RCC_LPTIM1CLKSOURCE_PCLK7)
967 {
968 frequency = HAL_RCC_GetPCLK7Freq();
969 }
970 else if (srcclk == RCC_LPTIM1CLKSOURCE_LSI)
971 {
972 /* Check if LSI1 or LIS2 is ready */
973 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY))
974 {
975 /* LSI Frequency */
976 frequency = LSI_VALUE;
977
978 /* Check is LSI1 is divided */
979 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV))
980 {
981 frequency /= 128U;
982 }
983 }
984 #if defined(RCC_LSI2_SUPPORT)
985 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY))
986 {
987 frequency = LSI2_VALUE;
988 }
989 else
990 {
991 /* Do nothing ; for misra 15.7 error only */
992 }
993 #endif
994 }
995 else if (srcclk == RCC_LPTIM1CLKSOURCE_HSI)
996 {
997 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
998 {
999 frequency = HSI_VALUE;
1000 }
1001 }
1002 else
1003 {
1004 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
1005 {
1006 frequency = LSE_VALUE;
1007 }
1008 }
1009 break;
1010
1011 case RCC_PERIPHCLK_ADC:
1012 /* Get the current ADC kernel source */
1013 srcclk = __HAL_RCC_GET_ADC_SOURCE();
1014
1015 if (srcclk == RCC_ADCCLKSOURCE_HCLK)
1016 {
1017 frequency = HAL_RCC_GetHCLKFreq();
1018 }
1019 else if (srcclk == RCC_ADCCLKSOURCE_SYSCLK)
1020 {
1021 frequency = HAL_RCC_GetSysClockFreq();
1022 }
1023 else if (srcclk == RCC_ADCCLKSOURCE_PLL1P)
1024 {
1025 frequency = HAL_RCC_GetPLL1PFreq();
1026 }
1027 else if (srcclk == RCC_ADCCLKSOURCE_HSE)
1028 {
1029 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
1030 {
1031 frequency = HSE_VALUE;
1032 }
1033 }
1034 else if (srcclk == RCC_ADCCLKSOURCE_HSI)
1035 {
1036 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1037 {
1038 frequency = HSI_VALUE;
1039 }
1040 }
1041 else
1042 {
1043 /* Do nothing ; for misra 15.7 error only */
1044 }
1045 break;
1046
1047 case RCC_PERIPHCLK_RTC:
1048 /* Get the current RTC source */
1049 srcclk = __HAL_RCC_GET_RTC_SOURCE();
1050
1051 /* Check if LSE is ready and if RTC clock selection is LSE */
1052 if (srcclk == RCC_RTCCLKSOURCE_LSE)
1053 {
1054 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
1055 {
1056 frequency = LSE_VALUE;
1057 }
1058 }
1059 /* Check if LSI1 or LIS2 is ready and if RTC clock selection is LSI */
1060 else if (srcclk == RCC_RTCCLKSOURCE_LSI)
1061 {
1062 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY))
1063 {
1064 /* LSI Frequency */
1065 frequency = LSI_VALUE;
1066
1067 /* Check is LSI1 is divided */
1068 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV))
1069 {
1070 frequency /= 128U;
1071 }
1072 }
1073 #if defined(RCC_LSI2_SUPPORT)
1074 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY))
1075 {
1076 frequency = LSI2_VALUE;
1077 }
1078 else
1079 {
1080 /* Do nothing ; for misra 15.7 error only */
1081 }
1082 #endif /* RCC_LSI2_SUPPORT */
1083 }
1084 /* Check if HSE is ready and if RTC clock selection is HSI_DIV32 */
1085 else
1086 {
1087 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
1088 {
1089 frequency = (HSE_VALUE / 32U);
1090 }
1091 }
1092 break;
1093
1094 case RCC_PERIPHCLK_RADIOST:
1095 /* Get the current RADIOST kernel source */
1096 srcclk = __HAL_RCC_GET_RADIOSLPTIM_SOURCE();
1097
1098 if (srcclk == RCC_RADIOSTCLKSOURCE_HSE_DIV1000)
1099 {
1100 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
1101 {
1102 frequency = (HSE_VALUE / 1000U);
1103 }
1104 }
1105 else if (srcclk == RCC_RADIOSTCLKSOURCE_LSE)
1106 {
1107 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
1108 {
1109 frequency = LSE_VALUE;
1110 }
1111 }
1112 else if (srcclk == RCC_RADIOSTCLKSOURCE_LSI)
1113 {
1114 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY))
1115 {
1116 /* LSI Frequency */
1117 frequency = LSI_VALUE;
1118
1119 /* Check is LSI1 is divided */
1120 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV))
1121 {
1122 frequency /= 128U;
1123 }
1124 }
1125 #if defined(RCC_LSI2_SUPPORT)
1126 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY))
1127 {
1128 frequency = LSI2_VALUE;
1129 }
1130 else
1131 {
1132 /* Do nothing ; for misra 15.7 error only */
1133 }
1134 #endif
1135 }
1136 else
1137 {
1138 /* Do nothing ; for misra 15.7 error only */
1139 }
1140 break;
1141
1142 default:
1143 break;
1144 }
1145
1146 return (frequency);
1147 }
1148
1149 /**
1150 * @}
1151 */
1152
1153 /** @addtogroup RCCEx_Exported_Functions_Group2
1154 * @brief Extended Clock management functions
1155 *
1156 @verbatim
1157 ===============================================================================
1158 ##### Extended clock management functions #####
1159 ===============================================================================
1160 [..]
1161 This subsection provides a set of functions allowing to control the
1162 activation or deactivation of LSE CSS, Low Speed Clock Output (LSCO), HSE and
1163 LSE trimming and LSI2 configuration (when applicable).
1164 @endverbatim
1165 * @{
1166 */
1167
1168 /**
1169 * @brief Enable the LSE Clock Security System.
1170 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
1171 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
1172 * clock with HAL_RCCEx_PeriphCLKConfig().
1173 * @retval None
1174 */
HAL_RCCEx_EnableLSECSS(void)1175 void HAL_RCCEx_EnableLSECSS(void)
1176 {
1177 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON);
1178 }
1179
1180 /**
1181 * @brief Disable the LSE Clock Security System.
1182 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
1183 * @retval None
1184 */
HAL_RCCEx_DisableLSECSS(void)1185 void HAL_RCCEx_DisableLSECSS(void)
1186 {
1187 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON);
1188 }
1189
1190 /**
1191 * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
1192 * @param LSCOSource specifies the Low Speed clock source to output.
1193 * This parameter can be one of the following values:
1194 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
1195 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
1196 * @retval None
1197 */
HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)1198 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
1199 {
1200 /* Check the parameters */
1201 assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
1202
1203 /* Update LSCO selection according to parameter and enable LSCO */
1204 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSCOSEL, LSCOSource | RCC_BDCR1_LSCOEN);
1205 }
1206
1207 /**
1208 * @brief Disable the Low Speed clock output.
1209 * @retval None
1210 */
HAL_RCCEx_DisableLSCO(void)1211 void HAL_RCCEx_DisableLSCO(void)
1212 {
1213 /* Clear LSCOEN in BDCR register */
1214 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSCOEN);
1215 }
1216
1217 /**
1218 * @brief Set HSE trimming value
1219 * @param Trimming specifies the HSE trimming value.
1220 * This parameter should be below 0x3F.
1221 * @retval None
1222 */
HAL_RCCEx_HSESetTrimming(uint32_t Trimming)1223 void HAL_RCCEx_HSESetTrimming(uint32_t Trimming)
1224 {
1225 /* Check the parameters */
1226 assert_param(IS_RCC_HSETRIM(Trimming));
1227
1228 MODIFY_REG(RCC->ECSCR1, RCC_ECSCR1_HSETRIM, Trimming << RCC_ECSCR1_HSETRIM_Pos);
1229 }
1230
1231 /**
1232 * @brief Get HSE trimming value
1233 * @retval The programmed HSE trimming value
1234 */
HAL_RCCEx_HSEGetTrimming(void)1235 uint32_t HAL_RCCEx_HSEGetTrimming(void)
1236 {
1237 return ((RCC->ECSCR1 & RCC_ECSCR1_HSETRIM) >> RCC_ECSCR1_HSETRIM_Pos);
1238 }
1239
1240 /**
1241 * @brief Set LSE trimming value
1242 * @param Trimming specifies the Low Speed clock source to output.
1243 * This parameter can be one of the following values:
1244 * @arg @ref RCC_LSETRIMMING_R current source resistance R
1245 * @arg @ref RCC_LSETRIMMING_3_4_R current source resistance 3/4*R
1246 * @arg @ref RCC_LSETRIMMING_2_3_R current source resistance 2/3*R
1247 * @arg @ref RCC_LSETRIMMING_1_2_R current source resistance 1/2*R
1248 * @retval None
1249 */
HAL_RCCEx_LSESetTrimming(uint32_t Trimming)1250 void HAL_RCCEx_LSESetTrimming(uint32_t Trimming)
1251 {
1252 /* Check the parameters */
1253 assert_param(IS_RCC_LSETRIM(Trimming));
1254
1255 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSETRIM, Trimming);
1256 }
1257
1258 /**
1259 * @brief Get LSE trimming value
1260 * @retval The programmed LSE trimming value
1261 */
HAL_RCCEx_LSEGetTrimming(void)1262 uint32_t HAL_RCCEx_LSEGetTrimming(void)
1263 {
1264 return (RCC->BDCR1 & RCC_BDCR1_LSETRIM);
1265 }
1266
1267 #if defined(RCC_LSI2_SUPPORT)
1268 /**
1269 * @brief Set LSI2 Configuration
1270 * @param pConfig pointer to an RCC_LSIConfigTypeDef structure that
1271 * contains the configuration information for the LSI2 oscillattor
1272 * @retval None
1273 */
HAL_RCCEx_LSI2SetConfig(const RCC_LSIConfigTypeDef * pConfig)1274 void HAL_RCCEx_LSI2SetConfig(const RCC_LSIConfigTypeDef *pConfig)
1275 {
1276 /* Check the parameters */
1277 assert_param(pConfig != NULL);
1278 assert_param(IS_RCC_LSI2_FREQTEMPSENS(pConfig->FreqTempSens));
1279 assert_param(IS_RCC_LSI2_OPERATINGMODE(pConfig->OpMode));
1280
1281 WRITE_REG(RCC->BDCR2, (pConfig->FreqTempSens | pConfig->OpMode));
1282 }
1283
1284 /**
1285 * @brief Set LSI2 Configuration
1286 * @param pConfig pointer to an RCC_LSIConfigTypeDef structure that
1287 * contains the configuration information for the LSI2 oscillattor
1288 * @retval None
1289 */
HAL_RCCEx_LSI2GetConfig(RCC_LSIConfigTypeDef * pConfig)1290 void HAL_RCCEx_LSI2GetConfig(RCC_LSIConfigTypeDef *pConfig)
1291 {
1292 uint32_t regbdcr2;
1293
1294 /* Check the parameters */
1295 assert_param(pConfig != NULL);
1296
1297 /* Get register value */
1298 regbdcr2 = RCC->BDCR2;
1299
1300 pConfig->FreqTempSens = (regbdcr2 & RCC_BDCR2_LSI2CFG);
1301 pConfig->OpMode = (regbdcr2 & RCC_BDCR2_LSI2MODE);
1302 }
1303
1304 #endif /* RCC_BDCR1_LSI2ON */
1305
1306 /**
1307 * @}
1308 */
1309
1310 /** @addtogroup RCCEx_Exported_Functions_Group3
1311 * @brief Radio clock management functions
1312 *
1313 @verbatim
1314 ===============================================================================
1315 ##### Extended radio clock management functions #####
1316 ===============================================================================
1317 [..]
1318 This subsection provides a set of functions allowing to control the
1319 radio-related parameters.
1320 @endverbatim
1321 * @{
1322 */
1323
1324 /**
1325 * @brief Enable the 2.4 GHz RADIO baseband clock
1326 * @retval None
1327 */
HAL_RCCEx_EnableRadioBBClock(void)1328 void HAL_RCCEx_EnableRadioBBClock(void)
1329 {
1330 SET_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN);
1331 }
1332
1333 /**
1334 * @brief Disable the 2.4 GHz RADIO baseband clock
1335 * @retval None
1336 */
HAL_RCCEx_DisableRadioBBClock(void)1337 void HAL_RCCEx_DisableRadioBBClock(void)
1338 {
1339 CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN);
1340 }
1341
1342 /**
1343 * @brief Enable the 2.4 GHz RADIO bus clock and HSE32 oscillator by 2.4 GHz RADIO sleep timer wakeup event
1344 * @retval None
1345 */
HAL_RCCEx_EnableRequestUponRadioWakeUpEvent(void)1346 void HAL_RCCEx_EnableRequestUponRadioWakeUpEvent(void)
1347 {
1348 SET_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON);
1349 }
1350
1351 /**
1352 * @brief Disable the 2.4 GHz RADIO bus clock and HSE32 oscillator by 2.4 GHz RADIO sleep timer wakeup event
1353 * @retval None
1354 */
HAL_RCCEx_DisableRequestUponRadioWakeUpEvent(void)1355 void HAL_RCCEx_DisableRequestUponRadioWakeUpEvent(void)
1356 {
1357 CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON);
1358 }
1359
1360 /**
1361 * @brief Get the 2.4 GHz RADIO bus clock readiness.
1362 * @note Indicate that the 2.4 GHz RADIO bus clock is ready and the 2.4 GHz RADIO registers can be accessed.
1363 * @note The output can be one of the following values :
1364 * @arg RCC_RADIO_BUS_CLOCK_NOT_READY : 2.4 GHz RADIO bus clock not ready.
1365 * @arg RCC_RADIO_BUS_CLOCK_READY : 2.4 GHz RADIO bus clock ready.
1366 * @retval The regulator REG_VDDHPA input supply selection.
1367 */
HAL_RCCEx_GetRadioBusClockReadiness(void)1368 uint32_t HAL_RCCEx_GetRadioBusClockReadiness(void)
1369 {
1370 return READ_BIT(RCC->RADIOENR, RCC_RADIOENR_RADIOCLKRDY);
1371 }
1372 /**
1373 * @}
1374 */
1375
1376 #if defined(RCC_CCIPR2_ASSEL)
1377 /** @addtogroup RCCEx_Exported_Functions_Group4
1378 * @brief Radio clock management functions
1379 *
1380 @verbatim
1381 ===============================================================================
1382 ##### Extended radio clock management functions #####
1383 ===============================================================================
1384 [..]
1385 This subsection provides a set of functions allowing to control the
1386 audio-synchronization-related parameters.
1387 @endverbatim
1388 * @{
1389 */
1390
1391 /**
1392 * @brief Enable the Audio Synchronization counter and kernel clock
1393 * @retval None
1394 */
HAL_RCCEx_EnableAudioSyncClock(void)1395 void HAL_RCCEx_EnableAudioSyncClock(void)
1396 {
1397 SET_BIT(RCC->ASCR, RCC_ASCR_CEN);
1398 }
1399
1400 /**
1401 * @brief Disable the Audio Synchronization counter and kernel clock
1402 * @retval None
1403 */
HAL_RCCEx_DisableAudioSyncClock(void)1404 void HAL_RCCEx_DisableAudioSyncClock(void)
1405 {
1406 CLEAR_BIT(RCC->ASCR, RCC_ASCR_CEN);
1407 }
1408
1409 /**
1410 * @brief Set Audio Synchronization Configuration
1411 * @param pConf pointer to an RCC_AudioSyncConfigTypeDef structure that
1412 * contains the configuration information for the Audio Synchronization
1413 * @retval None
1414 */
HAL_RCCEx_SetConfigAudioSync(const RCC_AudioSyncConfigTypeDef * pConf)1415 HAL_StatusTypeDef HAL_RCCEx_SetConfigAudioSync(const RCC_AudioSyncConfigTypeDef *pConf)
1416 {
1417 /* Check the parameters */
1418 assert_param(pConf != (void *)NULL);
1419 assert_param(IS_RCC_AUDIOSYNC_CAPTUREPRESCALER(pConf->CapturePrescaler));
1420 assert_param(IS_RCC_AUDIOSYNC_CLOCKPRESCALER(pConf->ClockPrescaler));
1421 assert_param(IS_RCC_AUDIOSYNC_AUTORELOAD(pConf->AutoReloadValue));
1422 assert_param(IS_RCC_AUDIOSYNC_COMPARE(pConf->CompareValue));
1423
1424 /* Set ASCR register value */
1425 RCC->ASCR = (((pConf->CapturePrescaler) << RCC_ASCR_CPS_Pos) & \
1426 ((pConf->ClockPrescaler) << RCC_ASCR_PSC_Pos));
1427
1428 /* Set Auto Reload value */
1429 RCC->ASARR = ((pConf->AutoReloadValue) << RCC_ASARR_AR_Pos);
1430
1431 /* Set Compare value */
1432 RCC->ASCOR = ((pConf->CompareValue) << RCC_ASCOR_CO_Pos);
1433
1434 return HAL_OK;
1435 }
1436
1437 /**
1438 * @brief Configure the pConf according to the internal
1439 * RCC configuration registers.
1440 * @param pConf pointer to an RCC_AudioSyncConfigTypeDef
1441 * structure that will be configured.
1442 * @retval None
1443 */
HAL_RCCEx_GetConfigAudioSync(RCC_AudioSyncConfigTypeDef * pConf)1444 void HAL_RCCEx_GetConfigAudioSync(RCC_AudioSyncConfigTypeDef *pConf)
1445 {
1446 uint32_t regvalue;
1447
1448 /* Check the parameters */
1449 assert_param(pConf != (void *)NULL);
1450
1451 /* Get Audio ASCR register */
1452 regvalue = RCC->ASCR;
1453
1454 /* Get Capture prescaler value */
1455 pConf->CapturePrescaler = ((regvalue & RCC_ASCR_CPS) >> RCC_ASCR_CPS_Pos);
1456
1457 /* Get Clock prescaler value */
1458 pConf->ClockPrescaler = ((regvalue & RCC_ASCR_PSC) >> RCC_ASCR_PSC_Pos);
1459
1460 /* Get Auto Reload value */
1461 pConf->AutoReloadValue = ((RCC->ASARR & RCC_ASCAR_CA) >> RCC_ASCAR_CA_Pos);
1462
1463 /* Get Compare value */
1464 pConf->CompareValue = ((RCC->ASCOR & RCC_ASCOR_CO) >> RCC_ASCOR_CO_Pos);
1465 }
1466
1467 /**
1468 * @brief Get AudioSync Counter value
1469 * @retval The Counter value
1470 */
HAL_RCCEx_GetAudioSyncCounterValue(void)1471 uint32_t HAL_RCCEx_GetAudioSyncCounterValue(void)
1472 {
1473 return ((RCC->ASCNTR & RCC_ASCNTR_CNT) >> RCC_ASCNTR_CNT_Pos);
1474 }
1475
1476 /**
1477 * @brief Get AudioSync Capture value
1478 * @retval The programmed Capture value
1479 */
HAL_RCCEx_GetAudioSyncCaptureValue(void)1480 uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void)
1481 {
1482 return ((RCC->ASCAR & RCC_ASCAR_CA) >> RCC_ASCAR_CA_Pos);
1483 }
1484
1485 /**
1486 * @}
1487 */
1488 #endif /* RCC_CCIPR2_ASSEL */
1489
1490 /**
1491 * @}
1492 */
1493
1494 #endif /* HAL_RCC_MODULE_ENABLED */
1495 /**
1496 * @}
1497 */
1498
1499 /**
1500 * @}
1501 */
1502
