1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller extension peripheral :
8 * + Power Supply Control Functions
9 * + Low Power Control Functions
10 * + Voltage Monitoring Functions
11 * + Memories Retention Functions
12 * + I/O Retention Functions
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2022 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### How to use this driver #####
27 ==============================================================================
28 [..]
29 (#) Call HAL_PWREx_ControlVoltageScaling() and HAL_PWREx_GetVoltageRange() to
30 set / get the voltage scaling range.
31 (+) Voltage scaling can be one of the following values :
32 (++) voltage output scale 1 :
33 => Used when system clock frequency is up to 100 MHz
34 (++) voltage output scale 2 :
35 => Used when system clock frequency is up to 16 MHz
36
37 (#) Call HAL_PWREx_EnableUltraLowPowerMode() and
38 HAL_PWREx_DisableUltraLowPowerMode() to enable / disable the BOR ultra
39 low power mode.
40
41 (#) Call HAL_PWREx_EnableSRAM1ContentStandbyRetention() and
42 HAL_PWREx_DisableSRAM1ContentStandbyRetention() to
43 enable / disable the SRAM1 content retention in Standby low
44 power mode.
45
46 (#) Call HAL_PWREx_EnableSRAM2ContentStandbyRetention() and
47 HAL_PWREx_DisableSRAM2ContentStandbyRetention() to
48 enable / disable the SRAM2 content retention in Standby low
49 power mode.
50
51 (#) Call HAL_PWREx_EnableRAMsContentStopRetention() and
52 HAL_PWREx_DisableRAMsContentStopRetention() to
53 enable / disable the RAMs content retention in Stop mode (Stop 0/1).
54 (+) Retained RAM can be one of the following RAMs :
55 (++) SRAM1
56 (++) SRAM2
57 (++) ICACHE
58
59 (#) Call HAL_PWREx_EnableFlashFastWakeUp() and
60 HAL_PWREx_DisableFlashFastWakeUp() to enable / disable the flash memory
61 fast wakeup from Stop mode (Stop 0/1).
62
63 (#) Call HAL_PWREx_EnableStandbyIORetention() and HAL_PWREx_DisableStandbyIORetention()
64 to enable / disable the IO state retention while in Standby mode.
65
66 (#) Call HAL_PWREx_GetStandbyIORetentionStatus() to retrieve for a given port for which
67 IO the state was retained while in Standby mode.
68
69 (#) Call HAL_PWREx_DisableStandbyRetainedIOState() to disable the IO state retained in
70 Standby mode.
71
72 (#) Call HAL_PWREx_ConfigSupply to Configure the system Power Supply.
73
74 (#) Call HAL_PWREx_GetRADIOOperatingMode to get the 2.4 GHz RADIO operating mode.
75
76 (#) Call HAL_PWREx_GetRADIOPHYOperatingModeto get the 2.4 GHz RADIO PHY operating mode.
77
78 (#) Call HAL_PWREx_GetRADIOEncryptionOperatingMode to get the radio encryption mode.
79
80 (#) Call HAL_PWREx_GetRFVDDHPA to get the 2.4 GHz RADIO control.
81
82 (#) Call HAL_PWREx_SetREGVDDHPAInputSupply and HAL_PWREx_GetREGVDDHPAInputSupply
83 set / get the regulator VDDHPA input supply selection.
84
85 (#) Call HAL_PWREx_EnableREGVDDHPABypass and HAL_PWREx_DisableREGVDDHPABypass
86 to enable / disable regulator REG_VDDHPA bypass
87
88 @endverbatim
89 ******************************************************************************
90 */
91
92 /* Includes ------------------------------------------------------------------*/
93 #include "stm32wbaxx_hal.h"
94
95 /** @addtogroup STM32WBAxx_HAL_Driver
96 * @{
97 */
98
99 /** @defgroup PWREx PWREx
100 * @brief PWR Extended HAL module driver
101 * @{
102 */
103
104 #if defined(HAL_PWR_MODULE_ENABLED)
105
106 /* Private typedef -----------------------------------------------------------*/
107 /* Private define ------------------------------------------------------------*/
108
109 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
110 * @{
111 */
112 #if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx)
113 #define PWR_PORTA_AVAILABLE_PINS (0x0FFFFU)
114 #define PWR_PORTB_AVAILABLE_PINS (0x0FFFFU)
115 #define PWR_PORTC_AVAILABLE_PINS (0x0E000U)
116 #define PWR_PORTH_AVAILABLE_PINS (0x00008U)
117 #elif defined(STM32WBA50xx)
118 #define PWR_PORTA_AVAILABLE_PINS (0x0F1E3U)
119 #define PWR_PORTB_AVAILABLE_PINS (0x09318U)
120 #define PWR_PORTC_AVAILABLE_PINS (0x0C000U)
121 #define PWR_PORTH_AVAILABLE_PINS (0x00008U)
122 #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA5Mxx) */
123 /*!< Time out value of flags setting */
124 #define PWR_VOSF_SETTING_DELAY_VALUE (0x32U) /*!< Time out value for VOSF flag setting */
125 #define PWR_MODE_CHANGE_DELAY_VALUE (0x32U) /*!< Time out for step down converter operating mode */
126 /**
127 * @}
128 */
129
130 /* Private macro -------------------------------------------------------------*/
131 /* Private variables ---------------------------------------------------------*/
132 /* Private function prototypes -----------------------------------------------*/
133 /* Exported functions --------------------------------------------------------*/
134
135 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
136 * @{
137 */
138
139 /** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
140 * @brief Power supply control functions
141 *
142 @verbatim
143 ===============================================================================
144 ##### Power supply control functions #####
145 ===============================================================================
146 [..]
147 This section provides functions allowing to control power supply.
148
149 [..]
150 (+) The STM32WBA series devices embed two regulators : one LDO (linear
151 voltage regulator) and one SMPS (step down converter) in parallel to
152 provide the VCORE supply for digital peripherals, SRAM1, SRAM2 and
153 embedded Flash memory.
154
155 (+) The SMPS allows the power consumption to be reduced but some
156 peripherals can be perturbed by the noise generated by the SMPS,
157 requiring the application to switch to LDO when running this
158 peripheral in order to reach the best performances.
159
160 (+) The LDO and the SMPS regulators have two modes: Main regulator mode
161 (used when performance is needed), and Low-power regulator mode. LDO
162 or SMPS can be used in all voltage scaling ranges, and in all Stop
163 and Standby with retention modes.
164
165 (+) After reset, the regulator is the LDO, in Range 2. Switching to SMPS
166 provides lower consumption in particular at high VDD voltage. It is
167 possible to switch from LDO to SMPS, or from SMPS to LDO on the fly in
168 any range, by configuring the REGSEL bit. It is recommended to switch
169 first to SMPS before changing the voltage range.
170
171 (+) When exiting from Stop or Standby retention modes, the regulator is the
172 same than when entering these low-power modes.
173
174 (+) When exiting from Standby modes, the LDO regulator is always used. When Standby
175 has been entered from the SMPS regulator, after exiting standby with the LDO,
176 the regulator is subsequently switched to SMPS regulator.
177
178 (+) When exiting from Stop 0 modes the voltage range is the same as on entering Stop 0
179 mode. When exiting from Stop 1 and Standby modes the voltage range 2 is used.
180
181 (+) When the 2.4 GHz RADIO is active the regulator and range can not be changed. Any
182 requested regulator or range change while the 2.4 GHz RADIO is active is suspended
183 and will only take effect after the 2.4 GHz RADIO has entered Sleep or Deepsleep mode.
184
185 (+) Both regulators can provide four different voltages (voltage scaling)
186 and can operate in Stop modes.
187 Voltage scaling ranges can be one of the following values :
188 (++) voltage output scale 1 :
189 => Used when system clock frequency is up to 100 MHz
190 (++) voltage output scale 2 :
191 => Used when system clock frequency is up to 16 MHz
192
193 @endverbatim
194 * @{
195 */
196
197 /**
198 * @brief Configure the main internal regulator output voltage to achieve
199 * a tradeoff between performance and power consumption.
200 * @param VoltageScaling : Specifies the regulator output voltage scale.
201 * This parameter can be one of the following values :
202 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output range 1.
203 * Used when system clock frequency is up to 100 MHz.
204 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output range 2.
205 * Used when system clock frequency is up to 16 MHz.
206 * @note Before moving to voltage scaling 2, it is mandatory to ensure that
207 * the system frequency is equal or below 16 MHz.
208 * @note When the 2.4 GHz RADIO is active, the range cannot be changed.
209 * Any requested range change while the 2.4 GHz RADIO is active is suspended and will
210 * only take effect after the 2.4 GHz RADIO has entered Sleep or Deepsleep mode.
211 * @note In range 2, the 2.4 GHz RADIO shall not transmit nor receive.
212 * @retval HAL Status.
213 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)214 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
215 {
216 uint32_t timeout;
217
218 /* Check the parameter */
219 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
220
221 /* Get the current voltage scale applied */
222 uint32_t vos_old = READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS);
223
224 /* No change, nothing to do */
225 if (vos_old == VoltageScaling)
226 {
227 return HAL_OK;
228 }
229
230 /* Set voltage scaling level */
231 MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling);
232
233
234 /* Wait until VOSRDY is set */
235 timeout = ((PWR_VOSF_SETTING_DELAY_VALUE * SystemCoreClock) / 1000000U) + 1U;
236 while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY) && (timeout != 0U))
237 {
238 timeout--;
239 }
240
241 /* Check time out */
242 if (timeout == 0U)
243 {
244 return HAL_TIMEOUT;
245 }
246
247 /* Wait until ACTVOSRDY is set */
248 timeout = ((PWR_VOSF_SETTING_DELAY_VALUE * SystemCoreClock) / 1000000U) + 1U;
249 while ((HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)) && (timeout != 0U))
250 {
251 timeout--;
252 }
253
254 /* Check time out */
255 if (timeout == 0U)
256 {
257 return HAL_TIMEOUT;
258 }
259
260 return HAL_OK;
261 }
262
263 /**
264 * @brief Return voltage scaling range.
265 * @retval Applied voltage scaling value.
266 */
HAL_PWREx_GetVoltageRange(void)267 uint32_t HAL_PWREx_GetVoltageRange(void)
268 {
269 return (PWR->SVMSR & PWR_SVMSR_ACTVOS);
270 }
271
272 #if defined(PWR_CR3_REGSEL)
273 /**
274 * @brief Configure the system Power Supply.
275 * @param SupplySource : Specifies the Power Supply source.
276 * This parameter can be one of the following values :
277 * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power Domains.
278 * @arg PWR_SMPS_SUPPLY : The SMPS regulator supplies the Vcore Power Domains.
279 * @retval HAL status.
280 */
HAL_PWREx_ConfigSupply(uint32_t SupplySource)281 HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
282 {
283 uint32_t timeout;
284
285 /* Check the parameter */
286 assert_param(IS_PWR_SUPPLY(SupplySource));
287
288 /* Set maximum time out */
289 timeout = ((PWR_MODE_CHANGE_DELAY_VALUE * SystemCoreClock) / 1000000U) + 1U;
290
291 /* Configure the LDO as system regulator supply */
292 if (SupplySource == PWR_LDO_SUPPLY)
293 {
294 /* Set the power supply configuration */
295 CLEAR_BIT(PWR->CR3, PWR_CR3_REGSEL);
296
297 /* Wait until system switch on new regulator */
298 while (HAL_IS_BIT_SET(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U))
299 {
300 timeout--;
301 }
302 }
303 /* Configure the SMPS as system regulator supply */
304 else
305 {
306 /* Set the power supply configuration */
307 SET_BIT(PWR->CR3, PWR_CR3_REGSEL);
308
309 /* Wait until system switch on new regulator */
310 while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U))
311 {
312 timeout--;
313 }
314 }
315
316 /* Check time out */
317 if (timeout == 0U)
318 {
319 return HAL_TIMEOUT;
320 }
321
322 return HAL_OK;
323 }
324
325 /**
326 * @brief Get the power supply configuration.
327 * @retval The supply configured.
328 */
HAL_PWREx_GetSupplyConfig(void)329 uint32_t HAL_PWREx_GetSupplyConfig(void)
330 {
331 return (PWR->SVMSR & PWR_SVMSR_REGS);
332 }
333 #endif /* defined(PWR_CR3_REGSEL) */
334
335 #if defined(PWR_CR2_FPWM)
336 /**
337 * @brief Enable SMPS PWM mode
338 * @note FPWM bit is used to reduce the SMPS switching harmonics in range 1.
339 * @note Setting FPWM bit has no effect in range 2
340 * @retval None.
341 */
HAL_PWREx_EnableSMPSPWM(void)342 void HAL_PWREx_EnableSMPSPWM(void)
343 {
344 SET_BIT(PWR->CR2, PWR_CR2_FPWM);
345 }
346
347 /**
348 * @brief Disable SMPS PWM mode
349 * @retval None.
350 */
HAL_PWREx_DisableSMPSPWM(void)351 void HAL_PWREx_DisableSMPSPWM(void)
352 {
353 CLEAR_BIT(PWR->CR2, PWR_CR2_FPWM);
354 }
355 #endif /* defined(PWR_CR2_FPWM) */
356 /**
357 * @brief Enable fast soft start for the current regulator.
358 * @retval None.
359 */
HAL_PWREx_EnableFastSoftStart(void)360 void HAL_PWREx_EnableFastSoftStart(void)
361 {
362 SET_BIT(PWR->CR3, PWR_CR3_FSTEN);
363 }
364
365 /**
366 * @brief Disable fast soft start for the current regulator.
367 * @retval None.
368 */
HAL_PWREx_DisableFastSoftStart(void)369 void HAL_PWREx_DisableFastSoftStart(void)
370 {
371 CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN);
372 }
373
374 /**
375 * @}
376 */
377
378 /** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
379 * @brief Low power control functions
380 */
381
382 /**
383 * @brief Enable BOR and PVD ultra-low power mode.
384 * @note BOR and PVD operations can be in discontinuous (ultra-low power) mode in
385 * Stop 1 and Standby modes.
386 * @note This bit must be set to reach the lowest power consumption in the low-power modes.
387 * @note This bit shall not be set together with autonomous peripherals using HSI16
388 * as kernel clock.
389 * @retval None.
390 */
HAL_PWREx_EnableUltraLowPowerMode(void)391 void HAL_PWREx_EnableUltraLowPowerMode(void)
392 {
393 SET_BIT(PWR->CR1, PWR_CR1_ULPMEN);
394 }
395
396 /**
397 * @brief Disable BOR and PVD ultra-low power mode.
398 * @retval None.
399 */
HAL_PWREx_DisableUltraLowPowerMode(void)400 void HAL_PWREx_DisableUltraLowPowerMode(void)
401 {
402 CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN);
403 }
404 /**
405 * @}
406 */
407
408
409
410 /** @defgroup PWREx_Exported_Functions_Group4 Memories Retention Functions
411 * @brief Memories retention functions
412 *
413 @verbatim
414 ===============================================================================
415 ##### Memories Retention Functions #####
416 ===============================================================================
417 [..]
418 Several STM32WBA devices RAMs are configurable to retain or lose RAMs content
419 during Stop mode.
420 (+) Retained content RAMs in Stop modes are :
421 (++) SRAM1
422 (++) SRAM2
423 (++) ICACHE
424
425 [..]
426 Several STM32WBA devices RAMs are configurable to retain or lose RAMs content
427 in Standby mode.
428 (+) Retained content RAMs in Standby mode are :
429 (++) SRAM1
430 (++) SRAM2
431
432 @endverbatim
433 * @{
434 */
435
436 /**
437 * @brief Enable SRAM1 content retention in Standby mode.
438 * @note When R1RSB1 bit is set, SRAM1 is powered by the low-power regulator in
439 * Standby mode and its content is kept.
440 * @param SRAM1Pages : Specifies the SRAM1 area
441 * This parameter can be combination of the following values :
442 * @arg PWR_SRAM1_FULL_STANDBY_RETENTION : full SRAM1 retention.
443 * @retval None.
444 */
HAL_PWREx_EnableSRAM1ContentStandbyRetention(uint32_t SRAM1Pages)445 void HAL_PWREx_EnableSRAM1ContentStandbyRetention(uint32_t SRAM1Pages)
446 {
447 /* Check the parameters */
448 assert_param(IS_PWR_SRAM1_STANDBY_RETENTION(SRAM1Pages));
449
450 /* Set RRSx bit(s) */
451 MODIFY_REG(PWR->CR1, PWR_SRAM1_FULL_STANDBY_RETENTION, SRAM1Pages);
452 }
453
454 /**
455 * @brief Disable SRAM1 content retention in Standby mode.
456 * @note When R1RSB1 bit is reset, SRAM1 is powered off in Standby
457 * mode and its content is lost.
458 * @retval None.
459 */
HAL_PWREx_DisableSRAM1ContentStandbyRetention(void)460 void HAL_PWREx_DisableSRAM1ContentStandbyRetention(void)
461 {
462 /* Clear R1RSB1 bit */
463 CLEAR_BIT(PWR->CR1, PWR_SRAM1_FULL_STANDBY_RETENTION);
464 }
465
466 /**
467 * @brief Enable SRAM2 content retention in Standby mode.
468 * @note When R2RSB1 bit is set, SRAM2 is powered by the low-power regulator in
469 * Standby mode and its content is kept.
470 * @param SRAM2Pages : Specifies the SRAM2 area
471 * This parameter can be one of the following values :
472 * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : full SRAM2 retention.
473 * @retval None.
474 */
HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)475 void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)
476 {
477 /* Check the parameters */
478 assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages));
479
480 /* Set RRSx bit(s) */
481 MODIFY_REG(PWR->CR1, PWR_SRAM2_FULL_STANDBY_RETENTION, SRAM2Pages);
482 }
483
484 /**
485 * @brief Disable SRAM2 content retention in Standby mode.
486 * @note When R2RSB1 bit is reset, SRAM2 is powered off in Standby
487 * mode and its content is lost.
488 * @retval None.
489 */
HAL_PWREx_DisableSRAM2ContentStandbyRetention(void)490 void HAL_PWREx_DisableSRAM2ContentStandbyRetention(void)
491 {
492 /* Clear R2RSB1 bit */
493 CLEAR_BIT(PWR->CR1, PWR_SRAM2_FULL_STANDBY_RETENTION);
494 }
495
496 /**
497 * @brief Enable 2.4GHz RADIO SRAMs and Sleep clock retention in Standby mode.
498 * @note When RADIORSB bit is set, the 2.4 GHz RADIO SRAMs (TXRX and Sequence) content
499 * is retained in Standby mode and the 2.4 GHz RADIO sleep timer counter remains
500 * operational.
501 * @param RadioSRAM : Specifies the Radio SRAM area
502 * This parameter can be one of the following values :
503 * @arg PWR_RADIOSRAM_FULL_STANDBY_RETENTION: full Radio SRAM and sleep counter retention.
504 * @retval None.
505 */
HAL_PWREx_EnableRadioSRAMClockStandbyRetention(uint32_t RadioSRAM)506 void HAL_PWREx_EnableRadioSRAMClockStandbyRetention(uint32_t RadioSRAM)
507 {
508 /* Check the parameters */
509 assert_param(IS_PWR_RADIOSRAM_STANDBY_RETENTION(RadioSRAM));
510
511 /* Set Radio RAM retention bit(s) */
512 MODIFY_REG(PWR->CR1, PWR_RADIOSRAM_FULL_STANDBY_RETENTION, RadioSRAM);
513 }
514
515 /**
516 * @brief Disable 2.4GHz RADIO SRAMs and Sleep clock retention in Standby mode.
517 * @note When RADIORSB bit is reset, the 2.4 GHz RADIO SRAMs and the sleep timer counter
518 * are not retained in Standby mode.
519 * @retval None.
520 */
HAL_PWREx_DisableRadioSRAMClockStandbyRetention(void)521 void HAL_PWREx_DisableRadioSRAMClockStandbyRetention(void)
522 {
523 /* Clear RADIORSB bit */
524 CLEAR_BIT(PWR->CR1, PWR_RADIOSRAM_FULL_STANDBY_RETENTION);
525 }
526
527 /**
528 * @brief Enable RAMs content retention in Stop modes.
529 * @note When enabling content retention for a given ram, memory is kept powered
530 * on in Stop mode. (Consumption is not optimized)
531 * @note On Silicon Cut 1.0, it is mandatory to disable the ICACHE before going into
532 * stop modes otherwise an hard fault may occur when waking up from stop modes.
533 * @param RAMSelection: Specifies RAMs content to be retained in Stop mode.
534 * This parameter can be one or a combination of the values:
535 * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention.
536 * @arg PWR_SRAM2_FULL_STOP_RETENTION : full SRAM2 retention.
537 * @arg PWR_ICACHE_FULL_STOP_RETENTION : I-CACHE SRAM retention.
538 * @retval None.
539 */
HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection)540 void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection)
541 {
542 /* Check the parameters */
543 assert_param(IS_PWR_RAM_STOP_RETENTION(RAMSelection));
544
545 /* Enable RAM retention in Stop mode */
546 CLEAR_BIT(PWR->CR2, RAMSelection);
547 }
548
549 /**
550 * @brief Disable RAMs content retention in Stop modes.
551 * @note When disabling content retention for a given RAM, memory is
552 * powered down in Stop mode. (Consumption is optimized)
553 * @param RAMSelection: Specifies RAMs content to be lost in Stop mode.
554 * This parameter can be one or a combination of the values:
555 * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention.
556 * @arg PWR_SRAM2_FULL_STOP_RETENTION : full SRAM2 retention.
557 * @arg PWR_ICACHE_FULL_STOP_RETENTION : I-CACHE SRAM retention.
558 * @retval None.
559 */
HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection)560 void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection)
561 {
562 /* Check the parameters */
563 assert_param(IS_PWR_RAM_STOP_RETENTION(RAMSelection));
564
565 /* Disable RAM retention in Stop mode */
566 MODIFY_REG(PWR->CR2, PWR_ALL_RAM_STOP_RETENTION_MASK, RAMSelection);
567 }
568
569 /**
570 * @brief Enable the flash memory fast wakeup from Stop 0 and Stop 1 modes.
571 * @note This feature is used to obtain the best trade-off between low-power
572 * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.
573 * When this feature is enabled, the Flash memory remains in normal
574 * mode in Stop 0 and Stop 1 modes, which offers a faster startup time
575 * with higher consumption.
576 * @retval None.
577 */
HAL_PWREx_EnableFlashFastWakeUp(void)578 void HAL_PWREx_EnableFlashFastWakeUp(void)
579 {
580 SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
581 }
582
583 /**
584 * @brief Disable the Flash Power Down in Stop mode.
585 * @note This feature is used to obtain the best trade-off between low-power
586 * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.
587 * When this feature is disabled, the Flash memory enters low-power
588 * mode in Stop 0 and Stop 1 modes, which causes a slower startup time
589 * with lower consumption.
590 * @retval None.
591 */
HAL_PWREx_DisableFlashFastWakeUp(void)592 void HAL_PWREx_DisableFlashFastWakeUp(void)
593 {
594 CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
595 }
596 /**
597 * @}
598 */
599
600 /** @defgroup PWREx_Exported_Functions_Group5 I/O Retention Functions
601 * @brief I/O retention functions
602 *
603 @verbatim
604 ===============================================================================
605 ##### IOs retention functions #####
606 ===============================================================================
607 [..]
608 In Standby mode, the GPIOs are by default in floating state. If Standby GPIO
609 retention is enabled in the PWR_IORETENRx register, the GPIO will retain the pull
610 or output level. When entering Standby mode, GPIOs that are enabled for Standby mode
611 retention keep their pull or level during and after exiting from Standby mode until
612 the PWR_IORETRx bit is cleared by software.
613
614 [..]
615 When entering Standby mode the PWR_IORETRx bit will be set by hardware for the GPIOs with
616 Standby retention enabled in. Once PWR_IORETRx is cleared by software, the GPIO configuration
617 will switch to the one defined as below:
618 (+) when GPIO is not selecting an alternate function, GPIO configuration is applied,
619 (+) when GPIO is selecting an alternate function, the selected peripheral alternate function
620 control will be applied.
621 The GPIO Standby retention enable information in PWR_IORETENRx is lost and has to be reconfigured
622 for sub-sequent entering into Standby mode.
623
624 @endverbatim
625 * @{
626 */
627
628 /**
629 * @brief Enable GPIO state retention in Standby mode.
630 * @note Set the relevant Pxy bits of PWR_IORETENRx register to configure the I/O
631 * state retention in Standby mode.
632 * @note The configuration is kept when exiting the Standby mode.
633 * @param GPIO_Port : Specify the IO port.
634 * This parameter can be a value of
635 * @ref PWREx_GPIO_Port.
636 * @param GPIO_Pin : Specify the I/O pins numbers.
637 * This parameter can be a value of
638 * @ref PWREx_GPIO_Pin_Mask.
639 * @retval HAL Status.
640 */
HAL_PWREx_EnableStandbyIORetention(uint32_t GPIO_Port,uint32_t GPIO_Pin)641 HAL_StatusTypeDef HAL_PWREx_EnableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin)
642 {
643 HAL_StatusTypeDef ret = HAL_OK;
644
645 /* Check the parameters */
646 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
647 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
648
649 /* Check GPIO port */
650 switch (GPIO_Port)
651 {
652 case PWR_GPIO_A: /* Enables the Standby GPIO retention feature for PAy */
653 if (((GPIO_Pin & PWR_PORTA_AVAILABLE_PINS) == 0U) || \
654 ((GPIO_Pin & (~PWR_PORTA_AVAILABLE_PINS)) != 0U))
655 {
656 ret = HAL_ERROR;
657 }
658 else
659 {
660 SET_BIT(PWR->IORETENRA, GPIO_Pin);
661 }
662 break;
663
664 case PWR_GPIO_B: /* Enables the Standby GPIO retention feature for PBy */
665 if (((GPIO_Pin & PWR_PORTB_AVAILABLE_PINS) == 0U) || \
666 ((GPIO_Pin & (~PWR_PORTB_AVAILABLE_PINS)) != 0U))
667 {
668 ret = HAL_ERROR;
669 }
670 else
671 {
672 SET_BIT(PWR->IORETENRB, GPIO_Pin);
673 }
674 break;
675
676 case PWR_GPIO_C: /* Enables the Standby GPIO retention feature for PCy */
677 if (((GPIO_Pin & PWR_PORTC_AVAILABLE_PINS) == 0U) || \
678 ((GPIO_Pin & (~PWR_PORTC_AVAILABLE_PINS)) != 0U))
679 {
680 ret = HAL_ERROR;
681 }
682 else
683 {
684 SET_BIT(PWR->IORETENRC, GPIO_Pin);
685 }
686 break;
687
688 case PWR_GPIO_H: /* Enables the Standby GPIO retention feature for PHy */
689 if (((GPIO_Pin & PWR_PORTH_AVAILABLE_PINS) == 0U) || \
690 ((GPIO_Pin & (~PWR_PORTH_AVAILABLE_PINS)) != 0U))
691 {
692 ret = HAL_ERROR;
693 }
694 else
695 {
696 SET_BIT(PWR->IORETENRH, GPIO_Pin);
697 }
698 break;
699
700 default:
701 ret = HAL_ERROR;
702 break;
703 }
704
705 return ret;
706 }
707
708 /**
709 * @brief Disable GPIO state retention in Standby mode.
710 * @note Clear the relevant Pxy bits of PWR_IORETENRx register to disable
711 * the I/O state retention in Standby mode.
712 * @note The configuration is kept when exiting the Standby mode.
713 * @param GPIO_Port : Specify the IO port.
714 * This parameter can be a value of
715 * @ref PWREx_GPIO_Port.
716 * @param GPIO_Pin : Specify the I/O pins numbers.
717 * This parameter can be a value of
718 * @ref PWREx_GPIO_Pin_Mask.
719 * @retval HAL Status.
720 */
HAL_PWREx_DisableStandbyIORetention(uint32_t GPIO_Port,uint32_t GPIO_Pin)721 HAL_StatusTypeDef HAL_PWREx_DisableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin)
722 {
723 HAL_StatusTypeDef ret = HAL_OK;
724
725 /* Check the parameters */
726 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
727 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
728
729 /* Check GPIO port */
730 switch (GPIO_Port)
731 {
732 case PWR_GPIO_A: /* Disables the Standby GPIO retention feature for PAy */
733 if (((GPIO_Pin & PWR_PORTA_AVAILABLE_PINS) == 0U) || \
734 ((GPIO_Pin & (~PWR_PORTA_AVAILABLE_PINS)) != 0U))
735 {
736 ret = HAL_ERROR;
737 }
738 else
739 {
740 CLEAR_BIT(PWR->IORETENRA, GPIO_Pin);
741 }
742 break;
743
744 case PWR_GPIO_B: /* Disables the Standby GPIO retention feature for PBy */
745 if (((GPIO_Pin & PWR_PORTB_AVAILABLE_PINS) == 0U) || \
746 ((GPIO_Pin & (~PWR_PORTB_AVAILABLE_PINS)) != 0U))
747 {
748 ret = HAL_ERROR;
749 }
750 else
751 {
752 CLEAR_BIT(PWR->IORETENRB, GPIO_Pin);
753 }
754 break;
755
756 case PWR_GPIO_C: /* Disables the Standby GPIO retention feature for PCy */
757 if (((GPIO_Pin & PWR_PORTC_AVAILABLE_PINS) == 0U) || \
758 ((GPIO_Pin & (~PWR_PORTC_AVAILABLE_PINS)) != 0U))
759 {
760 ret = HAL_ERROR;
761 }
762 else
763 {
764 CLEAR_BIT(PWR->IORETENRC, GPIO_Pin);
765 }
766 break;
767
768 case PWR_GPIO_H: /* Disables the Standby GPIO retention feature for PHy */
769 if (((GPIO_Pin & PWR_PORTH_AVAILABLE_PINS) == 0U) || \
770 ((GPIO_Pin & (~PWR_PORTH_AVAILABLE_PINS)) != 0U))
771 {
772 ret = HAL_ERROR;
773 }
774 else
775 {
776 CLEAR_BIT(PWR->IORETENRH, GPIO_Pin);
777 }
778 break;
779
780 default:
781 ret = HAL_ERROR;
782 break;
783 }
784
785 return ret;
786 }
787
788 /**
789 * @brief Return for a given port for which IO the state was retained in Standby mode.
790 * @param GPIO_Port : Specify the IO port.
791 * This parameter can be a value of
792 * @ref PWREx_GPIO_Port.
793 * @note The API returns the whole set of IOs for a given GPIO. A '1' at GPIO_Pin
794 * position indicates that this IO state (pull or level) was retained when
795 * the device entered Standby mode.
796 * @retval HAL Status.
797 */
HAL_PWREx_GetStandbyIORetentionStatus(uint32_t GPIO_Port)798 uint32_t HAL_PWREx_GetStandbyIORetentionStatus(uint32_t GPIO_Port)
799 {
800 /* Check the parameters */
801 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
802
803 /* Check GPIO port Standby IO retention status */
804 switch (GPIO_Port)
805 {
806 case PWR_GPIO_A: /* Get port A standby GPIO retention status */
807 return READ_REG(PWR->IORETRA);
808 break;
809
810 case PWR_GPIO_B: /* Get port B standby GPIO retention status */
811 return READ_REG(PWR->IORETRB);
812 break;
813
814 case PWR_GPIO_C: /* Get port C standby GPIO retention status */
815 return READ_REG(PWR->IORETRC);
816 break;
817
818 case PWR_GPIO_H: /* Get port H standby GPIO retention status */
819 return READ_REG(PWR->IORETRH);
820 break;
821
822 default:
823 return 0U;
824 break;
825 }
826 }
827
828 /**
829 * @brief Disable the GPIO state retained in Standby mode
830 * @param GPIO_Port : Specify the IO port.
831 * This parameter can be a value of
832 * @ref PWREx_GPIO_Port.
833 * @param GPIO_Pin : Specify the I/O pins numbers.
834 * This parameter can be a value of
835 * @ref PWREx_GPIO_Pin_Mask.
836 * @note This API can be used to disable after Standby mode the IO state that
837 * was configured to be retained by HAL_PWREx_EnableStandbyIORetention().
838 * @retval HAL Status.
839 */
HAL_PWREx_DisableStandbyRetainedIOState(uint32_t GPIO_Port,uint32_t GPIO_Pin)840 HAL_StatusTypeDef HAL_PWREx_DisableStandbyRetainedIOState(uint32_t GPIO_Port, uint32_t GPIO_Pin)
841 {
842 HAL_StatusTypeDef ret = HAL_OK;
843
844 /* Check the parameters */
845 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
846 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
847
848 /* Check GPIO port */
849 switch (GPIO_Port)
850 {
851 case PWR_GPIO_A: /* Disable the IO state (pull or level) retained for PAy in Standby mode */
852 if (((GPIO_Pin & PWR_PORTA_AVAILABLE_PINS) == 0U) || \
853 ((GPIO_Pin & (~PWR_PORTA_AVAILABLE_PINS)) != 0U))
854 {
855 ret = HAL_ERROR;
856 }
857 else
858 {
859 CLEAR_BIT(PWR->IORETRA, GPIO_Pin);
860 }
861 break;
862
863 case PWR_GPIO_B: /* Disable the IO state (pull or level) retained for PBy in Standby mode */
864 if (((GPIO_Pin & PWR_PORTB_AVAILABLE_PINS) == 0U) || \
865 ((GPIO_Pin & (~PWR_PORTB_AVAILABLE_PINS)) != 0U))
866 {
867 ret = HAL_ERROR;
868 }
869 else
870 {
871 CLEAR_BIT(PWR->IORETRB, GPIO_Pin);
872 }
873 break;
874
875 case PWR_GPIO_C: /* Disable the IO state (pull or level) retained for PCy in Standby mode */
876 if (((GPIO_Pin & PWR_PORTC_AVAILABLE_PINS) == 0U) || \
877 ((GPIO_Pin & (~PWR_PORTC_AVAILABLE_PINS)) != 0U))
878 {
879 ret = HAL_ERROR;
880 }
881 else
882 {
883 CLEAR_BIT(PWR->IORETRC, GPIO_Pin);
884 }
885 break;
886
887 case PWR_GPIO_H: /* Disable the IO state (pull or level) retained for PHy in Standby mode */
888 if (((GPIO_Pin & PWR_PORTH_AVAILABLE_PINS) == 0U) || \
889 ((GPIO_Pin & (~PWR_PORTH_AVAILABLE_PINS)) != 0U))
890 {
891 ret = HAL_ERROR;
892 }
893 else
894 {
895 CLEAR_BIT(PWR->IORETRH, GPIO_Pin);
896 }
897 break;
898
899 default:
900 ret = HAL_ERROR;
901 break;
902 }
903
904 return ret;
905 }
906
907 /**
908 * @}
909 */
910
911 /** @defgroup PWREx_Exported_Functions_Group6 I/O RADIO Configuration and Status Reading Functions
912 * @brief RADIO power amplifier setting and RADIO status reading functions
913 *
914 @verbatim
915 ===============================================================================
916 ##### RADIO configuration and status reading functions #####
917 ===============================================================================
918 @endverbatim
919 * @{
920 */
921
922 /**
923 * @brief Get the 2.4 GHz RADIO operating mode.
924 * @note The output can be any value from
925 * @ref PWREx_RADIO_Mode.
926 * @arg PWR_RADIO_DEEPSLEEP_MODE : 2.4 GHz RADIO deep sleep mode.
927 * @arg PWR_RADIO_SLEEP_MODE : 2.4 GHz RADIO sleep mode.
928 * @arg PWR_RADIO_ACTIVE_MODE : 2.4 GHz RADIO active mode.
929 * @retval The operating mode
930 */
HAL_PWREx_GetRADIOOperatingMode(void)931 uint32_t HAL_PWREx_GetRADIOOperatingMode(void)
932 {
933 uint32_t temp = READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_MODE);
934
935 if ((temp & PWR_RADIOSCR_MODE_1) == PWR_RADIOSCR_MODE_1)
936 {
937 temp = PWR_RADIO_ACTIVE_MODE;
938
939 }
940 return temp;
941 }
942
943 /**
944 * @brief Get the 2.4 GHz RADIO PHY operating mode.
945 * @note The output can be any value from
946 * @ref PWREx_RADIO_PHY_Mode.
947 * @arg PWR_RADIO_PHY_SLEEP_MODE : 2.4 GHz RADIO PHY sleep mode.
948 * @arg PWR_RADIO_PHY_STANDBY_MODE : 2.4 GHz RADIO PHY standby mode.
949 * @retval The PHY operating mode
950 */
HAL_PWREx_GetRADIOPHYOperatingMode(void)951 uint32_t HAL_PWREx_GetRADIOPHYOperatingMode(void)
952 {
953 return READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_PHYMODE);
954 }
955
956 /**
957 * @brief Get the 2.4 GHz RADIO encryption operating mode.
958 * @note The output can be any value from
959 * @arg PWR_RADIO_ENCMODE_ENABLED : 2.4 GHz RADIO encryption function enabled.
960 * @arg PWR_RADIO_ENCMODE_DISABLED : 2.4 GHz RADIO encryption function disabled.
961 * @retval The Radio encryption operating mode
962 */
HAL_PWREx_GetRADIOEncryptionOperatingMode(void)963 uint32_t HAL_PWREx_GetRADIOEncryptionOperatingMode(void)
964 {
965 return READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_ENCMODE);
966 }
967
968 /**
969 * @brief Get the 2.4 GHz RADIO control.
970 * @note The output can be any value from
971 * Bits [3:0] output power table format
972 * Bit [4] rf_event.
973 * @retval The PHY operating mode
974 */
HAL_PWREx_GetRFVDDHPA(void)975 uint32_t HAL_PWREx_GetRFVDDHPA(void)
976 {
977 return READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_RFVDDHPA);
978 }
979
980 #if defined(PWR_RADIOSCR_REGPASEL)
981 /**
982 * @brief Set the regulator REG_VDDHPA input supply selection.
983 * @param SupplySelection : Specifies the regulator REG_VDDHPA input supply.
984 * This parameter can be one of the following values :
985 * @arg PWR_RADIO_REG_VDDRFPA : VDDRFPA pin selected as regulator REG_VDDHPA input supply.
986 * @arg PWR_RADIO_REG_VDDHPA_VD11 : Regulator REG_VDDHPA input supply selection between VDDRFPA
987 * and VDD11 dependent on requested regulated output voltage.
988 * @retval HAL Status.
989 */
HAL_PWREx_SetREGVDDHPAInputSupply(uint32_t SupplySelection)990 HAL_StatusTypeDef HAL_PWREx_SetREGVDDHPAInputSupply(uint32_t SupplySelection)
991 {
992 /* Check the parameters */
993 assert_param(IS_PWR_REGPASEL_SUPPLYSELECTION(SupplySelection));
994
995 MODIFY_REG(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL, SupplySelection);
996
997 return HAL_OK;
998 }
999
1000 /**
1001 * @brief Get the regulator REG_VDDHPA input supply selection.
1002 * @note The output can be one of the following values :
1003 * @arg PWR_RADIO_REG_VDDRFPA : VDDRFPA pin selected as regulator REG_VDDHPA input supply.
1004 * @arg PWR_RADIO_REG_VDDHPA_VD11 : Regulator REG_VDDHPA input supply selection between VDDRFPA
1005 * and VDD11 dependent on requested regulated output voltage.
1006 * @retval The regulator REG_VDDHPA input supply selection.
1007 */
HAL_PWREx_GetREGVDDHPAInputSupply(void)1008 uint32_t HAL_PWREx_GetREGVDDHPAInputSupply(void)
1009 {
1010 return READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL);
1011 }
1012 #endif /* defined(PWR_RADIOSCR_REGPASEL) */
1013
1014 #if defined(PWR_RADIOSCR_REGPABYPEN)
1015 /**
1016 * @brief Enable regulator REG_VDDHPA bypass
1017 * @note Make 2.4 GHz RADIO PA 1.2 V supplied directly from internal VDD11. (only available when
1018 * REGPASEL = 0)
1019 * @note This API shall only be called when the VDDHPA regulator is not used
1020 * @retval None.
1021 */
HAL_PWREx_EnableREGVDDHPABypass(void)1022 void HAL_PWREx_EnableREGVDDHPABypass(void)
1023 {
1024 SET_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN);
1025 }
1026
1027 /**
1028 * @brief Disable regulator REG_VDDHPA bypass
1029 * @retval None.
1030 */
HAL_PWREx_DisableREGVDDHPABypass(void)1031 void HAL_PWREx_DisableREGVDDHPABypass(void)
1032 {
1033 CLEAR_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN);
1034 }
1035 #endif /* defined(PWR_RADIOSCR_REGPABYPEN) */
1036
1037 /**
1038 * @}
1039 */
1040
1041 #endif /* defined(HAL_PWR_MODULE_ENABLED) */
1042
1043 /**
1044 * @}
1045 */
1046
1047 /**
1048 * @}
1049 */
1050
1051 /**
1052 * @}
1053 */
1054
1055
