1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_hal_gtzc.c
4 * @author MCD Application Team
5 * @brief GTZC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of GTZC peripheral:
8 * + TZSC Initialization and Configuration functions
9 * + MPCBB Initialization and Configuration functions
10 * + TZSC and MPCBB Lock functions
11 * + TZIC Initialization and Configuration functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2022 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### GTZC main features #####
27 ==============================================================================
28 [..]
29 (+) Global TrustZone Controller (GTZC) composed of three sub-blocks:
30 (++) TZSC: TrustZone security controller
31 This sub-block defines the secure/privileged state of master and slave
32 peripherals.
33 (++) MPCBB: Block-Based memory protection controller
34 This sub-block defines the secure/privileged state of all blocks
35 (512-byte pages) of the associated SRAM.
36 (++) TZIC: TrustZone illegal access controller
37 This sub-block gathers all illegal access events in the system and
38 generates a secure interrupt towards NVIC.
39
40 (+) These sub-blocks are used to configure TrustZone system security in
41 a product having bus agents with programmable-security and privileged
42 attributes (securable) such as:
43 (++) on-chip RAM with programmable secure and/or privilege blocks (pages)
44 (++) AHB and APB peripherals with programmable security and/or privilege access
45 (++) AHB master granted as secure and/or privilege
46 (++) off-chip memories with secure and/or privilege areas
47
48 [..]
49 (+) TZIC accessible only with secure privileged transactions.
50 (+) Secure and non-secure access supported for privileged and unprivileged
51 part of TZSC and MPCBB
52 (+) Set of registers to define product security settings:
53 (++) Secure and privilege blocks for internal memories
54 (++) Secure and privilege regions for external memories
55 (++) Secure and privileged access mode for securable peripherals
56
57 ==============================================================================
58 ##### How to use this driver #####
59 ==============================================================================
60 [..]
61 The GTZC HAL driver can be used as follows:
62
63 (#) Configure or get back securable peripherals attributes using
64 HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes()
65
66 (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() /
67 HAL_GTZC_TZSC_GetLock()
68
69 (#) Configure or get back MPCBB memories complete configuration using
70 HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem()
71
72 (#) Configure or get back MPCBB memories attributes using
73 HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes()
74
75 (#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() /
76 HAL_GTZC_MPCBB_GetLock()
77
78 (#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() /
79 HAL_GTZC_MPCBB_GetLockConfig()
80
81 (#) Illegal access detection can be configured through TZIC sub-block using
82 following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT()
83
84 (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and
85 HAL_GTZC_TZIC_ClearFlag() functions
86
87 (#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler()
88 and user can add his own code using HAL_GTZC_TZIC_Callback()
89
90 @endverbatim
91 */
92
93 /* Includes ------------------------------------------------------------------*/
94 #include "stm32wbaxx_hal.h"
95
96 /** @addtogroup STM32WBAxx_HAL_Driver
97 * @{
98 */
99
100 #if defined(GTZC_TZSC) && defined(HAL_GTZC_MODULE_ENABLED)
101
102 /** @defgroup GTZC GTZC
103 * @brief GTZC HAL module driver
104 * @{
105 */
106
107 /* Private typedef -----------------------------------------------------------*/
108 /* Private constants ---------------------------------------------------------*/
109
110 /** @defgroup GTZC_Private_Constants GTZC Private Constants
111 * @{
112 */
113
114 /* Definitions for GTZC TZSC & TZIC ALL register values */
115 /* TZSC1 / TZIC1 instances */
116 #if defined (STM32WBA54xx) || defined (STM32WBA55xx) || defined(STM32WBA5Mxx)
117 #define TZSC1_SECCFGR1_ALL (0x000222C3UL)
118 #define TZSC1_SECCFGR2_ALL (0x018F00EBUL)
119 #define TZSC1_SECCFGR3_ALL (0x01C17858UL)
120 #define TZIC1_IER4_ALL (0xC3C0EF87UL)
121 #else
122 #define TZSC1_SECCFGR1_ALL (0x000222C3UL)
123 #define TZSC1_SECCFGR2_ALL (0x010F006BUL)
124 #define TZSC1_SECCFGR3_ALL (0x00C17858UL)
125 #define TZIC1_IER4_ALL (0xC3C0EF87UL)
126 #endif /* STM32WBA54xx || STM32WBA55xx || STM32WBA5Mxx */
127
128 #define TZSC1_PRIVCFGR1_ALL TZSC1_SECCFGR1_ALL
129 #define TZSC1_PRIVCFGR2_ALL TZSC1_SECCFGR2_ALL
130 #define TZSC1_PRIVCFGR3_ALL TZSC1_SECCFGR3_ALL
131 #define TZIC1_IER1_ALL TZSC1_SECCFGR1_ALL
132 #define TZIC1_IER2_ALL TZSC1_SECCFGR2_ALL
133 #define TZIC1_IER3_ALL TZSC1_SECCFGR3_ALL
134 #define TZIC1_FCR1_ALL TZIC1_IER1_ALL
135 #define TZIC1_FCR2_ALL TZIC1_IER2_ALL
136 #define TZIC1_FCR3_ALL TZIC1_IER3_ALL
137 #define TZIC1_FCR4_ALL TZIC1_IER4_ALL
138 /**
139 * @}
140 */
141
142 /* Private macros ------------------------------------------------------------*/
143
144 /** @defgroup GTZC_Private_Macros GTZC Private Macros
145 * @{
146 */
147
148 #define IS_ADDRESS_IN(mem, address)\
149 ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
150 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
151 || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
152 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
153
154 #define IS_ADDRESS_IN_S(mem, address)\
155 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
156 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
157
158 #define IS_ADDRESS_IN_NS(mem, address)\
159 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
160 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
161
162 /* MISRA C:2012 Rule-20.10 deviation granted to use the definition of GTZC_BASE_ADDRESS() */
163 #define GTZC_BASE_ADDRESS(mem)\
164 ( mem ## _BASE )
165
166 /**
167 * @}
168 */
169
170 /* Private variables ---------------------------------------------------------*/
171 /* Private function prototypes -----------------------------------------------*/
172 /* Exported functions --------------------------------------------------------*/
173
174 /** @defgroup GTZC_Exported_Functions GTZC Exported Functions
175 * @{
176 */
177
178 /** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions
179 * @brief TZSC Configuration functions
180 *
181 @verbatim
182 ==============================================================================
183 ##### TZSC Configuration functions #####
184 ==============================================================================
185 [..]
186 This section provides functions allowing to configure TZSC
187 TZSC: TrustZone Security Controller
188 @endverbatim
189 * @{
190 */
191
192 /**
193 * @brief Configure TZSC on a single peripheral or on all peripherals.
194 * @note Secure and non-secure attributes can only be set from the secure
195 * state when the system implements the security (TZEN=1).
196 * @note Privilege and non-privilege attributes can only be set from the
197 * privilege state when TZEN=0 or TZEN=1
198 * @note Security and privilege attributes can be set independently.
199 * @note Default state is non-secure and unprivileged access allowed.
200 * @param PeriphId Peripheral identifier
201 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
202 * Use GTZC_PERIPH_ALL to select all peripherals.
203 * @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes.
204 * @retval HAL status.
205 */
HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,uint32_t PeriphAttributes)206 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
207 uint32_t PeriphAttributes)
208 {
209 uint32_t register_address;
210
211 /* check entry parameters */
212 if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV))
213 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
214 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
215 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
216 {
217 return HAL_ERROR;
218 }
219
220 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
221 {
222 /* special case where same attributes are applied to all peripherals */
223
224 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
225 /* secure configuration */
226 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
227 {
228 SET_BIT(GTZC_TZSC->SECCFGR1, TZSC1_SECCFGR1_ALL);
229 SET_BIT(GTZC_TZSC->SECCFGR2, TZSC1_SECCFGR2_ALL);
230 SET_BIT(GTZC_TZSC->SECCFGR3, TZSC1_SECCFGR3_ALL);
231 }
232 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
233 {
234 CLEAR_BIT(GTZC_TZSC->SECCFGR1, TZSC1_SECCFGR1_ALL);
235 CLEAR_BIT(GTZC_TZSC->SECCFGR2, TZSC1_SECCFGR2_ALL);
236 CLEAR_BIT(GTZC_TZSC->SECCFGR3, TZSC1_SECCFGR3_ALL);
237 }
238 else
239 {
240 /* do nothing */
241 }
242 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
243
244 /* privilege configuration */
245 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
246 {
247 SET_BIT(GTZC_TZSC->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
248 SET_BIT(GTZC_TZSC->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
249 SET_BIT(GTZC_TZSC->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
250 }
251 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
252 {
253 CLEAR_BIT(GTZC_TZSC->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
254 CLEAR_BIT(GTZC_TZSC->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
255 CLEAR_BIT(GTZC_TZSC->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
256 }
257 else
258 {
259 /* do nothing */
260 }
261 }
262 else
263 {
264 /* common case where only one peripheral is configured */
265
266 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
267 /* secure configuration */
268 register_address = (uint32_t) &(GTZC_TZSC->SECCFGR1)
269 + (4U * GTZC_GET_REG_INDEX(PeriphId));
270 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
271 {
272 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
273 }
274 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
275 {
276 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
277 }
278 else
279 {
280 /* do nothing */
281 }
282 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
283
284 /* privilege configuration */
285 register_address = (uint32_t) &(GTZC_TZSC->PRIVCFGR1)
286 + (4U * GTZC_GET_REG_INDEX(PeriphId));
287 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
288 {
289 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
290 }
291 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
292 {
293 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
294 }
295 else
296 {
297 /* do nothing */
298 }
299 }
300 return HAL_OK;
301 }
302
303 /**
304 * @brief Get TZSC configuration on a single peripheral or on all peripherals.
305 * @param PeriphId Peripheral identifier.
306 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
307 * Use GTZC_PERIPH_ALL to select all peripherals.
308 * @param PeriphAttributes Peripheral attribute pointer.
309 * This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes.
310 * If PeriphId target a single peripheral, pointer on a single element.
311 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of
312 * GTZC_TZSC_PERIPH_NUMBER elements is to be provided.
313 * @retval HAL status.
314 */
HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,uint32_t * PeriphAttributes)315 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
316 uint32_t *PeriphAttributes)
317 {
318 uint32_t i;
319 uint32_t reg_value;
320 uint32_t register_address;
321
322 /* check entry parameters */
323 if ((PeriphAttributes == NULL)
324 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
325 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
326 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
327 {
328 return HAL_ERROR;
329 }
330
331 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
332 {
333 /* get secure configuration: read each register and deploy each bit value
334 * of corresponding index in the destination array
335 */
336 reg_value = READ_REG(GTZC_TZSC->SECCFGR1);
337 for (i = 0U; i < 32U; i++)
338 {
339 if (((reg_value & (1UL << i)) >> i) != 0U)
340 {
341 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
342 }
343 else
344 {
345 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
346 }
347 }
348
349 reg_value = READ_REG(GTZC_TZSC->SECCFGR2);
350 for (i = 32U; i < 64U; i++)
351 {
352 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
353 {
354 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
355 }
356 else
357 {
358 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
359 }
360 }
361
362 reg_value = READ_REG(GTZC_TZSC->SECCFGR3);
363 for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
364 {
365 if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
366 {
367 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
368 }
369 else
370 {
371 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
372 }
373 }
374
375 /* get privilege configuration: read each register and deploy each bit value
376 * of corresponding index in the destination array
377 */
378 reg_value = READ_REG(GTZC_TZSC->PRIVCFGR1);
379 for (i = 0U; i < 32U; i++)
380 {
381 if (((reg_value & (1UL << i)) >> i) != 0U)
382 {
383 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
384 }
385 else
386 {
387 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
388 }
389 }
390
391 reg_value = READ_REG(GTZC_TZSC->PRIVCFGR2);
392 for (i = 32U; i < 64U; i++)
393 {
394 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
395 {
396 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
397 }
398 else
399 {
400 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
401 }
402 }
403
404 reg_value = READ_REG(GTZC_TZSC->PRIVCFGR3);
405 for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
406 {
407 if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
408 {
409 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
410 }
411 else
412 {
413 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
414 }
415 }
416
417 }
418 else
419 {
420 /* common case where only one peripheral is configured */
421
422 /* secure configuration */
423 register_address = (uint32_t) &(GTZC_TZSC->SECCFGR1)
424 + (4U * GTZC_GET_REG_INDEX(PeriphId));
425
426 if (((READ_BIT(*(__IO uint32_t *)register_address,
427 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
428 != 0U)
429 {
430 *PeriphAttributes = GTZC_TZSC_PERIPH_SEC;
431 }
432 else
433 {
434 *PeriphAttributes = GTZC_TZSC_PERIPH_NSEC;
435 }
436
437 /* privilege configuration */
438 register_address = (uint32_t) &(GTZC_TZSC->PRIVCFGR1)
439 + (4U * GTZC_GET_REG_INDEX(PeriphId));
440 if (((READ_BIT(*(__IO uint32_t *)register_address,
441 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
442 != 0U)
443 {
444 *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV;
445 }
446 else
447 {
448 *PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV;
449 }
450 }
451 return HAL_OK;
452 }
453
454 /**
455 * @}
456 */
457
458 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
459
460 /** @defgroup GTZC_Exported_Functions_Group3 TZSC Lock functions
461 * @brief TZSC Lock functions
462 *
463 @verbatim
464 ==============================================================================
465 ##### TZSC Lock functions #####
466 ==============================================================================
467 [..]
468 This section provides functions allowing to manage the TZSC (TrustZone
469 Security Controller) lock. It includes lock enable, and current value read.
470 @endverbatim
471 * @{
472 */
473
474 /**
475 * @brief Lock TZSC configuration.
476 * @note This function locks the configuration of TZSC_SECCFGRx and TZSC_PRIVCFGRx
477 * registers until next reset
478 * @param TZSC_Instance TZSC sub-block instance.
479 */
HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef * TZSC_Instance)480 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance)
481 {
482 SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
483 }
484
485 /**
486 * @brief Get TZSC configuration lock state.
487 * @param TZSC_Instance TZSC sub-block instance.
488 * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
489 */
HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef * TZSC_Instance)490 uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance)
491 {
492 return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
493 }
494
495 /**
496 * @}
497 */
498 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
499
500 /** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions
501 * @brief MPCBB Configuration functions
502 *
503 @verbatim
504 ==============================================================================
505 ##### MPCBB Configuration functions #####
506 ==============================================================================
507 [..]
508 This section provides functions allowing to configure MPCBB
509 MPCBB is Memory Protection Controller Block Base
510 @endverbatim
511 * @{
512 */
513
514 /**
515 * @brief Set a complete MPCBB configuration on the SRAM passed as parameter.
516 * @param MemBaseAddress MPCBB identifier.
517 * @param pMPCBB_desc pointer to MPCBB descriptor.
518 * The structure description is available in @ref GTZC_Exported_Types.
519 * @retval HAL status.
520 */
HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,const MPCBB_ConfigTypeDef * pMPCBB_desc)521 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
522 const MPCBB_ConfigTypeDef *pMPCBB_desc)
523 {
524 GTZC_MPCBB_TypeDef *mpcbb_ptr;
525 uint32_t reg_value;
526 uint32_t mem_size;
527 uint32_t size_in_superblocks;
528 uint32_t i;
529 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
530 uint32_t size_mask;
531 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
532
533 /* check entry parameters */
534 if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
535 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
536 && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)))
537 || ((pMPCBB_desc->SecureRWIllegalMode
538 != GTZC_MPCBB_SRWILADIS_ENABLE)
539 && (pMPCBB_desc->SecureRWIllegalMode
540 != GTZC_MPCBB_SRWILADIS_DISABLE))
541 || ((pMPCBB_desc->InvertSecureState
542 != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
543 && (pMPCBB_desc->InvertSecureState
544 != GTZC_MPCBB_INVSECSTATE_INVERTED)))
545 {
546 return HAL_ERROR;
547 }
548
549 /* write InvertSecureState and SecureRWIllegalMode properties */
550 /* assume their Position/Mask is identical for all sub-blocks */
551 reg_value = pMPCBB_desc->InvertSecureState;
552 reg_value |= pMPCBB_desc->SecureRWIllegalMode;
553 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
554 {
555 mpcbb_ptr = GTZC_MPCBB1;
556 mem_size = GTZC_MEM_SIZE(SRAM1);
557 }
558 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
559 {
560 mpcbb_ptr = GTZC_MPCBB2;
561 mem_size = GTZC_MEM_SIZE(SRAM2);
562 }
563 else
564 {
565 /* Here MemBaseAddress is inside SRAM6 (parameter already checked) */
566 mpcbb_ptr = GTZC_MPCBB6;
567 mem_size = GTZC_MEM_SIZE(SRAM6);
568 }
569
570 /* translate mem_size in number of super-blocks */
571 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
572
573 /* write PRIVCFGR register information */
574 for (i = 0U; i < size_in_superblocks; i++)
575 {
576 WRITE_REG(mpcbb_ptr->PRIVCFGR[i],
577 pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]);
578 }
579
580 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
581 /* write SECCFGR register information */
582 for (i = 0U; i < size_in_superblocks; i++)
583 {
584 WRITE_REG(mpcbb_ptr->SECCFGR[i],
585 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
586 }
587
588 /* write configuration and lock register information */
589 MODIFY_REG(mpcbb_ptr->CR,
590 GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
591 size_mask = (1UL << size_in_superblocks) - 1U;
592 /* limitation: code not portable with memory > 512K */
593 MODIFY_REG(mpcbb_ptr->CFGLOCK, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
594 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
595
596 return HAL_OK;
597 }
598
599 /**
600 * @brief Get a complete MPCBB configuration on the SRAM passed as parameter.
601 * @param MemBaseAddress MPCBB identifier.
602 * @param pMPCBB_desc pointer to a MPCBB descriptor.
603 * The structure description is available in @ref GTZC_Exported_Types.
604 * @retval HAL status.
605 */
HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,MPCBB_ConfigTypeDef * pMPCBB_desc)606 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
607 MPCBB_ConfigTypeDef *pMPCBB_desc)
608 {
609 GTZC_MPCBB_TypeDef *mpcbb_ptr;
610 uint32_t mem_size;
611 uint32_t size_in_superblocks;
612 uint32_t i;
613
614 /* check entry parameters */
615 if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
616 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
617 && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)))
618 {
619 return HAL_ERROR;
620 }
621
622 /* read InvertSecureState and SecureRWIllegalMode properties */
623 /* assume their Position/Mask is identical for all sub-blocks */
624 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
625 {
626 mpcbb_ptr = GTZC_MPCBB1;
627 mem_size = GTZC_MEM_SIZE(SRAM1);
628 }
629 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
630 {
631 mpcbb_ptr = GTZC_MPCBB2;
632 mem_size = GTZC_MEM_SIZE(SRAM2);
633 }
634 else
635 {
636 mpcbb_ptr = GTZC_MPCBB6;
637 mem_size = GTZC_MEM_SIZE(SRAM6);
638 }
639
640 /* translate mem_size in number of super-blocks */
641 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
642
643 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
644 uint32_t reg_value;
645 uint32_t size_mask;
646
647 /* read configuration and lock register information */
648 reg_value = READ_REG(mpcbb_ptr->CR);
649 pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk);
650 pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
651 size_mask = (1UL << size_in_superblocks) - 1U;
652 /* limitation: code not portable with memory > 512K */
653 pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCK)
654 & size_mask;
655 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
656
657 /* read SECCFGR / PRIVCFGR registers information */
658 for (i = 0U; i < size_in_superblocks; i++)
659 {
660 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->SECCFGR[i];
661 pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i] = mpcbb_ptr->PRIVCFGR[i];
662 }
663
664 return HAL_OK;
665 }
666
667 /**
668 * @brief Set a MPCBB attribute configuration on the SRAM passed as parameter
669 * for a number of blocks.
670 * @param MemAddress MPCBB identifier, and start block to configure
671 * (must be 512 Bytes aligned).
672 * @param NbBlocks Number of blocks to configure
673 * (Block size is 512 Bytes).
674 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
675 * with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
676 * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
677 * @retval HAL status.
678 */
HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,const uint32_t * pMemAttributes)679 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
680 uint32_t NbBlocks,
681 const uint32_t *pMemAttributes)
682 {
683 GTZC_MPCBB_TypeDef *mpcbb_ptr;
684 uint32_t base_address;
685 uint32_t end_address;
686 uint32_t block_start;
687 uint32_t offset_reg_start;
688 uint32_t offset_bit_start;
689 uint32_t i;
690 uint32_t do_attr_change;
691
692 /* firstly check that MemAddress is well 512 Bytes aligned */
693 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
694 {
695 return HAL_ERROR;
696 }
697
698 /* check entry parameters and deduce physical base address */
699 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
700 if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
701 && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U)
702 {
703 mpcbb_ptr = GTZC_MPCBB1;
704 base_address = SRAM1_BASE_NS;
705 }
706 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
707 else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress))
708 && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U)
709 {
710 mpcbb_ptr = GTZC_MPCBB1;
711 base_address = SRAM1_BASE_S;
712 }
713 #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
714 else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
715 && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U)
716 {
717 mpcbb_ptr = GTZC_MPCBB2;
718 base_address = SRAM2_BASE_NS;
719 }
720 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
721 else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress))
722 && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U)
723 {
724 mpcbb_ptr = GTZC_MPCBB2;
725 base_address = SRAM2_BASE_S;
726 }
727 #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
728 else if (((IS_ADDRESS_IN_NS(SRAM6, MemAddress))
729 && (IS_ADDRESS_IN_NS(SRAM6, end_address))) != 0U)
730 {
731 mpcbb_ptr = GTZC_MPCBB6;
732 base_address = SRAM6_BASE_NS;
733 }
734 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
735 else if (((IS_ADDRESS_IN_S(SRAM6, MemAddress))
736 && (IS_ADDRESS_IN_S(SRAM6, end_address))) != 0U)
737 {
738 mpcbb_ptr = GTZC_MPCBB6;
739 base_address = SRAM6_BASE_S;
740 }
741 #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
742 else
743 {
744 return HAL_ERROR;
745 }
746
747 /* get start coordinates of the configuration */
748 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
749 offset_reg_start = block_start / 32U;
750 offset_bit_start = block_start % 32U;
751
752 for (i = 0U; i < NbBlocks; i++)
753 {
754 /* Indicate change done for protection attributes */
755 do_attr_change = 0U;
756
757 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
758 /* secure configuration */
759 if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_SEC) == GTZC_MCPBB_BLOCK_SEC)
760 {
761 SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
762 1UL << (offset_bit_start % 32U));
763 do_attr_change = 1U;
764 }
765 else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NSEC) == GTZC_MCPBB_BLOCK_NSEC)
766 {
767 CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
768 1UL << (offset_bit_start % 32U));
769 do_attr_change = 1U;
770 }
771 else
772 {
773 /* nothing to do */
774 }
775 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
776
777 /* privilege configuration */
778 if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_PRIV) == GTZC_MCPBB_BLOCK_PRIV)
779 {
780 SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
781 1UL << (offset_bit_start % 32U));
782 }
783 else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NPRIV) == GTZC_MCPBB_BLOCK_NPRIV)
784 {
785 CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
786 1UL << (offset_bit_start % 32U));
787 }
788 else
789 {
790 /* if no change is done for security and privilege attributes: break the loop */
791 if (do_attr_change == 0U)
792 {
793 break;
794 }
795 }
796
797 offset_bit_start++;
798 if (offset_bit_start == 32U)
799 {
800 offset_bit_start = 0U;
801 offset_reg_start++;
802 }
803 }
804
805 /* an unexpected value in pMemAttributes array leads to error status */
806 if (i != NbBlocks)
807 {
808 return HAL_ERROR;
809 }
810
811 return HAL_OK;
812 }
813
814 /**
815 * @brief Get a MPCBB attribute configuration on the SRAM passed as parameter
816 * for a number of blocks.
817 * @param MemAddress MPCBB identifier, and start block to get configuration
818 * (must be 512 Bytes aligned).
819 * @param NbBlocks Number of blocks to get configuration.
820 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
821 * with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
822 * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
823 * @retval HAL status.
824 */
HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,uint32_t * pMemAttributes)825 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
826 uint32_t NbBlocks,
827 uint32_t *pMemAttributes)
828 {
829 GTZC_MPCBB_TypeDef *mpcbb_ptr;
830 uint32_t base_address;
831 uint32_t end_address;
832 uint32_t block_start;
833 uint32_t offset_reg_start;
834 uint32_t offset_bit_start;
835 uint32_t i;
836
837 /* firstly check that MemAddress is well 512 Bytes aligned */
838 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
839 {
840 return HAL_ERROR;
841 }
842
843 /* check entry parameters and deduce physical base address */
844 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
845 if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
846 && (IS_ADDRESS_IN_NS(SRAM1, end_address)))
847 {
848 mpcbb_ptr = GTZC_MPCBB1_NS;
849 base_address = SRAM1_BASE_NS;
850 }
851 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
852 else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress))
853 && (IS_ADDRESS_IN_S(SRAM1, end_address)))
854 {
855 mpcbb_ptr = GTZC_MPCBB1_S;
856 base_address = SRAM1_BASE_S;
857 }
858 #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
859 else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
860 && (IS_ADDRESS_IN_NS(SRAM2, end_address)))
861 {
862 mpcbb_ptr = GTZC_MPCBB2_NS;
863 base_address = SRAM2_BASE_NS;
864 }
865 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
866 else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress))
867 && (IS_ADDRESS_IN_S(SRAM2, end_address)))
868 {
869 mpcbb_ptr = GTZC_MPCBB2_S;
870 base_address = SRAM2_BASE_S;
871 }
872 #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
873 else if ((IS_ADDRESS_IN_NS(SRAM6, MemAddress))
874 && (IS_ADDRESS_IN_NS(SRAM6, end_address)))
875 {
876 mpcbb_ptr = GTZC_MPCBB6_NS;
877 base_address = SRAM6_BASE_NS;
878 }
879 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
880 else if ((IS_ADDRESS_IN_S(SRAM6, MemAddress))
881 && (IS_ADDRESS_IN_S(SRAM6, end_address)))
882 {
883 mpcbb_ptr = GTZC_MPCBB6_S;
884 base_address = SRAM6_BASE_S;
885 }
886 #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
887 else
888 {
889 return HAL_ERROR;
890 }
891
892 /* get start coordinates of the configuration */
893 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
894 offset_reg_start = block_start / 32U;
895 offset_bit_start = block_start % 32U;
896
897 for (i = 0U; i < NbBlocks; i++)
898 {
899 pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
900 1UL << (offset_bit_start % 32U))
901 >> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK;
902 pMemAttributes[i] |= (READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
903 1UL << (offset_bit_start % 32U))
904 >> (offset_bit_start % 32U)) | GTZC_ATTR_PRIV_MASK;
905
906 offset_bit_start++;
907 if (offset_bit_start == 32U)
908 {
909 offset_bit_start = 0U;
910 offset_reg_start++;
911 }
912 }
913
914 return HAL_OK;
915 }
916
917 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
918 /**
919 * @brief Lock MPCBB super-blocks on the SRAM passed as parameter.
920 * @param MemAddress MPCBB start-address of super-block to configure
921 * (must be 16KBytes aligned).
922 * @param NbSuperBlocks Number of super-blocks to configure.
923 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
924 * with for each element:
925 * value 0 super-block is unlocked, value 1 super-block is locked
926 * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
927 * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
928 * @retval HAL status.
929 */
HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,const uint32_t * pLockAttributes)930 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
931 uint32_t NbSuperBlocks,
932 const uint32_t *pLockAttributes)
933 {
934 __IO uint32_t *reg_mpcbb;
935 uint32_t base_address;
936 uint32_t superblock_start;
937 uint32_t offset_bit_start;
938 uint32_t i;
939
940 /* firstly check that MemAddress is well 16KBytes aligned */
941 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
942 {
943 return HAL_ERROR;
944 }
945
946 /* check entry parameters */
947 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
948 && (IS_ADDRESS_IN(SRAM1, (MemAddress
949 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
950 - 1U))))
951 {
952 base_address = GTZC_BASE_ADDRESS(SRAM1);
953 /* limitation: code not portable with memory > 512K */
954 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCK;
955 }
956 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
957 && (IS_ADDRESS_IN(SRAM2, (MemAddress
958 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
959 - 1U))))
960 {
961 base_address = GTZC_BASE_ADDRESS(SRAM2);
962 /* limitation: code not portable with memory > 512K */
963 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCK;
964 }
965
966 else if ((IS_ADDRESS_IN(SRAM6, MemAddress))
967 && (IS_ADDRESS_IN(SRAM6, (MemAddress
968 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
969 - 1U))))
970 {
971 base_address = GTZC_BASE_ADDRESS(SRAM6);
972 /* limitation: code not portable with memory > 512K */
973 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCK;
974 }
975 else
976 {
977 return HAL_ERROR;
978 }
979
980 /* get start coordinates of the configuration */
981 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
982 offset_bit_start = superblock_start % 32U;
983
984 for (i = 0U; i < NbSuperBlocks; i++)
985 {
986 if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED)
987 {
988 SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
989 }
990 else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED)
991 {
992 CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
993 }
994 else
995 {
996 break;
997 }
998
999 offset_bit_start++;
1000 }
1001
1002 /* an unexpected value in pLockAttributes array leads to an error status */
1003 if (i != NbSuperBlocks)
1004 {
1005 return HAL_ERROR;
1006 }
1007
1008 return HAL_OK;
1009 }
1010
1011 /**
1012 * @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter.
1013 * @param MemAddress MPCBB start-address of super-block to get configuration
1014 * (must be 16KBytes aligned).
1015 * @param NbSuperBlocks Number of super-blocks to get configuration.
1016 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
1017 * with for each element:
1018 * value 0 super-block is unlocked, value 1 super-block is locked
1019 * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
1020 * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
1021 * @retval HAL status.
1022 */
HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,uint32_t * pLockAttributes)1023 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
1024 uint32_t NbSuperBlocks,
1025 uint32_t *pLockAttributes)
1026 {
1027 uint32_t reg_mpcbb;
1028 uint32_t base_address;
1029 uint32_t superblock_start;
1030 uint32_t offset_bit_start;
1031 uint32_t i;
1032
1033 /* firstly check that MemAddress is well 16KBytes aligned */
1034 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1035 {
1036 return HAL_ERROR;
1037 }
1038
1039 /* check entry parameters */
1040 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1041 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1042 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1043 - 1U))))
1044 {
1045 base_address = GTZC_BASE_ADDRESS(SRAM1);
1046 /* limitation: code not portable with memory > 512K */
1047 reg_mpcbb = GTZC_MPCBB1_S->CFGLOCK;
1048 }
1049 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1050 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1051 + (NbSuperBlocks
1052 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1053 - 1U))))
1054 {
1055 base_address = GTZC_BASE_ADDRESS(SRAM2);
1056 /* limitation: code not portable with memory > 512K */
1057 reg_mpcbb = GTZC_MPCBB2_S->CFGLOCK;
1058 }
1059 else if ((IS_ADDRESS_IN(SRAM6, MemAddress))
1060 && (IS_ADDRESS_IN(SRAM6, (MemAddress
1061 + (NbSuperBlocks
1062 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1063 - 1U))))
1064 {
1065 base_address = GTZC_BASE_ADDRESS(SRAM6);
1066 /* limitation: code not portable with memory > 512K */
1067 reg_mpcbb = GTZC_MPCBB6_S->CFGLOCK;
1068 }
1069 else
1070 {
1071 return HAL_ERROR;
1072 }
1073
1074 /* get start coordinates of the configuration */
1075 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1076 offset_bit_start = superblock_start % 32U;
1077
1078 for (i = 0U; i < NbSuperBlocks; i++)
1079 {
1080 pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U)))
1081 >> (offset_bit_start % 32U);
1082 offset_bit_start++;
1083 }
1084
1085 return HAL_OK;
1086 }
1087
1088 /**
1089 * @brief Lock a MPCBB configuration on the SRAM base address passed as parameter.
1090 * @note This functions locks the control register of the MPCBB until next reset.
1091 * @param MemBaseAddress MPCBB identifier.
1092 * @retval HAL status.
1093 */
HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)1094 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)
1095 {
1096 /* check entry parameters */
1097 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1098 {
1099 SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1100 }
1101 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1102 {
1103 SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1104 }
1105 else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
1106 {
1107 SET_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1108 }
1109 else
1110 {
1111 return HAL_ERROR;
1112 }
1113
1114 return HAL_OK;
1115 }
1116
1117 /**
1118 * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter.
1119 * @param MemBaseAddress MPCBB identifier.
1120 * @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON).
1121 * @retval HAL status.
1122 */
HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,uint32_t * pLockState)1123 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
1124 uint32_t *pLockState)
1125 {
1126 /* check entry parameters */
1127 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1128 {
1129 *pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1130 }
1131 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1132 {
1133 *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1134 }
1135 else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
1136 {
1137 *pLockState = READ_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1138 }
1139 else
1140 {
1141 return HAL_ERROR;
1142 }
1143
1144 return HAL_OK;
1145 }
1146
1147 /**
1148 * @}
1149 */
1150
1151 /** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions
1152 * @brief TZIC Configuration and Control functions
1153 *
1154 @verbatim
1155 ==============================================================================
1156 ##### TZIC Configuration and Control functions #####
1157 ==============================================================================
1158 [..]
1159 This section provides functions allowing to configure and control TZIC
1160 TZIC is Trust Zone Interrupt Controller
1161 @endverbatim
1162 * @{
1163 */
1164
1165 /**
1166 * @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals.
1167 * @param PeriphId Peripheral identifier.
1168 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1169 * Use GTZC_PERIPH_ALL to select all peripherals.
1170 * @retval HAL status.
1171 */
HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)1172 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)
1173 {
1174 uint32_t register_address;
1175
1176 /* check entry parameters */
1177 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1178 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1179 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1180 {
1181 return HAL_ERROR;
1182 }
1183
1184 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1185 {
1186 /* same configuration is applied to all peripherals */
1187 WRITE_REG(GTZC_TZIC->IER1, 0U);
1188 WRITE_REG(GTZC_TZIC->IER2, 0U);
1189 WRITE_REG(GTZC_TZIC->IER3, 0U);
1190 WRITE_REG(GTZC_TZIC->IER4, 0U);
1191 }
1192 else
1193 {
1194 /* common case where only one peripheral is configured */
1195 register_address = (uint32_t) &(GTZC_TZIC->IER1)
1196 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1197 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1198 }
1199
1200 return HAL_OK;
1201 }
1202
1203 /**
1204 * @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals.
1205 * @param PeriphId Peripheral identifier.
1206 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1207 * Use GTZC_PERIPH_ALL to select all peripherals.
1208 * @retval HAL status.
1209 */
HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)1210 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)
1211 {
1212 uint32_t register_address;
1213
1214 /* check entry parameters */
1215 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1216 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1217 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1218 {
1219 return HAL_ERROR;
1220 }
1221
1222 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1223 {
1224 /* same configuration is applied to all peripherals */
1225 WRITE_REG(GTZC_TZIC->IER1, TZIC1_IER1_ALL);
1226 WRITE_REG(GTZC_TZIC->IER2, TZIC1_IER2_ALL);
1227 WRITE_REG(GTZC_TZIC->IER3, TZIC1_IER3_ALL);
1228 WRITE_REG(GTZC_TZIC->IER4, TZIC1_IER4_ALL);
1229 }
1230 else
1231 {
1232 /* common case where only one peripheral is configured */
1233 register_address = (uint32_t) &(GTZC_TZIC->IER1)
1234 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1235 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1236 }
1237
1238 return HAL_OK;
1239 }
1240
1241 /**
1242 * @brief Get TZIC flag on a single TZIC peripheral or on all peripherals.
1243 * @param PeriphId Peripheral identifier.
1244 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1245 * Use GTZC_PERIPH_ALL to select all peripherals.
1246 * @param pFlag Pointer to the flags.
1247 * If PeriphId target a single peripheral, pointer on a single element.
1248 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array
1249 * of GTZC_TZIC_PERIPH_NUMBER elements.
1250 * Element content is either GTZC_TZIC_NO_ILA_EVENT
1251 * or GTZC_TZSC_ILA_EVENT_PENDING.
1252 * @retval HAL status
1253 */
HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId,uint32_t * pFlag)1254 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
1255 {
1256 uint32_t i;
1257 uint32_t reg_value;
1258 uint32_t register_address;
1259
1260 /* check entry parameters */
1261 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1262 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1263 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1264 {
1265 return HAL_ERROR;
1266 }
1267
1268 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1269 {
1270 /* special case where it is applied to all peripherals */
1271 reg_value = READ_REG(GTZC_TZIC->SR1);
1272 for (i = 0U; i < 32U; i++)
1273 {
1274 pFlag[i] = (reg_value & (1UL << i)) >> i;
1275 }
1276
1277 reg_value = READ_REG(GTZC_TZIC->SR2);
1278 for (i = 32U; i < 64U; i++)
1279 {
1280 pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U);
1281 }
1282
1283 reg_value = READ_REG(GTZC_TZIC->SR3);
1284 for (i = 64; i < 96U; i++)
1285 {
1286 pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U);
1287 }
1288
1289 reg_value = READ_REG(GTZC_TZIC->SR4);
1290 for (i = 96U; i < GTZC_TZIC_PERIPH_NUMBER; i++)
1291 {
1292 pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U);
1293 }
1294 }
1295 else
1296 {
1297 /* common case where only one peripheral is concerned */
1298 register_address = (uint32_t) &(GTZC_TZIC->SR1)
1299 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1300 *pFlag = READ_BIT(*(__IO uint32_t *)register_address,
1301 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
1302 }
1303
1304 return HAL_OK;
1305 }
1306
1307 /**
1308 * @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals.
1309 * @param PeriphId Peripheral identifier.
1310 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1311 * Use GTZC_PERIPH_ALL to select all peripherals.
1312 * @retval HAL status.
1313 */
HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)1314 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)
1315 {
1316 uint32_t register_address;
1317
1318 /* check entry parameters */
1319 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1320 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1321 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1322 {
1323 return HAL_ERROR;
1324 }
1325
1326 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1327 {
1328 /* same configuration is applied to all peripherals */
1329 WRITE_REG(GTZC_TZIC->FCR1, TZIC1_FCR1_ALL);
1330 WRITE_REG(GTZC_TZIC->FCR2, TZIC1_FCR2_ALL);
1331 WRITE_REG(GTZC_TZIC->FCR3, TZIC1_FCR3_ALL);
1332 WRITE_REG(GTZC_TZIC->FCR4, TZIC1_FCR4_ALL);
1333 }
1334 else
1335 {
1336 /* common case where only one peripheral is configured */
1337 register_address = (uint32_t) &(GTZC_TZIC->FCR1)
1338 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1339 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1340 }
1341
1342 return HAL_OK;
1343 }
1344
1345 /**
1346 * @}
1347 */
1348
1349 /** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions
1350 * @brief IRQ related functions
1351 *
1352 @verbatim
1353 ==============================================================================
1354 ##### TZIC IRQ Handler and Callback functions #####
1355 ==============================================================================
1356 [..]
1357 This section provides functions allowing to treat ISR and provide user callback
1358 @endverbatim
1359 * @{
1360 */
1361
1362 /**
1363 * @brief This function handles GTZC TZIC interrupt request.
1364 * @retval None.
1365 */
HAL_GTZC_IRQHandler(void)1366 void HAL_GTZC_IRQHandler(void)
1367 {
1368 uint32_t position;
1369 uint32_t flag;
1370 uint32_t ier_itsources;
1371 uint32_t sr_flags;
1372
1373 /*********************************************************************/
1374 /****************************** TZIC1 ******************************/
1375 /*********************************************************************/
1376
1377 /* Get current IT Flags and IT sources value on 1st register of TZIC1 */
1378 ier_itsources = READ_REG(GTZC_TZIC_S->IER1);
1379 sr_flags = READ_REG(GTZC_TZIC_S->SR1);
1380
1381 /* Get Mask interrupt and then clear them */
1382 flag = ier_itsources & sr_flags;
1383 if (flag != 0U)
1384 {
1385 WRITE_REG(GTZC_TZIC_S->FCR1, flag);
1386
1387 /* Loop on flag to check, which ones have been raised */
1388 position = 0U;
1389 while ((flag >> position) != 0U)
1390 {
1391 if ((flag & (1UL << position)) != 0U)
1392 {
1393 HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG1 | position);
1394 }
1395
1396 /* Position bit to be updated */
1397 position++;
1398 }
1399 }
1400
1401 /* Get current IT Flags and IT sources value on 2nd register of TZIC1 */
1402 ier_itsources = READ_REG(GTZC_TZIC_S->IER2);
1403 sr_flags = READ_REG(GTZC_TZIC_S->SR2);
1404
1405 /* Get Mask interrupt and then clear them */
1406 flag = ier_itsources & sr_flags;
1407 if (flag != 0U)
1408 {
1409 WRITE_REG(GTZC_TZIC_S->FCR2, flag);
1410
1411 /* Loop on flag to check, which ones have been raised */
1412 position = 0U;
1413 while ((flag >> position) != 0U)
1414 {
1415 if ((flag & (1UL << position)) != 0U)
1416 {
1417 HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG2 | position);
1418 }
1419
1420 /* Position bit to be updated */
1421 position++;
1422 }
1423 }
1424
1425 /* Get current IT Flags and IT sources value on 3rd register of TZIC1 */
1426 ier_itsources = READ_REG(GTZC_TZIC_S->IER3);
1427 sr_flags = READ_REG(GTZC_TZIC_S->SR3);
1428
1429 /* Get Mask interrupt and then clear them */
1430 flag = ier_itsources & sr_flags;
1431 if (flag != 0U)
1432 {
1433 WRITE_REG(GTZC_TZIC_S->FCR3, flag);
1434
1435 /* Loop on flag to check, which ones have been raised */
1436 position = 0U;
1437 while ((flag >> position) != 0U)
1438 {
1439 if ((flag & (1UL << position)) != 0U)
1440 {
1441 HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG3 | position);
1442 }
1443
1444 /* Position bit to be updated */
1445 position++;
1446 }
1447 }
1448
1449 /* Get current IT Flags and IT sources value on 4th register of TZIC1 */
1450 ier_itsources = READ_REG(GTZC_TZIC_S->IER4);
1451 sr_flags = READ_REG(GTZC_TZIC_S->SR4);
1452
1453 /* Get Mask interrupt and then clear them */
1454 flag = ier_itsources & sr_flags;
1455 if (flag != 0U)
1456 {
1457 WRITE_REG(GTZC_TZIC_S->FCR4, flag);
1458
1459 /* Loop on flag to check, which ones have been raised */
1460 position = 0U;
1461 while ((flag >> position) != 0U)
1462 {
1463 if ((flag & (1UL << position)) != 0U)
1464 {
1465 HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG4 | position);
1466 }
1467
1468 /* Position bit to be updated */
1469 position++;
1470 }
1471 }
1472
1473 }
1474
1475 /**
1476 * @brief GTZC TZIC sub-block interrupt callback.
1477 * @param PeriphId Peripheral identifier triggering the illegal access.
1478 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId
1479 * @retval None.
1480 */
HAL_GTZC_TZIC_Callback(uint32_t PeriphId)1481 __weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId)
1482 {
1483 /* Prevent unused argument(s) compilation warning */
1484 UNUSED(PeriphId);
1485
1486 /* NOTE: This function should not be modified. When the callback is needed,
1487 * the HAL_GTZC_TZIC_Callback is to be implemented in the user file
1488 */
1489 }
1490
1491 /**
1492 * @}
1493 */
1494
1495 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1496
1497 /**
1498 * @}
1499 */
1500
1501 /**
1502 * @}
1503 */
1504
1505 #endif /* defined(GTZC_TZSC) && defined(HAL_GTZC_MODULE_ENABLED) */
1506
1507 /**
1508 * @}
1509 */
1510
