1 /**
2 ******************************************************************************
3 * @file stm32wb0x_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wb0x_ll_tim.h"
22 #include "stm32wb0x_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32WB0x_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM16) || defined (TIM17)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
71
72 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
73 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
74
75 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
76 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
77
78 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
79 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
80
81 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
82 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
84
85 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
86 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
89
90 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
106
107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
108 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
110
111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
112 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
114
115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
116 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
117
118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
119 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
120
121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
122 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
123
124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
125 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
128
129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
130 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
131
132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
133 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
134 #if defined(TIM_BDTR_BKF)
135
136 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
151 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
152 #endif /* TIM_BDTR_BKF */
153 #if defined(TIM_BDTR_BKBID)
154
155 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
156 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
157 #endif /* TIM_BDTR_BKBID */
158 #if defined(TIM_BDTR_BK2E)
159
160 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
161 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
162
163 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
164 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
165
166 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
177 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
178 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
179 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
180 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
181 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
182 #endif /* TIM_BDTR_BK2E */
183
184 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
185 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
186 /**
187 * @}
188 */
189
190
191 /* Private function prototypes -----------------------------------------------*/
192 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
193 * @{
194 */
195 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
196 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
197 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
198 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
199 #if defined(TIM_CCER_CC5E)
200 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
201 #endif /* TIM_CCER_CC5E */
202 #if defined(TIM_CCER_CC6E)
203 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
204 #endif /* TIM_CCER_CC6E */
205 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
206 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
207 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
208 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
209 /**
210 * @}
211 */
212
213 /* Exported functions --------------------------------------------------------*/
214 /** @addtogroup TIM_LL_Exported_Functions
215 * @{
216 */
217
218 /** @addtogroup TIM_LL_EF_Init
219 * @{
220 */
221
222 /**
223 * @brief Set TIMx registers to their reset values.
224 * @param TIMx Timer instance
225 * @retval An ErrorStatus enumeration value:
226 * - SUCCESS: TIMx registers are de-initialized
227 * - ERROR: invalid TIMx instance
228 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)229 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
230 {
231 ErrorStatus result = SUCCESS;
232
233 /* Check the parameters */
234 assert_param(IS_TIM_INSTANCE(TIMx));
235
236 #if defined(TIM1)
237 if (TIMx == TIM1)
238 {
239 LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_TIM1);
240 LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_TIM1);
241 }
242 #else
243 if (TIMx == TIM2)
244 {
245 LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_TIM2);
246 LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_TIM2);
247 }
248 else if (TIMx == TIM16)
249 {
250 LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_TIM16);
251 LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_TIM16);
252 }
253
254 else if (TIMx == TIM17)
255 {
256 LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_TIM17);
257 LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_TIM17);
258 }
259 #endif /* TIM1 */
260 else
261 {
262 result = ERROR;
263 }
264
265 return result;
266 }
267
268 /**
269 * @brief Set the fields of the time base unit configuration data structure
270 * to their default values.
271 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
272 * @retval None
273 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)274 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
275 {
276 /* Set the default configuration */
277 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
278 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
279 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
280 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
281 TIM_InitStruct->RepetitionCounter = 0x00000000U;
282 }
283
284 /**
285 * @brief Configure the TIMx time base unit.
286 * @param TIMx Timer Instance
287 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
288 * (TIMx time base unit configuration data structure)
289 * @retval An ErrorStatus enumeration value:
290 * - SUCCESS: TIMx registers are de-initialized
291 * - ERROR: not applicable
292 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)293 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
294 {
295 uint32_t tmpcr1;
296
297 /* Check the parameters */
298 assert_param(IS_TIM_INSTANCE(TIMx));
299 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
300 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
301
302 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
303
304 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
305 {
306 /* Select the Counter Mode */
307 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
308 }
309
310 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
311 {
312 /* Set the clock division */
313 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
314 }
315
316 /* Write to TIMx CR1 */
317 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
318
319 /* Set the Autoreload value */
320 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
321
322 /* Set the Prescaler value */
323 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
324
325 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
326 {
327 /* Set the Repetition Counter value */
328 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
329 }
330
331 /* Generate an update event to reload the Prescaler
332 and the repetition counter value (if applicable) immediately */
333 LL_TIM_GenerateEvent_UPDATE(TIMx);
334
335 return SUCCESS;
336 }
337
338 /**
339 * @brief Set the fields of the TIMx output channel configuration data
340 * structure to their default values.
341 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
342 * (the output channel configuration data structure)
343 * @retval None
344 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)345 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
346 {
347 /* Set the default configuration */
348 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
349 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
350 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
351 TIM_OC_InitStruct->CompareValue = 0x00000000U;
352 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
353 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
354 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
355 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
356 }
357
358 /**
359 * @brief Configure the TIMx output channel.
360 * @param TIMx Timer Instance
361 * @param Channel This parameter can be one of the following values:
362 * @arg @ref LL_TIM_CHANNEL_CH1
363 * @arg @ref LL_TIM_CHANNEL_CH2
364 * @arg @ref LL_TIM_CHANNEL_CH3
365 * @arg @ref LL_TIM_CHANNEL_CH4
366 * @arg @ref LL_TIM_CHANNEL_CH5
367 * @arg @ref LL_TIM_CHANNEL_CH6
368 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
369 * data structure)
370 * @retval An ErrorStatus enumeration value:
371 * - SUCCESS: TIMx output channel is initialized
372 * - ERROR: TIMx output channel is not initialized
373 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)374 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
375 {
376 ErrorStatus result = ERROR;
377
378 switch (Channel)
379 {
380 case LL_TIM_CHANNEL_CH1:
381 result = OC1Config(TIMx, TIM_OC_InitStruct);
382 break;
383 case LL_TIM_CHANNEL_CH2:
384 result = OC2Config(TIMx, TIM_OC_InitStruct);
385 break;
386 case LL_TIM_CHANNEL_CH3:
387 result = OC3Config(TIMx, TIM_OC_InitStruct);
388 break;
389 case LL_TIM_CHANNEL_CH4:
390 result = OC4Config(TIMx, TIM_OC_InitStruct);
391 break;
392 #if defined(TIM_CCER_CC5E)
393 case LL_TIM_CHANNEL_CH5:
394 result = OC5Config(TIMx, TIM_OC_InitStruct);
395 break;
396 #endif /* TIM_CCER_CC5E */
397 #if defined(TIM_CCER_CC6E)
398 case LL_TIM_CHANNEL_CH6:
399 result = OC6Config(TIMx, TIM_OC_InitStruct);
400 break;
401 #endif /* TIM_CCER_CC6E */
402 default:
403 break;
404 }
405
406 return result;
407 }
408
409 /**
410 * @brief Set the fields of the TIMx input channel configuration data
411 * structure to their default values.
412 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
413 * data structure)
414 * @retval None
415 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)416 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
417 {
418 /* Set the default configuration */
419 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
420 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
421 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
422 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
423 }
424
425 /**
426 * @brief Configure the TIMx input channel.
427 * @param TIMx Timer Instance
428 * @param Channel This parameter can be one of the following values:
429 * @arg @ref LL_TIM_CHANNEL_CH1
430 * @arg @ref LL_TIM_CHANNEL_CH2
431 * @arg @ref LL_TIM_CHANNEL_CH3
432 * @arg @ref LL_TIM_CHANNEL_CH4
433 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
434 * structure)
435 * @retval An ErrorStatus enumeration value:
436 * - SUCCESS: TIMx output channel is initialized
437 * - ERROR: TIMx output channel is not initialized
438 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)439 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
440 {
441 ErrorStatus result = ERROR;
442
443 switch (Channel)
444 {
445 case LL_TIM_CHANNEL_CH1:
446 result = IC1Config(TIMx, TIM_IC_InitStruct);
447 break;
448 case LL_TIM_CHANNEL_CH2:
449 result = IC2Config(TIMx, TIM_IC_InitStruct);
450 break;
451 case LL_TIM_CHANNEL_CH3:
452 result = IC3Config(TIMx, TIM_IC_InitStruct);
453 break;
454 case LL_TIM_CHANNEL_CH4:
455 result = IC4Config(TIMx, TIM_IC_InitStruct);
456 break;
457 default:
458 break;
459 }
460
461 return result;
462 }
463
464 /**
465 * @brief Fills each TIM_EncoderInitStruct field with its default value
466 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
467 * configuration data structure)
468 * @retval None
469 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)470 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
471 {
472 /* Set the default configuration */
473 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
474 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
475 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
476 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
477 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
478 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
479 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
480 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
481 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
482 }
483
484 /**
485 * @brief Configure the encoder interface of the timer instance.
486 * @param TIMx Timer Instance
487 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
488 * configuration data structure)
489 * @retval An ErrorStatus enumeration value:
490 * - SUCCESS: TIMx registers are de-initialized
491 * - ERROR: not applicable
492 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)493 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
494 {
495 uint32_t tmpccmr1;
496 uint32_t tmpccer;
497
498 /* Check the parameters */
499 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
500 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
501 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
502 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
503 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
504 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
505 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
506 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
507 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
508 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
509
510 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
511 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
512
513 /* Get the TIMx CCMR1 register value */
514 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
515
516 /* Get the TIMx CCER register value */
517 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
518
519 /* Configure TI1 */
520 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
521 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
522 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
523 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
524
525 /* Configure TI2 */
526 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
527 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
528 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
529 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
530
531 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
532 #if defined(TIM_CCER_CC2NP)
533 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
534 #else
535 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P);
536 #endif /* TIM_CCER_CC2NP */
537 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
538 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
539 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
540
541 /* Set encoder mode */
542 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
543
544 /* Write to TIMx CCMR1 */
545 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
546
547 /* Write to TIMx CCER */
548 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
549
550 return SUCCESS;
551 }
552
553
554 /**
555 * @brief Set the fields of the Break and Dead Time configuration data structure
556 * to their default values.
557 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
558 * data structure)
559 * @retval None
560 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)561 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
562 {
563 /* Set the default configuration */
564 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
565 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
566 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
567 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
568 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
569 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
570 #if defined(TIM_BDTR_BKF)
571 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
572 #endif /* TIM_BDTR_BKF */
573 #if defined(TIM_BDTR_BKBID)
574 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
575 #endif /* TIM_BDTR_BKBID */
576 #if defined(TIM_BDTR_BK2E)
577 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
578 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
579 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
580 #endif /* TIM_BDTR_BK2E */
581 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
582 }
583
584 /**
585 * @brief Configure the Break and Dead Time feature of the timer instance.
586 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
587 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
588 * can be necessary to configure all of them during the first write access to
589 * the TIMx_BDTR register.
590 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
591 * a timer instance provides a break input.
592 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
593 * a timer instance provides a second break input.
594 * @param TIMx Timer Instance
595 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
596 * data structure)
597 * @retval An ErrorStatus enumeration value:
598 * - SUCCESS: Break and Dead Time is initialized
599 * - ERROR: not applicable
600 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)601 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
602 {
603 uint32_t tmpbdtr = 0;
604
605 /* Check the parameters */
606 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
607 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
608 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
609 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
610 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
611 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
612 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
613 #if defined(TIM_BDTR_BKF)
614 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
615 #endif /* TIM_BDTR_BKF */
616 #if defined(TIM_BDTR_BKBID)
617 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
618 #endif /*TIM_BDTR_BKBID */
619
620 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
621 the OSSI State, the dead time value and the Automatic Output Enable Bit */
622
623 /* Set the BDTR bits */
624 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
625 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
626 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
627 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
628 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
629 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
630 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
631 #if defined(TIM_BDTR_BKF)
632 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
633 #endif /* TIM_BDTR_BKF */
634 #if defined(TIM_BDTR_BKBID)
635 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
636 #endif /*TIM_BDTR_BKBID */
637 #if defined(TIM_BDTR_BK2E)
638
639 if (IS_TIM_BKIN2_INSTANCE(TIMx))
640 {
641 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
642 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
643 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
644
645 /* Set the BREAK2 input related BDTR bit-fields */
646 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
647 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
648 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
649 }
650 #endif /* TIM_BDTR_BK2E */
651
652 /* Set TIMx_BDTR */
653 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
654
655 return SUCCESS;
656 }
657 /**
658 * @}
659 */
660
661 /**
662 * @}
663 */
664
665 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
666 * @brief Private functions
667 * @{
668 */
669 /**
670 * @brief Configure the TIMx output channel 1.
671 * @param TIMx Timer Instance
672 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
673 * @retval An ErrorStatus enumeration value:
674 * - SUCCESS: TIMx registers are de-initialized
675 * - ERROR: not applicable
676 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)677 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
678 {
679 uint32_t tmpccmr1;
680 uint32_t tmpccer;
681 uint32_t tmpcr2;
682
683 /* Check the parameters */
684 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
685 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
686 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
687 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
688
689 /* Disable the Channel 1: Reset the CC1E Bit */
690 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
691
692 /* Get the TIMx CCER register value */
693 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
694
695 /* Get the TIMx CR2 register value */
696 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
697
698 /* Get the TIMx CCMR1 register value */
699 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
700
701 /* Reset Capture/Compare selection Bits */
702 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
703
704 /* Set the Output Compare Mode */
705 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
706
707 /* Set the Output Compare Polarity */
708 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
709
710 /* Set the Output State */
711 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
712
713 if (IS_TIM_BREAK_INSTANCE(TIMx))
714 {
715 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
716 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
717 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
718 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
719
720 /* Set the complementary output Polarity */
721 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
722
723 /* Set the complementary output State */
724 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
725
726 /* Set the Output Idle state */
727 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
728
729 /* Set the complementary output Idle state */
730 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
731 }
732
733 /* Write to TIMx CR2 */
734 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
735
736 /* Write to TIMx CCMR1 */
737 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
738
739 /* Set the Capture Compare Register value */
740 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
741
742 /* Write to TIMx CCER */
743 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
744
745 return SUCCESS;
746 }
747
748 /**
749 * @brief Configure the TIMx output channel 2.
750 * @param TIMx Timer Instance
751 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
752 * @retval An ErrorStatus enumeration value:
753 * - SUCCESS: TIMx registers are de-initialized
754 * - ERROR: not applicable
755 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)756 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
757 {
758 uint32_t tmpccmr1;
759 uint32_t tmpccer;
760 uint32_t tmpcr2;
761
762 /* Check the parameters */
763 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
764 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
765 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
766 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
767
768 /* Disable the Channel 2: Reset the CC2E Bit */
769 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
770
771 /* Get the TIMx CCER register value */
772 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
773
774 /* Get the TIMx CR2 register value */
775 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
776
777 /* Get the TIMx CCMR1 register value */
778 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
779
780 /* Reset Capture/Compare selection Bits */
781 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
782
783 /* Select the Output Compare Mode */
784 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
785
786 /* Set the Output Compare Polarity */
787 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
788
789 /* Set the Output State */
790 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
791
792 #if defined(TIM_CR2_OIS2)
793 if (IS_TIM_BREAK_INSTANCE(TIMx))
794 {
795 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
796 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
797 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
798 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
799
800 /* Set the complementary output Polarity */
801 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
802
803 /* Set the complementary output State */
804 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
805
806 /* Set the Output Idle state */
807 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
808
809 /* Set the complementary output Idle state */
810 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
811 }
812 #endif /* TIM_CR2_OIS2 */
813
814 /* Write to TIMx CR2 */
815 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
816
817 /* Write to TIMx CCMR1 */
818 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
819
820 /* Set the Capture Compare Register value */
821 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
822
823 /* Write to TIMx CCER */
824 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
825
826 return SUCCESS;
827 }
828
829 /**
830 * @brief Configure the TIMx output channel 3.
831 * @param TIMx Timer Instance
832 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
833 * @retval An ErrorStatus enumeration value:
834 * - SUCCESS: TIMx registers are de-initialized
835 * - ERROR: not applicable
836 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)837 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
838 {
839 uint32_t tmpccmr2;
840 uint32_t tmpccer;
841 uint32_t tmpcr2;
842
843 /* Check the parameters */
844 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
845 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
846 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
847 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
848
849 /* Disable the Channel 3: Reset the CC3E Bit */
850 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
851
852 /* Get the TIMx CCER register value */
853 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
854
855 /* Get the TIMx CR2 register value */
856 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
857
858 /* Get the TIMx CCMR2 register value */
859 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
860
861 /* Reset Capture/Compare selection Bits */
862 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
863
864 /* Select the Output Compare Mode */
865 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
866
867 /* Set the Output Compare Polarity */
868 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
869
870 /* Set the Output State */
871 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
872
873 #if defined(TIM_CR2_OIS3)
874 if (IS_TIM_BREAK_INSTANCE(TIMx))
875 {
876 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
877 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
878 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
879 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
880
881 /* Set the complementary output Polarity */
882 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
883
884 /* Set the complementary output State */
885 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
886
887 /* Set the Output Idle state */
888 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
889
890 /* Set the complementary output Idle state */
891 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
892 }
893 #endif /* TIM_CR2_OIS3 */
894
895 /* Write to TIMx CR2 */
896 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
897
898 /* Write to TIMx CCMR2 */
899 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
900
901 /* Set the Capture Compare Register value */
902 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
903
904 /* Write to TIMx CCER */
905 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
906
907 return SUCCESS;
908 }
909
910 /**
911 * @brief Configure the TIMx output channel 4.
912 * @param TIMx Timer Instance
913 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
914 * @retval An ErrorStatus enumeration value:
915 * - SUCCESS: TIMx registers are de-initialized
916 * - ERROR: not applicable
917 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)918 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
919 {
920 uint32_t tmpccmr2;
921 uint32_t tmpccer;
922 uint32_t tmpcr2;
923
924 /* Check the parameters */
925 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
926 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
927 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
928 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
929
930 /* Disable the Channel 4: Reset the CC4E Bit */
931 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
932
933 /* Get the TIMx CCER register value */
934 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
935
936 /* Get the TIMx CR2 register value */
937 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
938
939 /* Get the TIMx CCMR2 register value */
940 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
941
942 /* Reset Capture/Compare selection Bits */
943 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
944
945 /* Select the Output Compare Mode */
946 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
947
948 /* Set the Output Compare Polarity */
949 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
950
951 /* Set the Output State */
952 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
953
954 #if defined(TIM_CR2_OIS4)
955 if (IS_TIM_BREAK_INSTANCE(TIMx))
956 {
957 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
958
959 /* Set the Output Idle state */
960 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
961 }
962 #endif /* TIM_CCER_CC4NE */
963
964 /* Write to TIMx CR2 */
965 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
966
967 /* Write to TIMx CCMR2 */
968 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
969
970 /* Set the Capture Compare Register value */
971 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
972
973 /* Write to TIMx CCER */
974 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
975
976 return SUCCESS;
977 }
978
979 #if defined(TIM_CCER_CC5E)
980 /**
981 * @brief Configure the TIMx output channel 5.
982 * @param TIMx Timer Instance
983 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
984 * @retval An ErrorStatus enumeration value:
985 * - SUCCESS: TIMx registers are de-initialized
986 * - ERROR: not applicable
987 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)988 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
989 {
990 uint32_t tmpccmr3;
991 uint32_t tmpccer;
992
993 /* Check the parameters */
994 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
995 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
996 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
997 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
998 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
999 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1000
1001 /* Disable the Channel 5: Reset the CC5E Bit */
1002 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1003
1004 /* Get the TIMx CCER register value */
1005 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1006
1007 /* Get the TIMx CCMR3 register value */
1008 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1009
1010 /* Select the Output Compare Mode */
1011 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1012
1013 /* Set the Output Compare Polarity */
1014 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1015
1016 /* Set the Output State */
1017 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1018
1019 if (IS_TIM_BREAK_INSTANCE(TIMx))
1020 {
1021 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1022 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1023
1024 /* Set the Output Idle state */
1025 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1026
1027 }
1028
1029 /* Write to TIMx CCMR3 */
1030 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1031
1032 /* Set the Capture Compare Register value */
1033 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1034
1035 /* Write to TIMx CCER */
1036 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1037
1038 return SUCCESS;
1039 }
1040 #endif /* TIM_CCER_CC5E */
1041
1042 #if defined(TIM_CCER_CC6E)
1043 /**
1044 * @brief Configure the TIMx output channel 6.
1045 * @param TIMx Timer Instance
1046 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1047 * @retval An ErrorStatus enumeration value:
1048 * - SUCCESS: TIMx registers are de-initialized
1049 * - ERROR: not applicable
1050 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1051 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1052 {
1053 uint32_t tmpccmr3;
1054 uint32_t tmpccer;
1055
1056 /* Check the parameters */
1057 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1058 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1059 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1060 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1061 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1062 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1063
1064 /* Disable the Channel 5: Reset the CC6E Bit */
1065 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1066
1067 /* Get the TIMx CCER register value */
1068 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1069
1070 /* Get the TIMx CCMR3 register value */
1071 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1072
1073 /* Select the Output Compare Mode */
1074 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1075
1076 /* Set the Output Compare Polarity */
1077 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1078
1079 /* Set the Output State */
1080 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1081
1082 if (IS_TIM_BREAK_INSTANCE(TIMx))
1083 {
1084 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1085 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1086
1087 /* Set the Output Idle state */
1088 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1089 }
1090
1091 /* Write to TIMx CCMR3 */
1092 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1093
1094 /* Set the Capture Compare Register value */
1095 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1096
1097 /* Write to TIMx CCER */
1098 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1099
1100 return SUCCESS;
1101 }
1102 #endif /* TIM_CCER_CC6E */
1103
1104 /**
1105 * @brief Configure the TIMx input channel 1.
1106 * @param TIMx Timer Instance
1107 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1108 * @retval An ErrorStatus enumeration value:
1109 * - SUCCESS: TIMx registers are de-initialized
1110 * - ERROR: not applicable
1111 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1112 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1113 {
1114 /* Check the parameters */
1115 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1116 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1117 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1118 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1119 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1120
1121 /* Disable the Channel 1: Reset the CC1E Bit */
1122 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1123
1124 /* Select the Input and set the filter and the prescaler value */
1125 MODIFY_REG(TIMx->CCMR1,
1126 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1127 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1128
1129 /* Select the Polarity and set the CC1E Bit */
1130 MODIFY_REG(TIMx->CCER,
1131 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1132 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1133
1134 return SUCCESS;
1135 }
1136
1137 /**
1138 * @brief Configure the TIMx input channel 2.
1139 * @param TIMx Timer Instance
1140 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1141 * @retval An ErrorStatus enumeration value:
1142 * - SUCCESS: TIMx registers are de-initialized
1143 * - ERROR: not applicable
1144 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1145 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1146 {
1147 /* Check the parameters */
1148 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1149 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1150 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1151 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1152 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1153
1154 /* Disable the Channel 2: Reset the CC2E Bit */
1155 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1156
1157 /* Select the Input and set the filter and the prescaler value */
1158 MODIFY_REG(TIMx->CCMR1,
1159 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1160 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1161
1162 /* Select the Polarity and set the CC2E Bit */
1163 #if defined(TIM_CCER_CC2NP)
1164 MODIFY_REG(TIMx->CCER,
1165 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1166 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1167 #else
1168 MODIFY_REG(TIMx->CCER,
1169 TIM_CCER_CC2P,
1170 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1171 #endif /* TIM_CCER_CC2NP */
1172
1173 return SUCCESS;
1174 }
1175
1176 /**
1177 * @brief Configure the TIMx input channel 3.
1178 * @param TIMx Timer Instance
1179 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1180 * @retval An ErrorStatus enumeration value:
1181 * - SUCCESS: TIMx registers are de-initialized
1182 * - ERROR: not applicable
1183 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1184 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1185 {
1186 /* Check the parameters */
1187 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1188 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1189 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1190 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1191 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1192
1193 /* Disable the Channel 3: Reset the CC3E Bit */
1194 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1195
1196 /* Select the Input and set the filter and the prescaler value */
1197 MODIFY_REG(TIMx->CCMR2,
1198 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1199 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1200
1201 /* Select the Polarity and set the CC3E Bit */
1202 #if defined(TIM_CCER_CC3NP)
1203 MODIFY_REG(TIMx->CCER,
1204 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1205 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1206 #else
1207 MODIFY_REG(TIMx->CCER,
1208 TIM_CCER_CC3P,
1209 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1210 #endif /*TIM_CCER_CC3NP */
1211
1212 return SUCCESS;
1213 }
1214
1215 /**
1216 * @brief Configure the TIMx input channel 4.
1217 * @param TIMx Timer Instance
1218 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1219 * @retval An ErrorStatus enumeration value:
1220 * - SUCCESS: TIMx registers are de-initialized
1221 * - ERROR: not applicable
1222 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1223 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1224 {
1225 /* Check the parameters */
1226 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1227 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1228 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1229 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1230 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1231
1232 /* Disable the Channel 4: Reset the CC4E Bit */
1233 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1234
1235 /* Select the Input and set the filter and the prescaler value */
1236 MODIFY_REG(TIMx->CCMR2,
1237 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1238 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1239
1240 /* Select the Polarity and set the CC4E Bit */
1241 #if defined(TIM_CCER_CC4NP)
1242 MODIFY_REG(TIMx->CCER,
1243 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1244 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1245 #else
1246 MODIFY_REG(TIMx->CCER,
1247 TIM_CCER_CC4P,
1248 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1249 #endif /* TIM_CCER_CC4NP */
1250
1251 return SUCCESS;
1252 }
1253
1254
1255 /**
1256 * @}
1257 */
1258
1259 /**
1260 * @}
1261 */
1262
1263 #endif /* TIM1 || TIM2 || TIM16 || TIM17 */
1264
1265 /**
1266 * @}
1267 */
1268
1269 #endif /* USE_FULL_LL_DRIVER */
1270
