1 /**
2 ******************************************************************************
3 * @file stm32wb0x_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wb0x_ll_spi.h"
22 #include "stm32wb0x_ll_bus.h"
23 #include "stm32wb0x_ll_rcc.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32WB0x_LL_Driver
32 * @{
33 */
34
35 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
36
37 /** @addtogroup SPI_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
46 * @{
47 */
48 /* SPI registers Masks */
49 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
50 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
51 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
52 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
53 SPI_CR1_BIDIMODE)
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
60 * @{
61 */
62 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
63 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
64 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
65 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
66
67 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
68 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
69
70 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
71 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
72 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
73 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
74 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
75 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
76 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
77 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
78 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
79 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
80 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
81 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
82 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
83
84 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
85 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
86
87 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
88 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
89
90 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
91 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
92 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
93
94 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
95 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
96 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
97 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
98 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
99 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
100 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
101 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
102
103 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
104 || ((__VALUE__) == LL_SPI_MSB_FIRST))
105
106 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
107 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
108
109 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
110
111 /**
112 * @}
113 */
114
115 /* Private function prototypes -----------------------------------------------*/
116
117 /* Exported functions --------------------------------------------------------*/
118 /** @addtogroup SPI_LL_Exported_Functions
119 * @{
120 */
121
122 /** @addtogroup SPI_LL_EF_Init
123 * @{
124 */
125
126 /**
127 * @brief De-initialize the SPI registers to their default reset values.
128 * @param SPIx SPI Instance
129 * @retval An ErrorStatus enumeration value:
130 * - SUCCESS: SPI registers are de-initialized
131 * - ERROR: SPI registers are not de-initialized
132 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)133 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
134 {
135 ErrorStatus status = ERROR;
136
137 /* Check the parameters */
138 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
139
140 #if defined(SPI1)
141 if (SPIx == SPI1)
142 {
143 /* Force reset of SPI clock */
144 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI1);
145
146 /* Release reset of SPI clock */
147 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI1);
148
149 status = SUCCESS;
150 }
151 #endif /* SPI1 */
152 #if defined(SPI2)
153 if (SPIx == SPI2)
154 {
155 /* Force reset of SPI clock */
156 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
157
158 /* Release reset of SPI clock */
159 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
160
161 status = SUCCESS;
162 }
163 #endif /* SPI2 */
164 #if defined(SPI3)
165 if (SPIx == SPI3)
166 {
167 /* Force reset of SPI clock */
168 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
169
170 /* Release reset of SPI clock */
171 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
172
173 status = SUCCESS;
174 }
175 #endif /* SPI3 */
176
177 return status;
178 }
179
180 /**
181 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
182 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
183 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
184 * @param SPIx SPI Instance
185 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
186 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
187 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)188 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
189 {
190 ErrorStatus status = ERROR;
191
192 /* Check the SPI Instance SPIx*/
193 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
194
195 /* Check the SPI parameters from SPI_InitStruct*/
196 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
197 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
198 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
199 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
200 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
201 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
202 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
203 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
204 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
205
206 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
207 {
208 /*---------------------------- SPIx CR1 Configuration ------------------------
209 * Configure SPIx CR1 with parameters:
210 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
211 * - Master/Slave Mode: SPI_CR1_MSTR bit
212 * - ClockPolarity: SPI_CR1_CPOL bit
213 * - ClockPhase: SPI_CR1_CPHA bit
214 * - NSS management: SPI_CR1_SSM bit
215 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
216 * - BitOrder: SPI_CR1_LSBFIRST bit
217 * - CRCCalculation: SPI_CR1_CRCEN bit
218 */
219 MODIFY_REG(SPIx->CR1,
220 SPI_CR1_CLEAR_MASK,
221 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
222 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
223 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
224 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
225
226 /*---------------------------- SPIx CR2 Configuration ------------------------
227 * Configure SPIx CR2 with parameters:
228 * - DataWidth: DS[3:0] bits
229 * - NSS management: SSOE bit
230 */
231 MODIFY_REG(SPIx->CR2,
232 SPI_CR2_DS | SPI_CR2_SSOE,
233 SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
234
235 /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
236 if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
237 {
238 LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
239 }
240
241 /*---------------------------- SPIx CRCPR Configuration ----------------------
242 * Configure SPIx CRCPR with parameters:
243 * - CRCPoly: CRCPOLY[15:0] bits
244 */
245 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
246 {
247 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
248 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
249 }
250 status = SUCCESS;
251 }
252
253 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
254 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
255 return status;
256 }
257
258 /**
259 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
260 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
261 * whose fields will be set to default values.
262 * @retval None
263 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)264 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
265 {
266 /* Set SPI_InitStruct fields to default values */
267 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
268 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
269 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
270 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
271 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
272 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
273 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
274 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
275 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
276 SPI_InitStruct->CRCPoly = 7U;
277 }
278
279 /**
280 * @}
281 */
282
283 /**
284 * @}
285 */
286
287 /**
288 * @}
289 */
290
291 /** @addtogroup I2S_LL
292 * @{
293 */
294
295 /* Private types -------------------------------------------------------------*/
296 /* Private variables ---------------------------------------------------------*/
297 /* Private constants ---------------------------------------------------------*/
298 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
299 * @{
300 */
301 /* I2S registers Masks */
302 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
303 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
304 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
305
306 #define I2S_I2SPR_CLEAR_MASK 0x0002U
307 /**
308 * @}
309 */
310 /* Private macros ------------------------------------------------------------*/
311 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
312 * @{
313 */
314
315 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
316 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
317 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
318 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
319
320 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
321 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
322
323 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
324 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
325 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
326 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
327 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
328
329 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
330 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
331 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
332 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
333
334 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
335 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
336
337 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
338 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
339 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
340
341 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
342
343 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
344 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
345 /**
346 * @}
347 */
348
349 /* Private function prototypes -----------------------------------------------*/
350
351 /* Exported functions --------------------------------------------------------*/
352 /** @addtogroup I2S_LL_Exported_Functions
353 * @{
354 */
355
356 /** @addtogroup I2S_LL_EF_Init
357 * @{
358 */
359
360 /**
361 * @brief De-initialize the SPI/I2S registers to their default reset values.
362 * @param SPIx SPI Instance
363 * @retval An ErrorStatus enumeration value:
364 * - SUCCESS: SPI registers are de-initialized
365 * - ERROR: SPI registers are not de-initialized
366 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)367 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
368 {
369 return LL_SPI_DeInit(SPIx);
370 }
371
372 /**
373 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
374 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
375 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
376 * @param SPIx SPI Instance
377 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
378 * @retval An ErrorStatus enumeration value:
379 * - SUCCESS: SPI registers are Initialized
380 * - ERROR: SPI registers are not Initialized
381 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)382 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
383 {
384 uint32_t i2sdiv = 2U;
385 uint32_t i2sodd = 0U;
386 uint32_t packetlength = 1U;
387 uint32_t tmp;
388 uint32_t sourceclock, rcc_clock;
389 ErrorStatus status = ERROR;
390
391 /* Check the I2S parameters */
392 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
393 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
394 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
395 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
396 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
397 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
398 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
399
400 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
401 {
402 /*---------------------------- SPIx I2SCFGR Configuration --------------------
403 * Configure SPIx I2SCFGR with parameters:
404 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
405 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
406 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
407 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
408 */
409
410 /* Write to SPIx I2SCFGR */
411 MODIFY_REG(SPIx->I2SCFGR,
412 I2S_I2SCFGR_CLEAR_MASK,
413 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
414 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
415 SPI_I2SCFGR_I2SMOD);
416
417 /*---------------------------- SPIx I2SPR Configuration ----------------------
418 * Configure SPIx I2SPR with parameters:
419 * - MCLKOutput: SPI_I2SPR_MCKOE bit
420 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
421 */
422
423 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
424 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
425 */
426 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
427 {
428 /* Check the frame length (For the Prescaler computing)
429 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
430 */
431 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
432 {
433 /* Packet length is 32 bits */
434 packetlength = 2U;
435 }
436
437 #if defined(SPI2)
438 if (SPIx == SPI3)
439 {
440 #endif /* SPI2 */
441 /* Retrieve I2S3 Clock Source from RCC */
442 rcc_clock = LL_RCC_GetSPI3I2SClockSource();
443
444 /* Update sourceclock to I2S3 frequency */
445 if (rcc_clock == LL_RCC_SPI3_I2S_CLK16M)
446 {
447 sourceclock = 16000000;
448 }
449 else if (rcc_clock == LL_RCC_SPI3_I2S_CLK32M)
450 {
451 sourceclock = 32000000;
452 }
453 else /* LL_RCC_SPI3_I2S_CLK64M available for WB05 and WB09 */
454 {
455 sourceclock = 64000000;
456 }
457 #if defined(SPI2)
458 }
459 else /* SPI2/I2S2 not available on all devices */
460 {
461 /* Retrieve I2S2 Clock Source from RCC */
462 rcc_clock = LL_RCC_GetSPI2I2SClockSource();
463
464 /* Update sourceclock to I2S2 frequency */
465 if (rcc_clock == LL_RCC_SPI2_I2S_CLK16M)
466 {
467 sourceclock = 16000000;
468 }
469 else
470 {
471 sourceclock = 32000000;
472 }
473 }
474 #endif /* SPI2 */
475
476 /* Compute the Real divider depending on the MCLK output state with a floating point */
477 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
478 {
479 /* MCLK output is enabled */
480 tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
481 }
482 else
483 {
484 /* MCLK output is disabled */
485 tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
486 }
487
488 /* Remove the floating point */
489 tmp = tmp / 10U;
490
491 /* Check the parity of the divider */
492 i2sodd = (tmp & (uint16_t)0x0001U);
493
494 /* Compute the i2sdiv prescaler */
495 i2sdiv = ((tmp - i2sodd) / 2U);
496
497 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
498 i2sodd = (i2sodd << 8U);
499 }
500
501 /* Test if the divider is 1 or 0 or greater than 0xFF */
502 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
503 {
504 /* Set the default values */
505 i2sdiv = 2U;
506 i2sodd = 0U;
507 }
508
509 /* Write to SPIx I2SPR register the computed value */
510 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
511
512 status = SUCCESS;
513 }
514 return status;
515 }
516
517 /**
518 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
519 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
520 * whose fields will be set to default values.
521 * @retval None
522 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)523 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
524 {
525 /*--------------- Reset I2S init structure parameters values -----------------*/
526 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
527 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
528 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
529 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
530 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
531 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
532 }
533
534 /**
535 * @brief Set linear and parity prescaler.
536 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
537 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
538 * @param SPIx SPI Instance
539 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
540 * @param PrescalerParity This parameter can be one of the following values:
541 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
542 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
543 * @retval None
544 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)545 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
546 {
547 /* Check the I2S parameters */
548 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
549 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
550 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
551
552 /* Write to SPIx I2SPR */
553 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
554 }
555
556 /**
557 * @}
558 */
559
560 /**
561 * @}
562 */
563
564 /**
565 * @}
566 */
567
568 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
569
570 /**
571 * @}
572 */
573
574 #endif /* USE_FULL_LL_DRIVER */
575
