1 /**
2 ******************************************************************************
3 * @file stm32wb0x_ll_pwr.c
4 * @author MCD Application Team
5 * @brief PWR LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wb0x_ll_pwr.h"
22 #include "stm32wb0x_ll_bus.h"
23
24 /** @addtogroup STM32WB0x_LL_Driver
25 * @{
26 */
27
28 #if defined(PWR)
29
30 /** @defgroup PWR_LL PWR
31 * @brief PWR LL module driver
32 * @{
33 */
34
35 /* Private types -------------------------------------------------------------*/
36 /* Private variables ---------------------------------------------------------*/
37 /* Private constants ---------------------------------------------------------*/
38
39 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
40 * @{
41 */
42 /* Definitions of PWR registers reset value */
43 #if defined(STM32WB06) || defined(STM32WB07)
44 #define PWR_CR1_RESET_VALUE (0x00000010)
45 #define PWR_CR2_RESET_VALUE (0x00000100)
46 #define PWR_CR5_RESET_VALUE (0x00000014)
47 #define PWR_PUCRA_RESET_VALUE (0x0000FFF7)
48 #define PWR_PUCRB_RESET_VALUE (0x0000FFFF)
49 #define PWR_IOxCFG_RESET_VALUE (0x00000000)
50 #else
51 #define PWR_CR1_RESET_VALUE (0x00000114)
52 #define PWR_CR2_RESET_VALUE (0x00000000)
53 #define PWR_CR5_RESET_VALUE (0x00006014)
54 #define PWR_PUCRA_RESET_VALUE (0x00000F07)
55 #define PWR_PUCRB_RESET_VALUE (0x0000F0FF)
56 #endif /* STM32WB06 || STM32WB07*/
57 #define PWR_CR3_RESET_VALUE (0x00000000)
58 #define PWR_CR4_RESET_VALUE (0x00000000)
59 #define PWR_CR6_RESET_VALUE (0x00000000)
60 #define PWR_CR7_RESET_VALUE (0x00000000)
61 #define PWR_PDCRA_RESET_VALUE (0x00000008)
62 #define PWR_PDCRB_RESET_VALUE (0x00000000)
63 #define PWR_ENGTRIM_RESET_VALUE (0x00000000)
64 #define PWR_EWUA_RESET_VALUE (0x00000000)
65 #define PWR_EWUB_RESET_VALUE (0x00000000)
66 #define PWR_IEWU_RESET_VALUE (0x00000000)
67 /**
68 * @}
69 */
70
71 /* Private macros ------------------------------------------------------------*/
72 /* Private function prototypes -----------------------------------------------*/
73
74 /* Exported functions --------------------------------------------------------*/
75 /** @addtogroup PWR_LL_Exported_Functions
76 * @{
77 */
78
79 /** @addtogroup PWR_LL_EF_Init
80 * @{
81 */
82
83 /**
84 * @brief De-initialize the PWR registers to their default reset values.
85 * @retval An ErrorStatus enumeration value:
86 * - SUCCESS: PWR registers are de-initialized
87 * - ERROR: not applicable
88 */
LL_PWR_DeInit(void)89 ErrorStatus LL_PWR_DeInit(void)
90 {
91 /* Apply reset values to all PWR registers */
92 LL_PWR_WriteReg(CR1, PWR_CR1_RESET_VALUE);
93 LL_PWR_WriteReg(CR2, PWR_CR2_RESET_VALUE);
94 LL_PWR_WriteReg(CR3, PWR_CR3_RESET_VALUE);
95 LL_PWR_WriteReg(CR4, PWR_CR4_RESET_VALUE);
96 LL_PWR_WriteReg(CR5, PWR_CR5_RESET_VALUE);
97 LL_PWR_WriteReg(PUCRA, PWR_PUCRA_RESET_VALUE);
98 LL_PWR_WriteReg(PDCRA, PWR_PDCRA_RESET_VALUE);
99 LL_PWR_WriteReg(PUCRB, PWR_PUCRB_RESET_VALUE);
100 LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE);
101 LL_PWR_WriteReg(CR6, PWR_CR6_RESET_VALUE);
102 LL_PWR_WriteReg(CR7, PWR_CR7_RESET_VALUE);
103 #if defined(STM32WB06) || defined(STM32WB07)
104 LL_PWR_WriteReg(IOxCFG, PWR_IOxCFG_RESET_VALUE);
105 #endif /* STM32WB06 || STM32WB07 */
106 LL_PWR_WriteReg(ENGTRIM, PWR_ENGTRIM_RESET_VALUE);
107
108 /* Clear all flags */
109 LL_PWR_WriteReg(SR1,
110 LL_PWR_SR1_WUF0
111 | LL_PWR_SR1_WUF1
112 | LL_PWR_SR1_WUF2
113 | LL_PWR_SR1_WUF3
114 | LL_PWR_SR1_WUF4
115 | LL_PWR_SR1_WUF5
116 | LL_PWR_SR1_WUF6
117 | LL_PWR_SR1_WUF7
118 | LL_PWR_SR1_WUF8
119 | LL_PWR_SR1_WUF9
120 | LL_PWR_SR1_WUF10
121 | LL_PWR_SR1_WUF11
122 #if defined(PWR_CR3_EIWL2)
123 | LL_PWR_SR1_WUFI2
124 #endif /* PWR_CR3_EIWL2 */
125 );
126 LL_PWR_WriteReg(SR3,
127 (LL_PWR_SR3_WUF12 >> 16)
128 | (LL_PWR_SR3_WUF13 >> 16)
129 | (LL_PWR_SR3_WUF14 >> 16)
130 | (LL_PWR_SR3_WUF15 >> 16)
131 | (LL_PWR_SR3_WUF16 >> 16)
132 | (LL_PWR_SR3_WUF17 >> 16)
133 | (LL_PWR_SR3_WUF18 >> 16)
134 | (LL_PWR_SR3_WUF19 >> 16)
135 #if defined(PWR_CR6_EWU20)
136 | (LL_PWR_SR3_WUF20 >> 16)
137 #endif /* PWR_CR6_EWU20 */
138 #if defined(PWR_CR6_EWU21)
139 | (LL_PWR_SR3_WUF21 >> 16)
140 #endif /* PWR_CR6_EWU21 */
141 #if defined(PWR_CR6_EWU22)
142 | (LL_PWR_SR3_WUF22 >> 16)
143 #endif /* PWR_CR6_EWU22 */
144 #if defined(PWR_CR6_EWU23)
145 | (LL_PWR_SR3_WUF23 >> 16)
146 #endif /* PWR_CR6_EWU23 */
147 #if defined(PWR_CR6_EWU24)
148 | (LL_PWR_SR3_WUF24 >> 16)
149 #endif /* PWR_CR6_EWU24 */
150 #if defined(PWR_CR6_EWU25)
151 | (LL_PWR_SR3_WUF25 >> 16)
152 #endif /* PWR_CR6_EWU25 */
153 #if defined(PWR_CR6_EWU26)
154 | (LL_PWR_SR3_WUF26 >> 16)
155 #endif /* PWR_CR6_EWU26 */
156 #if defined(PWR_CR6_EWU27)
157 | (LL_PWR_SR3_WUF27 >> 16)
158 #endif /* PWR_CR6_EWU27 */
159 );
160
161 LL_PWR_WriteReg(EXTSRR,
162 LL_PWR_EXTSRR_RFPHASEF
163 | LL_PWR_EXTSRR_DEEPSTOPF
164 );
165 return SUCCESS;
166 }
167
168 /**
169 * @}
170 */
171
172 /**
173 * @}
174 */
175
176 /**
177 * @}
178 */
179 #endif /* PWR */
180 /**
181 * @}
182 */
183
184 #endif /* USE_FULL_LL_DRIVER */
185
