1 /**
2 ******************************************************************************
3 * @file stm32wb0x_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2024 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
88 Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
142 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
143 (+) TriggerCallback : TIM Trigger Callback.
144 (+) IC_CaptureCallback : TIM Input Capture Callback.
145 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
146 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
147 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
148 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
149 (+) ErrorCallback : TIM Error Callback.
150 (+) CommutationCallback : TIM Commutation Callback.
151 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
152 (+) BreakCallback : TIM Break Callback.
153 (+) Break2Callback : TIM Break2 Callback (when supported).
154
155 [..]
156 By default, after the Init and when the state is HAL_TIM_STATE_RESET
157 all interrupt callbacks are set to the corresponding weak functions:
158 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
159
160 [..]
161 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
162 functionalities in the Init / DeInit only when these callbacks are null
163 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
164 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
165
166 [..]
167 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
168 Exception done MspInit / MspDeInit that can be registered / unregistered
169 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
170 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
171 In that case first register the MspInit/MspDeInit user callbacks
172 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
173
174 [..]
175 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
176 not defined, the callback registration feature is not available and all callbacks
177 are set to the corresponding weak functions.
178
179 @endverbatim
180 ******************************************************************************
181 */
182
183 /* Includes ------------------------------------------------------------------*/
184 #include "stm32wb0x_hal.h"
185
186 /** @addtogroup STM32WB0x_HAL_Driver
187 * @{
188 */
189
190 /** @defgroup TIM TIM
191 * @brief TIM HAL module driver
192 * @{
193 */
194
195 #ifdef HAL_TIM_MODULE_ENABLED
196
197 /* Private typedef -----------------------------------------------------------*/
198 /* Private define ------------------------------------------------------------*/
199 /* Private macros ------------------------------------------------------------*/
200 /* Private variables ---------------------------------------------------------*/
201 /* Private function prototypes -----------------------------------------------*/
202 /** @addtogroup TIM_Private_Functions
203 * @{
204 */
205 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
206 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
207 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
208 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
209 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
210 #if defined(TIM_CCER_CC5E)
211 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
212 #endif /* TIM_CCER_CC5E */
213 #if defined(TIM_CCER_CC6E)
214 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
215 #endif /* TIM_CCER_CC6E */
216 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
217 uint32_t TIM_ICFilter);
218 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
219 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
220 uint32_t TIM_ICFilter);
221 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
222 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
223 uint32_t TIM_ICFilter);
224 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
225 uint32_t TIM_ICFilter);
226 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
227 static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
228 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
229 #if defined(TIM_DMA_SUPPORT)
230 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
231 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
232 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
233 #endif /* TIM_DMA_SUPPORT */
234 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
235 const TIM_SlaveConfigTypeDef *sSlaveConfig);
236 /**
237 * @}
238 */
239 /* Exported functions --------------------------------------------------------*/
240
241 /** @defgroup TIM_Exported_Functions TIM Exported Functions
242 * @{
243 */
244
245 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
246 * @brief Time Base functions
247 *
248 @verbatim
249 ==============================================================================
250 ##### Time Base functions #####
251 ==============================================================================
252 [..]
253 This section provides functions allowing to:
254 (+) Initialize and configure the TIM base.
255 (+) De-initialize the TIM base.
256 (+) Start the Time Base.
257 (+) Stop the Time Base.
258 (+) Start the Time Base and enable interrupt.
259 (+) Stop the Time Base and disable interrupt.
260 (+) Start the Time Base and enable DMA transfer.
261 (+) Stop the Time Base and disable DMA transfer.
262
263 @endverbatim
264 * @{
265 */
266 /**
267 * @brief Initializes the TIM Time base Unit according to the specified
268 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
269 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
270 * requires a timer reset to avoid unexpected direction
271 * due to DIR bit readonly in center aligned mode.
272 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
273 * @param htim TIM Base handle
274 * @retval HAL status
275 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)276 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
277 {
278 /* Check the TIM handle allocation */
279 if (htim == NULL)
280 {
281 return HAL_ERROR;
282 }
283
284 /* Check the parameters */
285 assert_param(IS_TIM_INSTANCE(htim->Instance));
286 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
287 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
288 assert_param(IS_TIM_PERIOD(htim->Init.Period));
289 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
290
291 if (htim->State == HAL_TIM_STATE_RESET)
292 {
293 /* Allocate lock resource and initialize it */
294 htim->Lock = HAL_UNLOCKED;
295
296 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
297 /* Reset interrupt callbacks to legacy weak callbacks */
298 TIM_ResetCallback(htim);
299
300 if (htim->Base_MspInitCallback == NULL)
301 {
302 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
303 }
304 /* Init the low level hardware : GPIO, CLOCK, NVIC */
305 htim->Base_MspInitCallback(htim);
306 #else
307 /* Init the low level hardware : GPIO, CLOCK, NVIC */
308 HAL_TIM_Base_MspInit(htim);
309 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
310 }
311
312 /* Set the TIM state */
313 htim->State = HAL_TIM_STATE_BUSY;
314
315 /* Set the Time Base configuration */
316 TIM_Base_SetConfig(htim->Instance, &htim->Init);
317
318 #if defined(TIM_DMA_SUPPORT)
319 /* Initialize the DMA burst operation state */
320 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
321 #endif /* TIM_DMA_SUPPORT */
322
323 /* Initialize the TIM channels state */
324 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
325 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
326
327 /* Initialize the TIM state*/
328 htim->State = HAL_TIM_STATE_READY;
329
330 return HAL_OK;
331 }
332
333 /**
334 * @brief DeInitializes the TIM Base peripheral
335 * @param htim TIM Base handle
336 * @retval HAL status
337 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)338 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
339 {
340 /* Check the parameters */
341 assert_param(IS_TIM_INSTANCE(htim->Instance));
342
343 htim->State = HAL_TIM_STATE_BUSY;
344
345 /* Disable the TIM Peripheral Clock */
346 __HAL_TIM_DISABLE(htim);
347
348 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
349 if (htim->Base_MspDeInitCallback == NULL)
350 {
351 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
352 }
353 /* DeInit the low level hardware */
354 htim->Base_MspDeInitCallback(htim);
355 #else
356 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
357 HAL_TIM_Base_MspDeInit(htim);
358 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
359
360 #if defined(TIM_DMA_SUPPORT)
361 /* Change the DMA burst operation state */
362 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
363 #endif /* TIM_DMA_SUPPORT */
364
365 /* Change the TIM channels state */
366 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
367 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
368
369 /* Change TIM state */
370 htim->State = HAL_TIM_STATE_RESET;
371
372 /* Release Lock */
373 __HAL_UNLOCK(htim);
374
375 return HAL_OK;
376 }
377
378 /**
379 * @brief Initializes the TIM Base MSP.
380 * @param htim TIM Base handle
381 * @retval None
382 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)383 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
384 {
385 /* Prevent unused argument(s) compilation warning */
386 UNUSED(htim);
387
388 /* NOTE : This function should not be modified, when the callback is needed,
389 the HAL_TIM_Base_MspInit could be implemented in the user file
390 */
391 }
392
393 /**
394 * @brief DeInitializes TIM Base MSP.
395 * @param htim TIM Base handle
396 * @retval None
397 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)398 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
399 {
400 /* Prevent unused argument(s) compilation warning */
401 UNUSED(htim);
402
403 /* NOTE : This function should not be modified, when the callback is needed,
404 the HAL_TIM_Base_MspDeInit could be implemented in the user file
405 */
406 }
407
408
409 /**
410 * @brief Starts the TIM Base generation.
411 * @param htim TIM Base handle
412 * @retval HAL status
413 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)414 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
415 {
416 uint32_t tmpsmcr;
417
418 /* Check the parameters */
419 assert_param(IS_TIM_INSTANCE(htim->Instance));
420
421 /* Check the TIM state */
422 if (htim->State != HAL_TIM_STATE_READY)
423 {
424 return HAL_ERROR;
425 }
426
427 /* Set the TIM state */
428 htim->State = HAL_TIM_STATE_BUSY;
429
430 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
431 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
432 {
433 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
434 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
435 {
436 __HAL_TIM_ENABLE(htim);
437 }
438 }
439 else
440 {
441 __HAL_TIM_ENABLE(htim);
442 }
443
444 /* Return function status */
445 return HAL_OK;
446 }
447
448 /**
449 * @brief Stops the TIM Base generation.
450 * @param htim TIM Base handle
451 * @retval HAL status
452 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)453 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
454 {
455 /* Check the parameters */
456 assert_param(IS_TIM_INSTANCE(htim->Instance));
457
458 /* Disable the Peripheral */
459 __HAL_TIM_DISABLE(htim);
460
461 /* Set the TIM state */
462 htim->State = HAL_TIM_STATE_READY;
463
464 /* Return function status */
465 return HAL_OK;
466 }
467
468 /**
469 * @brief Starts the TIM Base generation in interrupt mode.
470 * @param htim TIM Base handle
471 * @retval HAL status
472 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)473 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
474 {
475 uint32_t tmpsmcr;
476
477 /* Check the parameters */
478 assert_param(IS_TIM_INSTANCE(htim->Instance));
479
480 /* Check the TIM state */
481 if (htim->State != HAL_TIM_STATE_READY)
482 {
483 return HAL_ERROR;
484 }
485
486 /* Set the TIM state */
487 htim->State = HAL_TIM_STATE_BUSY;
488
489 /* Enable the TIM Update interrupt */
490 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
491
492 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
493 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
494 {
495 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
496 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
497 {
498 __HAL_TIM_ENABLE(htim);
499 }
500 }
501 else
502 {
503 __HAL_TIM_ENABLE(htim);
504 }
505
506 /* Return function status */
507 return HAL_OK;
508 }
509
510 /**
511 * @brief Stops the TIM Base generation in interrupt mode.
512 * @param htim TIM Base handle
513 * @retval HAL status
514 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)515 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
516 {
517 /* Check the parameters */
518 assert_param(IS_TIM_INSTANCE(htim->Instance));
519
520 /* Disable the TIM Update interrupt */
521 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
522
523 /* Disable the Peripheral */
524 __HAL_TIM_DISABLE(htim);
525
526 /* Set the TIM state */
527 htim->State = HAL_TIM_STATE_READY;
528
529 /* Return function status */
530 return HAL_OK;
531 }
532
533 #if defined(TIM_DMA_SUPPORT)
534 /**
535 * @brief Starts the TIM Base generation in DMA mode.
536 * @param htim TIM Base handle
537 * @param pData The source Buffer address.
538 * @param Length The length of data to be transferred from memory to peripheral.
539 * @retval HAL status
540 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)541 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
542 {
543 uint32_t tmpsmcr;
544
545 /* Check the parameters */
546 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
547
548 /* Set the TIM state */
549 if (htim->State == HAL_TIM_STATE_BUSY)
550 {
551 return HAL_BUSY;
552 }
553 else if (htim->State == HAL_TIM_STATE_READY)
554 {
555 if ((pData == NULL) || (Length == 0U))
556 {
557 return HAL_ERROR;
558 }
559 else
560 {
561 htim->State = HAL_TIM_STATE_BUSY;
562 }
563 }
564 else
565 {
566 return HAL_ERROR;
567 }
568
569 /* Set the DMA Period elapsed callbacks */
570 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
571 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
572
573 /* Set the DMA error callback */
574 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
575
576 /* Enable the DMA channel */
577 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
578 Length) != HAL_OK)
579 {
580 /* Return error status */
581 return HAL_ERROR;
582 }
583
584 /* Enable the TIM Update DMA request */
585 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
586
587 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
588 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
589 {
590 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
591 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
592 {
593 __HAL_TIM_ENABLE(htim);
594 }
595 }
596 else
597 {
598 __HAL_TIM_ENABLE(htim);
599 }
600
601 /* Return function status */
602 return HAL_OK;
603 }
604
605 /**
606 * @brief Stops the TIM Base generation in DMA mode.
607 * @param htim TIM Base handle
608 * @retval HAL status
609 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)610 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
611 {
612 /* Check the parameters */
613 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
614
615 /* Disable the TIM Update DMA request */
616 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
617
618 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
619
620 /* Disable the Peripheral */
621 __HAL_TIM_DISABLE(htim);
622
623 /* Set the TIM state */
624 htim->State = HAL_TIM_STATE_READY;
625
626 /* Return function status */
627 return HAL_OK;
628 }
629 #endif /* TIM_DMA_SUPPORT */
630
631 /**
632 * @}
633 */
634
635 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
636 * @brief TIM Output Compare functions
637 *
638 @verbatim
639 ==============================================================================
640 ##### TIM Output Compare functions #####
641 ==============================================================================
642 [..]
643 This section provides functions allowing to:
644 (+) Initialize and configure the TIM Output Compare.
645 (+) De-initialize the TIM Output Compare.
646 (+) Start the TIM Output Compare.
647 (+) Stop the TIM Output Compare.
648 (+) Start the TIM Output Compare and enable interrupt.
649 (+) Stop the TIM Output Compare and disable interrupt.
650 (+) Start the TIM Output Compare and enable DMA transfer.
651 (+) Stop the TIM Output Compare and disable DMA transfer.
652
653 @endverbatim
654 * @{
655 */
656 /**
657 * @brief Initializes the TIM Output Compare according to the specified
658 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
659 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
660 * requires a timer reset to avoid unexpected direction
661 * due to DIR bit readonly in center aligned mode.
662 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
663 * @param htim TIM Output Compare handle
664 * @retval HAL status
665 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)666 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
667 {
668 /* Check the TIM handle allocation */
669 if (htim == NULL)
670 {
671 return HAL_ERROR;
672 }
673
674 /* Check the parameters */
675 assert_param(IS_TIM_INSTANCE(htim->Instance));
676 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
677 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
678 assert_param(IS_TIM_PERIOD(htim->Init.Period));
679 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
680
681 if (htim->State == HAL_TIM_STATE_RESET)
682 {
683 /* Allocate lock resource and initialize it */
684 htim->Lock = HAL_UNLOCKED;
685
686 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
687 /* Reset interrupt callbacks to legacy weak callbacks */
688 TIM_ResetCallback(htim);
689
690 if (htim->OC_MspInitCallback == NULL)
691 {
692 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
693 }
694 /* Init the low level hardware : GPIO, CLOCK, NVIC */
695 htim->OC_MspInitCallback(htim);
696 #else
697 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
698 HAL_TIM_OC_MspInit(htim);
699 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
700 }
701
702 /* Set the TIM state */
703 htim->State = HAL_TIM_STATE_BUSY;
704
705 /* Init the base time for the Output Compare */
706 TIM_Base_SetConfig(htim->Instance, &htim->Init);
707
708 #if defined(TIM_DMA_SUPPORT)
709 /* Initialize the DMA burst operation state */
710 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
711 #endif /* TIM_DMA_SUPPORT */
712
713 /* Initialize the TIM channels state */
714 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
715 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
716
717 /* Initialize the TIM state*/
718 htim->State = HAL_TIM_STATE_READY;
719
720 return HAL_OK;
721 }
722
723 /**
724 * @brief DeInitializes the TIM peripheral
725 * @param htim TIM Output Compare handle
726 * @retval HAL status
727 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)728 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
729 {
730 /* Check the parameters */
731 assert_param(IS_TIM_INSTANCE(htim->Instance));
732
733 htim->State = HAL_TIM_STATE_BUSY;
734
735 /* Disable the TIM Peripheral Clock */
736 __HAL_TIM_DISABLE(htim);
737
738 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
739 if (htim->OC_MspDeInitCallback == NULL)
740 {
741 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
742 }
743 /* DeInit the low level hardware */
744 htim->OC_MspDeInitCallback(htim);
745 #else
746 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
747 HAL_TIM_OC_MspDeInit(htim);
748 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
749
750 #if defined(TIM_DMA_SUPPORT)
751 /* Change the DMA burst operation state */
752 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
753 #endif /* TIM_DMA_SUPPORT */
754
755 /* Change the TIM channels state */
756 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
757 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
758
759 /* Change TIM state */
760 htim->State = HAL_TIM_STATE_RESET;
761
762 /* Release Lock */
763 __HAL_UNLOCK(htim);
764
765 return HAL_OK;
766 }
767
768 /**
769 * @brief Initializes the TIM Output Compare MSP.
770 * @param htim TIM Output Compare handle
771 * @retval None
772 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)773 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
774 {
775 /* Prevent unused argument(s) compilation warning */
776 UNUSED(htim);
777
778 /* NOTE : This function should not be modified, when the callback is needed,
779 the HAL_TIM_OC_MspInit could be implemented in the user file
780 */
781 }
782
783 /**
784 * @brief DeInitializes TIM Output Compare MSP.
785 * @param htim TIM Output Compare handle
786 * @retval None
787 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)788 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
789 {
790 /* Prevent unused argument(s) compilation warning */
791 UNUSED(htim);
792
793 /* NOTE : This function should not be modified, when the callback is needed,
794 the HAL_TIM_OC_MspDeInit could be implemented in the user file
795 */
796 }
797
798 /**
799 * @brief Starts the TIM Output Compare signal generation.
800 * @param htim TIM Output Compare handle
801 * @param Channel TIM Channel to be enabled
802 * This parameter can be one of the following values:
803 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
804 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
805 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
806 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
807 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
808 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
809 * (*) Value not defined for all devices
810 * @retval HAL status
811 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)812 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
813 {
814 uint32_t tmpsmcr;
815
816 /* Check the parameters */
817 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
818
819 /* Check the TIM channel state */
820 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
821 {
822 return HAL_ERROR;
823 }
824
825 /* Set the TIM channel state */
826 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
827
828 /* Enable the Output compare channel */
829 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
830
831 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
832 {
833 /* Enable the main output */
834 __HAL_TIM_MOE_ENABLE(htim);
835 }
836
837 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
838 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
839 {
840 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
841 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
842 {
843 __HAL_TIM_ENABLE(htim);
844 }
845 }
846 else
847 {
848 __HAL_TIM_ENABLE(htim);
849 }
850
851 /* Return function status */
852 return HAL_OK;
853 }
854
855 /**
856 * @brief Stops the TIM Output Compare signal generation.
857 * @param htim TIM Output Compare handle
858 * @param Channel TIM Channel to be disabled
859 * This parameter can be one of the following values:
860 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
861 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
862 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
863 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
864 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
865 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
866 * (*) Value not defined for all devices
867 * @retval HAL status
868 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)869 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
870 {
871 /* Check the parameters */
872 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
873
874 /* Disable the Output compare channel */
875 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
876
877 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
878 {
879 /* Disable the Main Output */
880 __HAL_TIM_MOE_DISABLE(htim);
881 }
882
883 /* Disable the Peripheral */
884 __HAL_TIM_DISABLE(htim);
885
886 /* Set the TIM channel state */
887 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
888
889 /* Return function status */
890 return HAL_OK;
891 }
892
893 /**
894 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
895 * @param htim TIM Output Compare handle
896 * @param Channel TIM Channel to be enabled
897 * This parameter can be one of the following values:
898 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
899 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
900 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
901 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
902 * @retval HAL status
903 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)904 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
905 {
906 HAL_StatusTypeDef status = HAL_OK;
907 uint32_t tmpsmcr;
908
909 /* Check the parameters */
910 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
911
912 /* Check the TIM channel state */
913 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
914 {
915 return HAL_ERROR;
916 }
917
918 /* Set the TIM channel state */
919 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
920
921 switch (Channel)
922 {
923 case TIM_CHANNEL_1:
924 {
925 /* Enable the TIM Capture/Compare 1 interrupt */
926 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
927 break;
928 }
929
930 case TIM_CHANNEL_2:
931 {
932 /* Enable the TIM Capture/Compare 2 interrupt */
933 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
934 break;
935 }
936
937 case TIM_CHANNEL_3:
938 {
939 /* Enable the TIM Capture/Compare 3 interrupt */
940 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
941 break;
942 }
943
944 case TIM_CHANNEL_4:
945 {
946 /* Enable the TIM Capture/Compare 4 interrupt */
947 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
948 break;
949 }
950
951 default:
952 status = HAL_ERROR;
953 break;
954 }
955
956 if (status == HAL_OK)
957 {
958 /* Enable the Output compare channel */
959 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
960
961 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
962 {
963 /* Enable the main output */
964 __HAL_TIM_MOE_ENABLE(htim);
965 }
966
967 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
968 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
969 {
970 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
971 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
972 {
973 __HAL_TIM_ENABLE(htim);
974 }
975 }
976 else
977 {
978 __HAL_TIM_ENABLE(htim);
979 }
980 }
981
982 /* Return function status */
983 return status;
984 }
985
986 /**
987 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
988 * @param htim TIM Output Compare handle
989 * @param Channel TIM Channel to be disabled
990 * This parameter can be one of the following values:
991 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
992 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
993 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
994 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
995 * @retval HAL status
996 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)997 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
998 {
999 HAL_StatusTypeDef status = HAL_OK;
1000
1001 /* Check the parameters */
1002 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1003
1004 switch (Channel)
1005 {
1006 case TIM_CHANNEL_1:
1007 {
1008 /* Disable the TIM Capture/Compare 1 interrupt */
1009 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1010 break;
1011 }
1012
1013 case TIM_CHANNEL_2:
1014 {
1015 /* Disable the TIM Capture/Compare 2 interrupt */
1016 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1017 break;
1018 }
1019
1020 case TIM_CHANNEL_3:
1021 {
1022 /* Disable the TIM Capture/Compare 3 interrupt */
1023 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1024 break;
1025 }
1026
1027 case TIM_CHANNEL_4:
1028 {
1029 /* Disable the TIM Capture/Compare 4 interrupt */
1030 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1031 break;
1032 }
1033
1034 default:
1035 status = HAL_ERROR;
1036 break;
1037 }
1038
1039 if (status == HAL_OK)
1040 {
1041 /* Disable the Output compare channel */
1042 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1043
1044 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1045 {
1046 /* Disable the Main Output */
1047 __HAL_TIM_MOE_DISABLE(htim);
1048 }
1049
1050 /* Disable the Peripheral */
1051 __HAL_TIM_DISABLE(htim);
1052
1053 /* Set the TIM channel state */
1054 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1055 }
1056
1057 /* Return function status */
1058 return status;
1059 }
1060
1061 #if defined(TIM_DMA_SUPPORT)
1062 /**
1063 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1064 * @param htim TIM Output Compare handle
1065 * @param Channel TIM Channel to be enabled
1066 * This parameter can be one of the following values:
1067 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1068 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1069 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1070 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1071 * @param pData The source Buffer address.
1072 * @param Length The length of data to be transferred from memory to TIM peripheral
1073 * @retval HAL status
1074 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1075 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1076 uint16_t Length)
1077 {
1078 HAL_StatusTypeDef status = HAL_OK;
1079 uint32_t tmpsmcr;
1080
1081 /* Check the parameters */
1082 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1083
1084 /* Set the TIM channel state */
1085 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1086 {
1087 return HAL_BUSY;
1088 }
1089 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1090 {
1091 if ((pData == NULL) || (Length == 0U))
1092 {
1093 return HAL_ERROR;
1094 }
1095 else
1096 {
1097 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1098 }
1099 }
1100 else
1101 {
1102 return HAL_ERROR;
1103 }
1104
1105 switch (Channel)
1106 {
1107 case TIM_CHANNEL_1:
1108 {
1109 /* Set the DMA compare callbacks */
1110 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1111 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1112
1113 /* Set the DMA error callback */
1114 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1115
1116 /* Enable the DMA channel */
1117 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1118 Length) != HAL_OK)
1119 {
1120 /* Return error status */
1121 return HAL_ERROR;
1122 }
1123
1124 /* Enable the TIM Capture/Compare 1 DMA request */
1125 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1126 break;
1127 }
1128
1129 case TIM_CHANNEL_2:
1130 {
1131 /* Set the DMA compare callbacks */
1132 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1133 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1134
1135 /* Set the DMA error callback */
1136 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1137
1138 /* Enable the DMA channel */
1139 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1140 Length) != HAL_OK)
1141 {
1142 /* Return error status */
1143 return HAL_ERROR;
1144 }
1145
1146 /* Enable the TIM Capture/Compare 2 DMA request */
1147 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1148 break;
1149 }
1150
1151 case TIM_CHANNEL_3:
1152 {
1153 /* Set the DMA compare callbacks */
1154 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1155 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1156
1157 /* Set the DMA error callback */
1158 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1159
1160 /* Enable the DMA channel */
1161 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1162 Length) != HAL_OK)
1163 {
1164 /* Return error status */
1165 return HAL_ERROR;
1166 }
1167 /* Enable the TIM Capture/Compare 3 DMA request */
1168 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1169 break;
1170 }
1171
1172 case TIM_CHANNEL_4:
1173 {
1174 /* Set the DMA compare callbacks */
1175 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1176 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1177
1178 /* Set the DMA error callback */
1179 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1180
1181 /* Enable the DMA channel */
1182 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1183 Length) != HAL_OK)
1184 {
1185 /* Return error status */
1186 return HAL_ERROR;
1187 }
1188 /* Enable the TIM Capture/Compare 4 DMA request */
1189 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1190 break;
1191 }
1192
1193 default:
1194 status = HAL_ERROR;
1195 break;
1196 }
1197
1198 if (status == HAL_OK)
1199 {
1200 /* Enable the Output compare channel */
1201 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1202
1203 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1204 {
1205 /* Enable the main output */
1206 __HAL_TIM_MOE_ENABLE(htim);
1207 }
1208
1209 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1210 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1211 {
1212 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1213 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1214 {
1215 __HAL_TIM_ENABLE(htim);
1216 }
1217 }
1218 else
1219 {
1220 __HAL_TIM_ENABLE(htim);
1221 }
1222 }
1223
1224 /* Return function status */
1225 return status;
1226 }
1227
1228 /**
1229 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1230 * @param htim TIM Output Compare handle
1231 * @param Channel TIM Channel to be disabled
1232 * This parameter can be one of the following values:
1233 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1234 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1235 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1236 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1237 * @retval HAL status
1238 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1239 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1240 {
1241 HAL_StatusTypeDef status = HAL_OK;
1242
1243 /* Check the parameters */
1244 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1245
1246 switch (Channel)
1247 {
1248 case TIM_CHANNEL_1:
1249 {
1250 /* Disable the TIM Capture/Compare 1 DMA request */
1251 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1252 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1253 break;
1254 }
1255
1256 case TIM_CHANNEL_2:
1257 {
1258 /* Disable the TIM Capture/Compare 2 DMA request */
1259 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1260 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1261 break;
1262 }
1263
1264 case TIM_CHANNEL_3:
1265 {
1266 /* Disable the TIM Capture/Compare 3 DMA request */
1267 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1268 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1269 break;
1270 }
1271
1272 case TIM_CHANNEL_4:
1273 {
1274 /* Disable the TIM Capture/Compare 4 interrupt */
1275 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1276 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1277 break;
1278 }
1279
1280 default:
1281 status = HAL_ERROR;
1282 break;
1283 }
1284
1285 if (status == HAL_OK)
1286 {
1287 /* Disable the Output compare channel */
1288 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1289
1290 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1291 {
1292 /* Disable the Main Output */
1293 __HAL_TIM_MOE_DISABLE(htim);
1294 }
1295
1296 /* Disable the Peripheral */
1297 __HAL_TIM_DISABLE(htim);
1298
1299 /* Set the TIM channel state */
1300 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1301 }
1302
1303 /* Return function status */
1304 return status;
1305 }
1306 #endif /* TIM_DMA_SUPPORT */
1307
1308 /**
1309 * @}
1310 */
1311
1312 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1313 * @brief TIM PWM functions
1314 *
1315 @verbatim
1316 ==============================================================================
1317 ##### TIM PWM functions #####
1318 ==============================================================================
1319 [..]
1320 This section provides functions allowing to:
1321 (+) Initialize and configure the TIM PWM.
1322 (+) De-initialize the TIM PWM.
1323 (+) Start the TIM PWM.
1324 (+) Stop the TIM PWM.
1325 (+) Start the TIM PWM and enable interrupt.
1326 (+) Stop the TIM PWM and disable interrupt.
1327 (+) Start the TIM PWM and enable DMA transfer.
1328 (+) Stop the TIM PWM and disable DMA transfer.
1329
1330 @endverbatim
1331 * @{
1332 */
1333 /**
1334 * @brief Initializes the TIM PWM Time Base according to the specified
1335 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1336 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1337 * requires a timer reset to avoid unexpected direction
1338 * due to DIR bit readonly in center aligned mode.
1339 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1340 * @param htim TIM PWM handle
1341 * @retval HAL status
1342 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1343 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1344 {
1345 /* Check the TIM handle allocation */
1346 if (htim == NULL)
1347 {
1348 return HAL_ERROR;
1349 }
1350
1351 /* Check the parameters */
1352 assert_param(IS_TIM_INSTANCE(htim->Instance));
1353 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1354 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1355 assert_param(IS_TIM_PERIOD(htim->Init.Period));
1356 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1357
1358 if (htim->State == HAL_TIM_STATE_RESET)
1359 {
1360 /* Allocate lock resource and initialize it */
1361 htim->Lock = HAL_UNLOCKED;
1362
1363 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1364 /* Reset interrupt callbacks to legacy weak callbacks */
1365 TIM_ResetCallback(htim);
1366
1367 if (htim->PWM_MspInitCallback == NULL)
1368 {
1369 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1370 }
1371 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1372 htim->PWM_MspInitCallback(htim);
1373 #else
1374 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1375 HAL_TIM_PWM_MspInit(htim);
1376 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1377 }
1378
1379 /* Set the TIM state */
1380 htim->State = HAL_TIM_STATE_BUSY;
1381
1382 /* Init the base time for the PWM */
1383 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1384
1385 #if defined(TIM_DMA_SUPPORT)
1386 /* Initialize the DMA burst operation state */
1387 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1388 #endif /* TIM_DMA_SUPPORT */
1389
1390 /* Initialize the TIM channels state */
1391 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1392 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1393
1394 /* Initialize the TIM state*/
1395 htim->State = HAL_TIM_STATE_READY;
1396
1397 return HAL_OK;
1398 }
1399
1400 /**
1401 * @brief DeInitializes the TIM peripheral
1402 * @param htim TIM PWM handle
1403 * @retval HAL status
1404 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1405 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1406 {
1407 /* Check the parameters */
1408 assert_param(IS_TIM_INSTANCE(htim->Instance));
1409
1410 htim->State = HAL_TIM_STATE_BUSY;
1411
1412 /* Disable the TIM Peripheral Clock */
1413 __HAL_TIM_DISABLE(htim);
1414
1415 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1416 if (htim->PWM_MspDeInitCallback == NULL)
1417 {
1418 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1419 }
1420 /* DeInit the low level hardware */
1421 htim->PWM_MspDeInitCallback(htim);
1422 #else
1423 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1424 HAL_TIM_PWM_MspDeInit(htim);
1425 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1426
1427 #if defined(TIM_DMA_SUPPORT)
1428 /* Change the DMA burst operation state */
1429 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1430 #endif /* TIM_DMA_SUPPORT */
1431
1432 /* Change the TIM channels state */
1433 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1434 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1435
1436 /* Change TIM state */
1437 htim->State = HAL_TIM_STATE_RESET;
1438
1439 /* Release Lock */
1440 __HAL_UNLOCK(htim);
1441
1442 return HAL_OK;
1443 }
1444
1445 /**
1446 * @brief Initializes the TIM PWM MSP.
1447 * @param htim TIM PWM handle
1448 * @retval None
1449 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1450 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1451 {
1452 /* Prevent unused argument(s) compilation warning */
1453 UNUSED(htim);
1454
1455 /* NOTE : This function should not be modified, when the callback is needed,
1456 the HAL_TIM_PWM_MspInit could be implemented in the user file
1457 */
1458 }
1459
1460 /**
1461 * @brief DeInitializes TIM PWM MSP.
1462 * @param htim TIM PWM handle
1463 * @retval None
1464 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1465 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1466 {
1467 /* Prevent unused argument(s) compilation warning */
1468 UNUSED(htim);
1469
1470 /* NOTE : This function should not be modified, when the callback is needed,
1471 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1472 */
1473 }
1474
1475 /**
1476 * @brief Starts the PWM signal generation.
1477 * @param htim TIM handle
1478 * @param Channel TIM Channels to be enabled
1479 * This parameter can be one of the following values:
1480 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1481 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1482 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1483 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1484 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
1485 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
1486 * (*) Value not defined for all devices
1487 * @retval HAL status
1488 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1489 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1490 {
1491 uint32_t tmpsmcr;
1492
1493 /* Check the parameters */
1494 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1495
1496 /* Check the TIM channel state */
1497 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1498 {
1499 return HAL_ERROR;
1500 }
1501
1502 /* Set the TIM channel state */
1503 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1504
1505 /* Enable the Capture compare channel */
1506 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1507
1508 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1509 {
1510 /* Enable the main output */
1511 __HAL_TIM_MOE_ENABLE(htim);
1512 }
1513
1514 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1515 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1516 {
1517 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1518 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1519 {
1520 __HAL_TIM_ENABLE(htim);
1521 }
1522 }
1523 else
1524 {
1525 __HAL_TIM_ENABLE(htim);
1526 }
1527
1528 /* Return function status */
1529 return HAL_OK;
1530 }
1531
1532 /**
1533 * @brief Stops the PWM signal generation.
1534 * @param htim TIM PWM handle
1535 * @param Channel TIM Channels to be disabled
1536 * This parameter can be one of the following values:
1537 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1538 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1539 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1540 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1541 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
1542 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
1543 * (*) Value not defined for all devices
1544 * @retval HAL status
1545 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1546 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1547 {
1548 /* Check the parameters */
1549 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1550
1551 /* Disable the Capture compare channel */
1552 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1553
1554 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1555 {
1556 /* Disable the Main Output */
1557 __HAL_TIM_MOE_DISABLE(htim);
1558 }
1559
1560 /* Disable the Peripheral */
1561 __HAL_TIM_DISABLE(htim);
1562
1563 /* Set the TIM channel state */
1564 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1565
1566 /* Return function status */
1567 return HAL_OK;
1568 }
1569
1570 /**
1571 * @brief Starts the PWM signal generation in interrupt mode.
1572 * @param htim TIM PWM handle
1573 * @param Channel TIM Channel to be enabled
1574 * This parameter can be one of the following values:
1575 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1576 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1577 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1578 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1579 * @retval HAL status
1580 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1581 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1582 {
1583 HAL_StatusTypeDef status = HAL_OK;
1584 uint32_t tmpsmcr;
1585
1586 /* Check the parameters */
1587 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1588
1589 /* Check the TIM channel state */
1590 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1591 {
1592 return HAL_ERROR;
1593 }
1594
1595 /* Set the TIM channel state */
1596 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1597
1598 switch (Channel)
1599 {
1600 case TIM_CHANNEL_1:
1601 {
1602 /* Enable the TIM Capture/Compare 1 interrupt */
1603 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1604 break;
1605 }
1606
1607 case TIM_CHANNEL_2:
1608 {
1609 /* Enable the TIM Capture/Compare 2 interrupt */
1610 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1611 break;
1612 }
1613
1614 case TIM_CHANNEL_3:
1615 {
1616 /* Enable the TIM Capture/Compare 3 interrupt */
1617 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1618 break;
1619 }
1620
1621 case TIM_CHANNEL_4:
1622 {
1623 /* Enable the TIM Capture/Compare 4 interrupt */
1624 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1625 break;
1626 }
1627
1628 default:
1629 status = HAL_ERROR;
1630 break;
1631 }
1632
1633 if (status == HAL_OK)
1634 {
1635 /* Enable the Capture compare channel */
1636 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1637
1638 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1639 {
1640 /* Enable the main output */
1641 __HAL_TIM_MOE_ENABLE(htim);
1642 }
1643
1644 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1645 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1646 {
1647 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1648 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1649 {
1650 __HAL_TIM_ENABLE(htim);
1651 }
1652 }
1653 else
1654 {
1655 __HAL_TIM_ENABLE(htim);
1656 }
1657 }
1658
1659 /* Return function status */
1660 return status;
1661 }
1662
1663 /**
1664 * @brief Stops the PWM signal generation in interrupt mode.
1665 * @param htim TIM PWM handle
1666 * @param Channel TIM Channels to be disabled
1667 * This parameter can be one of the following values:
1668 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1669 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1670 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1671 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1672 * @retval HAL status
1673 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1674 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1675 {
1676 HAL_StatusTypeDef status = HAL_OK;
1677
1678 /* Check the parameters */
1679 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1680
1681 switch (Channel)
1682 {
1683 case TIM_CHANNEL_1:
1684 {
1685 /* Disable the TIM Capture/Compare 1 interrupt */
1686 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1687 break;
1688 }
1689
1690 case TIM_CHANNEL_2:
1691 {
1692 /* Disable the TIM Capture/Compare 2 interrupt */
1693 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1694 break;
1695 }
1696
1697 case TIM_CHANNEL_3:
1698 {
1699 /* Disable the TIM Capture/Compare 3 interrupt */
1700 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1701 break;
1702 }
1703
1704 case TIM_CHANNEL_4:
1705 {
1706 /* Disable the TIM Capture/Compare 4 interrupt */
1707 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1708 break;
1709 }
1710
1711 default:
1712 status = HAL_ERROR;
1713 break;
1714 }
1715
1716 if (status == HAL_OK)
1717 {
1718 /* Disable the Capture compare channel */
1719 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1720
1721 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1722 {
1723 /* Disable the Main Output */
1724 __HAL_TIM_MOE_DISABLE(htim);
1725 }
1726
1727 /* Disable the Peripheral */
1728 __HAL_TIM_DISABLE(htim);
1729
1730 /* Set the TIM channel state */
1731 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1732 }
1733
1734 /* Return function status */
1735 return status;
1736 }
1737
1738 #if defined(TIM_DMA_SUPPORT)
1739 /**
1740 * @brief Starts the TIM PWM signal generation in DMA mode.
1741 * @param htim TIM PWM handle
1742 * @param Channel TIM Channels to be enabled
1743 * This parameter can be one of the following values:
1744 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1745 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1746 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1747 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1748 * @param pData The source Buffer address.
1749 * @param Length The length of data to be transferred from memory to TIM peripheral
1750 * @retval HAL status
1751 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1752 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1753 uint16_t Length)
1754 {
1755 HAL_StatusTypeDef status = HAL_OK;
1756 uint32_t tmpsmcr;
1757
1758 /* Check the parameters */
1759 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1760
1761 /* Set the TIM channel state */
1762 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1763 {
1764 return HAL_BUSY;
1765 }
1766 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1767 {
1768 if ((pData == NULL) || (Length == 0U))
1769 {
1770 return HAL_ERROR;
1771 }
1772 else
1773 {
1774 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1775 }
1776 }
1777 else
1778 {
1779 return HAL_ERROR;
1780 }
1781
1782 switch (Channel)
1783 {
1784 case TIM_CHANNEL_1:
1785 {
1786 /* Set the DMA compare callbacks */
1787 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1788 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1789
1790 /* Set the DMA error callback */
1791 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1792
1793 /* Enable the DMA channel */
1794 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1795 Length) != HAL_OK)
1796 {
1797 /* Return error status */
1798 return HAL_ERROR;
1799 }
1800
1801 /* Enable the TIM Capture/Compare 1 DMA request */
1802 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1803 break;
1804 }
1805
1806 case TIM_CHANNEL_2:
1807 {
1808 /* Set the DMA compare callbacks */
1809 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1810 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1811
1812 /* Set the DMA error callback */
1813 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1814
1815 /* Enable the DMA channel */
1816 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1817 Length) != HAL_OK)
1818 {
1819 /* Return error status */
1820 return HAL_ERROR;
1821 }
1822 /* Enable the TIM Capture/Compare 2 DMA request */
1823 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1824 break;
1825 }
1826
1827 case TIM_CHANNEL_3:
1828 {
1829 /* Set the DMA compare callbacks */
1830 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1831 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1832
1833 /* Set the DMA error callback */
1834 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1835
1836 /* Enable the DMA channel */
1837 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1838 Length) != HAL_OK)
1839 {
1840 /* Return error status */
1841 return HAL_ERROR;
1842 }
1843 /* Enable the TIM Output Capture/Compare 3 request */
1844 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1845 break;
1846 }
1847
1848 case TIM_CHANNEL_4:
1849 {
1850 /* Set the DMA compare callbacks */
1851 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1852 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1853
1854 /* Set the DMA error callback */
1855 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1856
1857 /* Enable the DMA channel */
1858 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1859 Length) != HAL_OK)
1860 {
1861 /* Return error status */
1862 return HAL_ERROR;
1863 }
1864 /* Enable the TIM Capture/Compare 4 DMA request */
1865 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1866 break;
1867 }
1868
1869 default:
1870 status = HAL_ERROR;
1871 break;
1872 }
1873
1874 if (status == HAL_OK)
1875 {
1876 /* Enable the Capture compare channel */
1877 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1878
1879 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1880 {
1881 /* Enable the main output */
1882 __HAL_TIM_MOE_ENABLE(htim);
1883 }
1884
1885 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1886 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1887 {
1888 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1889 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1890 {
1891 __HAL_TIM_ENABLE(htim);
1892 }
1893 }
1894 else
1895 {
1896 __HAL_TIM_ENABLE(htim);
1897 }
1898 }
1899
1900 /* Return function status */
1901 return status;
1902 }
1903
1904 /**
1905 * @brief Stops the TIM PWM signal generation in DMA mode.
1906 * @param htim TIM PWM handle
1907 * @param Channel TIM Channels to be disabled
1908 * This parameter can be one of the following values:
1909 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1910 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1911 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1912 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1913 * @retval HAL status
1914 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1915 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1916 {
1917 HAL_StatusTypeDef status = HAL_OK;
1918
1919 /* Check the parameters */
1920 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1921
1922 switch (Channel)
1923 {
1924 case TIM_CHANNEL_1:
1925 {
1926 /* Disable the TIM Capture/Compare 1 DMA request */
1927 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1928 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1929 break;
1930 }
1931
1932 case TIM_CHANNEL_2:
1933 {
1934 /* Disable the TIM Capture/Compare 2 DMA request */
1935 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1936 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1937 break;
1938 }
1939
1940 case TIM_CHANNEL_3:
1941 {
1942 /* Disable the TIM Capture/Compare 3 DMA request */
1943 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1944 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1945 break;
1946 }
1947
1948 case TIM_CHANNEL_4:
1949 {
1950 /* Disable the TIM Capture/Compare 4 interrupt */
1951 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1952 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1953 break;
1954 }
1955
1956 default:
1957 status = HAL_ERROR;
1958 break;
1959 }
1960
1961 if (status == HAL_OK)
1962 {
1963 /* Disable the Capture compare channel */
1964 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1965
1966 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1967 {
1968 /* Disable the Main Output */
1969 __HAL_TIM_MOE_DISABLE(htim);
1970 }
1971
1972 /* Disable the Peripheral */
1973 __HAL_TIM_DISABLE(htim);
1974
1975 /* Set the TIM channel state */
1976 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1977 }
1978
1979 /* Return function status */
1980 return status;
1981 }
1982 #endif /* TIM_DMA_SUPPORT */
1983
1984 /**
1985 * @}
1986 */
1987
1988 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1989 * @brief TIM Input Capture functions
1990 *
1991 @verbatim
1992 ==============================================================================
1993 ##### TIM Input Capture functions #####
1994 ==============================================================================
1995 [..]
1996 This section provides functions allowing to:
1997 (+) Initialize and configure the TIM Input Capture.
1998 (+) De-initialize the TIM Input Capture.
1999 (+) Start the TIM Input Capture.
2000 (+) Stop the TIM Input Capture.
2001 (+) Start the TIM Input Capture and enable interrupt.
2002 (+) Stop the TIM Input Capture and disable interrupt.
2003 (+) Start the TIM Input Capture and enable DMA transfer.
2004 (+) Stop the TIM Input Capture and disable DMA transfer.
2005
2006 @endverbatim
2007 * @{
2008 */
2009 /**
2010 * @brief Initializes the TIM Input Capture Time base according to the specified
2011 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2012 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2013 * requires a timer reset to avoid unexpected direction
2014 * due to DIR bit readonly in center aligned mode.
2015 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
2016 * @param htim TIM Input Capture handle
2017 * @retval HAL status
2018 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)2019 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
2020 {
2021 /* Check the TIM handle allocation */
2022 if (htim == NULL)
2023 {
2024 return HAL_ERROR;
2025 }
2026
2027 /* Check the parameters */
2028 assert_param(IS_TIM_INSTANCE(htim->Instance));
2029 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2030 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2031 assert_param(IS_TIM_PERIOD(htim->Init.Period));
2032 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2033
2034 if (htim->State == HAL_TIM_STATE_RESET)
2035 {
2036 /* Allocate lock resource and initialize it */
2037 htim->Lock = HAL_UNLOCKED;
2038
2039 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2040 /* Reset interrupt callbacks to legacy weak callbacks */
2041 TIM_ResetCallback(htim);
2042
2043 if (htim->IC_MspInitCallback == NULL)
2044 {
2045 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2046 }
2047 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2048 htim->IC_MspInitCallback(htim);
2049 #else
2050 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2051 HAL_TIM_IC_MspInit(htim);
2052 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2053 }
2054
2055 /* Set the TIM state */
2056 htim->State = HAL_TIM_STATE_BUSY;
2057
2058 /* Init the base time for the input capture */
2059 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2060
2061 #if defined(TIM_DMA_SUPPORT)
2062 /* Initialize the DMA burst operation state */
2063 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2064 #endif /* TIM_DMA_SUPPORT */
2065
2066 /* Initialize the TIM channels state */
2067 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2068 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2069
2070 /* Initialize the TIM state*/
2071 htim->State = HAL_TIM_STATE_READY;
2072
2073 return HAL_OK;
2074 }
2075
2076 /**
2077 * @brief DeInitializes the TIM peripheral
2078 * @param htim TIM Input Capture handle
2079 * @retval HAL status
2080 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2081 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2082 {
2083 /* Check the parameters */
2084 assert_param(IS_TIM_INSTANCE(htim->Instance));
2085
2086 htim->State = HAL_TIM_STATE_BUSY;
2087
2088 /* Disable the TIM Peripheral Clock */
2089 __HAL_TIM_DISABLE(htim);
2090
2091 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2092 if (htim->IC_MspDeInitCallback == NULL)
2093 {
2094 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2095 }
2096 /* DeInit the low level hardware */
2097 htim->IC_MspDeInitCallback(htim);
2098 #else
2099 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2100 HAL_TIM_IC_MspDeInit(htim);
2101 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2102
2103 #if defined(TIM_DMA_SUPPORT)
2104 /* Change the DMA burst operation state */
2105 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2106 #endif /* TIM_DMA_SUPPORT */
2107
2108 /* Change the TIM channels state */
2109 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2110 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2111
2112 /* Change TIM state */
2113 htim->State = HAL_TIM_STATE_RESET;
2114
2115 /* Release Lock */
2116 __HAL_UNLOCK(htim);
2117
2118 return HAL_OK;
2119 }
2120
2121 /**
2122 * @brief Initializes the TIM Input Capture MSP.
2123 * @param htim TIM Input Capture handle
2124 * @retval None
2125 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2126 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2127 {
2128 /* Prevent unused argument(s) compilation warning */
2129 UNUSED(htim);
2130
2131 /* NOTE : This function should not be modified, when the callback is needed,
2132 the HAL_TIM_IC_MspInit could be implemented in the user file
2133 */
2134 }
2135
2136 /**
2137 * @brief DeInitializes TIM Input Capture MSP.
2138 * @param htim TIM handle
2139 * @retval None
2140 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2141 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2142 {
2143 /* Prevent unused argument(s) compilation warning */
2144 UNUSED(htim);
2145
2146 /* NOTE : This function should not be modified, when the callback is needed,
2147 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2148 */
2149 }
2150
2151 /**
2152 * @brief Starts the TIM Input Capture measurement.
2153 * @param htim TIM Input Capture handle
2154 * @param Channel TIM Channels to be enabled
2155 * This parameter can be one of the following values:
2156 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2157 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2158 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2159 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2160 * @retval HAL status
2161 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2162 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2163 {
2164 uint32_t tmpsmcr;
2165 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2166 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2167
2168 /* Check the parameters */
2169 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2170
2171 /* Check the TIM channel state */
2172 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2173 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2174 {
2175 return HAL_ERROR;
2176 }
2177
2178 /* Set the TIM channel state */
2179 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2180 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2181
2182 /* Enable the Input Capture channel */
2183 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2184
2185 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2186 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2187 {
2188 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2189 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2190 {
2191 __HAL_TIM_ENABLE(htim);
2192 }
2193 }
2194 else
2195 {
2196 __HAL_TIM_ENABLE(htim);
2197 }
2198
2199 /* Return function status */
2200 return HAL_OK;
2201 }
2202
2203 /**
2204 * @brief Stops the TIM Input Capture measurement.
2205 * @param htim TIM Input Capture handle
2206 * @param Channel TIM Channels to be disabled
2207 * This parameter can be one of the following values:
2208 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2209 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2210 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2211 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2212 * @retval HAL status
2213 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2214 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2215 {
2216 /* Check the parameters */
2217 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2218
2219 /* Disable the Input Capture channel */
2220 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2221
2222 /* Disable the Peripheral */
2223 __HAL_TIM_DISABLE(htim);
2224
2225 /* Set the TIM channel state */
2226 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2227 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2228
2229 /* Return function status */
2230 return HAL_OK;
2231 }
2232
2233 /**
2234 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2235 * @param htim TIM Input Capture handle
2236 * @param Channel TIM Channels to be enabled
2237 * This parameter can be one of the following values:
2238 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2239 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2240 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2241 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2242 * @retval HAL status
2243 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2244 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2245 {
2246 HAL_StatusTypeDef status = HAL_OK;
2247 uint32_t tmpsmcr;
2248
2249 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2250 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2251
2252 /* Check the parameters */
2253 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2254
2255 /* Check the TIM channel state */
2256 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2257 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2258 {
2259 return HAL_ERROR;
2260 }
2261
2262 /* Set the TIM channel state */
2263 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2264 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2265
2266 switch (Channel)
2267 {
2268 case TIM_CHANNEL_1:
2269 {
2270 /* Enable the TIM Capture/Compare 1 interrupt */
2271 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2272 break;
2273 }
2274
2275 case TIM_CHANNEL_2:
2276 {
2277 /* Enable the TIM Capture/Compare 2 interrupt */
2278 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2279 break;
2280 }
2281
2282 case TIM_CHANNEL_3:
2283 {
2284 /* Enable the TIM Capture/Compare 3 interrupt */
2285 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2286 break;
2287 }
2288
2289 case TIM_CHANNEL_4:
2290 {
2291 /* Enable the TIM Capture/Compare 4 interrupt */
2292 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2293 break;
2294 }
2295
2296 default:
2297 status = HAL_ERROR;
2298 break;
2299 }
2300
2301 if (status == HAL_OK)
2302 {
2303 /* Enable the Input Capture channel */
2304 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2305
2306 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2307 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2308 {
2309 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2310 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2311 {
2312 __HAL_TIM_ENABLE(htim);
2313 }
2314 }
2315 else
2316 {
2317 __HAL_TIM_ENABLE(htim);
2318 }
2319 }
2320
2321 /* Return function status */
2322 return status;
2323 }
2324
2325 /**
2326 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2327 * @param htim TIM Input Capture handle
2328 * @param Channel TIM Channels to be disabled
2329 * This parameter can be one of the following values:
2330 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2331 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2332 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2333 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2334 * @retval HAL status
2335 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2336 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2337 {
2338 HAL_StatusTypeDef status = HAL_OK;
2339
2340 /* Check the parameters */
2341 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2342
2343 switch (Channel)
2344 {
2345 case TIM_CHANNEL_1:
2346 {
2347 /* Disable the TIM Capture/Compare 1 interrupt */
2348 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2349 break;
2350 }
2351
2352 case TIM_CHANNEL_2:
2353 {
2354 /* Disable the TIM Capture/Compare 2 interrupt */
2355 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2356 break;
2357 }
2358
2359 case TIM_CHANNEL_3:
2360 {
2361 /* Disable the TIM Capture/Compare 3 interrupt */
2362 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2363 break;
2364 }
2365
2366 case TIM_CHANNEL_4:
2367 {
2368 /* Disable the TIM Capture/Compare 4 interrupt */
2369 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2370 break;
2371 }
2372
2373 default:
2374 status = HAL_ERROR;
2375 break;
2376 }
2377
2378 if (status == HAL_OK)
2379 {
2380 /* Disable the Input Capture channel */
2381 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2382
2383 /* Disable the Peripheral */
2384 __HAL_TIM_DISABLE(htim);
2385
2386 /* Set the TIM channel state */
2387 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2388 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2389 }
2390
2391 /* Return function status */
2392 return status;
2393 }
2394
2395 #if defined(TIM_DMA_SUPPORT)
2396 /**
2397 * @brief Starts the TIM Input Capture measurement in DMA mode.
2398 * @param htim TIM Input Capture handle
2399 * @param Channel TIM Channels to be enabled
2400 * This parameter can be one of the following values:
2401 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2402 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2403 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2404 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2405 * @param pData The destination Buffer address.
2406 * @param Length The length of data to be transferred from TIM peripheral to memory.
2407 * @retval HAL status
2408 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2409 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2410 {
2411 HAL_StatusTypeDef status = HAL_OK;
2412 uint32_t tmpsmcr;
2413
2414 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2415 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2416
2417 /* Check the parameters */
2418 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2419 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2420
2421 /* Set the TIM channel state */
2422 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2423 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2424 {
2425 return HAL_BUSY;
2426 }
2427 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2428 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2429 {
2430 if ((pData == NULL) || (Length == 0U))
2431 {
2432 return HAL_ERROR;
2433 }
2434 else
2435 {
2436 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2437 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2438 }
2439 }
2440 else
2441 {
2442 return HAL_ERROR;
2443 }
2444
2445 /* Enable the Input Capture channel */
2446 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2447
2448 switch (Channel)
2449 {
2450 case TIM_CHANNEL_1:
2451 {
2452 /* Set the DMA capture callbacks */
2453 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2454 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2455
2456 /* Set the DMA error callback */
2457 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2458
2459 /* Enable the DMA channel */
2460 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2461 Length) != HAL_OK)
2462 {
2463 /* Return error status */
2464 return HAL_ERROR;
2465 }
2466 /* Enable the TIM Capture/Compare 1 DMA request */
2467 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2468 break;
2469 }
2470
2471 case TIM_CHANNEL_2:
2472 {
2473 /* Set the DMA capture callbacks */
2474 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2475 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2476
2477 /* Set the DMA error callback */
2478 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2479
2480 /* Enable the DMA channel */
2481 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2482 Length) != HAL_OK)
2483 {
2484 /* Return error status */
2485 return HAL_ERROR;
2486 }
2487 /* Enable the TIM Capture/Compare 2 DMA request */
2488 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2489 break;
2490 }
2491
2492 case TIM_CHANNEL_3:
2493 {
2494 /* Set the DMA capture callbacks */
2495 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2496 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2497
2498 /* Set the DMA error callback */
2499 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2500
2501 /* Enable the DMA channel */
2502 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2503 Length) != HAL_OK)
2504 {
2505 /* Return error status */
2506 return HAL_ERROR;
2507 }
2508 /* Enable the TIM Capture/Compare 3 DMA request */
2509 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2510 break;
2511 }
2512
2513 case TIM_CHANNEL_4:
2514 {
2515 /* Set the DMA capture callbacks */
2516 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2517 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2518
2519 /* Set the DMA error callback */
2520 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2521
2522 /* Enable the DMA channel */
2523 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2524 Length) != HAL_OK)
2525 {
2526 /* Return error status */
2527 return HAL_ERROR;
2528 }
2529 /* Enable the TIM Capture/Compare 4 DMA request */
2530 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2531 break;
2532 }
2533
2534 default:
2535 status = HAL_ERROR;
2536 break;
2537 }
2538
2539 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2540 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2541 {
2542 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2543 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2544 {
2545 __HAL_TIM_ENABLE(htim);
2546 }
2547 }
2548 else
2549 {
2550 __HAL_TIM_ENABLE(htim);
2551 }
2552
2553 /* Return function status */
2554 return status;
2555 }
2556
2557 /**
2558 * @brief Stops the TIM Input Capture measurement in DMA mode.
2559 * @param htim TIM Input Capture handle
2560 * @param Channel TIM Channels to be disabled
2561 * This parameter can be one of the following values:
2562 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2563 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2564 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2565 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2566 * @retval HAL status
2567 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2568 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2569 {
2570 HAL_StatusTypeDef status = HAL_OK;
2571
2572 /* Check the parameters */
2573 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2574 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2575
2576 /* Disable the Input Capture channel */
2577 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2578
2579 switch (Channel)
2580 {
2581 case TIM_CHANNEL_1:
2582 {
2583 /* Disable the TIM Capture/Compare 1 DMA request */
2584 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2585 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2586 break;
2587 }
2588
2589 case TIM_CHANNEL_2:
2590 {
2591 /* Disable the TIM Capture/Compare 2 DMA request */
2592 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2593 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2594 break;
2595 }
2596
2597 case TIM_CHANNEL_3:
2598 {
2599 /* Disable the TIM Capture/Compare 3 DMA request */
2600 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2601 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2602 break;
2603 }
2604
2605 case TIM_CHANNEL_4:
2606 {
2607 /* Disable the TIM Capture/Compare 4 DMA request */
2608 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2609 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2610 break;
2611 }
2612
2613 default:
2614 status = HAL_ERROR;
2615 break;
2616 }
2617
2618 if (status == HAL_OK)
2619 {
2620 /* Disable the Peripheral */
2621 __HAL_TIM_DISABLE(htim);
2622
2623 /* Set the TIM channel state */
2624 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2625 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2626 }
2627
2628 /* Return function status */
2629 return status;
2630 }
2631 #endif /* TIM_DMA_SUPPORT */
2632 /**
2633 * @}
2634 */
2635
2636 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2637 * @brief TIM One Pulse functions
2638 *
2639 @verbatim
2640 ==============================================================================
2641 ##### TIM One Pulse functions #####
2642 ==============================================================================
2643 [..]
2644 This section provides functions allowing to:
2645 (+) Initialize and configure the TIM One Pulse.
2646 (+) De-initialize the TIM One Pulse.
2647 (+) Start the TIM One Pulse.
2648 (+) Stop the TIM One Pulse.
2649 (+) Start the TIM One Pulse and enable interrupt.
2650 (+) Stop the TIM One Pulse and disable interrupt.
2651 (+) Start the TIM One Pulse and enable DMA transfer.
2652 (+) Stop the TIM One Pulse and disable DMA transfer.
2653
2654 @endverbatim
2655 * @{
2656 */
2657 /**
2658 * @brief Initializes the TIM One Pulse Time Base according to the specified
2659 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2660 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2661 * requires a timer reset to avoid unexpected direction
2662 * due to DIR bit readonly in center aligned mode.
2663 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2664 * @note When the timer instance is initialized in One Pulse mode, timer
2665 * channels 1 and channel 2 are reserved and cannot be used for other
2666 * purpose.
2667 * @param htim TIM One Pulse handle
2668 * @param OnePulseMode Select the One pulse mode.
2669 * This parameter can be one of the following values:
2670 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2671 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2672 * @retval HAL status
2673 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2674 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2675 {
2676 /* Check the TIM handle allocation */
2677 if (htim == NULL)
2678 {
2679 return HAL_ERROR;
2680 }
2681
2682 /* Check the parameters */
2683 assert_param(IS_TIM_INSTANCE(htim->Instance));
2684 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2685 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2686 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2687 assert_param(IS_TIM_PERIOD(htim->Init.Period));
2688 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2689
2690 if (htim->State == HAL_TIM_STATE_RESET)
2691 {
2692 /* Allocate lock resource and initialize it */
2693 htim->Lock = HAL_UNLOCKED;
2694
2695 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2696 /* Reset interrupt callbacks to legacy weak callbacks */
2697 TIM_ResetCallback(htim);
2698
2699 if (htim->OnePulse_MspInitCallback == NULL)
2700 {
2701 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2702 }
2703 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2704 htim->OnePulse_MspInitCallback(htim);
2705 #else
2706 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2707 HAL_TIM_OnePulse_MspInit(htim);
2708 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2709 }
2710
2711 /* Set the TIM state */
2712 htim->State = HAL_TIM_STATE_BUSY;
2713
2714 /* Configure the Time base in the One Pulse Mode */
2715 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2716
2717 /* Reset the OPM Bit */
2718 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2719
2720 /* Configure the OPM Mode */
2721 htim->Instance->CR1 |= OnePulseMode;
2722
2723 #if defined(TIM_DMA_SUPPORT)
2724 /* Initialize the DMA burst operation state */
2725 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2726 #endif /* TIM_DMA_SUPPORT */
2727
2728 /* Initialize the TIM channels state */
2729 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2730 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2731 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2732 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2733
2734 /* Initialize the TIM state*/
2735 htim->State = HAL_TIM_STATE_READY;
2736
2737 return HAL_OK;
2738 }
2739
2740 /**
2741 * @brief DeInitializes the TIM One Pulse
2742 * @param htim TIM One Pulse handle
2743 * @retval HAL status
2744 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2745 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2746 {
2747 /* Check the parameters */
2748 assert_param(IS_TIM_INSTANCE(htim->Instance));
2749
2750 htim->State = HAL_TIM_STATE_BUSY;
2751
2752 /* Disable the TIM Peripheral Clock */
2753 __HAL_TIM_DISABLE(htim);
2754
2755 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2756 if (htim->OnePulse_MspDeInitCallback == NULL)
2757 {
2758 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2759 }
2760 /* DeInit the low level hardware */
2761 htim->OnePulse_MspDeInitCallback(htim);
2762 #else
2763 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2764 HAL_TIM_OnePulse_MspDeInit(htim);
2765 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2766
2767 #if defined(TIM_DMA_SUPPORT)
2768 /* Change the DMA burst operation state */
2769 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2770 #endif /* TIM_DMA_SUPPORT */
2771
2772 /* Set the TIM channel state */
2773 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2774 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2775 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2776 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2777
2778 /* Change TIM state */
2779 htim->State = HAL_TIM_STATE_RESET;
2780
2781 /* Release Lock */
2782 __HAL_UNLOCK(htim);
2783
2784 return HAL_OK;
2785 }
2786
2787 /**
2788 * @brief Initializes the TIM One Pulse MSP.
2789 * @param htim TIM One Pulse handle
2790 * @retval None
2791 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2792 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2793 {
2794 /* Prevent unused argument(s) compilation warning */
2795 UNUSED(htim);
2796
2797 /* NOTE : This function should not be modified, when the callback is needed,
2798 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2799 */
2800 }
2801
2802 /**
2803 * @brief DeInitializes TIM One Pulse MSP.
2804 * @param htim TIM One Pulse handle
2805 * @retval None
2806 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2807 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2808 {
2809 /* Prevent unused argument(s) compilation warning */
2810 UNUSED(htim);
2811
2812 /* NOTE : This function should not be modified, when the callback is needed,
2813 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2814 */
2815 }
2816
2817 /**
2818 * @brief Starts the TIM One Pulse signal generation.
2819 * @note Though OutputChannel parameter is deprecated and ignored by the function
2820 * it has been kept to avoid HAL_TIM API compatibility break.
2821 * @note The pulse output channel is determined when calling
2822 * @ref HAL_TIM_OnePulse_ConfigChannel().
2823 * @param htim TIM One Pulse handle
2824 * @param OutputChannel See note above
2825 * @retval HAL status
2826 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2827 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2828 {
2829 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2830 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2831 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2832 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2833
2834 /* Prevent unused argument(s) compilation warning */
2835 UNUSED(OutputChannel);
2836
2837 /* Check the TIM channels state */
2838 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2839 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2840 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2841 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2842 {
2843 return HAL_ERROR;
2844 }
2845
2846 /* Set the TIM channels state */
2847 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2848 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2849 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2850 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2851
2852 /* Enable the Capture compare and the Input Capture channels
2853 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2854 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2855 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2856 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2857
2858 No need to enable the counter, it's enabled automatically by hardware
2859 (the counter starts in response to a stimulus and generate a pulse */
2860
2861 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2862 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2863
2864 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2865 {
2866 /* Enable the main output */
2867 __HAL_TIM_MOE_ENABLE(htim);
2868 }
2869
2870 /* Return function status */
2871 return HAL_OK;
2872 }
2873
2874 /**
2875 * @brief Stops the TIM One Pulse signal generation.
2876 * @note Though OutputChannel parameter is deprecated and ignored by the function
2877 * it has been kept to avoid HAL_TIM API compatibility break.
2878 * @note The pulse output channel is determined when calling
2879 * @ref HAL_TIM_OnePulse_ConfigChannel().
2880 * @param htim TIM One Pulse handle
2881 * @param OutputChannel See note above
2882 * @retval HAL status
2883 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2884 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2885 {
2886 /* Prevent unused argument(s) compilation warning */
2887 UNUSED(OutputChannel);
2888
2889 /* Disable the Capture compare and the Input Capture channels
2890 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2891 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2892 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2893 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2894
2895 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2896 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2897
2898 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2899 {
2900 /* Disable the Main Output */
2901 __HAL_TIM_MOE_DISABLE(htim);
2902 }
2903
2904 /* Disable the Peripheral */
2905 __HAL_TIM_DISABLE(htim);
2906
2907 /* Set the TIM channels state */
2908 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2909 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2910 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2911 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2912
2913 /* Return function status */
2914 return HAL_OK;
2915 }
2916
2917 /**
2918 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2919 * @note Though OutputChannel parameter is deprecated and ignored by the function
2920 * it has been kept to avoid HAL_TIM API compatibility break.
2921 * @note The pulse output channel is determined when calling
2922 * @ref HAL_TIM_OnePulse_ConfigChannel().
2923 * @param htim TIM One Pulse handle
2924 * @param OutputChannel See note above
2925 * @retval HAL status
2926 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2927 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2928 {
2929 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2930 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2931 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2932 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2933
2934 /* Prevent unused argument(s) compilation warning */
2935 UNUSED(OutputChannel);
2936
2937 /* Check the TIM channels state */
2938 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2939 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2940 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2941 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2942 {
2943 return HAL_ERROR;
2944 }
2945
2946 /* Set the TIM channels state */
2947 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2948 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2949 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2950 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2951
2952 /* Enable the Capture compare and the Input Capture channels
2953 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2954 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2955 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2956 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2957
2958 No need to enable the counter, it's enabled automatically by hardware
2959 (the counter starts in response to a stimulus and generate a pulse */
2960
2961 /* Enable the TIM Capture/Compare 1 interrupt */
2962 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2963
2964 /* Enable the TIM Capture/Compare 2 interrupt */
2965 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2966
2967 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2968 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2969
2970 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2971 {
2972 /* Enable the main output */
2973 __HAL_TIM_MOE_ENABLE(htim);
2974 }
2975
2976 /* Return function status */
2977 return HAL_OK;
2978 }
2979
2980 /**
2981 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2982 * @note Though OutputChannel parameter is deprecated and ignored by the function
2983 * it has been kept to avoid HAL_TIM API compatibility break.
2984 * @note The pulse output channel is determined when calling
2985 * @ref HAL_TIM_OnePulse_ConfigChannel().
2986 * @param htim TIM One Pulse handle
2987 * @param OutputChannel See note above
2988 * @retval HAL status
2989 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2990 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2991 {
2992 /* Prevent unused argument(s) compilation warning */
2993 UNUSED(OutputChannel);
2994
2995 /* Disable the TIM Capture/Compare 1 interrupt */
2996 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2997
2998 /* Disable the TIM Capture/Compare 2 interrupt */
2999 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3000
3001 /* Disable the Capture compare and the Input Capture channels
3002 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
3003 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
3004 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
3005 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
3006 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3007 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3008
3009 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
3010 {
3011 /* Disable the Main Output */
3012 __HAL_TIM_MOE_DISABLE(htim);
3013 }
3014
3015 /* Disable the Peripheral */
3016 __HAL_TIM_DISABLE(htim);
3017
3018 /* Set the TIM channels state */
3019 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3020 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3021 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3022 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3023
3024 /* Return function status */
3025 return HAL_OK;
3026 }
3027
3028 /**
3029 * @}
3030 */
3031
3032 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
3033 * @brief TIM Encoder functions
3034 *
3035 @verbatim
3036 ==============================================================================
3037 ##### TIM Encoder functions #####
3038 ==============================================================================
3039 [..]
3040 This section provides functions allowing to:
3041 (+) Initialize and configure the TIM Encoder.
3042 (+) De-initialize the TIM Encoder.
3043 (+) Start the TIM Encoder.
3044 (+) Stop the TIM Encoder.
3045 (+) Start the TIM Encoder and enable interrupt.
3046 (+) Stop the TIM Encoder and disable interrupt.
3047 (+) Start the TIM Encoder and enable DMA transfer.
3048 (+) Stop the TIM Encoder and disable DMA transfer.
3049
3050 @endverbatim
3051 * @{
3052 */
3053 /**
3054 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
3055 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3056 * requires a timer reset to avoid unexpected direction
3057 * due to DIR bit readonly in center aligned mode.
3058 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3059 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
3060 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3061 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3062 * @note When the timer instance is initialized in Encoder mode, timer
3063 * channels 1 and channel 2 are reserved and cannot be used for other
3064 * purpose.
3065 * @param htim TIM Encoder Interface handle
3066 * @param sConfig TIM Encoder Interface configuration structure
3067 * @retval HAL status
3068 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)3069 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
3070 {
3071 uint32_t tmpsmcr;
3072 uint32_t tmpccmr1;
3073 uint32_t tmpccer;
3074
3075 /* Check the TIM handle allocation */
3076 if (htim == NULL)
3077 {
3078 return HAL_ERROR;
3079 }
3080
3081 /* Check the parameters */
3082 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3083 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3084 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3085 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3086 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3087 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3088 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3089 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3090 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3091 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3092 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3093 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3094 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3095 assert_param(IS_TIM_PERIOD(htim->Init.Period));
3096
3097 if (htim->State == HAL_TIM_STATE_RESET)
3098 {
3099 /* Allocate lock resource and initialize it */
3100 htim->Lock = HAL_UNLOCKED;
3101
3102 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3103 /* Reset interrupt callbacks to legacy weak callbacks */
3104 TIM_ResetCallback(htim);
3105
3106 if (htim->Encoder_MspInitCallback == NULL)
3107 {
3108 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3109 }
3110 /* Init the low level hardware : GPIO, CLOCK, NVIC */
3111 htim->Encoder_MspInitCallback(htim);
3112 #else
3113 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3114 HAL_TIM_Encoder_MspInit(htim);
3115 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3116 }
3117
3118 /* Set the TIM state */
3119 htim->State = HAL_TIM_STATE_BUSY;
3120
3121 /* Reset the SMS and ECE bits */
3122 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3123
3124 /* Configure the Time base in the Encoder Mode */
3125 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3126
3127 /* Get the TIMx SMCR register value */
3128 tmpsmcr = htim->Instance->SMCR;
3129
3130 /* Get the TIMx CCMR1 register value */
3131 tmpccmr1 = htim->Instance->CCMR1;
3132
3133 /* Get the TIMx CCER register value */
3134 tmpccer = htim->Instance->CCER;
3135
3136 /* Set the encoder Mode */
3137 tmpsmcr |= sConfig->EncoderMode;
3138
3139 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3140 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3141 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3142
3143 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3144 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3145 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3146 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3147 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3148
3149 /* Set the TI1 and the TI2 Polarities */
3150 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3151 tmpccer &= ~(TIM_CCER_CC1NP);
3152 #if defined(TIM_CCER_CC2NP)
3153 tmpccer &= ~(TIM_CCER_CC2NP);
3154 #endif /* TIM_CCER_CC2NP */
3155 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3156
3157 /* Write to TIMx SMCR */
3158 htim->Instance->SMCR = tmpsmcr;
3159
3160 /* Write to TIMx CCMR1 */
3161 htim->Instance->CCMR1 = tmpccmr1;
3162
3163 /* Write to TIMx CCER */
3164 htim->Instance->CCER = tmpccer;
3165
3166 #if defined(TIM_DMA_SUPPORT)
3167 /* Initialize the DMA burst operation state */
3168 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3169 #endif /* TIM_DMA_SUPPORT */
3170
3171 /* Set the TIM channels state */
3172 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3173 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3174 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3175 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3176
3177 /* Initialize the TIM state*/
3178 htim->State = HAL_TIM_STATE_READY;
3179
3180 return HAL_OK;
3181 }
3182
3183
3184 /**
3185 * @brief DeInitializes the TIM Encoder interface
3186 * @param htim TIM Encoder Interface handle
3187 * @retval HAL status
3188 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3189 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3190 {
3191 /* Check the parameters */
3192 assert_param(IS_TIM_INSTANCE(htim->Instance));
3193
3194 htim->State = HAL_TIM_STATE_BUSY;
3195
3196 /* Disable the TIM Peripheral Clock */
3197 __HAL_TIM_DISABLE(htim);
3198
3199 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3200 if (htim->Encoder_MspDeInitCallback == NULL)
3201 {
3202 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3203 }
3204 /* DeInit the low level hardware */
3205 htim->Encoder_MspDeInitCallback(htim);
3206 #else
3207 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3208 HAL_TIM_Encoder_MspDeInit(htim);
3209 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3210
3211 #if defined(TIM_DMA_SUPPORT)
3212 /* Change the DMA burst operation state */
3213 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3214 #endif /* TIM_DMA_SUPPORT */
3215
3216 /* Set the TIM channels state */
3217 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3218 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3219 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3220 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3221
3222 /* Change TIM state */
3223 htim->State = HAL_TIM_STATE_RESET;
3224
3225 /* Release Lock */
3226 __HAL_UNLOCK(htim);
3227
3228 return HAL_OK;
3229 }
3230
3231 /**
3232 * @brief Initializes the TIM Encoder Interface MSP.
3233 * @param htim TIM Encoder Interface handle
3234 * @retval None
3235 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3236 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3237 {
3238 /* Prevent unused argument(s) compilation warning */
3239 UNUSED(htim);
3240
3241 /* NOTE : This function should not be modified, when the callback is needed,
3242 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3243 */
3244 }
3245
3246 /**
3247 * @brief DeInitializes TIM Encoder Interface MSP.
3248 * @param htim TIM Encoder Interface handle
3249 * @retval None
3250 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3251 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3252 {
3253 /* Prevent unused argument(s) compilation warning */
3254 UNUSED(htim);
3255
3256 /* NOTE : This function should not be modified, when the callback is needed,
3257 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3258 */
3259 }
3260
3261 /**
3262 * @brief Starts the TIM Encoder Interface.
3263 * @param htim TIM Encoder Interface handle
3264 * @param Channel TIM Channels to be enabled
3265 * This parameter can be one of the following values:
3266 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3267 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3268 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3269 * @retval HAL status
3270 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3271 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3272 {
3273 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3274 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3275 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3276 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3277
3278 /* Check the parameters */
3279 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3280
3281 /* Set the TIM channel(s) state */
3282 if (Channel == TIM_CHANNEL_1)
3283 {
3284 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3285 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3286 {
3287 return HAL_ERROR;
3288 }
3289 else
3290 {
3291 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3292 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3293 }
3294 }
3295 else if (Channel == TIM_CHANNEL_2)
3296 {
3297 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3298 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3299 {
3300 return HAL_ERROR;
3301 }
3302 else
3303 {
3304 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3305 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3306 }
3307 }
3308 else
3309 {
3310 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3311 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3312 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3313 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3314 {
3315 return HAL_ERROR;
3316 }
3317 else
3318 {
3319 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3320 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3321 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3322 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3323 }
3324 }
3325
3326 /* Enable the encoder interface channels */
3327 switch (Channel)
3328 {
3329 case TIM_CHANNEL_1:
3330 {
3331 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3332 break;
3333 }
3334
3335 case TIM_CHANNEL_2:
3336 {
3337 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3338 break;
3339 }
3340
3341 default :
3342 {
3343 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3344 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3345 break;
3346 }
3347 }
3348 /* Enable the Peripheral */
3349 __HAL_TIM_ENABLE(htim);
3350
3351 /* Return function status */
3352 return HAL_OK;
3353 }
3354
3355 /**
3356 * @brief Stops the TIM Encoder Interface.
3357 * @param htim TIM Encoder Interface handle
3358 * @param Channel TIM Channels to be disabled
3359 * This parameter can be one of the following values:
3360 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3361 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3362 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3363 * @retval HAL status
3364 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3365 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3366 {
3367 /* Check the parameters */
3368 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3369
3370 /* Disable the Input Capture channels 1 and 2
3371 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3372 switch (Channel)
3373 {
3374 case TIM_CHANNEL_1:
3375 {
3376 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3377 break;
3378 }
3379
3380 case TIM_CHANNEL_2:
3381 {
3382 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3383 break;
3384 }
3385
3386 default :
3387 {
3388 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3389 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3390 break;
3391 }
3392 }
3393
3394 /* Disable the Peripheral */
3395 __HAL_TIM_DISABLE(htim);
3396
3397 /* Set the TIM channel(s) state */
3398 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3399 {
3400 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3401 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3402 }
3403 else
3404 {
3405 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3406 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3407 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3408 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3409 }
3410
3411 /* Return function status */
3412 return HAL_OK;
3413 }
3414
3415 /**
3416 * @brief Starts the TIM Encoder Interface in interrupt mode.
3417 * @param htim TIM Encoder Interface handle
3418 * @param Channel TIM Channels to be enabled
3419 * This parameter can be one of the following values:
3420 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3421 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3422 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3423 * @retval HAL status
3424 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3425 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3426 {
3427 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3428 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3429 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3430 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3431
3432 /* Check the parameters */
3433 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3434
3435 /* Set the TIM channel(s) state */
3436 if (Channel == TIM_CHANNEL_1)
3437 {
3438 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3439 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3440 {
3441 return HAL_ERROR;
3442 }
3443 else
3444 {
3445 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3446 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3447 }
3448 }
3449 else if (Channel == TIM_CHANNEL_2)
3450 {
3451 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3452 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3453 {
3454 return HAL_ERROR;
3455 }
3456 else
3457 {
3458 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3459 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3460 }
3461 }
3462 else
3463 {
3464 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3465 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3466 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3467 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3468 {
3469 return HAL_ERROR;
3470 }
3471 else
3472 {
3473 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3474 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3475 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3476 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3477 }
3478 }
3479
3480 /* Enable the encoder interface channels */
3481 /* Enable the capture compare Interrupts 1 and/or 2 */
3482 switch (Channel)
3483 {
3484 case TIM_CHANNEL_1:
3485 {
3486 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3487 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3488 break;
3489 }
3490
3491 case TIM_CHANNEL_2:
3492 {
3493 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3494 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3495 break;
3496 }
3497
3498 default :
3499 {
3500 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3501 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3502 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3503 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3504 break;
3505 }
3506 }
3507
3508 /* Enable the Peripheral */
3509 __HAL_TIM_ENABLE(htim);
3510
3511 /* Return function status */
3512 return HAL_OK;
3513 }
3514
3515 /**
3516 * @brief Stops the TIM Encoder Interface in interrupt mode.
3517 * @param htim TIM Encoder Interface handle
3518 * @param Channel TIM Channels to be disabled
3519 * This parameter can be one of the following values:
3520 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3521 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3522 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3523 * @retval HAL status
3524 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3525 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3526 {
3527 /* Check the parameters */
3528 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3529
3530 /* Disable the Input Capture channels 1 and 2
3531 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3532 if (Channel == TIM_CHANNEL_1)
3533 {
3534 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3535
3536 /* Disable the capture compare Interrupts 1 */
3537 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3538 }
3539 else if (Channel == TIM_CHANNEL_2)
3540 {
3541 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3542
3543 /* Disable the capture compare Interrupts 2 */
3544 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3545 }
3546 else
3547 {
3548 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3549 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3550
3551 /* Disable the capture compare Interrupts 1 and 2 */
3552 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3553 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3554 }
3555
3556 /* Disable the Peripheral */
3557 __HAL_TIM_DISABLE(htim);
3558
3559 /* Set the TIM channel(s) state */
3560 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3561 {
3562 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3563 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3564 }
3565 else
3566 {
3567 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3568 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3569 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3570 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3571 }
3572
3573 /* Return function status */
3574 return HAL_OK;
3575 }
3576
3577 #if defined(TIM_DMA_SUPPORT)
3578 /**
3579 * @brief Starts the TIM Encoder Interface in DMA mode.
3580 * @param htim TIM Encoder Interface handle
3581 * @param Channel TIM Channels to be enabled
3582 * This parameter can be one of the following values:
3583 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3584 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3585 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3586 * @param pData1 The destination Buffer address for IC1.
3587 * @param pData2 The destination Buffer address for IC2.
3588 * @param Length The length of data to be transferred from TIM peripheral to memory.
3589 * @retval HAL status
3590 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3591 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3592 uint32_t *pData2, uint16_t Length)
3593 {
3594 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3595 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3596 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3597 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3598
3599 /* Check the parameters */
3600 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3601
3602 /* Set the TIM channel(s) state */
3603 if (Channel == TIM_CHANNEL_1)
3604 {
3605 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3606 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3607 {
3608 return HAL_BUSY;
3609 }
3610 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3611 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3612 {
3613 if ((pData1 == NULL) || (Length == 0U))
3614 {
3615 return HAL_ERROR;
3616 }
3617 else
3618 {
3619 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3620 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3621 }
3622 }
3623 else
3624 {
3625 return HAL_ERROR;
3626 }
3627 }
3628 else if (Channel == TIM_CHANNEL_2)
3629 {
3630 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3631 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3632 {
3633 return HAL_BUSY;
3634 }
3635 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3636 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3637 {
3638 if ((pData2 == NULL) || (Length == 0U))
3639 {
3640 return HAL_ERROR;
3641 }
3642 else
3643 {
3644 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3645 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3646 }
3647 }
3648 else
3649 {
3650 return HAL_ERROR;
3651 }
3652 }
3653 else
3654 {
3655 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3656 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3657 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3658 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3659 {
3660 return HAL_BUSY;
3661 }
3662 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3663 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3664 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3665 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3666 {
3667 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3668 {
3669 return HAL_ERROR;
3670 }
3671 else
3672 {
3673 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3674 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3675 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3676 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3677 }
3678 }
3679 else
3680 {
3681 return HAL_ERROR;
3682 }
3683 }
3684
3685 switch (Channel)
3686 {
3687 case TIM_CHANNEL_1:
3688 {
3689 /* Set the DMA capture callbacks */
3690 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3691 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3692
3693 /* Set the DMA error callback */
3694 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3695
3696 /* Enable the DMA channel */
3697 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3698 Length) != HAL_OK)
3699 {
3700 /* Return error status */
3701 return HAL_ERROR;
3702 }
3703 /* Enable the TIM Input Capture DMA request */
3704 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3705
3706 /* Enable the Capture compare channel */
3707 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3708
3709 /* Enable the Peripheral */
3710 __HAL_TIM_ENABLE(htim);
3711
3712 break;
3713 }
3714
3715 case TIM_CHANNEL_2:
3716 {
3717 /* Set the DMA capture callbacks */
3718 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3719 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3720
3721 /* Set the DMA error callback */
3722 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3723 /* Enable the DMA channel */
3724 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3725 Length) != HAL_OK)
3726 {
3727 /* Return error status */
3728 return HAL_ERROR;
3729 }
3730 /* Enable the TIM Input Capture DMA request */
3731 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3732
3733 /* Enable the Capture compare channel */
3734 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3735
3736 /* Enable the Peripheral */
3737 __HAL_TIM_ENABLE(htim);
3738
3739 break;
3740 }
3741
3742 default:
3743 {
3744 /* Set the DMA capture callbacks */
3745 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3746 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3747
3748 /* Set the DMA error callback */
3749 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3750
3751 /* Enable the DMA channel */
3752 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3753 Length) != HAL_OK)
3754 {
3755 /* Return error status */
3756 return HAL_ERROR;
3757 }
3758
3759 /* Set the DMA capture callbacks */
3760 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3761 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3762
3763 /* Set the DMA error callback */
3764 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3765
3766 /* Enable the DMA channel */
3767 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3768 Length) != HAL_OK)
3769 {
3770 /* Return error status */
3771 return HAL_ERROR;
3772 }
3773
3774 /* Enable the TIM Input Capture DMA request */
3775 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3776 /* Enable the TIM Input Capture DMA request */
3777 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3778
3779 /* Enable the Capture compare channel */
3780 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3781 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3782
3783 /* Enable the Peripheral */
3784 __HAL_TIM_ENABLE(htim);
3785
3786 break;
3787 }
3788 }
3789
3790 /* Return function status */
3791 return HAL_OK;
3792 }
3793
3794 /**
3795 * @brief Stops the TIM Encoder Interface in DMA mode.
3796 * @param htim TIM Encoder Interface handle
3797 * @param Channel TIM Channels to be enabled
3798 * This parameter can be one of the following values:
3799 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3800 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3801 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3802 * @retval HAL status
3803 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3804 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3805 {
3806 /* Check the parameters */
3807 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3808
3809 /* Disable the Input Capture channels 1 and 2
3810 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3811 if (Channel == TIM_CHANNEL_1)
3812 {
3813 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3814
3815 /* Disable the capture compare DMA Request 1 */
3816 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3817 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3818 }
3819 else if (Channel == TIM_CHANNEL_2)
3820 {
3821 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3822
3823 /* Disable the capture compare DMA Request 2 */
3824 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3825 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3826 }
3827 else
3828 {
3829 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3830 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3831
3832 /* Disable the capture compare DMA Request 1 and 2 */
3833 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3834 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3835 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3836 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3837 }
3838
3839 /* Disable the Peripheral */
3840 __HAL_TIM_DISABLE(htim);
3841
3842 /* Set the TIM channel(s) state */
3843 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3844 {
3845 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3846 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3847 }
3848 else
3849 {
3850 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3851 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3852 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3853 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3854 }
3855
3856 /* Return function status */
3857 return HAL_OK;
3858 }
3859 #endif /* TIM_DMA_SUPPORT */
3860
3861 /**
3862 * @}
3863 */
3864 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3865 * @brief TIM IRQ handler management
3866 *
3867 @verbatim
3868 ==============================================================================
3869 ##### IRQ handler management #####
3870 ==============================================================================
3871 [..]
3872 This section provides Timer IRQ handler function.
3873
3874 @endverbatim
3875 * @{
3876 */
3877 /**
3878 * @brief This function handles TIM interrupts requests.
3879 * @param htim TIM handle
3880 * @retval None
3881 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3882 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3883 {
3884 uint32_t itsource = htim->Instance->DIER;
3885 uint32_t itflag = htim->Instance->SR;
3886
3887 /* Capture compare 1 event */
3888 if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
3889 {
3890 if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
3891 {
3892 {
3893 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3894 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3895
3896 /* Input capture event */
3897 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3898 {
3899 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3900 htim->IC_CaptureCallback(htim);
3901 #else
3902 HAL_TIM_IC_CaptureCallback(htim);
3903 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3904 }
3905 /* Output compare event */
3906 else
3907 {
3908 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3909 htim->OC_DelayElapsedCallback(htim);
3910 htim->PWM_PulseFinishedCallback(htim);
3911 #else
3912 HAL_TIM_OC_DelayElapsedCallback(htim);
3913 HAL_TIM_PWM_PulseFinishedCallback(htim);
3914 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3915 }
3916 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3917 }
3918 }
3919 }
3920 /* Capture compare 2 event */
3921 if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
3922 {
3923 if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
3924 {
3925 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3926 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3927 /* Input capture event */
3928 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3929 {
3930 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3931 htim->IC_CaptureCallback(htim);
3932 #else
3933 HAL_TIM_IC_CaptureCallback(htim);
3934 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3935 }
3936 /* Output compare event */
3937 else
3938 {
3939 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3940 htim->OC_DelayElapsedCallback(htim);
3941 htim->PWM_PulseFinishedCallback(htim);
3942 #else
3943 HAL_TIM_OC_DelayElapsedCallback(htim);
3944 HAL_TIM_PWM_PulseFinishedCallback(htim);
3945 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3946 }
3947 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3948 }
3949 }
3950 /* Capture compare 3 event */
3951 if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
3952 {
3953 if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
3954 {
3955 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3956 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3957 /* Input capture event */
3958 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3959 {
3960 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3961 htim->IC_CaptureCallback(htim);
3962 #else
3963 HAL_TIM_IC_CaptureCallback(htim);
3964 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3965 }
3966 /* Output compare event */
3967 else
3968 {
3969 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3970 htim->OC_DelayElapsedCallback(htim);
3971 htim->PWM_PulseFinishedCallback(htim);
3972 #else
3973 HAL_TIM_OC_DelayElapsedCallback(htim);
3974 HAL_TIM_PWM_PulseFinishedCallback(htim);
3975 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3976 }
3977 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3978 }
3979 }
3980 /* Capture compare 4 event */
3981 if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
3982 {
3983 if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
3984 {
3985 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3986 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3987 /* Input capture event */
3988 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3989 {
3990 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3991 htim->IC_CaptureCallback(htim);
3992 #else
3993 HAL_TIM_IC_CaptureCallback(htim);
3994 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3995 }
3996 /* Output compare event */
3997 else
3998 {
3999 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4000 htim->OC_DelayElapsedCallback(htim);
4001 htim->PWM_PulseFinishedCallback(htim);
4002 #else
4003 HAL_TIM_OC_DelayElapsedCallback(htim);
4004 HAL_TIM_PWM_PulseFinishedCallback(htim);
4005 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4006 }
4007 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4008 }
4009 }
4010 /* TIM Update event */
4011 if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
4012 {
4013 if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
4014 {
4015 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
4016 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4017 htim->PeriodElapsedCallback(htim);
4018 #else
4019 HAL_TIM_PeriodElapsedCallback(htim);
4020 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4021 }
4022 }
4023 /* TIM Break input event */
4024 if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
4025 {
4026 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
4027 {
4028 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
4029 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4030 htim->BreakCallback(htim);
4031 #else
4032 HAL_TIMEx_BreakCallback(htim);
4033 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4034 }
4035 }
4036 #if defined(TIM_BDTR_BK2E)
4037 /* TIM Break2 input event */
4038 if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
4039 {
4040 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
4041 {
4042 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
4043 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4044 htim->Break2Callback(htim);
4045 #else
4046 HAL_TIMEx_Break2Callback(htim);
4047 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4048 }
4049 }
4050 #endif /* TIM_BDTR_BK2E */
4051 /* TIM Trigger detection event */
4052 if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
4053 {
4054 if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
4055 {
4056 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
4057 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4058 htim->TriggerCallback(htim);
4059 #else
4060 HAL_TIM_TriggerCallback(htim);
4061 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4062 }
4063 }
4064 /* TIM commutation event */
4065 if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
4066 {
4067 if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
4068 {
4069 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
4070 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4071 htim->CommutationCallback(htim);
4072 #else
4073 HAL_TIMEx_CommutCallback(htim);
4074 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4075 }
4076 }
4077 }
4078
4079 /**
4080 * @}
4081 */
4082
4083 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4084 * @brief TIM Peripheral Control functions
4085 *
4086 @verbatim
4087 ==============================================================================
4088 ##### Peripheral Control functions #####
4089 ==============================================================================
4090 [..]
4091 This section provides functions allowing to:
4092 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4093 (+) Configure External Clock source.
4094 (+) Configure Complementary channels, break features and dead time.
4095 (+) Configure Master and the Slave synchronization.
4096 (+) Configure the DMA Burst Mode.
4097
4098 @endverbatim
4099 * @{
4100 */
4101
4102 /**
4103 * @brief Initializes the TIM Output Compare Channels according to the specified
4104 * parameters in the TIM_OC_InitTypeDef.
4105 * @param htim TIM Output Compare handle
4106 * @param sConfig TIM Output Compare configuration structure
4107 * @param Channel TIM Channels to configure
4108 * This parameter can be one of the following values:
4109 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4110 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4111 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4112 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4113 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
4114 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
4115 * (*) Value not defined for all devices
4116 * @retval HAL status
4117 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4118 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4119 const TIM_OC_InitTypeDef *sConfig,
4120 uint32_t Channel)
4121 {
4122 HAL_StatusTypeDef status = HAL_OK;
4123
4124 /* Check the parameters */
4125 assert_param(IS_TIM_CHANNELS(Channel));
4126 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
4127 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4128
4129 /* Process Locked */
4130 __HAL_LOCK(htim);
4131
4132 switch (Channel)
4133 {
4134 case TIM_CHANNEL_1:
4135 {
4136 /* Check the parameters */
4137 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4138
4139 /* Configure the TIM Channel 1 in Output Compare */
4140 TIM_OC1_SetConfig(htim->Instance, sConfig);
4141 break;
4142 }
4143
4144 case TIM_CHANNEL_2:
4145 {
4146 /* Check the parameters */
4147 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4148
4149 /* Configure the TIM Channel 2 in Output Compare */
4150 TIM_OC2_SetConfig(htim->Instance, sConfig);
4151 break;
4152 }
4153
4154 case TIM_CHANNEL_3:
4155 {
4156 /* Check the parameters */
4157 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4158
4159 /* Configure the TIM Channel 3 in Output Compare */
4160 TIM_OC3_SetConfig(htim->Instance, sConfig);
4161 break;
4162 }
4163
4164 case TIM_CHANNEL_4:
4165 {
4166 /* Check the parameters */
4167 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4168
4169 /* Configure the TIM Channel 4 in Output Compare */
4170 TIM_OC4_SetConfig(htim->Instance, sConfig);
4171 break;
4172 }
4173
4174 #if defined(TIM_CCER_CC5E)
4175 case TIM_CHANNEL_5:
4176 {
4177 /* Check the parameters */
4178 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4179
4180 /* Configure the TIM Channel 5 in Output Compare */
4181 TIM_OC5_SetConfig(htim->Instance, sConfig);
4182 break;
4183 }
4184 #endif /* TIM_CCER_CC5E */
4185
4186 #if defined(TIM_CCER_CC6E)
4187 case TIM_CHANNEL_6:
4188 {
4189 /* Check the parameters */
4190 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4191
4192 /* Configure the TIM Channel 6 in Output Compare */
4193 TIM_OC6_SetConfig(htim->Instance, sConfig);
4194 break;
4195 }
4196 #endif /* TIM_CCER_CC6E */
4197
4198 default:
4199 status = HAL_ERROR;
4200 break;
4201 }
4202
4203 __HAL_UNLOCK(htim);
4204
4205 return status;
4206 }
4207
4208 /**
4209 * @brief Initializes the TIM Input Capture Channels according to the specified
4210 * parameters in the TIM_IC_InitTypeDef.
4211 * @param htim TIM IC handle
4212 * @param sConfig TIM Input Capture configuration structure
4213 * @param Channel TIM Channel to configure
4214 * This parameter can be one of the following values:
4215 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4216 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4217 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4218 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4219 * @retval HAL status
4220 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4221 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4222 {
4223 HAL_StatusTypeDef status = HAL_OK;
4224
4225 /* Check the parameters */
4226 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4227 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4228 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4229 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4230 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4231
4232 /* Process Locked */
4233 __HAL_LOCK(htim);
4234
4235 if (Channel == TIM_CHANNEL_1)
4236 {
4237 /* TI1 Configuration */
4238 TIM_TI1_SetConfig(htim->Instance,
4239 sConfig->ICPolarity,
4240 sConfig->ICSelection,
4241 sConfig->ICFilter);
4242
4243 /* Reset the IC1PSC Bits */
4244 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4245
4246 /* Set the IC1PSC value */
4247 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4248 }
4249 else if (Channel == TIM_CHANNEL_2)
4250 {
4251 /* TI2 Configuration */
4252 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4253
4254 TIM_TI2_SetConfig(htim->Instance,
4255 sConfig->ICPolarity,
4256 sConfig->ICSelection,
4257 sConfig->ICFilter);
4258
4259 /* Reset the IC2PSC Bits */
4260 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4261
4262 /* Set the IC2PSC value */
4263 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4264 }
4265 else if (Channel == TIM_CHANNEL_3)
4266 {
4267 /* TI3 Configuration */
4268 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4269
4270 TIM_TI3_SetConfig(htim->Instance,
4271 sConfig->ICPolarity,
4272 sConfig->ICSelection,
4273 sConfig->ICFilter);
4274
4275 /* Reset the IC3PSC Bits */
4276 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4277
4278 /* Set the IC3PSC value */
4279 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4280 }
4281 else if (Channel == TIM_CHANNEL_4)
4282 {
4283 /* TI4 Configuration */
4284 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4285
4286 TIM_TI4_SetConfig(htim->Instance,
4287 sConfig->ICPolarity,
4288 sConfig->ICSelection,
4289 sConfig->ICFilter);
4290
4291 /* Reset the IC4PSC Bits */
4292 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4293
4294 /* Set the IC4PSC value */
4295 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4296 }
4297 else
4298 {
4299 status = HAL_ERROR;
4300 }
4301
4302 __HAL_UNLOCK(htim);
4303
4304 return status;
4305 }
4306
4307 /**
4308 * @brief Initializes the TIM PWM channels according to the specified
4309 * parameters in the TIM_OC_InitTypeDef.
4310 * @param htim TIM PWM handle
4311 * @param sConfig TIM PWM configuration structure
4312 * @param Channel TIM Channels to be configured
4313 * This parameter can be one of the following values:
4314 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4315 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4316 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4317 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4318 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
4319 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
4320 * (*) Value not defined for all devices
4321 * @retval HAL status
4322 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4323 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4324 const TIM_OC_InitTypeDef *sConfig,
4325 uint32_t Channel)
4326 {
4327 HAL_StatusTypeDef status = HAL_OK;
4328
4329 /* Check the parameters */
4330 assert_param(IS_TIM_CHANNELS(Channel));
4331 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4332 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4333 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4334
4335 /* Process Locked */
4336 __HAL_LOCK(htim);
4337
4338 switch (Channel)
4339 {
4340 case TIM_CHANNEL_1:
4341 {
4342 /* Check the parameters */
4343 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4344
4345 /* Configure the Channel 1 in PWM mode */
4346 TIM_OC1_SetConfig(htim->Instance, sConfig);
4347
4348 /* Set the Preload enable bit for channel1 */
4349 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4350
4351 /* Configure the Output Fast mode */
4352 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4353 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4354 break;
4355 }
4356
4357 case TIM_CHANNEL_2:
4358 {
4359 /* Check the parameters */
4360 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4361
4362 /* Configure the Channel 2 in PWM mode */
4363 TIM_OC2_SetConfig(htim->Instance, sConfig);
4364
4365 /* Set the Preload enable bit for channel2 */
4366 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4367
4368 /* Configure the Output Fast mode */
4369 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4370 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4371 break;
4372 }
4373
4374 case TIM_CHANNEL_3:
4375 {
4376 /* Check the parameters */
4377 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4378
4379 /* Configure the Channel 3 in PWM mode */
4380 TIM_OC3_SetConfig(htim->Instance, sConfig);
4381
4382 /* Set the Preload enable bit for channel3 */
4383 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4384
4385 /* Configure the Output Fast mode */
4386 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4387 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4388 break;
4389 }
4390
4391 case TIM_CHANNEL_4:
4392 {
4393 /* Check the parameters */
4394 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4395
4396 /* Configure the Channel 4 in PWM mode */
4397 TIM_OC4_SetConfig(htim->Instance, sConfig);
4398
4399 /* Set the Preload enable bit for channel4 */
4400 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4401
4402 /* Configure the Output Fast mode */
4403 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4404 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4405 break;
4406 }
4407
4408 #if defined(TIM_CCER_CC5E)
4409 case TIM_CHANNEL_5:
4410 {
4411 /* Check the parameters */
4412 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4413
4414 /* Configure the Channel 5 in PWM mode */
4415 TIM_OC5_SetConfig(htim->Instance, sConfig);
4416
4417 /* Set the Preload enable bit for channel5*/
4418 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4419
4420 /* Configure the Output Fast mode */
4421 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4422 htim->Instance->CCMR3 |= sConfig->OCFastMode;
4423 break;
4424 }
4425 #endif /* TIM_CCER_CC5E */
4426
4427 #if defined(TIM_CCER_CC6E)
4428 case TIM_CHANNEL_6:
4429 {
4430 /* Check the parameters */
4431 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4432
4433 /* Configure the Channel 6 in PWM mode */
4434 TIM_OC6_SetConfig(htim->Instance, sConfig);
4435
4436 /* Set the Preload enable bit for channel6 */
4437 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4438
4439 /* Configure the Output Fast mode */
4440 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4441 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4442 break;
4443 }
4444 #endif /* TIM_CCER_CC6E */
4445
4446 default:
4447 status = HAL_ERROR;
4448 break;
4449 }
4450
4451 __HAL_UNLOCK(htim);
4452
4453 return status;
4454 }
4455
4456 /**
4457 * @brief Initializes the TIM One Pulse Channels according to the specified
4458 * parameters in the TIM_OnePulse_InitTypeDef.
4459 * @param htim TIM One Pulse handle
4460 * @param sConfig TIM One Pulse configuration structure
4461 * @param OutputChannel TIM output channel to configure
4462 * This parameter can be one of the following values:
4463 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4464 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4465 * @param InputChannel TIM input Channel to configure
4466 * This parameter can be one of the following values:
4467 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4468 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4469 * @note To output a waveform with a minimum delay user can enable the fast
4470 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4471 * output is forced in response to the edge detection on TIx input,
4472 * without taking in account the comparison.
4473 * @retval HAL status
4474 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4475 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4476 uint32_t OutputChannel, uint32_t InputChannel)
4477 {
4478 HAL_StatusTypeDef status = HAL_OK;
4479 TIM_OC_InitTypeDef temp1;
4480
4481 /* Check the parameters */
4482 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4483 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4484
4485 if (OutputChannel != InputChannel)
4486 {
4487 /* Process Locked */
4488 __HAL_LOCK(htim);
4489
4490 htim->State = HAL_TIM_STATE_BUSY;
4491
4492 /* Extract the Output compare configuration from sConfig structure */
4493 temp1.OCMode = sConfig->OCMode;
4494 temp1.Pulse = sConfig->Pulse;
4495 temp1.OCPolarity = sConfig->OCPolarity;
4496 temp1.OCNPolarity = sConfig->OCNPolarity;
4497 temp1.OCIdleState = sConfig->OCIdleState;
4498 temp1.OCNIdleState = sConfig->OCNIdleState;
4499
4500 switch (OutputChannel)
4501 {
4502 case TIM_CHANNEL_1:
4503 {
4504 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4505
4506 TIM_OC1_SetConfig(htim->Instance, &temp1);
4507 break;
4508 }
4509
4510 case TIM_CHANNEL_2:
4511 {
4512 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4513
4514 TIM_OC2_SetConfig(htim->Instance, &temp1);
4515 break;
4516 }
4517
4518 default:
4519 status = HAL_ERROR;
4520 break;
4521 }
4522
4523 if (status == HAL_OK)
4524 {
4525 switch (InputChannel)
4526 {
4527 case TIM_CHANNEL_1:
4528 {
4529 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4530
4531 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4532 sConfig->ICSelection, sConfig->ICFilter);
4533
4534 /* Reset the IC1PSC Bits */
4535 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4536
4537 /* Select the Trigger source */
4538 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4539 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4540
4541 /* Select the Slave Mode */
4542 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4543 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4544 break;
4545 }
4546
4547 case TIM_CHANNEL_2:
4548 {
4549 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4550
4551 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4552 sConfig->ICSelection, sConfig->ICFilter);
4553
4554 /* Reset the IC2PSC Bits */
4555 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4556
4557 /* Select the Trigger source */
4558 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4559 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4560
4561 /* Select the Slave Mode */
4562 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4563 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4564 break;
4565 }
4566
4567 default:
4568 status = HAL_ERROR;
4569 break;
4570 }
4571 }
4572
4573 htim->State = HAL_TIM_STATE_READY;
4574
4575 __HAL_UNLOCK(htim);
4576
4577 return status;
4578 }
4579 else
4580 {
4581 return HAL_ERROR;
4582 }
4583 }
4584
4585 #if defined(TIM_DMA_SUPPORT)
4586 /**
4587 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4588 * @param htim TIM handle
4589 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4590 * This parameter can be one of the following values:
4591 * @arg TIM_DMABASE_CR1
4592 * @arg TIM_DMABASE_CR2
4593 * @arg TIM_DMABASE_SMCR
4594 * @arg TIM_DMABASE_DIER
4595 * @arg TIM_DMABASE_SR
4596 * @arg TIM_DMABASE_EGR
4597 * @arg TIM_DMABASE_CCMR1
4598 * @arg TIM_DMABASE_CCMR2
4599 * @arg TIM_DMABASE_CCER
4600 * @arg TIM_DMABASE_CNT
4601 * @arg TIM_DMABASE_PSC
4602 * @arg TIM_DMABASE_ARR
4603 * @arg TIM_DMABASE_RCR
4604 * @arg TIM_DMABASE_CCR1
4605 * @arg TIM_DMABASE_CCR2
4606 * @arg TIM_DMABASE_CCR3
4607 * @arg TIM_DMABASE_CCR4
4608 * @arg TIM_DMABASE_BDTR
4609 * @arg TIM_DMABASE_OR1
4610 * @arg TIM_DMABASE_AF1
4611 * @param BurstRequestSrc TIM DMA Request sources
4612 * This parameter can be one of the following values:
4613 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4614 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4615 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4616 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4617 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4618 * @param BurstBuffer The Buffer address.
4619 * @param BurstLength DMA Burst length. This parameter can be one value
4620 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4621 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4622 * @retval HAL status
4623 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4624 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4625 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
4626 {
4627 HAL_StatusTypeDef status;
4628
4629 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4630 ((BurstLength) >> 8U) + 1U);
4631
4632
4633
4634 return status;
4635 }
4636
4637 /**
4638 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4639 * @param htim TIM handle
4640 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4641 * This parameter can be one of the following values:
4642 * @arg TIM_DMABASE_CR1
4643 * @arg TIM_DMABASE_CR2
4644 * @arg TIM_DMABASE_SMCR
4645 * @arg TIM_DMABASE_DIER
4646 * @arg TIM_DMABASE_SR
4647 * @arg TIM_DMABASE_EGR
4648 * @arg TIM_DMABASE_CCMR1
4649 * @arg TIM_DMABASE_CCMR2
4650 * @arg TIM_DMABASE_CCER
4651 * @arg TIM_DMABASE_CNT
4652 * @arg TIM_DMABASE_PSC
4653 * @arg TIM_DMABASE_ARR
4654 * @arg TIM_DMABASE_RCR
4655 * @arg TIM_DMABASE_CCR1
4656 * @arg TIM_DMABASE_CCR2
4657 * @arg TIM_DMABASE_CCR3
4658 * @arg TIM_DMABASE_CCR4
4659 * @arg TIM_DMABASE_BDTR
4660 * @arg TIM_DMABASE_OR1
4661 * @arg TIM_DMABASE_AF1
4662 * @param BurstRequestSrc TIM DMA Request sources
4663 * This parameter can be one of the following values:
4664 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4665 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4666 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4667 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4668 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4669 * @param BurstBuffer The Buffer address.
4670 * @param BurstLength DMA Burst length. This parameter can be one value
4671 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4672 * @param DataLength Data length. This parameter can be one value
4673 * between 1 and 0xFFFF.
4674 * @retval HAL status
4675 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4676 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4677 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4678 uint32_t BurstLength, uint32_t DataLength)
4679 {
4680 HAL_StatusTypeDef status = HAL_OK;
4681
4682 /* Check the parameters */
4683 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4684 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4685 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4686 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4687 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4688
4689 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4690 {
4691 return HAL_BUSY;
4692 }
4693 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4694 {
4695 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4696 {
4697 return HAL_ERROR;
4698 }
4699 else
4700 {
4701 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4702 }
4703 }
4704 else
4705 {
4706 /* nothing to do */
4707 }
4708
4709 switch (BurstRequestSrc)
4710 {
4711 case TIM_DMA_UPDATE:
4712 {
4713 /* Set the DMA Period elapsed callbacks */
4714 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4715 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4716
4717 /* Set the DMA error callback */
4718 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4719
4720 /* Enable the DMA channel */
4721 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4722 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4723 {
4724 /* Return error status */
4725 return HAL_ERROR;
4726 }
4727 break;
4728 }
4729 case TIM_DMA_CC1:
4730 {
4731 /* Set the DMA compare callbacks */
4732 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4733 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4734
4735 /* Set the DMA error callback */
4736 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4737
4738 /* Enable the DMA channel */
4739 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4740 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4741 {
4742 /* Return error status */
4743 return HAL_ERROR;
4744 }
4745 break;
4746 }
4747 case TIM_DMA_CC2:
4748 {
4749 /* Set the DMA compare callbacks */
4750 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4751 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4752
4753 /* Set the DMA error callback */
4754 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4755
4756 /* Enable the DMA channel */
4757 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4758 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4759 {
4760 /* Return error status */
4761 return HAL_ERROR;
4762 }
4763 break;
4764 }
4765 case TIM_DMA_CC3:
4766 {
4767 /* Set the DMA compare callbacks */
4768 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4769 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4770
4771 /* Set the DMA error callback */
4772 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4773
4774 /* Enable the DMA channel */
4775 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4776 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4777 {
4778 /* Return error status */
4779 return HAL_ERROR;
4780 }
4781 break;
4782 }
4783 case TIM_DMA_CC4:
4784 {
4785 /* Set the DMA compare callbacks */
4786 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4787 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4788
4789 /* Set the DMA error callback */
4790 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4791
4792 /* Enable the DMA channel */
4793 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4794 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4795 {
4796 /* Return error status */
4797 return HAL_ERROR;
4798 }
4799 break;
4800 }
4801 default:
4802 status = HAL_ERROR;
4803 break;
4804 }
4805
4806 if (status == HAL_OK)
4807 {
4808 /* Configure the DMA Burst Mode */
4809 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4810 /* Enable the TIM DMA Request */
4811 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4812 }
4813
4814 /* Return function status */
4815 return status;
4816 }
4817
4818 /**
4819 * @brief Stops the TIM DMA Burst mode
4820 * @param htim TIM handle
4821 * @param BurstRequestSrc TIM DMA Request sources to disable
4822 * @retval HAL status
4823 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4824 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4825 {
4826 HAL_StatusTypeDef status = HAL_OK;
4827
4828 /* Check the parameters */
4829 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4830
4831 /* Abort the DMA transfer (at least disable the DMA channel) */
4832 switch (BurstRequestSrc)
4833 {
4834 case TIM_DMA_UPDATE:
4835 {
4836 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4837 break;
4838 }
4839 case TIM_DMA_CC1:
4840 {
4841 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4842 break;
4843 }
4844 case TIM_DMA_CC2:
4845 {
4846 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4847 break;
4848 }
4849 case TIM_DMA_CC3:
4850 {
4851 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4852 break;
4853 }
4854 case TIM_DMA_CC4:
4855 {
4856 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4857 break;
4858 }
4859 default:
4860 status = HAL_ERROR;
4861 break;
4862 }
4863
4864 if (status == HAL_OK)
4865 {
4866 /* Disable the TIM Update DMA request */
4867 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4868
4869 /* Change the DMA burst operation state */
4870 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4871 }
4872
4873 /* Return function status */
4874 return status;
4875 }
4876
4877 /**
4878 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4879 * @param htim TIM handle
4880 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4881 * This parameter can be one of the following values:
4882 * @arg TIM_DMABASE_CR1
4883 * @arg TIM_DMABASE_CR2
4884 * @arg TIM_DMABASE_SMCR
4885 * @arg TIM_DMABASE_DIER
4886 * @arg TIM_DMABASE_SR
4887 * @arg TIM_DMABASE_EGR
4888 * @arg TIM_DMABASE_CCMR1
4889 * @arg TIM_DMABASE_CCMR2
4890 * @arg TIM_DMABASE_CCER
4891 * @arg TIM_DMABASE_CNT
4892 * @arg TIM_DMABASE_PSC
4893 * @arg TIM_DMABASE_ARR
4894 * @arg TIM_DMABASE_RCR
4895 * @arg TIM_DMABASE_CCR1
4896 * @arg TIM_DMABASE_CCR2
4897 * @arg TIM_DMABASE_CCR3
4898 * @arg TIM_DMABASE_CCR4
4899 * @arg TIM_DMABASE_BDTR
4900 * @arg TIM_DMABASE_OR1
4901 * @arg TIM_DMABASE_AF1
4902 * @param BurstRequestSrc TIM DMA Request sources
4903 * This parameter can be one of the following values:
4904 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4905 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4906 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4907 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4908 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4909 * @param BurstBuffer The Buffer address.
4910 * @param BurstLength DMA Burst length. This parameter can be one value
4911 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4912 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4913 * @retval HAL status
4914 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4915 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4916 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4917 {
4918 HAL_StatusTypeDef status;
4919
4920 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4921 ((BurstLength) >> 8U) + 1U);
4922
4923
4924 return status;
4925 }
4926
4927 /**
4928 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4929 * @param htim TIM handle
4930 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4931 * This parameter can be one of the following values:
4932 * @arg TIM_DMABASE_CR1
4933 * @arg TIM_DMABASE_CR2
4934 * @arg TIM_DMABASE_SMCR
4935 * @arg TIM_DMABASE_DIER
4936 * @arg TIM_DMABASE_SR
4937 * @arg TIM_DMABASE_EGR
4938 * @arg TIM_DMABASE_CCMR1
4939 * @arg TIM_DMABASE_CCMR2
4940 * @arg TIM_DMABASE_CCER
4941 * @arg TIM_DMABASE_CNT
4942 * @arg TIM_DMABASE_PSC
4943 * @arg TIM_DMABASE_ARR
4944 * @arg TIM_DMABASE_RCR
4945 * @arg TIM_DMABASE_CCR1
4946 * @arg TIM_DMABASE_CCR2
4947 * @arg TIM_DMABASE_CCR3
4948 * @arg TIM_DMABASE_CCR4
4949 * @arg TIM_DMABASE_BDTR
4950 * @arg TIM_DMABASE_OR1
4951 * @arg TIM_DMABASE_AF1
4952 * @param BurstRequestSrc TIM DMA Request sources
4953 * This parameter can be one of the following values:
4954 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4955 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4956 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4957 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4958 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4959 * @param BurstBuffer The Buffer address.
4960 * @param BurstLength DMA Burst length. This parameter can be one value
4961 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4962 * @param DataLength Data length. This parameter can be one value
4963 * between 1 and 0xFFFF.
4964 * @retval HAL status
4965 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4966 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4967 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4968 uint32_t BurstLength, uint32_t DataLength)
4969 {
4970 HAL_StatusTypeDef status = HAL_OK;
4971
4972 /* Check the parameters */
4973 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4974 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4975 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4976 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4977 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4978
4979 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4980 {
4981 return HAL_BUSY;
4982 }
4983 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4984 {
4985 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4986 {
4987 return HAL_ERROR;
4988 }
4989 else
4990 {
4991 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4992 }
4993 }
4994 else
4995 {
4996 /* nothing to do */
4997 }
4998 switch (BurstRequestSrc)
4999 {
5000 case TIM_DMA_UPDATE:
5001 {
5002 /* Set the DMA Period elapsed callbacks */
5003 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
5004 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
5005
5006 /* Set the DMA error callback */
5007 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
5008
5009 /* Enable the DMA channel */
5010 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5011 DataLength) != HAL_OK)
5012 {
5013 /* Return error status */
5014 return HAL_ERROR;
5015 }
5016 break;
5017 }
5018 case TIM_DMA_CC1:
5019 {
5020 /* Set the DMA capture callbacks */
5021 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
5022 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5023
5024 /* Set the DMA error callback */
5025 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
5026
5027 /* Enable the DMA channel */
5028 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5029 DataLength) != HAL_OK)
5030 {
5031 /* Return error status */
5032 return HAL_ERROR;
5033 }
5034 break;
5035 }
5036 case TIM_DMA_CC2:
5037 {
5038 /* Set the DMA capture callbacks */
5039 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
5040 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5041
5042 /* Set the DMA error callback */
5043 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
5044
5045 /* Enable the DMA channel */
5046 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5047 DataLength) != HAL_OK)
5048 {
5049 /* Return error status */
5050 return HAL_ERROR;
5051 }
5052 break;
5053 }
5054 case TIM_DMA_CC3:
5055 {
5056 /* Set the DMA capture callbacks */
5057 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
5058 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5059
5060 /* Set the DMA error callback */
5061 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
5062
5063 /* Enable the DMA channel */
5064 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5065 DataLength) != HAL_OK)
5066 {
5067 /* Return error status */
5068 return HAL_ERROR;
5069 }
5070 break;
5071 }
5072 case TIM_DMA_CC4:
5073 {
5074 /* Set the DMA capture callbacks */
5075 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
5076 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5077
5078 /* Set the DMA error callback */
5079 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
5080
5081 /* Enable the DMA channel */
5082 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5083 DataLength) != HAL_OK)
5084 {
5085 /* Return error status */
5086 return HAL_ERROR;
5087 }
5088 break;
5089 }
5090 default:
5091 status = HAL_ERROR;
5092 break;
5093 }
5094
5095 if (status == HAL_OK)
5096 {
5097 /* Configure the DMA Burst Mode */
5098 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
5099
5100 /* Enable the TIM DMA Request */
5101 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5102 }
5103
5104 /* Return function status */
5105 return status;
5106 }
5107
5108 /**
5109 * @brief Stop the DMA burst reading
5110 * @param htim TIM handle
5111 * @param BurstRequestSrc TIM DMA Request sources to disable.
5112 * @retval HAL status
5113 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5114 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5115 {
5116 HAL_StatusTypeDef status = HAL_OK;
5117
5118 /* Check the parameters */
5119 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5120
5121 /* Abort the DMA transfer (at least disable the DMA channel) */
5122 switch (BurstRequestSrc)
5123 {
5124 case TIM_DMA_UPDATE:
5125 {
5126 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5127 break;
5128 }
5129 case TIM_DMA_CC1:
5130 {
5131 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5132 break;
5133 }
5134 case TIM_DMA_CC2:
5135 {
5136 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5137 break;
5138 }
5139 case TIM_DMA_CC3:
5140 {
5141 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5142 break;
5143 }
5144 case TIM_DMA_CC4:
5145 {
5146 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5147 break;
5148 }
5149 default:
5150 status = HAL_ERROR;
5151 break;
5152 }
5153
5154 if (status == HAL_OK)
5155 {
5156 /* Disable the TIM Update DMA request */
5157 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5158
5159 /* Change the DMA burst operation state */
5160 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5161 }
5162
5163 /* Return function status */
5164 return status;
5165 }
5166 #endif /* TIM_DMA_SUPPORT */
5167
5168 /**
5169 * @brief Generate a software event
5170 * @param htim TIM handle
5171 * @param EventSource specifies the event source.
5172 * This parameter can be one of the following values:
5173 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5174 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5175 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5176 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5177 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5178 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5179 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5180 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5181 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5182 * @note Basic timers can only generate an update event.
5183 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5184 * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
5185 * supporting a break input.
5186 * @retval HAL status
5187 */
5188
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5189 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5190 {
5191 /* Check the parameters */
5192 assert_param(IS_TIM_INSTANCE(htim->Instance));
5193 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5194
5195 /* Process Locked */
5196 __HAL_LOCK(htim);
5197
5198 /* Change the TIM state */
5199 htim->State = HAL_TIM_STATE_BUSY;
5200
5201 /* Set the event sources */
5202 htim->Instance->EGR = EventSource;
5203
5204 /* Change the TIM state */
5205 htim->State = HAL_TIM_STATE_READY;
5206
5207 __HAL_UNLOCK(htim);
5208
5209 /* Return function status */
5210 return HAL_OK;
5211 }
5212
5213 /**
5214 * @brief Configures the OCRef clear feature
5215 * @param htim TIM handle
5216 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5217 * contains the OCREF clear feature and parameters for the TIM peripheral.
5218 * @param Channel specifies the TIM Channel
5219 * This parameter can be one of the following values:
5220 * @arg TIM_CHANNEL_1: TIM Channel 1
5221 * @arg TIM_CHANNEL_2: TIM Channel 2
5222 * @arg TIM_CHANNEL_3: TIM Channel 3
5223 * @arg TIM_CHANNEL_4: TIM Channel 4
5224 * @arg TIM_CHANNEL_5: TIM Channel 5 (*)
5225 * @arg TIM_CHANNEL_6: TIM Channel 6 (*)
5226 * (*) Value not defined for all devices
5227 * @retval HAL status
5228 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5229 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5230 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5231 uint32_t Channel)
5232 {
5233 HAL_StatusTypeDef status = HAL_OK;
5234
5235 /* Check the parameters */
5236 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5237 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5238
5239 /* Process Locked */
5240 __HAL_LOCK(htim);
5241
5242 htim->State = HAL_TIM_STATE_BUSY;
5243
5244 switch (sClearInputConfig->ClearInputSource)
5245 {
5246 case TIM_CLEARINPUTSOURCE_NONE:
5247 {
5248 /* Clear the OCREF clear selection bit and the the ETR Bits */
5249 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5250 break;
5251 }
5252
5253 case TIM_CLEARINPUTSOURCE_ETR:
5254 {
5255 /* Check the parameters */
5256 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5257 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5258 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5259
5260 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5261 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5262 {
5263 htim->State = HAL_TIM_STATE_READY;
5264 __HAL_UNLOCK(htim);
5265 return HAL_ERROR;
5266 }
5267
5268 TIM_ETR_SetConfig(htim->Instance,
5269 sClearInputConfig->ClearInputPrescaler,
5270 sClearInputConfig->ClearInputPolarity,
5271 sClearInputConfig->ClearInputFilter);
5272
5273 /* Set the OCREF clear selection bit */
5274 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5275 break;
5276 }
5277
5278 default:
5279 status = HAL_ERROR;
5280 break;
5281 }
5282
5283 if (status == HAL_OK)
5284 {
5285 switch (Channel)
5286 {
5287 case TIM_CHANNEL_1:
5288 {
5289 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5290 {
5291 /* Enable the OCREF clear feature for Channel 1 */
5292 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5293 }
5294 else
5295 {
5296 /* Disable the OCREF clear feature for Channel 1 */
5297 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5298 }
5299 break;
5300 }
5301 case TIM_CHANNEL_2:
5302 {
5303 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5304 {
5305 /* Enable the OCREF clear feature for Channel 2 */
5306 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5307 }
5308 else
5309 {
5310 /* Disable the OCREF clear feature for Channel 2 */
5311 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5312 }
5313 break;
5314 }
5315 case TIM_CHANNEL_3:
5316 {
5317 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5318 {
5319 /* Enable the OCREF clear feature for Channel 3 */
5320 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5321 }
5322 else
5323 {
5324 /* Disable the OCREF clear feature for Channel 3 */
5325 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5326 }
5327 break;
5328 }
5329 case TIM_CHANNEL_4:
5330 {
5331 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5332 {
5333 /* Enable the OCREF clear feature for Channel 4 */
5334 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5335 }
5336 else
5337 {
5338 /* Disable the OCREF clear feature for Channel 4 */
5339 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5340 }
5341 break;
5342 }
5343 #if defined(TIM_CCER_CC5E)
5344 case TIM_CHANNEL_5:
5345 {
5346 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5347 {
5348 /* Enable the OCREF clear feature for Channel 5 */
5349 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5350 }
5351 else
5352 {
5353 /* Disable the OCREF clear feature for Channel 5 */
5354 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5355 }
5356 break;
5357 }
5358 #endif /* TIM_CCER_CC5E */
5359 #if defined(TIM_CCER_CC6E)
5360 case TIM_CHANNEL_6:
5361 {
5362 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5363 {
5364 /* Enable the OCREF clear feature for Channel 6 */
5365 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5366 }
5367 else
5368 {
5369 /* Disable the OCREF clear feature for Channel 6 */
5370 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5371 }
5372 break;
5373 }
5374 #endif /* TIM_CCER_CC6E */
5375 default:
5376 break;
5377 }
5378 }
5379
5380 htim->State = HAL_TIM_STATE_READY;
5381
5382 __HAL_UNLOCK(htim);
5383
5384 return status;
5385 }
5386
5387 /**
5388 * @brief Configures the clock source to be used
5389 * @param htim TIM handle
5390 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5391 * contains the clock source information for the TIM peripheral.
5392 * @retval HAL status
5393 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5394 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5395 {
5396 HAL_StatusTypeDef status = HAL_OK;
5397 uint32_t tmpsmcr;
5398
5399 /* Process Locked */
5400 __HAL_LOCK(htim);
5401
5402 htim->State = HAL_TIM_STATE_BUSY;
5403
5404 /* Check the parameters */
5405 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5406
5407 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5408 tmpsmcr = htim->Instance->SMCR;
5409 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5410 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5411 htim->Instance->SMCR = tmpsmcr;
5412
5413 switch (sClockSourceConfig->ClockSource)
5414 {
5415 case TIM_CLOCKSOURCE_INTERNAL:
5416 {
5417 assert_param(IS_TIM_INSTANCE(htim->Instance));
5418 break;
5419 }
5420
5421 case TIM_CLOCKSOURCE_ETRMODE1:
5422 {
5423 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5424 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5425
5426 /* Check ETR input conditioning related parameters */
5427 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5428 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5429 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5430
5431 /* Configure the ETR Clock source */
5432 TIM_ETR_SetConfig(htim->Instance,
5433 sClockSourceConfig->ClockPrescaler,
5434 sClockSourceConfig->ClockPolarity,
5435 sClockSourceConfig->ClockFilter);
5436
5437 /* Select the External clock mode1 and the ETRF trigger */
5438 tmpsmcr = htim->Instance->SMCR;
5439 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5440 /* Write to TIMx SMCR */
5441 htim->Instance->SMCR = tmpsmcr;
5442 break;
5443 }
5444
5445 case TIM_CLOCKSOURCE_ETRMODE2:
5446 {
5447 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5448 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5449
5450 /* Check ETR input conditioning related parameters */
5451 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5452 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5453 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5454
5455 /* Configure the ETR Clock source */
5456 TIM_ETR_SetConfig(htim->Instance,
5457 sClockSourceConfig->ClockPrescaler,
5458 sClockSourceConfig->ClockPolarity,
5459 sClockSourceConfig->ClockFilter);
5460 /* Enable the External clock mode2 */
5461 htim->Instance->SMCR |= TIM_SMCR_ECE;
5462 break;
5463 }
5464
5465 case TIM_CLOCKSOURCE_TI1:
5466 {
5467 /* Check whether or not the timer instance supports external clock mode 1 */
5468 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5469
5470 /* Check TI1 input conditioning related parameters */
5471 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5472 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5473
5474 TIM_TI1_ConfigInputStage(htim->Instance,
5475 sClockSourceConfig->ClockPolarity,
5476 sClockSourceConfig->ClockFilter);
5477 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5478 break;
5479 }
5480
5481 case TIM_CLOCKSOURCE_TI2:
5482 {
5483 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5484 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5485
5486 /* Check TI2 input conditioning related parameters */
5487 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5488 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5489
5490 TIM_TI2_ConfigInputStage(htim->Instance,
5491 sClockSourceConfig->ClockPolarity,
5492 sClockSourceConfig->ClockFilter);
5493 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5494 break;
5495 }
5496
5497 case TIM_CLOCKSOURCE_TI1ED:
5498 {
5499 /* Check whether or not the timer instance supports external clock mode 1 */
5500 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5501
5502 /* Check TI1 input conditioning related parameters */
5503 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5504 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5505
5506 TIM_TI1_ConfigInputStage(htim->Instance,
5507 sClockSourceConfig->ClockPolarity,
5508 sClockSourceConfig->ClockFilter);
5509 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5510 break;
5511 }
5512
5513
5514 default:
5515 status = HAL_ERROR;
5516 break;
5517 }
5518 htim->State = HAL_TIM_STATE_READY;
5519
5520 __HAL_UNLOCK(htim);
5521
5522 return status;
5523 }
5524
5525 /**
5526 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5527 * or a XOR combination between CH1_input, CH2_input & CH3_input
5528 * @param htim TIM handle.
5529 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5530 * output of a XOR gate.
5531 * This parameter can be one of the following values:
5532 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5533 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5534 * pins are connected to the TI1 input (XOR combination)
5535 * @retval HAL status
5536 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5537 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5538 {
5539 uint32_t tmpcr2;
5540
5541 /* Check the parameters */
5542 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5543 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5544
5545 /* Get the TIMx CR2 register value */
5546 tmpcr2 = htim->Instance->CR2;
5547
5548 /* Reset the TI1 selection */
5549 tmpcr2 &= ~TIM_CR2_TI1S;
5550
5551 /* Set the TI1 selection */
5552 tmpcr2 |= TI1_Selection;
5553
5554 /* Write to TIMxCR2 */
5555 htim->Instance->CR2 = tmpcr2;
5556
5557 return HAL_OK;
5558 }
5559
5560 /**
5561 * @brief Configures the TIM in Slave mode
5562 * @param htim TIM handle.
5563 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5564 * contains the selected trigger (internal trigger input, filtered
5565 * timer input or external trigger input) and the Slave mode
5566 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5567 * @retval HAL status
5568 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5569 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5570 {
5571 /* Check the parameters */
5572 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5573 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5574 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5575
5576 __HAL_LOCK(htim);
5577
5578 htim->State = HAL_TIM_STATE_BUSY;
5579
5580 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5581 {
5582 htim->State = HAL_TIM_STATE_READY;
5583 __HAL_UNLOCK(htim);
5584 return HAL_ERROR;
5585 }
5586
5587 /* Disable Trigger Interrupt */
5588 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5589
5590
5591 htim->State = HAL_TIM_STATE_READY;
5592
5593 __HAL_UNLOCK(htim);
5594
5595 return HAL_OK;
5596 }
5597
5598 /**
5599 * @brief Configures the TIM in Slave mode in interrupt mode
5600 * @param htim TIM handle.
5601 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5602 * contains the selected trigger (internal trigger input, filtered
5603 * timer input or external trigger input) and the Slave mode
5604 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5605 * @retval HAL status
5606 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5607 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5608 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5609 {
5610 /* Check the parameters */
5611 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5612 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5613 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5614
5615 __HAL_LOCK(htim);
5616
5617 htim->State = HAL_TIM_STATE_BUSY;
5618
5619 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5620 {
5621 htim->State = HAL_TIM_STATE_READY;
5622 __HAL_UNLOCK(htim);
5623 return HAL_ERROR;
5624 }
5625
5626 /* Enable Trigger Interrupt */
5627 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5628
5629
5630 htim->State = HAL_TIM_STATE_READY;
5631
5632 __HAL_UNLOCK(htim);
5633
5634 return HAL_OK;
5635 }
5636
5637 /**
5638 * @brief Read the captured value from Capture Compare unit
5639 * @param htim TIM handle.
5640 * @param Channel TIM Channels to be enabled
5641 * This parameter can be one of the following values:
5642 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5643 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5644 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5645 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5646 * @retval Captured value
5647 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)5648 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
5649 {
5650 uint32_t tmpreg = 0U;
5651
5652 switch (Channel)
5653 {
5654 case TIM_CHANNEL_1:
5655 {
5656 /* Check the parameters */
5657 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5658
5659 /* Return the capture 1 value */
5660 tmpreg = htim->Instance->CCR1;
5661
5662 break;
5663 }
5664 case TIM_CHANNEL_2:
5665 {
5666 /* Check the parameters */
5667 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5668
5669 /* Return the capture 2 value */
5670 tmpreg = htim->Instance->CCR2;
5671
5672 break;
5673 }
5674
5675 case TIM_CHANNEL_3:
5676 {
5677 /* Check the parameters */
5678 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5679
5680 /* Return the capture 3 value */
5681 tmpreg = htim->Instance->CCR3;
5682
5683 break;
5684 }
5685
5686 case TIM_CHANNEL_4:
5687 {
5688 /* Check the parameters */
5689 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5690
5691 /* Return the capture 4 value */
5692 tmpreg = htim->Instance->CCR4;
5693
5694 break;
5695 }
5696
5697 default:
5698 break;
5699 }
5700
5701 return tmpreg;
5702 }
5703
5704 /**
5705 * @}
5706 */
5707
5708 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5709 * @brief TIM Callbacks functions
5710 *
5711 @verbatim
5712 ==============================================================================
5713 ##### TIM Callbacks functions #####
5714 ==============================================================================
5715 [..]
5716 This section provides TIM callback functions:
5717 (+) TIM Period elapsed callback
5718 (+) TIM Output Compare callback
5719 (+) TIM Input capture callback
5720 (+) TIM Trigger callback
5721 (+) TIM Error callback
5722
5723 @endverbatim
5724 * @{
5725 */
5726
5727 /**
5728 * @brief Period elapsed callback in non-blocking mode
5729 * @param htim TIM handle
5730 * @retval None
5731 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5732 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5733 {
5734 /* Prevent unused argument(s) compilation warning */
5735 UNUSED(htim);
5736
5737 /* NOTE : This function should not be modified, when the callback is needed,
5738 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5739 */
5740 }
5741
5742 #if defined(TIM_DMA_SUPPORT)
5743 /**
5744 * @brief Period elapsed half complete callback in non-blocking mode
5745 * @param htim TIM handle
5746 * @retval None
5747 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5748 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5749 {
5750 /* Prevent unused argument(s) compilation warning */
5751 UNUSED(htim);
5752
5753 /* NOTE : This function should not be modified, when the callback is needed,
5754 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5755 */
5756 }
5757 #endif /* TIM_DMA_SUPPORT */
5758
5759 /**
5760 * @brief Output Compare callback in non-blocking mode
5761 * @param htim TIM OC handle
5762 * @retval None
5763 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5764 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5765 {
5766 /* Prevent unused argument(s) compilation warning */
5767 UNUSED(htim);
5768
5769 /* NOTE : This function should not be modified, when the callback is needed,
5770 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5771 */
5772 }
5773
5774 /**
5775 * @brief Input Capture callback in non-blocking mode
5776 * @param htim TIM IC handle
5777 * @retval None
5778 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5779 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5780 {
5781 /* Prevent unused argument(s) compilation warning */
5782 UNUSED(htim);
5783
5784 /* NOTE : This function should not be modified, when the callback is needed,
5785 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5786 */
5787 }
5788
5789 #if defined(TIM_DMA_SUPPORT)
5790 /**
5791 * @brief Input Capture half complete callback in non-blocking mode
5792 * @param htim TIM IC handle
5793 * @retval None
5794 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5795 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5796 {
5797 /* Prevent unused argument(s) compilation warning */
5798 UNUSED(htim);
5799
5800 /* NOTE : This function should not be modified, when the callback is needed,
5801 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5802 */
5803 }
5804 #endif /* TIM_DMA_SUPPORT */
5805
5806 /**
5807 * @brief PWM Pulse finished callback in non-blocking mode
5808 * @param htim TIM handle
5809 * @retval None
5810 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5811 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5812 {
5813 /* Prevent unused argument(s) compilation warning */
5814 UNUSED(htim);
5815
5816 /* NOTE : This function should not be modified, when the callback is needed,
5817 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5818 */
5819 }
5820
5821 #if defined(TIM_DMA_SUPPORT)
5822 /**
5823 * @brief PWM Pulse finished half complete callback in non-blocking mode
5824 * @param htim TIM handle
5825 * @retval None
5826 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5827 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5828 {
5829 /* Prevent unused argument(s) compilation warning */
5830 UNUSED(htim);
5831
5832 /* NOTE : This function should not be modified, when the callback is needed,
5833 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5834 */
5835 }
5836 #endif /* TIM_DMA_SUPPORT */
5837
5838 /**
5839 * @brief Hall Trigger detection callback in non-blocking mode
5840 * @param htim TIM handle
5841 * @retval None
5842 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5843 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5844 {
5845 /* Prevent unused argument(s) compilation warning */
5846 UNUSED(htim);
5847
5848 /* NOTE : This function should not be modified, when the callback is needed,
5849 the HAL_TIM_TriggerCallback could be implemented in the user file
5850 */
5851 }
5852
5853 #if defined(TIM_DMA_SUPPORT)
5854 /**
5855 * @brief Timer error callback in non-blocking mode
5856 * @param htim TIM handle
5857 * @retval None
5858 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5859 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5860 {
5861 /* Prevent unused argument(s) compilation warning */
5862 UNUSED(htim);
5863
5864 /* NOTE : This function should not be modified, when the callback is needed,
5865 the HAL_TIM_ErrorCallback could be implemented in the user file
5866 */
5867 }
5868 #endif /* TIM_DMA_SUPPORT */
5869
5870 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5871 /**
5872 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5873 * @param htim tim handle
5874 * @param CallbackID ID of the callback to be registered
5875 * This parameter can be one of the following values:
5876 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5877 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5878 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5879 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5880 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5881 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5882 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5883 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5884 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5885 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5886 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5887 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5888 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5889 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5890 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5891 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5892 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5893 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5894 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5895 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5896 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5897 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5898 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5899 #if defined(TIM_BDTR_BK2E)
5900 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5901 #endif
5902 * @param pCallback pointer to the callback function
5903 * @retval status
5904 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5905 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5906 pTIM_CallbackTypeDef pCallback)
5907 {
5908 HAL_StatusTypeDef status = HAL_OK;
5909
5910 if (pCallback == NULL)
5911 {
5912 return HAL_ERROR;
5913 }
5914
5915 if (htim->State == HAL_TIM_STATE_READY)
5916 {
5917 switch (CallbackID)
5918 {
5919 case HAL_TIM_BASE_MSPINIT_CB_ID :
5920 htim->Base_MspInitCallback = pCallback;
5921 break;
5922
5923 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5924 htim->Base_MspDeInitCallback = pCallback;
5925 break;
5926
5927 case HAL_TIM_IC_MSPINIT_CB_ID :
5928 htim->IC_MspInitCallback = pCallback;
5929 break;
5930
5931 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5932 htim->IC_MspDeInitCallback = pCallback;
5933 break;
5934
5935 case HAL_TIM_OC_MSPINIT_CB_ID :
5936 htim->OC_MspInitCallback = pCallback;
5937 break;
5938
5939 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5940 htim->OC_MspDeInitCallback = pCallback;
5941 break;
5942
5943 case HAL_TIM_PWM_MSPINIT_CB_ID :
5944 htim->PWM_MspInitCallback = pCallback;
5945 break;
5946
5947 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5948 htim->PWM_MspDeInitCallback = pCallback;
5949 break;
5950
5951 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5952 htim->OnePulse_MspInitCallback = pCallback;
5953 break;
5954
5955 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5956 htim->OnePulse_MspDeInitCallback = pCallback;
5957 break;
5958
5959 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5960 htim->Encoder_MspInitCallback = pCallback;
5961 break;
5962
5963 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5964 htim->Encoder_MspDeInitCallback = pCallback;
5965 break;
5966
5967 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5968 htim->PeriodElapsedCallback = pCallback;
5969 break;
5970
5971 #if defined(TIM_DMA_SUPPORT)
5972 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5973 htim->PeriodElapsedHalfCpltCallback = pCallback;
5974 break;
5975 #endif /* TIM_DMA_SUPPORT */
5976
5977 case HAL_TIM_TRIGGER_CB_ID :
5978 htim->TriggerCallback = pCallback;
5979 break;
5980
5981 case HAL_TIM_IC_CAPTURE_CB_ID :
5982 htim->IC_CaptureCallback = pCallback;
5983 break;
5984
5985 #if defined(TIM_DMA_SUPPORT)
5986 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5987 htim->IC_CaptureHalfCpltCallback = pCallback;
5988 break;
5989 #endif /* TIM_DMA_SUPPORT */
5990
5991 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5992 htim->OC_DelayElapsedCallback = pCallback;
5993 break;
5994
5995 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5996 htim->PWM_PulseFinishedCallback = pCallback;
5997 break;
5998
5999 #if defined(TIM_DMA_SUPPORT)
6000 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6001 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
6002 break;
6003
6004 case HAL_TIM_ERROR_CB_ID :
6005 htim->ErrorCallback = pCallback;
6006 break;
6007 #endif /* TIM_DMA_SUPPORT */
6008
6009 case HAL_TIM_COMMUTATION_CB_ID :
6010 htim->CommutationCallback = pCallback;
6011 break;
6012
6013 case HAL_TIM_BREAK_CB_ID :
6014 htim->BreakCallback = pCallback;
6015 break;
6016 #if defined(TIM_BDTR_BK2E)
6017
6018 case HAL_TIM_BREAK2_CB_ID :
6019 htim->Break2Callback = pCallback;
6020 break;
6021 #endif /* TIM_BDTR_BK2E */
6022
6023 default :
6024 /* Return error status */
6025 status = HAL_ERROR;
6026 break;
6027 }
6028 }
6029 else if (htim->State == HAL_TIM_STATE_RESET)
6030 {
6031 switch (CallbackID)
6032 {
6033 case HAL_TIM_BASE_MSPINIT_CB_ID :
6034 htim->Base_MspInitCallback = pCallback;
6035 break;
6036
6037 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6038 htim->Base_MspDeInitCallback = pCallback;
6039 break;
6040
6041 case HAL_TIM_IC_MSPINIT_CB_ID :
6042 htim->IC_MspInitCallback = pCallback;
6043 break;
6044
6045 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6046 htim->IC_MspDeInitCallback = pCallback;
6047 break;
6048
6049 case HAL_TIM_OC_MSPINIT_CB_ID :
6050 htim->OC_MspInitCallback = pCallback;
6051 break;
6052
6053 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6054 htim->OC_MspDeInitCallback = pCallback;
6055 break;
6056
6057 case HAL_TIM_PWM_MSPINIT_CB_ID :
6058 htim->PWM_MspInitCallback = pCallback;
6059 break;
6060
6061 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6062 htim->PWM_MspDeInitCallback = pCallback;
6063 break;
6064
6065 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6066 htim->OnePulse_MspInitCallback = pCallback;
6067 break;
6068
6069 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6070 htim->OnePulse_MspDeInitCallback = pCallback;
6071 break;
6072
6073 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6074 htim->Encoder_MspInitCallback = pCallback;
6075 break;
6076
6077 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6078 htim->Encoder_MspDeInitCallback = pCallback;
6079 break;
6080
6081 default :
6082 /* Return error status */
6083 status = HAL_ERROR;
6084 break;
6085 }
6086 }
6087 else
6088 {
6089 /* Return error status */
6090 status = HAL_ERROR;
6091 }
6092
6093 return status;
6094 }
6095
6096 /**
6097 * @brief Unregister a TIM callback
6098 * TIM callback is redirected to the weak predefined callback
6099 * @param htim tim handle
6100 * @param CallbackID ID of the callback to be unregistered
6101 * This parameter can be one of the following values:
6102 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6103 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6104 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6105 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6106 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6107 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6108 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6109 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6110 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6111 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6112 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6113 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6114 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6115 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6116 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6117 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6118 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6119 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6120 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6121 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6122 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6123 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6124 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6125 #if defined(TIM_BDTR_BK2E)
6126 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6127 #endif
6128 * @retval status
6129 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6130 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6131 {
6132 HAL_StatusTypeDef status = HAL_OK;
6133
6134 if (htim->State == HAL_TIM_STATE_READY)
6135 {
6136 switch (CallbackID)
6137 {
6138 case HAL_TIM_BASE_MSPINIT_CB_ID :
6139 /* Legacy weak Base MspInit Callback */
6140 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6141 break;
6142
6143 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6144 /* Legacy weak Base Msp DeInit Callback */
6145 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6146 break;
6147
6148 case HAL_TIM_IC_MSPINIT_CB_ID :
6149 /* Legacy weak IC Msp Init Callback */
6150 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6151 break;
6152
6153 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6154 /* Legacy weak IC Msp DeInit Callback */
6155 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6156 break;
6157
6158 case HAL_TIM_OC_MSPINIT_CB_ID :
6159 /* Legacy weak OC Msp Init Callback */
6160 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6161 break;
6162
6163 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6164 /* Legacy weak OC Msp DeInit Callback */
6165 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6166 break;
6167
6168 case HAL_TIM_PWM_MSPINIT_CB_ID :
6169 /* Legacy weak PWM Msp Init Callback */
6170 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6171 break;
6172
6173 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6174 /* Legacy weak PWM Msp DeInit Callback */
6175 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6176 break;
6177
6178 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6179 /* Legacy weak One Pulse Msp Init Callback */
6180 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6181 break;
6182
6183 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6184 /* Legacy weak One Pulse Msp DeInit Callback */
6185 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6186 break;
6187
6188 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6189 /* Legacy weak Encoder Msp Init Callback */
6190 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6191 break;
6192
6193 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6194 /* Legacy weak Encoder Msp DeInit Callback */
6195 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6196 break;
6197
6198 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6199 /* Legacy weak Period Elapsed Callback */
6200 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6201 break;
6202
6203 #if defined(TIM_DMA_SUPPORT)
6204 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6205 /* Legacy weak Period Elapsed half complete Callback */
6206 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6207 break;
6208 #endif /* TIM_DMA_SUPPORT */
6209
6210 case HAL_TIM_TRIGGER_CB_ID :
6211 /* Legacy weak Trigger Callback */
6212 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6213 break;
6214
6215 case HAL_TIM_IC_CAPTURE_CB_ID :
6216 /* Legacy weak IC Capture Callback */
6217 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6218 break;
6219
6220 #if defined(TIM_DMA_SUPPORT)
6221 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6222 /* Legacy weak IC Capture half complete Callback */
6223 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6224 break;
6225 #endif /* TIM_DMA_SUPPORT */
6226
6227 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6228 /* Legacy weak OC Delay Elapsed Callback */
6229 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6230 break;
6231
6232 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6233 /* Legacy weak PWM Pulse Finished Callback */
6234 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6235 break;
6236
6237 #if defined(TIM_DMA_SUPPORT)
6238 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6239 /* Legacy weak PWM Pulse Finished half complete Callback */
6240 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6241 break;
6242
6243 case HAL_TIM_ERROR_CB_ID :
6244 /* Legacy weak Error Callback */
6245 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6246 break;
6247 #endif /* TIM_DMA_SUPPORT */
6248
6249 case HAL_TIM_COMMUTATION_CB_ID :
6250 /* Legacy weak Commutation Callback */
6251 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6252 break;
6253
6254 case HAL_TIM_BREAK_CB_ID :
6255 /* Legacy weak Break Callback */
6256 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6257 break;
6258 #if defined(TIM_BDTR_BK2E)
6259
6260 case HAL_TIM_BREAK2_CB_ID :
6261 /* Legacy weak Break2 Callback */
6262 htim->Break2Callback = HAL_TIMEx_Break2Callback;
6263 break;
6264 #endif /* TIM_BDTR_BK2E */
6265
6266 default :
6267 /* Return error status */
6268 status = HAL_ERROR;
6269 break;
6270 }
6271 }
6272 else if (htim->State == HAL_TIM_STATE_RESET)
6273 {
6274 switch (CallbackID)
6275 {
6276 case HAL_TIM_BASE_MSPINIT_CB_ID :
6277 /* Legacy weak Base MspInit Callback */
6278 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6279 break;
6280
6281 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6282 /* Legacy weak Base Msp DeInit Callback */
6283 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6284 break;
6285
6286 case HAL_TIM_IC_MSPINIT_CB_ID :
6287 /* Legacy weak IC Msp Init Callback */
6288 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6289 break;
6290
6291 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6292 /* Legacy weak IC Msp DeInit Callback */
6293 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6294 break;
6295
6296 case HAL_TIM_OC_MSPINIT_CB_ID :
6297 /* Legacy weak OC Msp Init Callback */
6298 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6299 break;
6300
6301 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6302 /* Legacy weak OC Msp DeInit Callback */
6303 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6304 break;
6305
6306 case HAL_TIM_PWM_MSPINIT_CB_ID :
6307 /* Legacy weak PWM Msp Init Callback */
6308 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6309 break;
6310
6311 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6312 /* Legacy weak PWM Msp DeInit Callback */
6313 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6314 break;
6315
6316 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6317 /* Legacy weak One Pulse Msp Init Callback */
6318 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6319 break;
6320
6321 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6322 /* Legacy weak One Pulse Msp DeInit Callback */
6323 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6324 break;
6325
6326 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6327 /* Legacy weak Encoder Msp Init Callback */
6328 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6329 break;
6330
6331 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6332 /* Legacy weak Encoder Msp DeInit Callback */
6333 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6334 break;
6335
6336 default :
6337 /* Return error status */
6338 status = HAL_ERROR;
6339 break;
6340 }
6341 }
6342 else
6343 {
6344 /* Return error status */
6345 status = HAL_ERROR;
6346 }
6347
6348 return status;
6349 }
6350 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6351
6352 /**
6353 * @}
6354 */
6355
6356 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6357 * @brief TIM Peripheral State functions
6358 *
6359 @verbatim
6360 ==============================================================================
6361 ##### Peripheral State functions #####
6362 ==============================================================================
6363 [..]
6364 This subsection permits to get in run-time the status of the peripheral
6365 and the data flow.
6366
6367 @endverbatim
6368 * @{
6369 */
6370
6371 /**
6372 * @brief Return the TIM Base handle state.
6373 * @param htim TIM Base handle
6374 * @retval HAL state
6375 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6376 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6377 {
6378 return htim->State;
6379 }
6380
6381 /**
6382 * @brief Return the TIM OC handle state.
6383 * @param htim TIM Output Compare handle
6384 * @retval HAL state
6385 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6386 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6387 {
6388 return htim->State;
6389 }
6390
6391 /**
6392 * @brief Return the TIM PWM handle state.
6393 * @param htim TIM handle
6394 * @retval HAL state
6395 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6396 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6397 {
6398 return htim->State;
6399 }
6400
6401 /**
6402 * @brief Return the TIM Input Capture handle state.
6403 * @param htim TIM IC handle
6404 * @retval HAL state
6405 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6406 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6407 {
6408 return htim->State;
6409 }
6410
6411 /**
6412 * @brief Return the TIM One Pulse Mode handle state.
6413 * @param htim TIM OPM handle
6414 * @retval HAL state
6415 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6416 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6417 {
6418 return htim->State;
6419 }
6420
6421 /**
6422 * @brief Return the TIM Encoder Mode handle state.
6423 * @param htim TIM Encoder Interface handle
6424 * @retval HAL state
6425 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6426 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6427 {
6428 return htim->State;
6429 }
6430
6431 /**
6432 * @brief Return the TIM Encoder Mode handle state.
6433 * @param htim TIM handle
6434 * @retval Active channel
6435 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6436 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6437 {
6438 return htim->Channel;
6439 }
6440
6441 /**
6442 * @brief Return actual state of the TIM channel.
6443 * @param htim TIM handle
6444 * @param Channel TIM Channel
6445 * This parameter can be one of the following values:
6446 * @arg TIM_CHANNEL_1: TIM Channel 1
6447 * @arg TIM_CHANNEL_2: TIM Channel 2
6448 * @arg TIM_CHANNEL_3: TIM Channel 3
6449 * @arg TIM_CHANNEL_4: TIM Channel 4
6450 * @arg TIM_CHANNEL_5: TIM Channel 5
6451 * @arg TIM_CHANNEL_6: TIM Channel 6
6452 * @retval TIM Channel state
6453 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6454 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6455 {
6456 HAL_TIM_ChannelStateTypeDef channel_state;
6457
6458 /* Check the parameters */
6459 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6460
6461 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6462
6463 return channel_state;
6464 }
6465
6466 #if defined(TIM_DMA_SUPPORT)
6467 /**
6468 * @brief Return actual state of a DMA burst operation.
6469 * @param htim TIM handle
6470 * @retval DMA burst state
6471 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6472 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6473 {
6474 /* Check the parameters */
6475 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6476
6477 return htim->DMABurstState;
6478 }
6479 #endif /* TIM_DMA_SUPPORT */
6480
6481 /**
6482 * @}
6483 */
6484
6485 /**
6486 * @}
6487 */
6488
6489 /** @defgroup TIM_Private_Functions TIM Private Functions
6490 * @{
6491 */
6492
6493 #if defined(TIM_DMA_SUPPORT)
6494 /**
6495 * @brief TIM DMA error callback
6496 * @param hdma pointer to DMA handle.
6497 * @retval None
6498 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6499 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6500 {
6501 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6502
6503 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6504 {
6505 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6506 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6507 }
6508 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6509 {
6510 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6511 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6512 }
6513 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6514 {
6515 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6516 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6517 }
6518 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6519 {
6520 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6521 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6522 }
6523 else
6524 {
6525 htim->State = HAL_TIM_STATE_READY;
6526 }
6527
6528 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6529 htim->ErrorCallback(htim);
6530 #else
6531 HAL_TIM_ErrorCallback(htim);
6532 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6533
6534 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6535 }
6536
6537 /**
6538 * @brief TIM DMA Delay Pulse complete callback.
6539 * @param hdma pointer to DMA handle.
6540 * @retval None
6541 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6542 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6543 {
6544 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6545
6546 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6547 {
6548 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6549
6550 if (hdma->Init.Mode == DMA_NORMAL)
6551 {
6552 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6553 }
6554 }
6555 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6556 {
6557 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6558
6559 if (hdma->Init.Mode == DMA_NORMAL)
6560 {
6561 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6562 }
6563 }
6564 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6565 {
6566 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6567
6568 if (hdma->Init.Mode == DMA_NORMAL)
6569 {
6570 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6571 }
6572 }
6573 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6574 {
6575 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6576
6577 if (hdma->Init.Mode == DMA_NORMAL)
6578 {
6579 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6580 }
6581 }
6582 else
6583 {
6584 /* nothing to do */
6585 }
6586
6587 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6588 htim->PWM_PulseFinishedCallback(htim);
6589 #else
6590 HAL_TIM_PWM_PulseFinishedCallback(htim);
6591 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6592
6593 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6594 }
6595
6596 /**
6597 * @brief TIM DMA Delay Pulse half complete callback.
6598 * @param hdma pointer to DMA handle.
6599 * @retval None
6600 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6601 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6602 {
6603 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6604
6605 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6606 {
6607 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6608 }
6609 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6610 {
6611 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6612 }
6613 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6614 {
6615 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6616 }
6617 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6618 {
6619 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6620 }
6621 else
6622 {
6623 /* nothing to do */
6624 }
6625
6626 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6627 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6628 #else
6629 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6630 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6631
6632 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6633 }
6634
6635 /**
6636 * @brief TIM DMA Capture complete callback.
6637 * @param hdma pointer to DMA handle.
6638 * @retval None
6639 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6640 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6641 {
6642 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6643
6644 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6645 {
6646 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6647
6648 if (hdma->Init.Mode == DMA_NORMAL)
6649 {
6650 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6651 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6652 }
6653 }
6654 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6655 {
6656 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6657
6658 if (hdma->Init.Mode == DMA_NORMAL)
6659 {
6660 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6661 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6662 }
6663 }
6664 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6665 {
6666 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6667
6668 if (hdma->Init.Mode == DMA_NORMAL)
6669 {
6670 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6671 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6672 }
6673 }
6674 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6675 {
6676 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6677
6678 if (hdma->Init.Mode == DMA_NORMAL)
6679 {
6680 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6681 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6682 }
6683 }
6684 else
6685 {
6686 /* nothing to do */
6687 }
6688
6689 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6690 htim->IC_CaptureCallback(htim);
6691 #else
6692 HAL_TIM_IC_CaptureCallback(htim);
6693 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6694
6695 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6696 }
6697
6698 /**
6699 * @brief TIM DMA Capture half complete callback.
6700 * @param hdma pointer to DMA handle.
6701 * @retval None
6702 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6703 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6704 {
6705 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6706
6707 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6708 {
6709 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6710 }
6711 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6712 {
6713 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6714 }
6715 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6716 {
6717 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6718 }
6719 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6720 {
6721 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6722 }
6723 else
6724 {
6725 /* nothing to do */
6726 }
6727
6728 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6729 htim->IC_CaptureHalfCpltCallback(htim);
6730 #else
6731 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6732 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6733
6734 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6735 }
6736
6737 /**
6738 * @brief TIM DMA Period Elapse complete callback.
6739 * @param hdma pointer to DMA handle.
6740 * @retval None
6741 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6742 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6743 {
6744 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6745
6746 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6747 {
6748 htim->State = HAL_TIM_STATE_READY;
6749 }
6750
6751 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6752 htim->PeriodElapsedCallback(htim);
6753 #else
6754 HAL_TIM_PeriodElapsedCallback(htim);
6755 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6756 }
6757
6758 /**
6759 * @brief TIM DMA Period Elapse half complete callback.
6760 * @param hdma pointer to DMA handle.
6761 * @retval None
6762 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6763 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6764 {
6765 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6766
6767 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6768 htim->PeriodElapsedHalfCpltCallback(htim);
6769 #else
6770 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6771 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6772 }
6773 #endif /* TIM_DMA_SUPPORT */
6774
6775 /**
6776 * @brief Time Base configuration
6777 * @param TIMx TIM peripheral
6778 * @param Structure TIM Base configuration structure
6779 * @retval None
6780 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)6781 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
6782 {
6783 uint32_t tmpcr1;
6784 tmpcr1 = TIMx->CR1;
6785
6786 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6787 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6788 {
6789 /* Select the Counter Mode */
6790 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6791 tmpcr1 |= Structure->CounterMode;
6792 }
6793
6794 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6795 {
6796 /* Set the clock division */
6797 tmpcr1 &= ~TIM_CR1_CKD;
6798 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6799 }
6800
6801 /* Set the auto-reload preload */
6802 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6803
6804 TIMx->CR1 = tmpcr1;
6805
6806 /* Set the Autoreload value */
6807 TIMx->ARR = (uint32_t)Structure->Period ;
6808
6809 /* Set the Prescaler value */
6810 TIMx->PSC = Structure->Prescaler;
6811
6812 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6813 {
6814 /* Set the Repetition Counter value */
6815 TIMx->RCR = Structure->RepetitionCounter;
6816 }
6817
6818 /* Generate an update event to reload the Prescaler
6819 and the repetition counter (only for advanced timer) value immediately */
6820 TIMx->EGR = TIM_EGR_UG;
6821 }
6822
6823 /**
6824 * @brief Timer Output Compare 1 configuration
6825 * @param TIMx to select the TIM peripheral
6826 * @param OC_Config The output configuration structure
6827 * @retval None
6828 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6829 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6830 {
6831 uint32_t tmpccmrx;
6832 uint32_t tmpccer;
6833 uint32_t tmpcr2;
6834
6835 /* Get the TIMx CCER register value */
6836 tmpccer = TIMx->CCER;
6837
6838 /* Disable the Channel 1: Reset the CC1E Bit */
6839 TIMx->CCER &= ~TIM_CCER_CC1E;
6840
6841 /* Get the TIMx CR2 register value */
6842 tmpcr2 = TIMx->CR2;
6843
6844 /* Get the TIMx CCMR1 register value */
6845 tmpccmrx = TIMx->CCMR1;
6846
6847 /* Reset the Output Compare Mode Bits */
6848 tmpccmrx &= ~TIM_CCMR1_OC1M;
6849 tmpccmrx &= ~TIM_CCMR1_CC1S;
6850 /* Select the Output Compare Mode */
6851 tmpccmrx |= OC_Config->OCMode;
6852
6853 /* Reset the Output Polarity level */
6854 tmpccer &= ~TIM_CCER_CC1P;
6855 /* Set the Output Compare Polarity */
6856 tmpccer |= OC_Config->OCPolarity;
6857
6858 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
6859 {
6860 /* Check parameters */
6861 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6862
6863 /* Reset the Output N Polarity level */
6864 tmpccer &= ~TIM_CCER_CC1NP;
6865 /* Set the Output N Polarity */
6866 tmpccer |= OC_Config->OCNPolarity;
6867 /* Reset the Output N State */
6868 tmpccer &= ~TIM_CCER_CC1NE;
6869 }
6870
6871 if (IS_TIM_BREAK_INSTANCE(TIMx))
6872 {
6873 /* Check parameters */
6874 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6875 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6876
6877 /* Reset the Output Compare and Output Compare N IDLE State */
6878 tmpcr2 &= ~TIM_CR2_OIS1;
6879 tmpcr2 &= ~TIM_CR2_OIS1N;
6880 /* Set the Output Idle state */
6881 tmpcr2 |= OC_Config->OCIdleState;
6882 /* Set the Output N Idle state */
6883 tmpcr2 |= OC_Config->OCNIdleState;
6884 }
6885
6886 /* Write to TIMx CR2 */
6887 TIMx->CR2 = tmpcr2;
6888
6889 /* Write to TIMx CCMR1 */
6890 TIMx->CCMR1 = tmpccmrx;
6891
6892 /* Set the Capture Compare Register value */
6893 TIMx->CCR1 = OC_Config->Pulse;
6894
6895 /* Write to TIMx CCER */
6896 TIMx->CCER = tmpccer;
6897 }
6898
6899 /**
6900 * @brief Timer Output Compare 2 configuration
6901 * @param TIMx to select the TIM peripheral
6902 * @param OC_Config The output configuration structure
6903 * @retval None
6904 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6905 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6906 {
6907 uint32_t tmpccmrx;
6908 uint32_t tmpccer;
6909 uint32_t tmpcr2;
6910
6911 /* Get the TIMx CCER register value */
6912 tmpccer = TIMx->CCER;
6913
6914 /* Disable the Channel 2: Reset the CC2E Bit */
6915 TIMx->CCER &= ~TIM_CCER_CC2E;
6916
6917 /* Get the TIMx CR2 register value */
6918 tmpcr2 = TIMx->CR2;
6919
6920 /* Get the TIMx CCMR1 register value */
6921 tmpccmrx = TIMx->CCMR1;
6922
6923 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6924 tmpccmrx &= ~TIM_CCMR1_OC2M;
6925 tmpccmrx &= ~TIM_CCMR1_CC2S;
6926
6927 /* Select the Output Compare Mode */
6928 tmpccmrx |= (OC_Config->OCMode << 8U);
6929
6930 /* Reset the Output Polarity level */
6931 tmpccer &= ~TIM_CCER_CC2P;
6932 /* Set the Output Compare Polarity */
6933 tmpccer |= (OC_Config->OCPolarity << 4U);
6934
6935 #if defined(TIM_CCER_CC2NE)
6936 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
6937 {
6938 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6939
6940 /* Reset the Output N Polarity level */
6941 tmpccer &= ~TIM_CCER_CC2NP;
6942 /* Set the Output N Polarity */
6943 tmpccer |= (OC_Config->OCNPolarity << 4U);
6944 /* Reset the Output N State */
6945 tmpccer &= ~TIM_CCER_CC2NE;
6946 }
6947 #endif /* TIM_CCER_CC2NE */
6948
6949 #if defined(TIM_CR2_OIS2N)
6950 if (IS_TIM_BREAK_INSTANCE(TIMx))
6951 {
6952 /* Check parameters */
6953 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6954 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6955
6956 /* Reset the Output Compare and Output Compare N IDLE State */
6957 tmpcr2 &= ~TIM_CR2_OIS2;
6958 tmpcr2 &= ~TIM_CR2_OIS2N;
6959 /* Set the Output Idle state */
6960 tmpcr2 |= (OC_Config->OCIdleState << 2U);
6961 /* Set the Output N Idle state */
6962 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
6963 }
6964 #endif /* TIM_CR2_OIS2N */
6965
6966 /* Write to TIMx CR2 */
6967 TIMx->CR2 = tmpcr2;
6968
6969 /* Write to TIMx CCMR1 */
6970 TIMx->CCMR1 = tmpccmrx;
6971
6972 /* Set the Capture Compare Register value */
6973 TIMx->CCR2 = OC_Config->Pulse;
6974
6975 /* Write to TIMx CCER */
6976 TIMx->CCER = tmpccer;
6977 }
6978
6979 /**
6980 * @brief Timer Output Compare 3 configuration
6981 * @param TIMx to select the TIM peripheral
6982 * @param OC_Config The output configuration structure
6983 * @retval None
6984 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6985 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6986 {
6987 uint32_t tmpccmrx;
6988 uint32_t tmpccer;
6989 uint32_t tmpcr2;
6990
6991 /* Get the TIMx CCER register value */
6992 tmpccer = TIMx->CCER;
6993
6994 /* Disable the Channel 3: Reset the CC2E Bit */
6995 TIMx->CCER &= ~TIM_CCER_CC3E;
6996
6997 /* Get the TIMx CR2 register value */
6998 tmpcr2 = TIMx->CR2;
6999
7000 /* Get the TIMx CCMR2 register value */
7001 tmpccmrx = TIMx->CCMR2;
7002
7003 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7004 tmpccmrx &= ~TIM_CCMR2_OC3M;
7005 tmpccmrx &= ~TIM_CCMR2_CC3S;
7006 /* Select the Output Compare Mode */
7007 tmpccmrx |= OC_Config->OCMode;
7008
7009 /* Reset the Output Polarity level */
7010 tmpccer &= ~TIM_CCER_CC3P;
7011 /* Set the Output Compare Polarity */
7012 tmpccer |= (OC_Config->OCPolarity << 8U);
7013
7014 #if defined(TIM_CCER_CC2NE)
7015 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7016 {
7017 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7018
7019 /* Reset the Output N Polarity level */
7020 tmpccer &= ~TIM_CCER_CC3NP;
7021 /* Set the Output N Polarity */
7022 tmpccer |= (OC_Config->OCNPolarity << 8U);
7023 /* Reset the Output N State */
7024 tmpccer &= ~TIM_CCER_CC3NE;
7025 }
7026 #endif /* TIM_CCER_CC2NE */
7027
7028 #if defined(TIM_CR2_OIS3)
7029 if (IS_TIM_BREAK_INSTANCE(TIMx))
7030 {
7031 /* Check parameters */
7032 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7033 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7034
7035 /* Reset the Output Compare and Output Compare N IDLE State */
7036 tmpcr2 &= ~TIM_CR2_OIS3;
7037 tmpcr2 &= ~TIM_CR2_OIS3N;
7038 /* Set the Output Idle state */
7039 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7040 /* Set the Output N Idle state */
7041 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7042 }
7043 #endif /* TIM_CR2_OIS3 */
7044
7045 /* Write to TIMx CR2 */
7046 TIMx->CR2 = tmpcr2;
7047
7048 /* Write to TIMx CCMR2 */
7049 TIMx->CCMR2 = tmpccmrx;
7050
7051 /* Set the Capture Compare Register value */
7052 TIMx->CCR3 = OC_Config->Pulse;
7053
7054 /* Write to TIMx CCER */
7055 TIMx->CCER = tmpccer;
7056 }
7057
7058 /**
7059 * @brief Timer Output Compare 4 configuration
7060 * @param TIMx to select the TIM peripheral
7061 * @param OC_Config The output configuration structure
7062 * @retval None
7063 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7064 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7065 {
7066 uint32_t tmpccmrx;
7067 uint32_t tmpccer;
7068 uint32_t tmpcr2;
7069
7070 /* Get the TIMx CCER register value */
7071 tmpccer = TIMx->CCER;
7072
7073 /* Disable the Channel 4: Reset the CC4E Bit */
7074 TIMx->CCER &= ~TIM_CCER_CC4E;
7075
7076 /* Get the TIMx CR2 register value */
7077 tmpcr2 = TIMx->CR2;
7078
7079 /* Get the TIMx CCMR2 register value */
7080 tmpccmrx = TIMx->CCMR2;
7081
7082 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7083 tmpccmrx &= ~TIM_CCMR2_OC4M;
7084 tmpccmrx &= ~TIM_CCMR2_CC4S;
7085
7086 /* Select the Output Compare Mode */
7087 tmpccmrx |= (OC_Config->OCMode << 8U);
7088
7089 /* Reset the Output Polarity level */
7090 tmpccer &= ~TIM_CCER_CC4P;
7091 /* Set the Output Compare Polarity */
7092 tmpccer |= (OC_Config->OCPolarity << 12U);
7093
7094 #if defined(TIM_CR2_OIS4)
7095 if (IS_TIM_BREAK_INSTANCE(TIMx))
7096 {
7097 /* Check parameters */
7098 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7099
7100 /* Reset the Output Compare IDLE State */
7101 tmpcr2 &= ~TIM_CR2_OIS4;
7102
7103 /* Set the Output Idle state */
7104 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7105 }
7106 #endif /* TIM_CR2_OIS4 */
7107
7108 /* Write to TIMx CR2 */
7109 TIMx->CR2 = tmpcr2;
7110
7111 /* Write to TIMx CCMR2 */
7112 TIMx->CCMR2 = tmpccmrx;
7113
7114 /* Set the Capture Compare Register value */
7115 TIMx->CCR4 = OC_Config->Pulse;
7116
7117 /* Write to TIMx CCER */
7118 TIMx->CCER = tmpccer;
7119 }
7120
7121 #if defined(TIM_CCER_CC5E)
7122 /**
7123 * @brief Timer Output Compare 5 configuration
7124 * @param TIMx to select the TIM peripheral
7125 * @param OC_Config The output configuration structure
7126 * @retval None
7127 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7128 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7129 const TIM_OC_InitTypeDef *OC_Config)
7130 {
7131 uint32_t tmpccmrx;
7132 uint32_t tmpccer;
7133 uint32_t tmpcr2;
7134
7135 /* Get the TIMx CCER register value */
7136 tmpccer = TIMx->CCER;
7137
7138 /* Disable the output: Reset the CCxE Bit */
7139 TIMx->CCER &= ~TIM_CCER_CC5E;
7140
7141 /* Get the TIMx CR2 register value */
7142 tmpcr2 = TIMx->CR2;
7143 /* Get the TIMx CCMR1 register value */
7144 tmpccmrx = TIMx->CCMR3;
7145
7146 /* Reset the Output Compare Mode Bits */
7147 tmpccmrx &= ~(TIM_CCMR3_OC5M);
7148 /* Select the Output Compare Mode */
7149 tmpccmrx |= OC_Config->OCMode;
7150
7151 /* Reset the Output Polarity level */
7152 tmpccer &= ~TIM_CCER_CC5P;
7153 /* Set the Output Compare Polarity */
7154 tmpccer |= (OC_Config->OCPolarity << 16U);
7155
7156 if (IS_TIM_BREAK_INSTANCE(TIMx))
7157 {
7158 /* Reset the Output Compare IDLE State */
7159 tmpcr2 &= ~TIM_CR2_OIS5;
7160 /* Set the Output Idle state */
7161 tmpcr2 |= (OC_Config->OCIdleState << 8U);
7162 }
7163 /* Write to TIMx CR2 */
7164 TIMx->CR2 = tmpcr2;
7165
7166 /* Write to TIMx CCMR3 */
7167 TIMx->CCMR3 = tmpccmrx;
7168
7169 /* Set the Capture Compare Register value */
7170 TIMx->CCR5 = OC_Config->Pulse;
7171
7172 /* Write to TIMx CCER */
7173 TIMx->CCER = tmpccer;
7174 }
7175 #endif /* TIM_CCER_CC5E */
7176
7177 #if defined(TIM_CCER_CC6E)
7178 /**
7179 * @brief Timer Output Compare 6 configuration
7180 * @param TIMx to select the TIM peripheral
7181 * @param OC_Config The output configuration structure
7182 * @retval None
7183 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7184 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7185 const TIM_OC_InitTypeDef *OC_Config)
7186 {
7187 uint32_t tmpccmrx;
7188 uint32_t tmpccer;
7189 uint32_t tmpcr2;
7190
7191 /* Get the TIMx CCER register value */
7192 tmpccer = TIMx->CCER;
7193
7194 /* Disable the output: Reset the CCxE Bit */
7195 TIMx->CCER &= ~TIM_CCER_CC6E;
7196
7197 /* Get the TIMx CR2 register value */
7198 tmpcr2 = TIMx->CR2;
7199 /* Get the TIMx CCMR1 register value */
7200 tmpccmrx = TIMx->CCMR3;
7201
7202 /* Reset the Output Compare Mode Bits */
7203 tmpccmrx &= ~(TIM_CCMR3_OC6M);
7204 /* Select the Output Compare Mode */
7205 tmpccmrx |= (OC_Config->OCMode << 8U);
7206
7207 /* Reset the Output Polarity level */
7208 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7209 /* Set the Output Compare Polarity */
7210 tmpccer |= (OC_Config->OCPolarity << 20U);
7211
7212 if (IS_TIM_BREAK_INSTANCE(TIMx))
7213 {
7214 /* Reset the Output Compare IDLE State */
7215 tmpcr2 &= ~TIM_CR2_OIS6;
7216 /* Set the Output Idle state */
7217 tmpcr2 |= (OC_Config->OCIdleState << 10U);
7218 }
7219
7220 /* Write to TIMx CR2 */
7221 TIMx->CR2 = tmpcr2;
7222
7223 /* Write to TIMx CCMR3 */
7224 TIMx->CCMR3 = tmpccmrx;
7225
7226 /* Set the Capture Compare Register value */
7227 TIMx->CCR6 = OC_Config->Pulse;
7228
7229 /* Write to TIMx CCER */
7230 TIMx->CCER = tmpccer;
7231 }
7232 #endif /* TIM_CCER_CC6E */
7233
7234 /**
7235 * @brief Slave Timer configuration function
7236 * @param htim TIM handle
7237 * @param sSlaveConfig Slave timer configuration
7238 * @retval None
7239 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)7240 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7241 const TIM_SlaveConfigTypeDef *sSlaveConfig)
7242 {
7243 HAL_StatusTypeDef status = HAL_OK;
7244 uint32_t tmpsmcr;
7245 uint32_t tmpccmr1;
7246 uint32_t tmpccer;
7247
7248 /* Get the TIMx SMCR register value */
7249 tmpsmcr = htim->Instance->SMCR;
7250
7251 /* Reset the Trigger Selection Bits */
7252 tmpsmcr &= ~TIM_SMCR_TS;
7253 /* Set the Input Trigger source */
7254 tmpsmcr |= sSlaveConfig->InputTrigger;
7255
7256 /* Reset the slave mode Bits */
7257 tmpsmcr &= ~TIM_SMCR_SMS;
7258 /* Set the slave mode */
7259 tmpsmcr |= sSlaveConfig->SlaveMode;
7260
7261 /* Write to TIMx SMCR */
7262 htim->Instance->SMCR = tmpsmcr;
7263
7264 /* Configure the trigger prescaler, filter, and polarity */
7265 switch (sSlaveConfig->InputTrigger)
7266 {
7267 case TIM_TS_ETRF:
7268 {
7269 /* Check the parameters */
7270 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7271 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7272 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7273 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7274 /* Configure the ETR Trigger source */
7275 TIM_ETR_SetConfig(htim->Instance,
7276 sSlaveConfig->TriggerPrescaler,
7277 sSlaveConfig->TriggerPolarity,
7278 sSlaveConfig->TriggerFilter);
7279 break;
7280 }
7281
7282 case TIM_TS_TI1F_ED:
7283 {
7284 /* Check the parameters */
7285 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7286 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7287
7288 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
7289 {
7290 return HAL_ERROR;
7291 }
7292
7293 /* Disable the Channel 1: Reset the CC1E Bit */
7294 tmpccer = htim->Instance->CCER;
7295 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7296 tmpccmr1 = htim->Instance->CCMR1;
7297
7298 /* Set the filter */
7299 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7300 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7301
7302 /* Write to TIMx CCMR1 and CCER registers */
7303 htim->Instance->CCMR1 = tmpccmr1;
7304 htim->Instance->CCER = tmpccer;
7305 break;
7306 }
7307
7308 case TIM_TS_TI1FP1:
7309 {
7310 /* Check the parameters */
7311 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7312 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7313 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7314
7315 /* Configure TI1 Filter and Polarity */
7316 TIM_TI1_ConfigInputStage(htim->Instance,
7317 sSlaveConfig->TriggerPolarity,
7318 sSlaveConfig->TriggerFilter);
7319 break;
7320 }
7321
7322 case TIM_TS_TI2FP2:
7323 {
7324 /* Check the parameters */
7325 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7326 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7327 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7328
7329 /* Configure TI2 Filter and Polarity */
7330 TIM_TI2_ConfigInputStage(htim->Instance,
7331 sSlaveConfig->TriggerPolarity,
7332 sSlaveConfig->TriggerFilter);
7333 break;
7334 }
7335
7336
7337 default:
7338 status = HAL_ERROR;
7339 break;
7340 }
7341
7342 return status;
7343 }
7344
7345 /**
7346 * @brief Configure the TI1 as Input.
7347 * @param TIMx to select the TIM peripheral.
7348 * @param TIM_ICPolarity The Input Polarity.
7349 * This parameter can be one of the following values:
7350 * @arg TIM_ICPOLARITY_RISING
7351 * @arg TIM_ICPOLARITY_FALLING
7352 * @arg TIM_ICPOLARITY_BOTHEDGE
7353 * @param TIM_ICSelection specifies the input to be used.
7354 * This parameter can be one of the following values:
7355 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7356 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7357 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7358 * @param TIM_ICFilter Specifies the Input Capture Filter.
7359 * This parameter must be a value between 0x00 and 0x0F.
7360 * @retval None
7361 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7362 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7363 * protected against un-initialized filter and polarity values.
7364 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7365 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7366 uint32_t TIM_ICFilter)
7367 {
7368 uint32_t tmpccmr1;
7369 uint32_t tmpccer;
7370
7371 /* Disable the Channel 1: Reset the CC1E Bit */
7372 tmpccer = TIMx->CCER;
7373 TIMx->CCER &= ~TIM_CCER_CC1E;
7374 tmpccmr1 = TIMx->CCMR1;
7375
7376 /* Select the Input */
7377 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7378 {
7379 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7380 tmpccmr1 |= TIM_ICSelection;
7381 }
7382 else
7383 {
7384 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7385 }
7386
7387 /* Set the filter */
7388 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7389 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7390
7391 /* Select the Polarity and set the CC1E Bit */
7392 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7393 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7394
7395 /* Write to TIMx CCMR1 and CCER registers */
7396 TIMx->CCMR1 = tmpccmr1;
7397 TIMx->CCER = tmpccer;
7398 }
7399
7400 /**
7401 * @brief Configure the Polarity and Filter for TI1.
7402 * @param TIMx to select the TIM peripheral.
7403 * @param TIM_ICPolarity The Input Polarity.
7404 * This parameter can be one of the following values:
7405 * @arg TIM_ICPOLARITY_RISING
7406 * @arg TIM_ICPOLARITY_FALLING
7407 * @arg TIM_ICPOLARITY_BOTHEDGE
7408 * @param TIM_ICFilter Specifies the Input Capture Filter.
7409 * This parameter must be a value between 0x00 and 0x0F.
7410 * @retval None
7411 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7412 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7413 {
7414 uint32_t tmpccmr1;
7415 uint32_t tmpccer;
7416
7417 /* Disable the Channel 1: Reset the CC1E Bit */
7418 tmpccer = TIMx->CCER;
7419 TIMx->CCER &= ~TIM_CCER_CC1E;
7420 tmpccmr1 = TIMx->CCMR1;
7421
7422 /* Set the filter */
7423 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7424 tmpccmr1 |= (TIM_ICFilter << 4U);
7425
7426 /* Select the Polarity and set the CC1E Bit */
7427 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7428 tmpccer |= TIM_ICPolarity;
7429
7430 /* Write to TIMx CCMR1 and CCER registers */
7431 TIMx->CCMR1 = tmpccmr1;
7432 TIMx->CCER = tmpccer;
7433 }
7434
7435 /**
7436 * @brief Configure the TI2 as Input.
7437 * @param TIMx to select the TIM peripheral
7438 * @param TIM_ICPolarity The Input Polarity.
7439 * This parameter can be one of the following values:
7440 * @arg TIM_ICPOLARITY_RISING
7441 * @arg TIM_ICPOLARITY_FALLING
7442 * @arg TIM_ICPOLARITY_BOTHEDGE
7443 * @param TIM_ICSelection specifies the input to be used.
7444 * This parameter can be one of the following values:
7445 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7446 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7447 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7448 * @param TIM_ICFilter Specifies the Input Capture Filter.
7449 * This parameter must be a value between 0x00 and 0x0F.
7450 * @retval None
7451 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7452 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7453 * protected against un-initialized filter and polarity values.
7454 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7455 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7456 uint32_t TIM_ICFilter)
7457 {
7458 uint32_t tmpccmr1;
7459 uint32_t tmpccer;
7460
7461 /* Disable the Channel 2: Reset the CC2E Bit */
7462 tmpccer = TIMx->CCER;
7463 TIMx->CCER &= ~TIM_CCER_CC2E;
7464 tmpccmr1 = TIMx->CCMR1;
7465
7466 /* Select the Input */
7467 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7468 tmpccmr1 |= (TIM_ICSelection << 8U);
7469
7470 /* Set the filter */
7471 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7472 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7473
7474 /* Select the Polarity and set the CC2E Bit */
7475 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7476 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7477
7478 /* Write to TIMx CCMR1 and CCER registers */
7479 TIMx->CCMR1 = tmpccmr1 ;
7480 TIMx->CCER = tmpccer;
7481 }
7482
7483 /**
7484 * @brief Configure the Polarity and Filter for TI2.
7485 * @param TIMx to select the TIM peripheral.
7486 * @param TIM_ICPolarity The Input Polarity.
7487 * This parameter can be one of the following values:
7488 * @arg TIM_ICPOLARITY_RISING
7489 * @arg TIM_ICPOLARITY_FALLING
7490 * @arg TIM_ICPOLARITY_BOTHEDGE
7491 * @param TIM_ICFilter Specifies the Input Capture Filter.
7492 * This parameter must be a value between 0x00 and 0x0F.
7493 * @retval None
7494 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7495 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7496 {
7497 uint32_t tmpccmr1;
7498 uint32_t tmpccer;
7499
7500 /* Disable the Channel 2: Reset the CC2E Bit */
7501 tmpccer = TIMx->CCER;
7502 TIMx->CCER &= ~TIM_CCER_CC2E;
7503 tmpccmr1 = TIMx->CCMR1;
7504
7505 /* Set the filter */
7506 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7507 tmpccmr1 |= (TIM_ICFilter << 12U);
7508
7509 /* Select the Polarity and set the CC2E Bit */
7510 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7511 tmpccer |= (TIM_ICPolarity << 4U);
7512
7513 /* Write to TIMx CCMR1 and CCER registers */
7514 TIMx->CCMR1 = tmpccmr1 ;
7515 TIMx->CCER = tmpccer;
7516 }
7517
7518 /**
7519 * @brief Configure the TI3 as Input.
7520 * @param TIMx to select the TIM peripheral
7521 * @param TIM_ICPolarity The Input Polarity.
7522 * This parameter can be one of the following values:
7523 * @arg TIM_ICPOLARITY_RISING
7524 * @arg TIM_ICPOLARITY_FALLING
7525 * @arg TIM_ICPOLARITY_BOTHEDGE
7526 * @param TIM_ICSelection specifies the input to be used.
7527 * This parameter can be one of the following values:
7528 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7529 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7530 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7531 * @param TIM_ICFilter Specifies the Input Capture Filter.
7532 * This parameter must be a value between 0x00 and 0x0F.
7533 * @retval None
7534 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7535 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7536 * protected against un-initialized filter and polarity values.
7537 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7538 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7539 uint32_t TIM_ICFilter)
7540 {
7541 uint32_t tmpccmr2;
7542 uint32_t tmpccer;
7543
7544 /* Disable the Channel 3: Reset the CC3E Bit */
7545 tmpccer = TIMx->CCER;
7546 TIMx->CCER &= ~TIM_CCER_CC3E;
7547 tmpccmr2 = TIMx->CCMR2;
7548
7549 /* Select the Input */
7550 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7551 tmpccmr2 |= TIM_ICSelection;
7552
7553 /* Set the filter */
7554 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7555 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7556
7557 /* Select the Polarity and set the CC3E Bit */
7558 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
7559 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7560
7561 /* Write to TIMx CCMR2 and CCER registers */
7562 TIMx->CCMR2 = tmpccmr2;
7563 TIMx->CCER = tmpccer;
7564 }
7565
7566 /**
7567 * @brief Configure the TI4 as Input.
7568 * @param TIMx to select the TIM peripheral
7569 * @param TIM_ICPolarity The Input Polarity.
7570 * This parameter can be one of the following values:
7571 * @arg TIM_ICPOLARITY_RISING
7572 * @arg TIM_ICPOLARITY_FALLING
7573 * @arg TIM_ICPOLARITY_BOTHEDGE
7574 * @param TIM_ICSelection specifies the input to be used.
7575 * This parameter can be one of the following values:
7576 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7577 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7578 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7579 * @param TIM_ICFilter Specifies the Input Capture Filter.
7580 * This parameter must be a value between 0x00 and 0x0F.
7581 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7582 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7583 * protected against un-initialized filter and polarity values.
7584 * @retval None
7585 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7586 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7587 uint32_t TIM_ICFilter)
7588 {
7589 uint32_t tmpccmr2;
7590 uint32_t tmpccer;
7591
7592 /* Disable the Channel 4: Reset the CC4E Bit */
7593 tmpccer = TIMx->CCER;
7594 TIMx->CCER &= ~TIM_CCER_CC4E;
7595 tmpccmr2 = TIMx->CCMR2;
7596
7597 /* Select the Input */
7598 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7599 tmpccmr2 |= (TIM_ICSelection << 8U);
7600
7601 /* Set the filter */
7602 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7603 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7604
7605 /* Select the Polarity and set the CC4E Bit */
7606 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7607 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7608
7609 /* Write to TIMx CCMR2 and CCER registers */
7610 TIMx->CCMR2 = tmpccmr2;
7611 TIMx->CCER = tmpccer ;
7612 }
7613
7614 /**
7615 * @brief Selects the Input Trigger source
7616 * @param TIMx to select the TIM peripheral
7617 * @param InputTriggerSource The Input Trigger source.
7618 * This parameter can be one of the following values:
7619 * @arg TIM_TS_ITR0: Internal Trigger 0
7620 * @arg TIM_TS_ITR1: Internal Trigger 1
7621 * @arg TIM_TS_ITR2: Internal Trigger 2
7622 * @arg TIM_TS_ITR3: Internal Trigger 3
7623 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7624 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7625 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7626 * @arg TIM_TS_ETRF: External Trigger input
7627 * @retval None
7628 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7629 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7630 {
7631 uint32_t tmpsmcr;
7632
7633 /* Get the TIMx SMCR register value */
7634 tmpsmcr = TIMx->SMCR;
7635 /* Reset the TS Bits */
7636 tmpsmcr &= ~TIM_SMCR_TS;
7637 /* Set the Input Trigger source and the slave mode*/
7638 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7639 /* Write to TIMx SMCR */
7640 TIMx->SMCR = tmpsmcr;
7641 }
7642 /**
7643 * @brief Configures the TIMx External Trigger (ETR).
7644 * @param TIMx to select the TIM peripheral
7645 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7646 * This parameter can be one of the following values:
7647 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7648 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7649 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7650 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7651 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7652 * This parameter can be one of the following values:
7653 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7654 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7655 * @param ExtTRGFilter External Trigger Filter.
7656 * This parameter must be a value between 0x00 and 0x0F
7657 * @retval None
7658 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7659 static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7660 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7661 {
7662 uint32_t tmpsmcr;
7663
7664 tmpsmcr = TIMx->SMCR;
7665
7666 /* Reset the ETR Bits */
7667 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7668
7669 /* Set the Prescaler, the Filter value and the Polarity */
7670 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7671
7672 /* Write to TIMx SMCR */
7673 TIMx->SMCR = tmpsmcr;
7674 }
7675
7676 /**
7677 * @brief Enables or disables the TIM Capture Compare Channel x.
7678 * @param TIMx to select the TIM peripheral
7679 * @param Channel specifies the TIM Channel
7680 * This parameter can be one of the following values:
7681 * @arg TIM_CHANNEL_1: TIM Channel 1
7682 * @arg TIM_CHANNEL_2: TIM Channel 2
7683 * @arg TIM_CHANNEL_3: TIM Channel 3
7684 * @arg TIM_CHANNEL_4: TIM Channel 4
7685 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
7686 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
7687 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7688 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7689 * @retval None
7690 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7691 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7692 {
7693 uint32_t tmp;
7694
7695 /* Check the parameters */
7696 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7697 assert_param(IS_TIM_CHANNELS(Channel));
7698
7699 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7700
7701 /* Reset the CCxE Bit */
7702 TIMx->CCER &= ~tmp;
7703
7704 /* Set or reset the CCxE Bit */
7705 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7706 }
7707
7708 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7709 /**
7710 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7711 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7712 * the configuration information for TIM module.
7713 * @retval None
7714 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7715 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7716 {
7717 /* Reset the TIM callback to the legacy weak callbacks */
7718 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
7719 #if defined(TIM_DMA_SUPPORT)
7720 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
7721 #endif /* TIM_DMA_SUPPORT */
7722 htim->TriggerCallback = HAL_TIM_TriggerCallback;
7723 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
7724 #if defined(TIM_DMA_SUPPORT)
7725 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
7726 #endif /* TIM_DMA_SUPPORT */
7727 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
7728 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
7729 #if defined(TIM_DMA_SUPPORT)
7730 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
7731 htim->ErrorCallback = HAL_TIM_ErrorCallback;
7732 #endif /* TIM_DMA_SUPPORT */
7733 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
7734 htim->BreakCallback = HAL_TIMEx_BreakCallback;
7735 #if defined(TIM_BDTR_BK2E)
7736 htim->Break2Callback = HAL_TIMEx_Break2Callback;
7737 #endif /* TIM_BDTR_BK2E */
7738 }
7739 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7740
7741 /**
7742 * @}
7743 */
7744
7745 #endif /* HAL_TIM_MODULE_ENABLED */
7746 /**
7747 * @}
7748 */
7749
7750 /**
7751 * @}
7752 */
7753
