1 /**
2 ******************************************************************************
3 * @file stm32wb0x_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization/de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2024 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32wb0x_hal.h"
26
27 /** @addtogroup STM32WB0x_HAL_Driver
28 * @{
29 */
30
31 /** @addtogroup PWR
32 * @{
33 */
34
35 #ifdef HAL_PWR_MODULE_ENABLED
36
37 /* Private typedef -----------------------------------------------------------*/
38 /* Private define ------------------------------------------------------------*/
39 /* Private macro -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private function prototypes -----------------------------------------------*/
43 /* Exported functions --------------------------------------------------------*/
44 /** @defgroup PWR_Exported_Functions PWR Exported Functions
45 * @{
46 */
47
48 /** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
49 * @brief Initialization and De-Initialization functions
50 *
51 @verbatim
52 ===============================================================================
53 ##### Initialization and De-Initialization Functions #####
54 ===============================================================================
55 [..]
56 This section provides functions allowing to deinitialize power peripheral.
57
58 @endverbatim
59 * @{
60 */
61 /**
62 * @brief Deinitialize the HAL PWR peripheral registers to their default reset
63 * values.
64 * @note This functionality is not available in this product.
65 * The prototype is kept just to maintain compatibility with other
66 * products.
67 * @retval None.
68 */
HAL_PWR_DeInit(void)69 void HAL_PWR_DeInit(void)
70 {
71 }
72
73 /**
74 * @}
75 */
76
77 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
78 * @brief Power Control functions
79 *
80 @verbatim
81
82 ===============================================================================
83 ##### Peripheral Control functions #####
84 ===============================================================================
85 [..]
86 (#) The Power control (PWR) provides an overview of the supply architecture
87 for the different power domains and of the supply configuration
88 controller.
89
90 (#) Every entity has low power mode as described below :
91 (#) The CPU low power modes are :
92 (+) CPU CRun.
93 (+) CPU Sleep WFI.
94 (+) CPU DeepSleep.
95 (#) The Core low power modes are :
96 (+) Run.
97 (+) Sleep.
98 (+) DEEPSTOP with with retention and low speed clock enabled.
99 (+) DEEPSTOP with with retention and low speed clock disabled.
100 (+) Shutdown.
101
102 [..]
103 *** PVD configuration ***
104 =========================
105 [..]
106 (+) The PVD is used to monitor the VDD power supply by comparing it to a
107 threshold selected by the PVD Level (PVDLS[2:0] bits in PWR_CR2 register).
108 (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
109 than the PVD threshold. This event can generate an interrupt if enabled.
110 This is done through __HAL_PVD_ENABLE_IT() macro.
111 (+) The PVD is stopped in Shutdown mode.
112
113 *** WakeUp pin configuration ***
114 ================================
115 [..]
116 (+) Wake-up pin is used to wake up the system from DEEPSTOP mode.
117 The pin selection is configurable through the CR3 and CR6 registers to map
118 signal to wake up pin line.
119 The pin polarity is configurable through the CR4 and CR7 registers to be
120 active on rising or falling edges.
121
122 (+) When a wakeup pin event is received the appropriate flag is set in
123 the SR1 and SR3 registers.
124 Then the wakeup pin flag will be cleared and the IOs user
125 callback will be called.
126 The user can add his own code by customization of this function
127 HAL_PWR_WKUPx_Callback.
128
129 @endverbatim
130 * @{
131 */
132
133 /**
134 * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
135 * @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the PVD
136 * configuration information.
137 * @note Refer to the electrical characteristics of your device datasheet for
138 * more details about the voltage thresholds corresponding to each
139 * detection level.
140 * @retval None
141 */
HAL_PWR_ConfigPVD(const PWR_PVDTypeDef * sConfigPVD)142 HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD)
143 {
144 /* Check the parameters */
145 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
146 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
147
148 /* Set PVDLS bits according to PVDLevel value */
149 MODIFY_REG(PWR->CR2, PWR_CR2_PVDLS, sConfigPVD->PVDLevel);
150
151 /* Clear any previous config. Keep it clear if IT mode is selected */
152 __HAL_PWR_PVD_DISABLE_IT();
153
154 /* Configure interrupt mode */
155 if ((sConfigPVD->Mode & PWR_PVD_MODE_IT) == PWR_PVD_MODE_IT)
156 {
157 __HAL_PWR_PVD_ENABLE_IT();
158 }
159
160 return HAL_OK;
161 }
162
163 /**
164 * @brief Enables the Power Voltage Detector(PVD).
165 * @retval None
166 */
HAL_PWR_EnablePVD(void)167 void HAL_PWR_EnablePVD(void)
168 {
169 /* Enable the power voltage detector */
170 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
171 }
172
173 /**
174 * @brief Disables the Power Voltage Detector(PVD).
175 * @retval None
176 */
HAL_PWR_DisablePVD(void)177 void HAL_PWR_DisablePVD(void)
178 {
179 /* Disable the power voltage detector */
180 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
181 }
182
183 /**
184 * @brief Enable the WakeUp PINx functionality.
185 * @param WakeUpPin Specifies which Wake-Up pin to enable.
186 * This parameter can be one of the following:
187 * @arg @ref PWR_WAKEUP_PA0
188 * @arg @ref PWR_WAKEUP_PA1
189 * @arg @ref PWR_WAKEUP_PA2
190 * @arg @ref PWR_WAKEUP_PA3
191 * @arg @ref PWR_WAKEUP_PA4 (*)
192 * @arg @ref PWR_WAKEUP_PA5 (*)
193 * @arg @ref PWR_WAKEUP_PA6 (*)
194 * @arg @ref PWR_WAKEUP_PA7 (*)
195 * @arg @ref PWR_WAKEUP_PA8
196 * @arg @ref PWR_WAKEUP_PA9
197 * @arg @ref PWR_WAKEUP_PA10
198 * @arg @ref PWR_WAKEUP_PA11
199 * @arg @ref PWR_WAKEUP_PA12 (*)
200 * @arg @ref PWR_WAKEUP_PA13 (*)
201 * @arg @ref PWR_WAKEUP_PA14 (*)
202 * @arg @ref PWR_WAKEUP_PA15 (*)
203 * @arg @ref PWR_WAKEUP_PB0
204 * @arg @ref PWR_WAKEUP_PB1
205 * @arg @ref PWR_WAKEUP_PB2
206 * @arg @ref PWR_WAKEUP_PB3
207 * @arg @ref PWR_WAKEUP_PB4
208 * @arg @ref PWR_WAKEUP_PB5
209 * @arg @ref PWR_WAKEUP_PB6
210 * @arg @ref PWR_WAKEUP_PB7
211 * @arg @ref PWR_WAKEUP_PB8 (*)
212 * @arg @ref PWR_WAKEUP_PB9 (*)
213 * @arg @ref PWR_WAKEUP_PB10 (*)
214 * @arg @ref PWR_WAKEUP_PB11 (*)
215 * @arg @ref PWR_WAKEUP_PB12 (**)
216 * @arg @ref PWR_WAKEUP_PB13 (**)
217 * @arg @ref PWR_WAKEUP_PB14 (**)
218 * @arg @ref PWR_WAKEUP_PB15 (**)
219 * (*) available only on STM32WB06 and STM32WB07 devices
220 * (**) available only on STM32WB05 and STM32WB09 devices
221 * @param WakeUpPolarity Specifies the polarity of the wake up pin source.
222 * This parameter can be one of the following:
223 * @arg @ref PWR_WUP_RISIEDG
224 * @arg @ref PWR_WUP_FALLEDG
225 *
226 * @retval None
227 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin,uint32_t WakeUpPolarity)228 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin, uint32_t WakeUpPolarity)
229 {
230 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin));
231 assert_param(IS_PWR_WAKEUP_PIN_POLARITY(WakeUpPolarity));
232
233 /* Specifies the wake up line polarity for the event detection (rising or falling edge) */
234 if (WakeUpPolarity == PWR_WUP_FALLEDG)
235 {
236 SET_BIT(PWR->CR4, (WakeUpPin & 0x0000FFFF));
237 SET_BIT(PWR->CR7, (WakeUpPin >> 16));
238 }
239 else
240 {
241 CLEAR_BIT(PWR->CR4, (WakeUpPin & 0x0000FFFF));
242 CLEAR_BIT(PWR->CR7, (WakeUpPin >> 16));
243 }
244 /* Enable wake-up line */
245 SET_BIT(PWR->CR3, (WakeUpPin & 0x0000FFFF));
246 SET_BIT(PWR->CR6, (WakeUpPin >> 16));
247
248 }
249
250 /**
251 * @brief Disable the WakeUp PINx functionality.
252 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
253 * This parameter can be one of the following:
254 * @arg @ref PWR_WAKEUP_PA0
255 * @arg @ref PWR_WAKEUP_PA1
256 * @arg @ref PWR_WAKEUP_PA2
257 * @arg @ref PWR_WAKEUP_PA3
258 * @arg @ref PWR_WAKEUP_PA4 (*)
259 * @arg @ref PWR_WAKEUP_PA5 (*)
260 * @arg @ref PWR_WAKEUP_PA6 (*)
261 * @arg @ref PWR_WAKEUP_PA7 (*)
262 * @arg @ref PWR_WAKEUP_PA8
263 * @arg @ref PWR_WAKEUP_PA9
264 * @arg @ref PWR_WAKEUP_PA10
265 * @arg @ref PWR_WAKEUP_PA11
266 * @arg @ref PWR_WAKEUP_PA12 (*)
267 * @arg @ref PWR_WAKEUP_PA13 (*)
268 * @arg @ref PWR_WAKEUP_PA14 (*)
269 * @arg @ref PWR_WAKEUP_PA15 (*)
270 * @arg @ref PWR_WAKEUP_PB0
271 * @arg @ref PWR_WAKEUP_PB1
272 * @arg @ref PWR_WAKEUP_PB2
273 * @arg @ref PWR_WAKEUP_PB3
274 * @arg @ref PWR_WAKEUP_PB4
275 * @arg @ref PWR_WAKEUP_PB5
276 * @arg @ref PWR_WAKEUP_PB6
277 * @arg @ref PWR_WAKEUP_PB7
278 * @arg @ref PWR_WAKEUP_PB8 (*)
279 * @arg @ref PWR_WAKEUP_PB9 (*)
280 * @arg @ref PWR_WAKEUP_PB10 (*)
281 * @arg @ref PWR_WAKEUP_PB11 (*)
282 * @arg @ref PWR_WAKEUP_PB12 (**)
283 * @arg @ref PWR_WAKEUP_PB13 (**)
284 * @arg @ref PWR_WAKEUP_PB14 (**)
285 * @arg @ref PWR_WAKEUP_PB15 (**)
286 * (*) available only on STM32WB06 and STM32WB07 devices
287 * (**) available only on STM32WB05 and STM32WB09 devices
288 *
289 * @retval None
290 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)291 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
292 {
293 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
294 CLEAR_BIT(PWR->CR3, (WakeUpPinx & 0x0000FFFF));
295 CLEAR_BIT(PWR->CR6, (WakeUpPinx >> 16));
296
297 }
298
299 /**
300 * @brief Get and Clear Wake-up source.
301 * @retval WakeUpPin : This parameter can be a combination of
302 * @ref PWREx_WakeUp_Pins define group
303 */
HAL_PWR_GetClearWakeupSource(void)304 uint32_t HAL_PWR_GetClearWakeupSource(void)
305 {
306 uint32_t wakeuppin;
307
308 /* Get all wake-up pins */
309 wakeuppin = LL_PWR_GetWakeupSource();
310
311 /* Clear all the wake-up pin flags */
312 LL_PWR_ClearWakeupSource(wakeuppin);
313
314 return wakeuppin;
315 }
316
317 /**
318 * @brief Enter the CPU in Sleep mode.
319 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
320 * @note CPU clock is off and all peripherals including Cortex-M0+ core such
321 * as NVIC and SysTick can run and wake up the CPU when an interrupt
322 * or an event occurs.
323 * @retval None.
324 */
HAL_PWR_EnterSLEEPMode(void)325 void HAL_PWR_EnterSLEEPMode(void)
326 {
327 /* Clear SLEEPDEEP bit of Cortex System Control Register */
328 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
329
330 /* Wait For Interrupt Request */
331 __WFI();
332
333 }
334
335 /**
336 * @brief Configures the system to allow the DEEPSTOP mode.
337 * @param sConfigDEEPSTOP : Pointer to a @ref PWR_DEEPSTOPTypeDef structure that
338 * contains the DEEPSTOP configuration information.
339 * @retval None.
340 */
HAL_PWR_ConfigDEEPSTOP(PWR_DEEPSTOPTypeDef * sConfigDEEPSTOP)341 HAL_StatusTypeDef HAL_PWR_ConfigDEEPSTOP(PWR_DEEPSTOPTypeDef *sConfigDEEPSTOP)
342 {
343 uint8_t radio_disabled = FALSE;
344
345 /* Disable the low speed clock if requested */
346 if (sConfigDEEPSTOP->deepStopMode == PWR_DEEPSTOP_WITH_SLOW_CLOCK_OFF)
347 {
348 LL_RCC_LSE_Disable();
349 LL_RCC_LSI_Disable();
350 }
351
352 /* If the radio IP is not used at all by the SoC (or not yet started), the
353 following steps need to be done after any reset to allow DEEPSTOP mode */
354 if (!LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_MRBLE))
355 {
356 radio_disabled = TRUE;
357 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_MRBLE);
358 }
359 if ((READ_BIT(WAKEUP->BLUE_SLEEP_REQUEST_MODE, WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_EN) == 0) &&
360 (READ_BIT(WAKEUP->CM0_SLEEP_REQUEST_MODE, WAKEUP_CM0_SLEEP_REQUEST_MODE_CPU_WAKEUP_EN) == 0))
361 {
362 SET_BIT(WAKEUP->BLUE_SLEEP_REQUEST_MODE, WAKEUP_BLUE_SLEEP_REQUEST_MODE_FORCE_SLEEPING);
363 }
364 if (radio_disabled)
365 {
366 LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_MRBLE);
367 }
368
369 #if defined(PWR_CR2_GPIORET)
370 /* Enable the GPIO retention in DEEPSTOP configuration */
371 LL_PWR_EnableGPIORET();
372 #endif /* PWR_CR2_GPIORET */
373
374 /* Disable DIRECT HSE configuration to allow DEEPSTOP request */
375 if (LL_RCC_DIRECT_HSE_IsEnabled())
376 {
377 LL_RCC_DIRECT_HSE_Disable();
378 }
379
380 /* Wait until the low speed clock if OFF */
381 if (sConfigDEEPSTOP->deepStopMode == PWR_DEEPSTOP_WITH_SLOW_CLOCK_OFF)
382 {
383 while (LL_RCC_LSE_IsReady() || LL_RCC_LSI_IsReady()) {}
384 }
385
386 return HAL_OK;
387 }
388
389 /**
390 * @brief Enter DEEPSTOP mode
391 * @note The DEEPSTOP is the only low power mode of the device allowing to
392 * restart from a saved context environment and go on running
393 * the application at wakeup.
394 * @note CPU clock and bus clocks are stopped, the VDD12i power domain is
395 * switched off, the VDD12o power domain is ON and supplied at 1.0V.
396 * All the RAM banks are retained (by configuration in SystemInit()).
397 * The slow clock can be running or stopped, depending on the software
398 * configuration.
399 * All the register content is lost. Only few peripheral can save
400 * the setting if configured like wake up source.
401 * @retval None
402 */
HAL_PWR_EnterDEEPSTOPMode(void)403 void HAL_PWR_EnterDEEPSTOPMode(void)
404 {
405 /* Clear all the wake-up pin flags */
406 LL_PWR_ClearWakeupSource(LL_PWR_WAKEUP_ALL);
407 /* Enable the device DEEPSTOP configuration */
408 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP);
409
410 /* Set SLEEPDEEP bit of Cortex System Control Register */
411 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
412
413 /* Request Wait For Interrupt */
414 __WFI();
415 }
416
417 /**
418 * @brief Configures the system to allow the SHUTDOWN mode.
419 * @param sConfigSHUTDOWN : Pointer to a @ref PWR_SHUTDOWNTypeDef structure that
420 * contains the SHUTDOWN configuration information.
421 * @retval None.
422 */
HAL_PWR_ConfigSHUTDOWN(PWR_SHUTDOWNTypeDef * sConfigSHUTDOWN)423 HAL_StatusTypeDef HAL_PWR_ConfigSHUTDOWN(PWR_SHUTDOWNTypeDef *sConfigSHUTDOWN)
424 {
425 /* Check the parameters */
426 assert_param(IS_PWR_WAKEUP_PIN_POLARITY(sConfigSHUTDOWN->WakeUpPol));
427
428 /* If the radio IP is not used at all by the SoC (or not yet started), the
429 following steps need to be done after any reset to allow Shutdown mode */
430 if (!LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_MRBLE))
431 {
432 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_MRBLE);
433 }
434 if ((SET_BIT(WAKEUP->BLUE_SLEEP_REQUEST_MODE, WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_EN) == 0) &&
435 (READ_BIT(WAKEUP->CM0_SLEEP_REQUEST_MODE, WAKEUP_CM0_SLEEP_REQUEST_MODE_CPU_WAKEUP_EN) == 0))
436 {
437 SET_BIT(WAKEUP->BLUE_SLEEP_REQUEST_MODE, WAKEUP_BLUE_SLEEP_REQUEST_MODE_FORCE_SLEEPING);
438 }
439
440 /* BOR configuration during Shutdown mode */
441 if (sConfigSHUTDOWN->BORStatus == ENABLE)
442 {
443 LL_PWR_EnableBORinSDN();
444 }
445 else
446 {
447 LL_PWR_DisableBORinSDN();
448 }
449
450 #if defined(STM32WB09)
451 if (sConfigSHUTDOWN->WakeUpPinStatus == ENABLE)
452 {
453 LL_PWR_IOWakeupPolaritySDN(sConfigSHUTDOWN->WakeUpPol);
454 LL_PWR_EnableIOWakeupSDN();
455 }
456 else
457 {
458 LL_PWR_DisableIOWakeupSDN();
459 }
460 #endif /* STM32WB09 */
461
462 #if defined(PWR_CR2_GPIORET)
463 /* Enable the GPIO retention in shutdown configuration */
464 LL_PWR_EnableGPIORET();
465 #endif /* PWR_CR2_GPIORET */
466
467 /* Disable DIRECT HSE configuration to allow shutdown request */
468 if (LL_RCC_DIRECT_HSE_IsEnabled())
469 {
470 LL_RCC_DIRECT_HSE_Disable();
471 }
472
473 return HAL_OK;
474 }
475
476 /**
477 * @brief Indicate SLEEP-ON-EXIT feature when returning from handler mode to
478 * thread mode.
479 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
480 * processor re-enters Sleep mode when an interruption handling is over.
481 * Setting this bit is useful when the processor is expected to run
482 * only on interruptions handling.
483 * @retval None.
484 */
HAL_PWR_EnableSleepOnExit(void)485 void HAL_PWR_EnableSleepOnExit(void)
486 {
487 /* Set SLEEPONEXIT bit of Cortex System Control Register */
488 SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
489 }
490
491 /**
492 * @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to
493 * thread mode.
494 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
495 * processor re-enters Sleep mode when an interruption handling is over.
496 * @retval None.
497 */
HAL_PWR_DisableSleepOnExit(void)498 void HAL_PWR_DisableSleepOnExit(void)
499 {
500 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
501 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
502 }
503
504 /**
505 * @brief Enable Cortex Sev On Pending feature.
506 * @note Set SEVONPEND bit of SCR register. When this bit is set, enabled
507 * events and all interrupts, including disabled ones can wakeup
508 * processor from WFE.
509 * @retval None
510 */
HAL_PWR_EnableSEVOnPend(void)511 void HAL_PWR_EnableSEVOnPend(void)
512 {
513 /* Set SEVONPEND bit of Cortex System Control Register */
514 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
515 }
516
517
518 /**
519 * @brief Disable Cortex Sev On Pending feature.
520 * @note Clear SEVONPEND bit of SCR register. When this bit is clear, only
521 * enable interrupts or events can wakeup processor from WFE
522 * @retval None
523 */
HAL_PWR_DisableSEVOnPend(void)524 void HAL_PWR_DisableSEVOnPend(void)
525 {
526 /* Clear SEVONPEND bit of Cortex System Control Register */
527 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
528 }
529
530 /**
531 * @brief This function handles the PWR PVD interrupt request.
532 * @note This API should be called under the PVD_IRQHandler().
533 * @retval None.
534 */
HAL_PWR_PVD_IRQHandler(void)535 void HAL_PWR_PVD_IRQHandler(void)
536 {
537 /* Check PWR flag */
538 if (__HAL_PWR_PVD_GET_FLAG() != 0U)
539 {
540 /* PWR PVD interrupt user callback */
541 HAL_PWR_PVDCallback();
542
543 /* Clear PVD exti pending bit */
544 __HAL_PWR_PVD_CLEAR_FLAG();
545 }
546 }
547
548 /**
549 * @brief PWR PVD interrupt callback
550 * @retval None
551 */
HAL_PWR_PVDCallback(void)552 __weak void HAL_PWR_PVDCallback(void)
553 {
554 /* NOTE : This function should not be modified; when the callback is needed,
555 the HAL_PWR_PVDCallback can be implemented in the user file
556 */
557 }
558
559 /**
560 * @brief This function handles the PWR WAKEUP interrupt request.
561 * @note This API should be called under the WKUP_IRQHandler().
562 * @retval None.
563 */
HAL_PWR_WKUP_IRQHandler(void)564 void HAL_PWR_WKUP_IRQHandler(void)
565 {
566 uint32_t wakeuppin;
567
568 wakeuppin = HAL_PWR_GetClearWakeupSource();
569
570 /* Wakeup pin line interrupt detected */
571 if (wakeuppin != 0U)
572 {
573 HAL_PWR_WKUPx_Callback(wakeuppin);
574 }
575 }
576
577 /**
578 * @brief PWR WKUPx interrupt callback.
579 * @param WakeupIOs IO wakeup line
580 * @retval None.
581 */
HAL_PWR_WKUPx_Callback(uint32_t WakeupIOs)582 __weak void HAL_PWR_WKUPx_Callback(uint32_t WakeupIOs)
583 {
584 /* NOTE : This function should not be modified, when the callback is needed,
585 the HAL_PWR_WKUPxCallback can be implemented in the user file
586 */
587 }
588
589 /**
590 * @}
591 */
592
593 /**
594 * @}
595 */
596
597 #endif /* HAL_PWR_MODULE_ENABLED */
598 /**
599 * @}
600 */
601
602 /**
603 * @}
604 */
605
