1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 #if defined (USE_FULL_LL_DRIVER)
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32u5xx_ll_dma.h"
43 #include "stm32u5xx_ll_bus.h"
44 #ifdef USE_FULL_ASSERT
45 #include "stm32_assert.h"
46 #else
47 #define assert_param(expr) ((void)0U)
48 #endif /* USE_FULL_ASSERT */
49
50 /** @addtogroup STM32U5xx_LL_Driver
51 * @{
52 */
53
54 #if (defined (GPDMA1) || defined (LPDMA1))
55
56 /** @addtogroup DMA_LL
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62 /* Private constants ---------------------------------------------------------*/
63 /* Private macros ------------------------------------------------------------*/
64
65 /** @addtogroup DMA_LL_Private_Macros
66 * @{
67 */
68 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == GPDMA1) && \
69 (((Channel) == LL_DMA_CHANNEL_0) || \
70 ((Channel) == LL_DMA_CHANNEL_1) || \
71 ((Channel) == LL_DMA_CHANNEL_2) || \
72 ((Channel) == LL_DMA_CHANNEL_3) || \
73 ((Channel) == LL_DMA_CHANNEL_4) || \
74 ((Channel) == LL_DMA_CHANNEL_5) || \
75 ((Channel) == LL_DMA_CHANNEL_6) || \
76 ((Channel) == LL_DMA_CHANNEL_7) || \
77 ((Channel) == LL_DMA_CHANNEL_8) || \
78 ((Channel) == LL_DMA_CHANNEL_9) || \
79 ((Channel) == LL_DMA_CHANNEL_10) || \
80 ((Channel) == LL_DMA_CHANNEL_11) || \
81 ((Channel) == LL_DMA_CHANNEL_12) || \
82 ((Channel) == LL_DMA_CHANNEL_13) || \
83 ((Channel) == LL_DMA_CHANNEL_14) || \
84 ((Channel) == LL_DMA_CHANNEL_15) || \
85 ((Channel) == LL_DMA_CHANNEL_ALL))) || \
86 (((INSTANCE) == LPDMA1) && \
87 (((Channel) == LL_DMA_CHANNEL_0) || \
88 ((Channel) == LL_DMA_CHANNEL_1) || \
89 ((Channel) == LL_DMA_CHANNEL_2) || \
90 ((Channel) == LL_DMA_CHANNEL_3) || \
91 ((Channel) == LL_DMA_CHANNEL_ALL))))
92
93 #define IS_LL_GPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \
94 (((Channel) == LL_DMA_CHANNEL_0) || \
95 ((Channel) == LL_DMA_CHANNEL_1) || \
96 ((Channel) == LL_DMA_CHANNEL_2) || \
97 ((Channel) == LL_DMA_CHANNEL_3) || \
98 ((Channel) == LL_DMA_CHANNEL_4) || \
99 ((Channel) == LL_DMA_CHANNEL_5) || \
100 ((Channel) == LL_DMA_CHANNEL_6) || \
101 ((Channel) == LL_DMA_CHANNEL_7) || \
102 ((Channel) == LL_DMA_CHANNEL_8) || \
103 ((Channel) == LL_DMA_CHANNEL_9) || \
104 ((Channel) == LL_DMA_CHANNEL_10) || \
105 ((Channel) == LL_DMA_CHANNEL_11) || \
106 ((Channel) == LL_DMA_CHANNEL_12) || \
107 ((Channel) == LL_DMA_CHANNEL_13) || \
108 ((Channel) == LL_DMA_CHANNEL_14) || \
109 ((Channel) == LL_DMA_CHANNEL_15)))
110
111 #define IS_LL_DMA_2D_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \
112 (((Channel) == LL_DMA_CHANNEL_12) || \
113 ((Channel) == LL_DMA_CHANNEL_13) || \
114 ((Channel) == LL_DMA_CHANNEL_14) || \
115 ((Channel) == LL_DMA_CHANNEL_15)))
116
117 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \
118 ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
119 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH))
120
121 #define IS_LL_DMA_DATA_ALIGNMENT(__VALUE__) (((__VALUE__) == LL_DMA_DATA_ALIGN_ZEROPADD) || \
122 ((__VALUE__) == LL_DMA_DATA_ALIGN_SIGNEXTPADD) || \
123 ((__VALUE__) == LL_DMA_DATA_PACK_UNPACK))
124
125 #define IS_LL_DMA_BURST_LENGTH(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= 64U))
126
127 #define IS_LL_DMA_SRC_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_SRC_DATAWIDTH_BYTE) || \
128 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_HALFWORD) || \
129 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_WORD))
130
131 #define IS_LL_DMA_DEST_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_DEST_DATAWIDTH_BYTE) || \
132 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_HALFWORD) || \
133 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_WORD))
134
135 #define IS_LL_DMA_SRC_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_FIXED) || \
136 ((__VALUE__) == LL_DMA_SRC_INCREMENT))
137
138 #define IS_LL_DMA_DEST_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_FIXED) || \
139 ((__VALUE__) == LL_DMA_DEST_INCREMENT))
140
141 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_LOW_PRIORITY_LOW_WEIGHT) || \
142 ((__VALUE__) == LL_DMA_LOW_PRIORITY_MID_WEIGHT) || \
143 ((__VALUE__) == LL_DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
144 ((__VALUE__) == LL_DMA_HIGH_PRIORITY))
145
146 #define IS_LL_DMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0xFFFFU)
147
148 #define IS_LL_DMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x0EFFU)
149
150 #define IS_LL_DMA_TRIGGER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TRIGM_BLK_TRANSFER) || \
151 ((__VALUE__) == LL_DMA_TRIGM_RPT_BLK_TRANSFER) || \
152 ((__VALUE__) == LL_DMA_TRIGM_LLI_LINK_TRANSFER) || \
153 ((__VALUE__) == LL_DMA_TRIGM_SINGLBURST_TRANSFER ))
154
155 #define IS_LL_DMA_TRIGGER_POLARITY(__VALUE__) (((__VALUE__) == LL_DMA_TRIG_POLARITY_MASKED) || \
156 ((__VALUE__) == LL_DMA_TRIG_POLARITY_RISING) || \
157 ((__VALUE__) == LL_DMA_TRIG_POLARITY_FALLING))
158
159 #define IS_LL_DMA_BLKHW_REQUEST(__VALUE__) (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \
160 ((__VALUE__) == LL_DMA_HWREQUEST_BLK))
161
162 #if defined (LL_GPDMA1_TRIGGER_JPEG_OFT)
163 #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_JPEG_OFT)
164 #else
165 #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_ADC1_AWD1)
166 #endif /* LL_GPDMA1_TRIGGER_JPEG_OFT */
167
168 #if defined (LL_GPDMA1_REQUEST_JPEG_TX)
169 #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_JPEG_TX)
170 #elif defined (LL_GPDMA1_REQUEST_ADC2)
171 #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_ADC2)
172 #else
173 #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM3_UE)
174 #endif /* LL_GPDMA1_REQUEST_JPEG_TX */
175
176 #define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \
177 ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \
178 ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \
179 ((__VALUE__) == LL_DMA_TCEM_LAST_LLITEM_TRANSFER))
180
181 #define IS_LL_DMA_DEST_HALFWORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_HALFWORD_PRESERVE) || \
182 ((__VALUE__) == LL_DMA_DEST_HALFWORD_EXCHANGE))
183
184 #define IS_LL_DMA_DEST_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_BYTE_PRESERVE) || \
185 ((__VALUE__) == LL_DMA_DEST_BYTE_EXCHANGE))
186
187 #define IS_LL_DMA_SRC_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_BYTE_PRESERVE) || \
188 ((__VALUE__) == LL_DMA_SRC_BYTE_EXCHANGE))
189
190 #define IS_LL_DMA_LINK_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT0) || \
191 ((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT1))
192
193 #define IS_LL_DMA_SRC_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT0) || \
194 ((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT1))
195
196 #define IS_LL_DMA_DEST_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT0) || \
197 ((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT1))
198
199 #define IS_LL_DMA_LINK_STEP_MODE(__VALUE__) (((__VALUE__) == LL_DMA_LSM_FULL_EXECUTION) || \
200 ((__VALUE__) == LL_DMA_LSM_1LINK_EXECUTION))
201
202 #define IS_LL_DMA_BURST_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_SRC_ADDR_INCREMENT) || \
203 ((__VALUE__) == LL_DMA_BURST_SRC_ADDR_DECREMENT))
204
205 #define IS_LL_DMA_BURST_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_DEST_ADDR_INCREMENT) || \
206 ((__VALUE__) == LL_DMA_BURST_DEST_ADDR_DECREMENT))
207
208 #define IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
209
210 #define IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_INCREMENT) || \
211 ((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_DECREMENT))
212
213 #define IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_INCREMENT) || \
214 ((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_DECREMENT))
215
216 #define IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0xFFFFU)
217
218 #define IS_LL_DMA_LINK_BASEADDR(__VALUE__) (((__VALUE__) & 0xFFFFU) == 0U)
219
220 #define IS_LL_DMA_LINK_ADDR_OFFSET(__VALUE__) (((__VALUE__) & 0x03U) == 0U)
221
222 #define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__) ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U))
223
224 #define IS_LL_DMA_LINK_NODETYPE(__VALUE__) (((__VALUE__) == LL_DMA_GPDMA_2D_NODE) || \
225 ((__VALUE__) == LL_DMA_GPDMA_LINEAR_NODE) || \
226 ((__VALUE__) == LL_DMA_LPDMA_LINEAR_NODE))
227
228 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
229 #define IS_LL_DMA_CHANNEL_SRC_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_SRC_NSEC) || \
230 ((__VALUE__) == LL_DMA_CHANNEL_SRC_SEC))
231
232 #define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \
233 ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC))
234
235 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
236 /**
237 * @}
238 */
239
240 /* Private function prototypes -----------------------------------------------*/
241 /* Exported functions --------------------------------------------------------*/
242
243 /** @addtogroup DMA_LL_Exported_Functions
244 * @{
245 */
246
247 /** @addtogroup DMA_LL_EF_Init
248 * @{
249 */
250
251 /**
252 * @brief De-initialize the DMA registers to their default reset values.
253 * @note This API is used for all available DMA channels.
254 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
255 * helper macros :
256 * @arg @ref LL_DMA_GET_INSTANCE
257 * @arg @ref LL_DMA_GET_CHANNEL
258 * @param DMAx DMAx Instance
259 * @param Channel This parameter can be one of the following values:
260 * @arg @ref LL_DMA_CHANNEL_0
261 * @arg @ref LL_DMA_CHANNEL_1
262 * @arg @ref LL_DMA_CHANNEL_2
263 * @arg @ref LL_DMA_CHANNEL_3
264 * @arg @ref LL_DMA_CHANNEL_4
265 * @arg @ref LL_DMA_CHANNEL_5
266 * @arg @ref LL_DMA_CHANNEL_6
267 * @arg @ref LL_DMA_CHANNEL_7
268 * @arg @ref LL_DMA_CHANNEL_8
269 * @arg @ref LL_DMA_CHANNEL_9
270 * @arg @ref LL_DMA_CHANNEL_10
271 * @arg @ref LL_DMA_CHANNEL_11
272 * @arg @ref LL_DMA_CHANNEL_12
273 * @arg @ref LL_DMA_CHANNEL_13
274 * @arg @ref LL_DMA_CHANNEL_14
275 * @arg @ref LL_DMA_CHANNEL_15
276 * @retval An ErrorStatus enumeration value:
277 * - SUCCESS : DMA registers are de-initialized.
278 * - ERROR : DMA registers are not de-initialized.
279 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)280 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
281 {
282 DMA_Channel_TypeDef *tmp;
283 ErrorStatus status = SUCCESS;
284
285 /* Check the DMA Instance DMAx and Channel parameters */
286 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
287
288 if (Channel == LL_DMA_CHANNEL_ALL)
289 {
290 if (DMAx == GPDMA1)
291 {
292 /* Force reset of DMA clock */
293 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
294
295 /* Release reset of DMA clock */
296 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
297 }
298 else
299 {
300 /* Force reset of DMA clock */
301 LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_LPDMA1);
302
303 /* Release reset of DMA clock */
304 LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_LPDMA1);
305 }
306 }
307 else
308 {
309 /* Get the DMA Channel Instance */
310 tmp = (DMA_Channel_TypeDef *)(LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
311
312 /* Suspend DMA channel */
313 LL_DMA_SuspendChannel(DMAx, Channel);
314
315 /* Disable the selected Channel */
316 LL_DMA_ResetChannel(DMAx, Channel);
317
318 /* Reset DMAx_Channely control register */
319 LL_DMA_WriteReg(tmp, CLBAR, 0U);
320
321 /* Reset DMAx_Channely control register */
322 LL_DMA_WriteReg(tmp, CCR, 0U);
323
324 /* Reset DMAx_Channely Configuration register */
325 LL_DMA_WriteReg(tmp, CTR1, 0U);
326
327 /* Reset DMAx_Channely transfer register 2 */
328 LL_DMA_WriteReg(tmp, CTR2, 0U);
329
330 /* Reset DMAx_Channely block number of data register */
331 LL_DMA_WriteReg(tmp, CBR1, 0U);
332
333 /* Reset DMAx_Channely source address register */
334 LL_DMA_WriteReg(tmp, CSAR, 0U);
335
336 /* Reset DMAx_Channely destination address register */
337 LL_DMA_WriteReg(tmp, CDAR, 0U);
338
339 /* Check DMA channel */
340 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
341 {
342 /* Reset DMAx_Channely transfer register 3 */
343 LL_DMA_WriteReg(tmp, CTR3, 0U);
344
345 /* Reset DMAx_Channely Block register 2 */
346 LL_DMA_WriteReg(tmp, CBR2, 0U);
347 }
348
349 /* Reset DMAx_Channely Linked list address register */
350 LL_DMA_WriteReg(tmp, CLLR, 0U);
351
352 /* Reset DMAx_Channely pending flags */
353 LL_DMA_WriteReg(tmp, CFCR, 0x00003F00U);
354
355 /* Reset DMAx_Channely attribute */
356 LL_DMA_DisableChannelPrivilege(DMAx, Channel);
357
358 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
359 LL_DMA_DisableChannelSecure(DMAx, Channel);
360 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
361 }
362
363 return (uint32_t)status;
364 }
365
366 /**
367 * @brief Initialize the DMA registers according to the specified parameters
368 * in DMA_InitStruct.
369 * @note This API is used for all available DMA channels.
370 * @note A software request transfer can be done once programming the direction
371 * field in memory to memory value.
372 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
373 * helper macros :
374 * @arg @ref LL_DMA_GET_INSTANCE
375 * @arg @ref LL_DMA_GET_CHANNEL
376 * @param DMAx DMAx Instance
377 * @param Channel This parameter can be one of the following values:
378 * @arg @ref LL_DMA_CHANNEL_0
379 * @arg @ref LL_DMA_CHANNEL_1
380 * @arg @ref LL_DMA_CHANNEL_2
381 * @arg @ref LL_DMA_CHANNEL_3
382 * @arg @ref LL_DMA_CHANNEL_4
383 * @arg @ref LL_DMA_CHANNEL_5
384 * @arg @ref LL_DMA_CHANNEL_6
385 * @arg @ref LL_DMA_CHANNEL_7
386 * @arg @ref LL_DMA_CHANNEL_8
387 * @arg @ref LL_DMA_CHANNEL_9
388 * @arg @ref LL_DMA_CHANNEL_10
389 * @arg @ref LL_DMA_CHANNEL_11
390 * @arg @ref LL_DMA_CHANNEL_12
391 * @arg @ref LL_DMA_CHANNEL_13
392 * @arg @ref LL_DMA_CHANNEL_14
393 * @arg @ref LL_DMA_CHANNEL_15
394 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
395 * @retval An ErrorStatus enumeration value:
396 * - SUCCESS : DMA registers are initialized.
397 * - ERROR : Not applicable.
398 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)399 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
400 {
401 /* Check the DMA Instance DMAx and Channel parameters*/
402 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
403
404 /* Check the DMA parameters from DMA_InitStruct */
405 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
406
407 /* Check direction */
408 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
409 {
410 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitStruct->Request));
411 }
412
413 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitStruct->DataAlignment));
414 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitStruct->SrcDataWidth));
415 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitStruct->DestDataWidth));
416 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitStruct->SrcIncMode));
417 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitStruct->DestIncMode));
418 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
419 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitStruct->BlkDataLength));
420 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitStruct->TriggerPolarity));
421 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitStruct->BlkHWRequest));
422 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitStruct->TransferEventMode));
423 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitStruct->LinkStepMode));
424 assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr));
425 assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset));
426
427 /* Check DMA instance */
428 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
429 {
430 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->SrcBurstLength));
431 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->DestBurstLength));
432 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitStruct->DestHWordExchange));
433 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitStruct->DestByteExchange));
434 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitStruct->SrcByteExchange));
435 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitStruct->LinkAllocatedPort));
436 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitStruct->SrcAllocatedPort));
437 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitStruct->DestAllocatedPort));
438 }
439
440 /* Check trigger polarity */
441 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
442 {
443 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitStruct->TriggerMode));
444 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitStruct->TriggerSelection));
445 }
446
447 /* Check DMA channel */
448 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
449 {
450 assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitStruct->BlkRptCount));
451 assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitStruct->SrcAddrUpdateMode));
452 assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitStruct->DestAddrUpdateMode));
453 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->SrcAddrOffset));
454 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->DestAddrOffset));
455 assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitStruct->BlkRptSrcAddrUpdateMode));
456 assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitStruct->BlkRptDestAddrUpdateMode));
457 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptSrcAddrOffset));
458 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptDestAddrOffset));
459 }
460
461 /*-------------------------- DMAx CLBAR Configuration ------------------------
462 * Configure the Transfer linked list address with parameter :
463 * - LinkedListBaseAdd: DMA_CLBAR_LBA[31:16] bits
464 */
465 LL_DMA_SetLinkedListBaseAddr(DMAx, Channel, DMA_InitStruct->LinkedListBaseAddr);
466
467 /*-------------------------- DMAx CCR Configuration --------------------------
468 * Configure the control parameter :
469 * - LinkAllocatedPort: DMA_CCR_LAP bit
470 * LinkAllocatedPort field is not supported by LPDMA channels.
471 * - LinkStepMode: DMA_CCR_LSM bit
472 * - Priority: DMA_CCR_PRIO [23:22] bits
473 */
474 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitStruct->Priority | \
475 DMA_InitStruct->LinkAllocatedPort | \
476 DMA_InitStruct->LinkStepMode);
477
478 /*-------------------------- DMAx CTR1 Configuration -------------------------
479 * Configure the Data transfer parameter :
480 * - DestAllocatedPort: DMA_CTR1_DAP bit
481 * DestAllocatedPort field is not supported by LPDMA channels.
482 * - DestHWordExchange: DMA_CTR1_DHX bit
483 * DestHWordExchange field is not supported by LPDMA channels.
484 * - DestByteExchange: DMA_CTR1_DBX bit
485 * DestByteExchange field is not supported by LPDMA channels.
486 * - DestIncMode: DMA_CTR1_DINC bit
487 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
488 * - SrcAllocatedPort: DMA_CTR1_SAP bit
489 * SrcAllocatedPort field is not supported by LPDMA channels.
490 * - SrcByteExchange: DMA_CTR1_SBX bit
491 * SrcByteExchange field is not supported by LPDMA channels.
492 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
493 * DataAlignment field is reduced to one bit by LPDMA channels.
494 * - SrcIncMode: DMA_CTR1_SINC bit
495 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
496 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
497 * SrcBurstLength field is not supported by LPDMA channels.
498 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
499 * DestBurstLength field is not supported by LPDMA channels.
500 */
501 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->DestAllocatedPort | \
502 DMA_InitStruct->DestHWordExchange | \
503 DMA_InitStruct->DestByteExchange | \
504 DMA_InitStruct->DestIncMode | \
505 DMA_InitStruct->DestDataWidth | \
506 DMA_InitStruct->SrcAllocatedPort | \
507 DMA_InitStruct->SrcByteExchange | \
508 DMA_InitStruct->DataAlignment | \
509 DMA_InitStruct->SrcIncMode | \
510 DMA_InitStruct->SrcDataWidth);
511 /* Check DMA instance */
512 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
513 {
514 LL_DMA_ConfigBurstLength(DMAx, Channel, DMA_InitStruct->SrcBurstLength,
515 DMA_InitStruct->DestBurstLength);
516 }
517
518 /*-------------------------- DMAx CTR2 Configuration -------------------------
519 * Configure the channel transfer parameter :
520 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
521 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
522 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
523 * - BlkHWRequest: DMA_CTR2_BREQ bit
524 * - Direction: DMA_CTR2_DREQ bit
525 * - Direction: DMA_CTR2_SWREQ bit
526 * Direction field is reduced to one bit for LPDMA channels (SWREQ).
527 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
528 * TriggerSelection field is reduced to 5 bits for LPDMA channels.
529 * - Request: DMA_CTR2_REQSEL [6:0] bits
530 * Request field is reduced to 5 bits for LPDMA channels.
531 */
532 LL_DMA_ConfigChannelTransfer(DMAx, Channel, DMA_InitStruct->TransferEventMode | \
533 DMA_InitStruct->TriggerPolarity | \
534 DMA_InitStruct->BlkHWRequest | \
535 DMA_InitStruct->Direction);
536
537 /* Check direction */
538 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
539 {
540 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->Request);
541 }
542
543 /* Check trigger polarity */
544 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
545 {
546 LL_DMA_SetHWTrigger(DMAx, Channel, DMA_InitStruct->TriggerSelection);
547 LL_DMA_SetTriggerMode(DMAx, Channel, DMA_InitStruct->TriggerMode);
548 }
549
550 /*-------------------------- DMAx CBR1 Configuration -------------------------
551 * Configure the Transfer Block counters and update mode with parameter :
552 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
553 * - BlkRptCount: DMA_CBR1_BRC[26:16] bits
554 * BlkRptCount field is supported only by 2D addressing channels.
555 * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit
556 * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
557 * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit
558 * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
559 * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit
560 * SrcAddrUpdateMode field is supported only by 2D addressing channels.
561 * - DestAddrUpdateMode: DMA_CBR1_DDEC bit
562 * DestAddrUpdateMode field is supported only by 2D addressing channels.
563 */
564 LL_DMA_SetBlkDataLength(DMAx, Channel, DMA_InitStruct->BlkDataLength);
565
566 /* Check DMA channel */
567 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
568 {
569 LL_DMA_SetBlkRptCount(DMAx, Channel, DMA_InitStruct->BlkRptCount);
570 LL_DMA_ConfigBlkRptAddrUpdate(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrUpdateMode | \
571 DMA_InitStruct->BlkRptDestAddrUpdateMode | \
572 DMA_InitStruct->SrcAddrUpdateMode | \
573 DMA_InitStruct->DestAddrUpdateMode);
574 }
575
576 /*-------------------------- DMAx CSAR and CDAR Configuration ----------------
577 * Configure the Transfer source address with parameter :
578 * - SrcAddress: DMA_CSAR_SA[31:0] bits
579 * - DestAddress: DMA_CDAR_DA[31:0] bits
580 */
581 LL_DMA_ConfigAddresses(DMAx, Channel, DMA_InitStruct->SrcAddress, DMA_InitStruct->DestAddress);
582
583 /* Check DMA channel */
584 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
585 {
586 /*------------------------ DMAx CTR3 Configuration -------------------------
587 * Configure the Transfer Block counters and update mode with parameter :
588 * - SrcAddrOffset: DMA_CTR3_SAO[28:16] bits
589 * SrcAddrOffset field is supported only by 2D addressing channels.
590 * - DestAddrOffset: DMA_CTR3_DAO[12:0] bits
591 * DestAddrOffset field is supported only by 2D addressing channels.
592 */
593 LL_DMA_ConfigAddrUpdateValue(DMAx, Channel, DMA_InitStruct->SrcAddrOffset, DMA_InitStruct->DestAddrOffset);
594
595 /*------------------------ DMAx CBR2 Configuration -----------------------
596 * Configure the Transfer Block counters and update mode with parameter :
597 * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits
598 * BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
599 * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits
600 * BlkRptDestAddrOffset field is supported only by 2D addressing channels.
601 */
602 LL_DMA_ConfigBlkRptAddrUpdateValue(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrOffset,
603 DMA_InitStruct->BlkRptDestAddrOffset);
604 }
605
606 /*-------------------------- DMAx CLLR Configuration -------------------------
607 * Configure the Transfer linked list address with parameter :
608 * - DestAddrOffset: DMA_CLLR_LA[15:2] bits
609 */
610 LL_DMA_SetLinkedListAddrOffset(DMAx, Channel, DMA_InitStruct->LinkedListAddrOffset);
611
612 return (uint32_t)SUCCESS;
613 }
614
615 /**
616 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
617 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
618 * @retval None.
619 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)620 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
621 {
622 /* Set DMA_InitStruct fields to default values */
623 DMA_InitStruct->SrcAddress = 0x00000000U;
624 DMA_InitStruct->DestAddress = 0x00000000U;
625 DMA_InitStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
626 DMA_InitStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
627 DMA_InitStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
628 DMA_InitStruct->SrcBurstLength = 1U;
629 DMA_InitStruct->DestBurstLength = 1U;
630 DMA_InitStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
631 DMA_InitStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
632 DMA_InitStruct->SrcIncMode = LL_DMA_SRC_FIXED;
633 DMA_InitStruct->DestIncMode = LL_DMA_DEST_FIXED;
634 DMA_InitStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
635 DMA_InitStruct->BlkDataLength = 0x00000000U;
636 DMA_InitStruct->BlkRptCount = 0x00000000U;
637 DMA_InitStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
638 DMA_InitStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
639 DMA_InitStruct->TriggerSelection = 0x00000000U;
640 DMA_InitStruct->Request = 0x00000000U;
641 DMA_InitStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
642 DMA_InitStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
643 DMA_InitStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
644 DMA_InitStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
645 DMA_InitStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
646 DMA_InitStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
647 DMA_InitStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
648 DMA_InitStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
649 DMA_InitStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
650 DMA_InitStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
651 DMA_InitStruct->SrcAddrOffset = 0x00000000U;
652 DMA_InitStruct->DestAddrOffset = 0x00000000U;
653 DMA_InitStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
654 DMA_InitStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
655 DMA_InitStruct->BlkRptSrcAddrOffset = 0x00000000U;
656 DMA_InitStruct->BlkRptDestAddrOffset = 0x00000000U;
657 DMA_InitStruct->LinkedListBaseAddr = 0x00000000U;
658 DMA_InitStruct->LinkedListAddrOffset = 0x00000000U;
659 }
660
661 /**
662 * @brief Set each @ref LL_DMA_InitLinkedListTypeDef field to default value.
663 * @param DMA_InitLinkedListStruct Pointer to
664 * a @ref LL_DMA_InitLinkedListTypeDef structure.
665 * @retval None.
666 */
LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)667 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
668 {
669 /* Set LL_DMA_InitLinkedListTypeDef fields to default values */
670 DMA_InitLinkedListStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
671 DMA_InitLinkedListStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
672 DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER;
673 DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
674 }
675
676 /**
677 * @brief De-initialize the DMA linked list.
678 * @note This API is used for all available DMA channels.
679 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
680 * helper macros :
681 * @arg @ref LL_DMA_GET_INSTANCE
682 * @arg @ref LL_DMA_GET_CHANNEL
683 * @param DMAx DMAx Instance
684 * @param Channel This parameter can be one of the following values:
685 * @arg @ref LL_DMA_CHANNEL_0
686 * @arg @ref LL_DMA_CHANNEL_1
687 * @arg @ref LL_DMA_CHANNEL_2
688 * @arg @ref LL_DMA_CHANNEL_3
689 * @arg @ref LL_DMA_CHANNEL_4
690 * @arg @ref LL_DMA_CHANNEL_5
691 * @arg @ref LL_DMA_CHANNEL_6
692 * @arg @ref LL_DMA_CHANNEL_7
693 * @arg @ref LL_DMA_CHANNEL_8
694 * @arg @ref LL_DMA_CHANNEL_9
695 * @arg @ref LL_DMA_CHANNEL_10
696 * @arg @ref LL_DMA_CHANNEL_11
697 * @arg @ref LL_DMA_CHANNEL_12
698 * @arg @ref LL_DMA_CHANNEL_13
699 * @arg @ref LL_DMA_CHANNEL_14
700 * @arg @ref LL_DMA_CHANNEL_15
701 * @retval An ErrorStatus enumeration value:
702 * - SUCCESS : DMA registers are de-initialized.
703 * - ERROR : DMA registers are not de-initialized.
704 */
LL_DMA_List_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)705 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
706 {
707 return LL_DMA_DeInit(DMAx, Channel);
708 }
709
710 /**
711 * @brief Initialize the DMA linked list according to the specified parameters
712 * in LL_DMA_InitLinkedListTypeDef.
713 * @note This API is used for all available DMA channels.
714 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
715 * helper macros :
716 * @arg @ref LL_DMA_GET_INSTANCE
717 * @arg @ref LL_DMA_GET_CHANNEL
718 * @param DMAx DMAx Instance
719 * @param Channel This parameter can be one of the following values:
720 * @arg @ref LL_DMA_CHANNEL_0
721 * @arg @ref LL_DMA_CHANNEL_1
722 * @arg @ref LL_DMA_CHANNEL_2
723 * @arg @ref LL_DMA_CHANNEL_3
724 * @arg @ref LL_DMA_CHANNEL_4
725 * @arg @ref LL_DMA_CHANNEL_5
726 * @arg @ref LL_DMA_CHANNEL_6
727 * @arg @ref LL_DMA_CHANNEL_7
728 * @arg @ref LL_DMA_CHANNEL_8
729 * @arg @ref LL_DMA_CHANNEL_9
730 * @arg @ref LL_DMA_CHANNEL_10
731 * @arg @ref LL_DMA_CHANNEL_11
732 * @arg @ref LL_DMA_CHANNEL_12
733 * @arg @ref LL_DMA_CHANNEL_13
734 * @arg @ref LL_DMA_CHANNEL_14
735 * @arg @ref LL_DMA_CHANNEL_15
736 * @param DMA_InitLinkedListStruct pointer to
737 * a @ref LL_DMA_InitLinkedListTypeDef structure.
738 * @retval An ErrorStatus enumeration value:
739 * - SUCCESS : DMA registers are initialized.
740 * - ERROR : Not applicable.
741 */
LL_DMA_List_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)742 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
743 {
744 /* Check the DMA Instance DMAx and Channel parameters*/
745 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
746
747 /* Check the DMA parameters from DMA_InitLinkedListStruct */
748 assert_param(IS_LL_DMA_PRIORITY(DMA_InitLinkedListStruct->Priority));
749 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitLinkedListStruct->LinkStepMode));
750 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitLinkedListStruct->TransferEventMode));
751 /* Check DMA instance */
752 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
753 {
754 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitLinkedListStruct->LinkAllocatedPort));
755 }
756
757 /*-------------------------- DMAx CCR Configuration --------------------------
758 * Configure the control parameter :
759 * - LinkAllocatedPort: DMA_CCR_LAP bit
760 * LinkAllocatedPort field is supported only by GPDMA channels.
761 * - LinkStepMode: DMA_CCR_LSM bit
762 * - Priority: DMA_CCR_PRIO [23:22] bits
763 */
764 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \
765 DMA_InitLinkedListStruct->LinkAllocatedPort | \
766 DMA_InitLinkedListStruct->LinkStepMode);
767
768 /*-------------------------- DMAx CTR2 Configuration -------------------------
769 * Configure the channel transfer parameter :
770 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
771 */
772 LL_DMA_SetTransferEventMode(DMAx, Channel, DMA_InitLinkedListStruct->TransferEventMode);
773
774 return (uint32_t)SUCCESS;
775 }
776
777 /**
778 * @brief Set each @ref LL_DMA_InitNodeTypeDef field to default value.
779 * @param DMA_InitNodeStruct Pointer to a @ref LL_DMA_InitNodeTypeDef
780 * structure.
781 * @retval None.
782 */
LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct)783 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct)
784 {
785 /* Set DMA_InitNodeStruct fields to default values */
786 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
787 DMA_InitNodeStruct->DestSecure = LL_DMA_CHANNEL_DEST_NSEC;
788 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
789 DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
790 DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
791 DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
792 DMA_InitNodeStruct->DestBurstLength = 1U;
793 DMA_InitNodeStruct->DestIncMode = LL_DMA_DEST_FIXED;
794 DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
795 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
796 DMA_InitNodeStruct->SrcSecure = LL_DMA_CHANNEL_SRC_NSEC;
797 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
798 DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
799 DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
800 DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
801 DMA_InitNodeStruct->SrcBurstLength = 1U;
802 DMA_InitNodeStruct->SrcIncMode = LL_DMA_SRC_FIXED;
803 DMA_InitNodeStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
804 DMA_InitNodeStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
805 DMA_InitNodeStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
806 DMA_InitNodeStruct->TriggerSelection = 0x00000000U;
807 DMA_InitNodeStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
808 DMA_InitNodeStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
809 DMA_InitNodeStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
810 DMA_InitNodeStruct->Request = 0x00000000U;
811 DMA_InitNodeStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
812 DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
813 DMA_InitNodeStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
814 DMA_InitNodeStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
815 DMA_InitNodeStruct->BlkRptCount = 0x00000000U;
816 DMA_InitNodeStruct->BlkDataLength = 0x00000000U;
817 DMA_InitNodeStruct->SrcAddress = 0x00000000U;
818 DMA_InitNodeStruct->DestAddress = 0x00000000U;
819 DMA_InitNodeStruct->DestAddrOffset = 0x00000000U;
820 DMA_InitNodeStruct->SrcAddrOffset = 0x00000000U;
821 DMA_InitNodeStruct->BlkRptDestAddrOffset = 0x00000000U;
822 DMA_InitNodeStruct->BlkRptSrcAddrOffset = 0x00000000U;
823 DMA_InitNodeStruct->UpdateRegisters = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | \
824 LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | \
825 LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CTR3 | \
826 LL_DMA_UPDATE_CBR2 | LL_DMA_UPDATE_CLLR);
827 DMA_InitNodeStruct->NodeType = LL_DMA_GPDMA_LINEAR_NODE;
828 }
829
830 /**
831 * @brief Initializes DMA linked list node according to the specified
832 * parameters in the DMA_InitNodeStruct.
833 * @param DMA_InitNodeStruct Pointer to a LL_DMA_InitNodeTypeDef structure
834 * that contains linked list node
835 * registers configurations.
836 * @param pNode Pointer to linked list node to fill according to
837 * LL_DMA_LinkNodeTypeDef parameters.
838 * @retval None
839 */
LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct,LL_DMA_LinkNodeTypeDef * pNode)840 uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode)
841 {
842 uint32_t reg_counter = 0U;
843
844 /* Check the DMA Node type */
845 assert_param(IS_LL_DMA_LINK_NODETYPE(DMA_InitNodeStruct->NodeType));
846
847 /* Check the DMA parameters from DMA_InitNodeStruct */
848 assert_param(IS_LL_DMA_DIRECTION(DMA_InitNodeStruct->Direction));
849
850 /* Check direction */
851 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
852 {
853 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitNodeStruct->Request));
854 }
855
856 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitNodeStruct->DataAlignment));
857 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitNodeStruct->SrcDataWidth));
858 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitNodeStruct->DestDataWidth));
859 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitNodeStruct->SrcIncMode));
860 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitNodeStruct->DestIncMode));
861 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitNodeStruct->BlkDataLength));
862 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitNodeStruct->TriggerPolarity));
863 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitNodeStruct->BlkHWRequest));
864 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitNodeStruct->TransferEventMode));
865 assert_param(IS_LL_DMA_LINK_UPDATE_REGISTERS(DMA_InitNodeStruct->UpdateRegisters));
866
867 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
868 assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure));
869 assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure));
870 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
871
872 /* Check trigger polarity */
873 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
874 {
875 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode));
876 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection));
877 }
878 /* Check non 2D addressing settings */
879 if (DMA_InitNodeStruct->NodeType != LL_DMA_LPDMA_LINEAR_NODE)
880 {
881 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength));
882 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength));
883 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitNodeStruct->DestHWordExchange));
884 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitNodeStruct->DestByteExchange));
885 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitNodeStruct->SrcByteExchange));
886 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitNodeStruct->SrcAllocatedPort));
887 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitNodeStruct->DestAllocatedPort));
888 }
889
890 /* Check DMA channel */
891 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
892 {
893 assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitNodeStruct->BlkRptCount));
894 assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitNodeStruct->SrcAddrUpdateMode));
895 assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitNodeStruct->DestAddrUpdateMode));
896 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->SrcAddrOffset));
897 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->DestAddrOffset));
898 assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode));
899 assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptDestAddrUpdateMode));
900 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptSrcAddrOffset));
901 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptDestAddrOffset));
902 }
903
904 /* Check if CTR1 register update is enabled */
905 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR1) == LL_DMA_UPDATE_CTR1)
906 {
907 /*-------------------------- DMAx CTR1 Configuration -----------------------
908 * Configure the Data transfer parameter :
909 * - DestAllocatedPort: DMA_CTR1_DAP bit
910 * DestAllocatedPort field is not supported by LPDMA channels.
911 * - DestHWordExchange: DMA_CTR1_DHX bit
912 * DestHWordExchange field is not supported by LPDMA channels.
913 * - DestByteExchange: DMA_CTR1_DBX bit
914 * DestByteExchange field is not supported by LPDMA channels.
915 * - DestIncMode: DMA_CTR1_DINC bit
916 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
917 * - SrcAllocatedPort: DMA_CTR1_SAP bit
918 * SrcAllocatedPort field is not supported by LPDMA channels.
919 * - SrcByteExchange: DMA_CTR1_SBX bit
920 * SrcByteExchange field is not supported by LPDMA channels.
921 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
922 * DataAlignment field is reduced to one bit for LPDMA channels.
923 * - SrcIncMode: DMA_CTR1_SINC bit
924 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
925 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
926 * SrcBurstLength field is not supported by LPDMA channels.
927 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
928 * DestBurstLength field is not supported by LPDMA channels.
929 */
930
931 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->DestIncMode | \
932 DMA_InitNodeStruct->DestDataWidth | \
933 DMA_InitNodeStruct->DataAlignment | \
934 DMA_InitNodeStruct->SrcIncMode | \
935 DMA_InitNodeStruct->SrcDataWidth);
936
937 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
938 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \
939 DMA_InitNodeStruct->SrcSecure);
940 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
941
942 /* Update CTR1 register fields for not LPDMA channels */
943 if (DMA_InitNodeStruct->NodeType != LL_DMA_LPDMA_LINEAR_NODE)
944 {
945 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \
946 DMA_InitNodeStruct->DestHWordExchange | \
947 DMA_InitNodeStruct->DestByteExchange | \
948 ((DMA_InitNodeStruct->DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) | \
949 DMA_InitNodeStruct->SrcAllocatedPort | \
950 DMA_InitNodeStruct->SrcByteExchange | \
951 ((DMA_InitNodeStruct->SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos));
952 }
953
954 /* Increment counter for the next register */
955 reg_counter++;
956 }
957
958
959 /* Check if CTR2 register update is enabled */
960 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR2) == LL_DMA_UPDATE_CTR2)
961 {
962 /*-------------------------- DMAx CTR2 Configuration -----------------------
963 * Configure the channel transfer parameter :
964 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
965 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
966 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
967 * - BlkHWRequest: DMA_CTR2_BREQ bit
968 * - Direction: DMA_CTR2_DREQ bit
969 * - Direction: DMA_CTR2_SWREQ bit
970 * Direction field is reduced to one bit for LPDMA channels (SWREQ).
971 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
972 * DataAlignment field is reduced to 5 bits for LPDMA channels.
973 * - Request: DMA_CTR2_REQSEL [6:0] bits
974 * DataAlignment field is reduced to 5 bits for LPDMA channels.
975 */
976 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->TransferEventMode | \
977 DMA_InitNodeStruct->TriggerPolarity | \
978 DMA_InitNodeStruct->BlkHWRequest | \
979 DMA_InitNodeStruct->Direction);
980
981 /* Check direction */
982 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
983 {
984 pNode->LinkRegisters[reg_counter] |= DMA_InitNodeStruct->Request & DMA_CTR2_REQSEL;
985 }
986
987 /* Check trigger polarity */
988 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
989 {
990 pNode->LinkRegisters[reg_counter] |= (((DMA_InitNodeStruct->TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & \
991 DMA_CTR2_TRIGSEL) | DMA_InitNodeStruct->TriggerMode);
992 }
993
994 /* Update CTR2 register fields for LPDMA */
995 if (DMA_InitNodeStruct->NodeType == LL_DMA_LPDMA_LINEAR_NODE)
996 {
997 pNode->LinkRegisters[reg_counter] &= (~(1UL << 21U) & ~(3UL << 5U));
998 }
999
1000 /* Increment counter for the next register */
1001 reg_counter++;
1002 }
1003
1004 /* Check if CBR1 register update is enabled */
1005 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR1) == LL_DMA_UPDATE_CBR1)
1006 {
1007 /*-------------------------- DMAx CBR1 Configuration -----------------------
1008 * Configure the Transfer Block counters and update mode with parameter :
1009 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
1010 * - BlkRptCount: DMA_CBR1_BRC[26:16] bits
1011 * BlkRptCount field is supported only by 2D addressing channels.
1012 * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit
1013 * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
1014 * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit
1015 * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
1016 * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit
1017 * SrcAddrUpdateMode field is supported only by 2D addressing channels.
1018 * - DestAddrUpdateMode: DMA_CBR1_DDEC bit
1019 * DestAddrUpdateMode field is supported only by 2D addressing channels.
1020 */
1021 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->BlkDataLength;
1022
1023 /* Update CBR1 register fields for 2D addressing channels */
1024 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
1025 {
1026 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->BlkRptDestAddrUpdateMode | \
1027 DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode | \
1028 DMA_InitNodeStruct->DestAddrUpdateMode | \
1029 DMA_InitNodeStruct->SrcAddrUpdateMode | \
1030 ((DMA_InitNodeStruct->BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC));
1031 }
1032
1033 /* Increment counter for the next register */
1034 reg_counter++;
1035 }
1036
1037 /* Check if CSAR register update is enabled */
1038 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CSAR) == LL_DMA_UPDATE_CSAR)
1039 {
1040 /*-------------------------- DMAx CSAR Configuration -----------------------
1041 * Configure the Transfer Block counters and update mode with parameter :
1042 * - SrcAddress: DMA_CSAR_SA[31:0] bits
1043 */
1044 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->SrcAddress;
1045
1046 /* Increment counter for the next register */
1047 reg_counter++;
1048 }
1049
1050
1051 /* Check if CDAR register update is enabled */
1052 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CDAR) == LL_DMA_UPDATE_CDAR)
1053 {
1054 /*-------------------------- DMAx CDAR Configuration -----------------------
1055 * Configure the Transfer Block counters and update mode with parameter :
1056 * - DestAddress: DMA_CDAR_DA[31:0] bits
1057 */
1058 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->DestAddress;
1059
1060 /* Increment counter for the next register */
1061 reg_counter++;
1062 }
1063
1064
1065 /* Update CTR3 register fields for 2D addressing channels */
1066 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
1067 {
1068 /* Check if CTR3 register update is enabled */
1069 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR3) == LL_DMA_UPDATE_CTR3)
1070 {
1071 /*-------------------------- DMAx CTR3 Configuration ---------------------
1072 * Configure the Block counters and update mode with parameter :
1073 * - DestAddressOffset: DMA_CTR3_DAO[12:0] bits
1074 * DestAddressOffset field is supported only by 2D addressing channels.
1075 * - SrcAddressOffset: DMA_CTR3_SAO[12:0] bits
1076 * SrcAddressOffset field is supported only by 2D addressing channels.
1077 */
1078 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->SrcAddrOffset | \
1079 ((DMA_InitNodeStruct->DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
1080
1081 /* Increment counter for the next register */
1082 reg_counter++;
1083 }
1084 }
1085
1086
1087 /* Update CBR2 register fields for 2D addressing channels */
1088 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
1089 {
1090 /* Check if CBR2 register update is enabled */
1091 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR2) == LL_DMA_UPDATE_CBR2)
1092 {
1093 /*-------------------------- DMAx CBR2 Configuration ---------------------
1094 * Configure the Block counters and update mode with parameter :
1095 * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits
1096 * BlkRptDestAddrOffset field is supported only by 2D addressing channels.
1097 * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits
1098 * BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
1099 */
1100 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->BlkRptSrcAddrOffset | \
1101 ((DMA_InitNodeStruct->BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & \
1102 DMA_CBR2_BRDAO));
1103
1104 /* Increment counter for the next register */
1105 reg_counter++;
1106 }
1107 }
1108
1109 /* Check if CLLR register update is enabled */
1110 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR)
1111 {
1112 /*-------------------------- DMAx CLLR Configuration -----------------------
1113 * Configure the Transfer Block counters and update mode with parameter :
1114 * - UpdateRegisters DMA_CLLR_UT1 bit
1115 * - UpdateRegisters DMA_CLLR_UT2 bit
1116 * - UpdateRegisters DMA_CLLR_UB1 bit
1117 * - UpdateRegisters DMA_CLLR_USA bit
1118 * - UpdateRegisters DMA_CLLR_UDA bit
1119 * - UpdateRegisters DMA_CLLR_UT3 bit
1120 * DMA_CLLR_UT3 bit is discarded for linear addressing channels.
1121 * - UpdateRegisters DMA_CLLR_UB2 bit
1122 * DMA_CLLR_UB2 bit is discarded for linear addressing channels.
1123 * - UpdateRegisters DMA_CLLR_ULL bit
1124 */
1125 pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CLLR_UT2 | \
1126 DMA_CLLR_UB1 | DMA_CLLR_USA | \
1127 DMA_CLLR_UDA | DMA_CLLR_ULL)));
1128
1129 /* Update CLLR register fields for 2D addressing channels */
1130 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
1131 {
1132 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2));
1133 }
1134 }
1135 else
1136 {
1137 /* Reset of the CLLR of the node being created */
1138 pNode->LinkRegisters[reg_counter] = 0U;
1139 }
1140
1141 return (uint32_t)SUCCESS;
1142 }
1143
1144 /**
1145 * @brief Connect Linked list Nodes.
1146 * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Linked list node.
1147 * @param PrevNodeCLLRIdx Offset of Previous Node CLLR register.
1148 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
1149 * @param pNewLinkNode Pointer to new Linked list.
1150 * @param NewNodeCLLRIdx Offset of New Node CLLR register.
1151 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
1152 * @retval None
1153 */
LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef * pPrevLinkNode,uint32_t PrevNodeCLLRIdx,LL_DMA_LinkNodeTypeDef * pNewLinkNode,uint32_t NewNodeCLLRIdx)1154 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
1155 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx)
1156 {
1157 pPrevLinkNode->LinkRegisters[PrevNodeCLLRIdx] = (((uint32_t)pNewLinkNode & DMA_CLLR_LA) | \
1158 (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \
1159 DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \
1160 DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL)));
1161 }
1162
1163 /**
1164 * @brief Disconnect the next linked list node.
1165 * @param pLinkNode Pointer to linked list node to be disconnected from the next one.
1166 * @param LinkNodeCLLRIdx Offset of Link Node CLLR register.
1167 * @retval None.
1168 */
LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef * pLinkNode,uint32_t LinkNodeCLLRIdx)1169 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx)
1170 {
1171 pLinkNode->LinkRegisters[LinkNodeCLLRIdx] = 0;
1172 }
1173
1174 /**
1175 * @}
1176 */
1177
1178 /**
1179 * @}
1180 */
1181
1182 /**
1183 * @}
1184 */
1185
1186 #endif /* GPDMA1 || LPDMA1 */
1187
1188 /**
1189 * @}
1190 */
1191
1192 #endif /* USE_FULL_LL_DRIVER */
1193
1194
