1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32u5xx_ll_adc.h"
22 #include "stm32u5xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC4)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency */
64 /* Unit: CPU cycles. */
65 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
66 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
67 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68
69 /**
70 * @}
71 */
72 /* Private macros ------------------------------------------------------------*/
73
74 /** @addtogroup ADC_LL_Private_Macros
75 * @{
76 */
77
78 /* Check of parameters for configuration of ADC hierarchical scope: */
79 /* applicable for the twoinstances. */
80 #define IS_LL_ADC_CLOCK(__CLOCK__) \
81 ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
82 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
83 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
84 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
85 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
93 )
94 /* Check of parameters for configuration of ADC hierarchical scope: */
95 /* ADC instance. */
96 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
97 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B) \
98 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
99 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
100 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
101 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
102 )
103
104 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
105 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
106 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
107 )
108
109 #define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__) \
110 ( ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE) \
111 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1) \
112 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2) \
113 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3) \
114 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4) \
115 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5) \
116 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6) \
117 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7) \
118 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8) \
119 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9) \
120 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10) \
121 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11) \
122 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12) \
123 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13) \
124 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14) \
125 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15) \
126 )
127
128 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
129 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
130 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
131 )
132
133 /* Check of parameters for configuration of ADC hierarchical scope: */
134 /* ADC group regular */
135 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
136 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
146 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
147 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
149 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
150 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE15) \
154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) \
155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) \
156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) \
157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM4_OUT) \
158 )
159
160 #define IS_LL_ADC4_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
161 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
162 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2_ADC4) \
163 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4_ADC4) \
164 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC4) \
165 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO_ADC4) \
166 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC4) \
167 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1_ADC4) \
168 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_CH2_ADC4) \
169 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE15_ADC4) \
170 )
171
172 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
173 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
174 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
175 )
176
177 #define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__) \
178 ( ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER) \
179 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
180 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
181 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_MDF_TRANSFER) \
182 )
183 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
184 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE_ADC4) \
185 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED_ADC4) \
186 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED_ADC4) \
187 )
188
189 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
190 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
191 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
192 )
193
194 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
195 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
196 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
197 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
198 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
199 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
200 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
201 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
202 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
203 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
204 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
205 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
206 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
207 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
208 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
209 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
210 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
211 )
212
213 #define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
214 ( ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
215 || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
216 )
217
218 #define IS_LL_ADC4_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
219 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_DISABLE) \
220 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_2RANKS) \
221 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_3RANKS) \
222 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_4RANKS) \
223 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_5RANKS) \
224 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_6RANKS) \
225 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_7RANKS) \
226 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC4_REG_SEQ_SCAN_ENABLE_8RANKS) \
227 )
228
229 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
230 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
231 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
232 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
233 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
234 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
235 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
236 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
237 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
238 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
239 )
240
241 /* Check of parameters for configuration of ADC hierarchical scope: */
242 /* ADC group injected */
243
244 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
245 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
246 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
247 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
248 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
249 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
250 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
251 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
252 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
253 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
254 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
255 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
256 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
257 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
258 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
259 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
260 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
261 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
262 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2) \
263 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2) \
264 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1) \
265 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM4_OUT) \
266 )
267
268 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
269 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
270 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
271 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
272 )
273
274 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
275 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
276 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
277 )
278
279 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
280 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
281 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
282 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
283 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
284 )
285
286 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
287 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
288 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
289 )
290
291 #if defined(ADC_MULTIMODE_SUPPORT)
292 /* Check of parameters for configuration of ADC hierarchical scope: */
293 /* multimode. */
294 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
295 (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
296 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
297 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
298 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
299 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
300 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
301 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
302 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
303 )
304
305 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
306 (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
307 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B) \
308 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B) \
309 )
310
311 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
312 (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
313 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
314 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
315 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
316 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
317 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
318 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
319 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
320 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
321 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
322 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
323 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
324 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
325 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
326 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
327 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
328 )
329
330 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
331 (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
332 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
333 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
334 )
335
336 #endif /* ADC_MULTIMODE_SUPPORT */
337 /**
338 * @}
339 */
340
341
342 /* Private function prototypes -----------------------------------------------*/
343
344 /* Exported functions --------------------------------------------------------*/
345 /** @addtogroup ADC_LL_Exported_Functions
346 * @{
347 */
348
349 /** @addtogroup ADC_LL_EF_Init
350 * @{
351 */
352 /**
353 * @brief De-initialize registers of all ADC instances belonging to
354 * the same ADC common instance to their default reset values.
355 * @note This function is performing a hard reset, using high level
356 * clock source RCC ADC reset.
357 * Caution: On this STM32 series, if several ADC instances are available
358 * on the selected device, RCC ADC reset will reset
359 * all ADC instances belonging to the common ADC instance.
360 * To de-initialize only 1 ADC instance, use
361 * function @ref LL_ADC_DeInit().
362 * @param pADCxy_COMMON ADC common instance
363 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
364 * @retval An ErrorStatus enumeration value:
365 * - SUCCESS: ADC common registers are de-initialized
366 * - ERROR: not applicable
367 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * pADCxy_COMMON)368 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *pADCxy_COMMON)
369 {
370 /* Check the parameters */
371 assert_param(IS_ADC_COMMON_INSTANCE(pADCxy_COMMON));
372
373 if (pADCxy_COMMON == ADC12_COMMON)
374 {
375 /* Force reset of ADC clock (core clock) */
376 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12);
377
378 /* Release reset of ADC clock (core clock) */
379 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12);
380 }
381 else /*if ( pADCxy_COMMON == ADC4_COMMON)*/
382 {
383 /* Force reset of ADC clock (core clock) */
384 LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_ADC4);
385
386 /* Release reset of ADC clock (core clock) */
387 LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_ADC4);
388 }
389
390 return SUCCESS;
391 }
392
393 /**
394 * @brief Initialize some features of ADC common parameters
395 * (all ADC instances belonging to the same ADC common instance)
396 * and multimode (for devices with several ADC instances available).
397 * @note The setting of ADC common parameters is conditioned to
398 * ADC instances state:
399 * All ADC instances belonging to the same ADC common instance
400 * must be disabled.
401 * @param pADCxy_COMMON ADC common instance
402 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
403 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
404 * @retval An ErrorStatus enumeration value:
405 * - SUCCESS: ADC common registers are initialized
406 * - ERROR: ADC common registers are not initialized
407 */
LL_ADC_CommonInit(ADC_Common_TypeDef * pADCxy_COMMON,LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)408 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *pADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
409 {
410 ErrorStatus status = SUCCESS;
411
412 /* Check the parameters */
413 assert_param(IS_ADC_COMMON_INSTANCE(pADCxy_COMMON));
414 assert_param(IS_LL_ADC_CLOCK(pADC_CommonInitStruct->CommonClock));
415
416 #if defined(ADC_MULTIMODE_SUPPORT)
417 assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode));
418 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
419 {
420 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer));
421 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay));
422 }
423 #endif /* ADC_MULTIMODE_SUPPORT */
424
425 /* Note: Hardware constraint (refer to description of functions */
426 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
427 /* On this STM32 series, setting of these features is conditioned to */
428 /* ADC state: */
429 /* All ADC instances of the ADC common group must be disabled. */
430 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(pADCxy_COMMON) == 0UL)
431 {
432 /* Configuration of ADC hierarchical scope: */
433 /* - common to several ADC */
434 /* (all ADC instances belonging to the same ADC common instance) */
435 /* - Set ADC clock (conversion clock) */
436 /* - multimode (if several ADC instances available on the */
437 /* selected device) */
438 /* - Set ADC multimode configuration */
439 /* - Set ADC multimode DMA transfer */
440 /* - Set ADC multimode: delay between 2 sampling phases */
441 #if defined(ADC_MULTIMODE_SUPPORT)
442 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
443 {
444 MODIFY_REG(pADCxy_COMMON->CCR,
445 ADC_CCR_PRESC
446 | ADC_CCR_DUAL
447 | ADC_CCR_DAMDF
448 | ADC_CCR_DELAY
449 ,
450 pADC_CommonInitStruct->CommonClock
451 | pADC_CommonInitStruct->Multimode
452 | pADC_CommonInitStruct->MultiDMATransfer
453 | pADC_CommonInitStruct->MultiTwoSamplingDelay
454 );
455 }
456 else
457 {
458 MODIFY_REG(pADCxy_COMMON->CCR,
459 ADC_CCR_PRESC
460 | ADC_CCR_DUAL
461 | ADC_CCR_DAMDF
462 | ADC_CCR_DELAY
463 ,
464 pADC_CommonInitStruct->CommonClock
465 | LL_ADC_MULTI_INDEPENDENT
466 );
467 }
468 #else
469 LL_ADC_SetCommonClock(pADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
470 #endif /* ADC_MULTIMODE_SUPPORT */
471 }
472 else
473 {
474 /* Initialization error: One or several ADC instances belonging to */
475 /* the same ADC common instance are not disabled. */
476 status = ERROR;
477 }
478
479 return status;
480 }
481
482 /**
483 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
484 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
485 * whose fields will be set to default values.
486 * @retval None
487 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)488 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
489 {
490 /* Set pADC_CommonInitStruct fields to default values */
491 /* Set fields of ADC common */
492 /* (all ADC instances belonging to the same ADC common instance) */
493 pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
494
495 #if defined(ADC_MULTIMODE_SUPPORT)
496 /* Set fields of ADC multimode */
497 pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
498 pADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
499 pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
500 #endif /* ADC_MULTIMODE_SUPPORT */
501 }
502
503 /**
504 * @brief De-initialize registers of the selected ADC instance
505 * to their default reset values.
506 * @note To reset all ADC instances quickly (perform a hard reset),
507 * use function @ref LL_ADC_CommonDeInit().
508 * @param pADCx ADC instance
509 * @retval An ErrorStatus enumeration value:
510 * - SUCCESS: ADC registers are de-initialized
511 * - ERROR: ADC registers are not de-initialized
512 */
LL_ADC_DeInit(ADC_TypeDef * pADCx)513 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *pADCx)
514 {
515 ErrorStatus status = SUCCESS;
516 __IO uint32_t timeout_cpu_cycles = 0UL;
517
518 /* Check the parameters */
519 assert_param(IS_ADC_ALL_INSTANCE(pADCx));
520
521 /* Disable ADC instance if not already disabled. */
522 if (LL_ADC_IsEnabled(pADCx) == 1UL)
523 {
524 /* Stop potential ADC conversion on going on ADC group regular. */
525 if (LL_ADC_REG_IsConversionOngoing(pADCx) != 0UL)
526 {
527 if (LL_ADC_REG_IsStopConversionOngoing(pADCx) == 0UL)
528 {
529 LL_ADC_REG_StopConversion(pADCx);
530 }
531 }
532
533 /* Wait for ADC conversions are effectively stopped */
534 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
535 if (pADCx != ADC4) /* ADC1 or ADC2 */
536 {
537 while ((LL_ADC_REG_IsStopConversionOngoing(pADCx)
538 | LL_ADC_INJ_IsStopConversionOngoing(pADCx)) == 1UL)
539 {
540 timeout_cpu_cycles--;
541 if (timeout_cpu_cycles == 0UL)
542 {
543 /* Time-out error */
544 status = ERROR;
545 break;
546 }
547 }
548 }
549 else
550 {
551 while (LL_ADC_REG_IsStopConversionOngoing(pADCx) == 1UL)
552 {
553 timeout_cpu_cycles--;
554 if (timeout_cpu_cycles == 0UL)
555 {
556 /* Time-out error */
557 status = ERROR;
558 }
559 }
560 }
561 /* Disable the ADC instance */
562 LL_ADC_Disable(pADCx);
563
564 /* Wait for ADC instance is effectively disabled */
565 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
566 while (LL_ADC_IsDisableOngoing(pADCx) == 1UL)
567 {
568 timeout_cpu_cycles--;
569 if (timeout_cpu_cycles == 0UL)
570 {
571 /* Time-out error */
572 status = ERROR;
573 }
574 }
575 }
576
577 if (pADCx != ADC4) /* ADC1 or ADC2 */
578 {
579 CLEAR_BIT(pADCx->IER,
580 (LL_ADC_IT_AWD3
581 | LL_ADC_IT_AWD2
582 | LL_ADC_IT_AWD1
583 | LL_ADC_IT_OVR
584 | LL_ADC_IT_JEOS
585 | LL_ADC_IT_JEOC
586 | LL_ADC_IT_EOS
587 | LL_ADC_IT_EOC
588 | LL_ADC_IT_EOSMP
589 | LL_ADC_IT_ADRDY
590 )
591 );
592
593 /* Reset register ISR */
594 SET_BIT(pADCx->ISR,
595 (LL_ADC_FLAG_AWD3
596 | LL_ADC_FLAG_AWD2
597 | LL_ADC_FLAG_AWD1
598 | LL_ADC_FLAG_OVR
599 | LL_ADC_FLAG_JEOS
600 | LL_ADC_FLAG_JEOC
601 | LL_ADC_FLAG_EOS
602 | LL_ADC_FLAG_EOC
603 | LL_ADC_FLAG_EOSMP
604 | LL_ADC_FLAG_ADRDY
605 )
606 );
607
608 /* Reset register CR */
609 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
610 /* "read-set": no direct reset applicable. */
611 CLEAR_BIT(pADCx->CR, ADC_CR_ADVREGEN);
612 SET_BIT(pADCx->CR, ADC_CR_DEEPPWD);
613
614 /* Reset register CFGR */
615 CLEAR_BIT(pADCx->CFGR1, ADC_CFGR1_AWD1CH | ADC_CFGR1_JAUTO | ADC_CFGR1_JAWD1EN |
616 ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_JDISCEN |
617 ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN | ADC_CFGR1_AUTDLY |
618 ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
619 ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL |
620 ADC_CFGR1_RES | ADC_CFGR1_DMNGT);
621
622 /* Reset register CFGR2 */
623 CLEAR_BIT(pADCx->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
624 ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
625
626 /* Reset register SMPR1 */
627 CLEAR_BIT(pADCx->SMPR1,
628 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
629 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
630 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
631 );
632
633 /* Reset register SMPR2 */
634 CLEAR_BIT(pADCx->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
635 ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
636 ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
637
638 /* Reset register LTR1 and HTR1 */
639 CLEAR_BIT(pADCx->LTR1, ADC_LTR_LT);
640 SET_BIT(pADCx->HTR1, ADC_HTR_HT);
641
642 /* Reset register LTR2 and HTR2*/
643 CLEAR_BIT(pADCx->LTR2, ADC_LTR_LT);
644 SET_BIT(pADCx->HTR2, ADC_HTR_HT);
645
646 /* Reset register LTR3 and HTR3 */
647 CLEAR_BIT(pADCx->LTR3, ADC_LTR_LT);
648 SET_BIT(pADCx->HTR3, ADC_HTR_HT);
649
650 /* Reset register SQR1 */
651 CLEAR_BIT(pADCx->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | ADC_SQR1_SQ1 | ADC_SQR1_L);
652
653 /* Reset register SQR2 */
654 CLEAR_BIT(pADCx->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
655
656 /* Reset register SQR3 */
657 CLEAR_BIT(pADCx->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
658
659 /* Reset register SQR4 */
660 CLEAR_BIT(pADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
661
662 /* Reset register JSQR */
663 CLEAR_BIT(pADCx->JSQR,
664 (ADC_JSQR_JL
665 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
666 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
667 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
668 );
669 /* Reset register DR */
670 /* bits in access mode read only, no direct reset applicable*/
671
672 /* Reset register OFR1 */
673 CLEAR_BIT(pADCx->OFR1, ADC_OFR1_SSAT | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
674 /* Reset register OFR2 */
675 CLEAR_BIT(pADCx->OFR2, ADC_OFR2_SSAT | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
676 /* Reset register OFR3 */
677 CLEAR_BIT(pADCx->OFR3, ADC_OFR3_SSAT | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
678 /* Reset register OFR4 */
679 CLEAR_BIT(pADCx->OFR4, ADC_OFR4_SSAT | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
680
681 /* Reset register GCOMP */
682 CLEAR_BIT(pADCx->GCOMP, ADC_GCOMP_GCOMP | ADC_GCOMP_GCOMPCOEFF);
683
684 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
685 /* bits in access mode read only, no direct reset applicable*/
686
687 /* Reset register AWD2CR */
688 CLEAR_BIT(pADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
689
690 /* Reset register AWD3CR */
691 CLEAR_BIT(pADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
692
693 /* Reset register DIFSEL */
694 CLEAR_BIT(pADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
695
696 /* Reset register PCSEL */
697 CLEAR_BIT(pADCx->PCSEL, ADC_PCSEL_PCSEL);
698
699 /* Reset register CALFACT */
700 CLEAR_BIT(pADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF | ADC_CALFACT_LATCH_COEF);
701 }
702 else
703 {
704 /* Check whether ADC state is compliant with expected state */
705 if (READ_BIT(pADCx->CR, (ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) == 0UL)
706 {
707 /* ========== Reset ADC registers ========== */
708 /* Reset register IER */
709 CLEAR_BIT(pADCx->IER,
710 (LL_ADC_IT_ADRDY
711 | LL_ADC_IT_EOC
712 | LL_ADC_IT_EOS
713 | LL_ADC_IT_OVR
714 | LL_ADC_IT_EOSMP
715 | LL_ADC_IT_AWD1
716 | LL_ADC_IT_AWD2
717 | LL_ADC_IT_AWD3
718 | LL_ADC_IT_EOCAL
719 | LL_ADC_IT_LDORDY
720 )
721 );
722
723 /* Reset register ISR */
724 SET_BIT(pADCx->ISR,
725 (LL_ADC_FLAG_ADRDY
726 | LL_ADC_FLAG_EOC
727 | LL_ADC_FLAG_EOS
728 | LL_ADC_FLAG_OVR
729 | LL_ADC_FLAG_EOSMP
730 | LL_ADC_FLAG_AWD1
731 | LL_ADC_FLAG_AWD2
732 | LL_ADC_FLAG_AWD3
733 | LL_ADC_FLAG_EOCAL
734 | LL_ADC_FLAG_LDORDY
735 )
736 );
737
738 /* Reset register CR */
739 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
740 /* "read-set": no direct reset applicable. */
741 CLEAR_BIT(pADCx->CR, ADC_CR_ADVREGEN);
742
743 /* Reset register CFGR1 */
744 CLEAR_BIT(pADCx->CFGR1,
745 (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
746 | ADC4_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
747 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC4_CFGR1_ALIGN | ADC_CFGR1_RES
748 | ADC4_CFGR1_SCANDIR | ADC4_CFGR1_DMACFG | ADC4_CFGR1_DMAEN)
749 );
750
751 /* Reset register CFGR2 */
752 /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
753 /* already done above. */
754 CLEAR_BIT(pADCx->CFGR2,
755 (ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | ADC4_CFGR2_OVSR
756 | ADC_CFGR2_ROVSE | ADC4_CFGR2_LFTRIG)
757 );
758
759 /* Reset register SMPR */
760 CLEAR_BIT(pADCx->SMPR1, ADC4_SMPR_SMP1 | ADC4_SMPR_SMP2 | ADC4_SMPR_SMPSEL);
761
762 /* Reset register TR1 */
763 MODIFY_REG(pADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
764
765 /* Reset register TR2 */
766 MODIFY_REG(pADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
767
768 /* Reset register TR3 */
769 MODIFY_REG(pADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
770
771 /* Reset register CHSELR */
772 CLEAR_BIT(pADCx->CHSELR,
773 (ADC_CHSELR_CHSEL23 | ADC_CHSELR_CHSEL22 | ADC_CHSELR_CHSEL21 | ADC_CHSELR_CHSEL20
774 | ADC_CHSELR_CHSEL19 | ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
775 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
776 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
777 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
778 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0)
779 );
780
781 /* Reset register DR */
782 /* bits in access mode read only, no direct reset applicable */
783
784 /* Reset register CALFACT */
785 CLEAR_BIT(pADCx->CALFACT, ADC4_CALFACT_CALFACT);
786
787 /* Reset register CCR */
788 CLEAR_BIT(ADC4_COMMON->CCR, ADC_CCR_VBATEN | ADC_CCR_VSENSEEN | ADC_CCR_VREFEN | ADC_CCR_PRESC);
789 }
790 else
791 {
792 /* ADC instance is in an unknown state */
793 /* Need to performing a hard reset of ADC instance, using high level */
794 /* clock source RCC ADC reset. */
795 /* Caution: On this STM32 series, if several ADC instances are available */
796 /* on the selected device, RCC ADC reset will reset */
797 /* all ADC instances belonging to the common ADC instance. */
798 status = ERROR;
799 }
800 }
801
802 return status;
803 }
804
805 /**
806 * @brief Initialize some features of ADC instance.
807 * @note These parameters have an impact on ADC scope: ADC instance.
808 * Affects both group regular and group injected (availability
809 * of ADC group injected depends on STM32 families).
810 * Refer to corresponding unitary functions into
811 * @ref ADC_LL_EF_Configuration_ADC_Instance .
812 * @note The setting of these parameters by function @ref LL_ADC_Init()
813 * is conditioned to ADC state:
814 * ADC instance must be disabled.
815 * This condition is applied to all ADC features, for efficiency
816 * and compatibility over all STM32 families. However, the different
817 * features can be set under different ADC state conditions
818 * (setting possible with ADC enabled without conversion on going,
819 * ADC enabled with conversion on going, ...)
820 * Each feature can be updated afterwards with a unitary function
821 * and potentially with ADC in a different state than disabled,
822 * refer to description of each function for setting
823 * conditioned to ADC state.
824 * @note After using this function, some other features must be configured
825 * using LL unitary functions.
826 * The minimum configuration remaining to be done is:
827 * - Set ADC group regular or group injected sequencer:
828 * map channel on the selected sequencer rank.
829 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
830 * - Set ADC channel sampling time
831 * Refer to function LL_ADC_SetChannelSamplingTime();
832 * @param pADCx ADC instance
833 * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
834 * @retval An ErrorStatus enumeration value:
835 * - SUCCESS: ADC registers are initialized
836 * - ERROR: ADC registers are not initialized
837 */
LL_ADC_Init(ADC_TypeDef * pADCx,LL_ADC_InitTypeDef * pADC_InitStruct)838 ErrorStatus LL_ADC_Init(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
839 {
840 ErrorStatus status = SUCCESS;
841
842 /* Check the parameters */
843 assert_param(IS_ADC_ALL_INSTANCE(pADCx));
844
845 assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
846 assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
847 if (pADCx != ADC4) /* ADC1 or ADC2 */
848 {
849 assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(pADC_InitStruct->LeftBitShift));
850 }
851 else
852 {
853 assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
854 }
855
856 /* Note: Hardware constraint (refer to description of this function): */
857 /* ADC instance must be disabled. */
858 if (LL_ADC_IsEnabled(pADCx) == 0UL)
859 {
860 /* Configuration of ADC hierarchical scope: */
861 /* - ADC instance */
862 /* - Set ADC data resolution */
863 /* - Set ADC conversion data alignment */
864 /* - Set ADC low power mode */
865 if (pADCx != ADC4) /* ADC1 or ADC2 */
866 {
867 MODIFY_REG(pADCx->CFGR1,
868 ADC_CFGR1_RES | ADC4_CFGR1_WAIT, pADC_InitStruct->Resolution | pADC_InitStruct->LowPowerMode);
869 MODIFY_REG(pADCx->CFGR2, ADC_CFGR2_LSHIFT, pADC_InitStruct->LeftBitShift);
870 }
871 else
872 {
873 MODIFY_REG(pADCx->CFGR1,
874 ADC4_CFGR1_ALIGN | ADC4_CFGR1_WAIT,
875 pADC_InitStruct->DataAlignment
876 | pADC_InitStruct->LowPowerMode
877 );
878 LL_ADC_SetResolution(pADCx, pADC_InitStruct->Resolution);
879 }
880 }
881 else
882 {
883 /* Initialization error: ADC instance is not disabled. */
884 status = ERROR;
885 }
886 return status;
887 }
888
889 /**
890 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
891 * @param pADCx ADC instance
892 * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
893 * whose fields will be set to default values.
894 * @retval None
895 */
LL_ADC_StructInit(const ADC_TypeDef * pADCx,LL_ADC_InitTypeDef * pADC_InitStruct)896 void LL_ADC_StructInit(const ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
897 {
898 /* Set pADC_InitStruct fields to default values */
899 /* Set fields of ADC instance */
900 pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
901 if (pADCx != ADC4) /* ADC1 or ADC2 */
902 {
903 pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_14B;
904 pADC_InitStruct->LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_NONE;
905 }
906 else
907 {
908 pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
909 pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
910 }
911 }
912
913 /**
914 * @brief Initialize some features of ADC group regular.
915 * @note These parameters have an impact on ADC scope: ADC group regular.
916 * Refer to corresponding unitary functions into
917 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
918 * (functions with prefix "REG").
919 * @note The setting of these parameters by function @ref LL_ADC_Init()
920 * is conditioned to ADC state:
921 * ADC instance must be disabled.
922 * This condition is applied to all ADC features, for efficiency
923 * and compatibility over all STM32 families. However, the different
924 * features can be set under different ADC state conditions
925 * (setting possible with ADC enabled without conversion on going,
926 * ADC enabled with conversion on going, ...)
927 * Each feature can be updated afterwards with a unitary function
928 * and potentially with ADC in a different state than disabled,
929 * refer to description of each function for setting
930 * conditioned to ADC state.
931 * @note After using this function, other features must be configured
932 * using LL unitary functions.
933 * The minimum configuration remaining to be done is:
934 * - Set ADC group regular or group injected sequencer:
935 * map channel on the selected sequencer rank.
936 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
937 * - Set ADC channel sampling time
938 * Refer to function LL_ADC_SetChannelSamplingTime();
939 * @param pADCx ADC instance
940 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
941 * @retval An ErrorStatus enumeration value:
942 * - SUCCESS: ADC registers are initialized
943 * - ERROR: ADC registers are not initialized
944 */
LL_ADC_REG_Init(ADC_TypeDef * pADCx,LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)945 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
946 {
947 ErrorStatus status = SUCCESS;
948
949 /* Check the parameters */
950 assert_param(IS_ADC_ALL_INSTANCE(pADCx));
951 if (pADCx == ADC4)
952 {
953 assert_param(IS_LL_ADC4_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
954 assert_param(IS_LL_ADC4_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
955 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
956 if ((LL_ADC_REG_GetSequencerConfigurable(pADCx) == LL_ADC_REG_SEQ_FIXED)
957 || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
958 )
959 {
960 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
961
962 /* ADC group regular continuous mode and discontinuous mode */
963 /* can not be enabled simultenaeously */
964 assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
965 || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
966 }
967 }
968 else /* ADC1 or ADC2 */
969 {
970 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
971 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
972 assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(pADC_RegInitStruct->DataTransferMode));
973 }
974
975 if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
976 {
977 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
978 }
979 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
980 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
981
982 /* Note: Hardware constraint (refer to description of this function): */
983 /* ADC instance must be disabled. */
984 if (LL_ADC_IsEnabled(pADCx) == 0UL)
985 {
986 /* Configuration of ADC hierarchical scope: */
987 /* - ADC group regular */
988 /* - Set ADC group regular trigger source */
989 /* - Set ADC group regular sequencer length */
990 /* - Set ADC group regular sequencer discontinuous mode */
991 /* - Set ADC group regular continuous mode */
992 /* - Set ADC group regular conversion data transfer: no transfer or */
993 /* transfer by DMA, and DMA requests mode */
994 /* - Set ADC group regular overrun behavior */
995 /* Note: On this STM32 series, ADC trigger edge is set when starting */
996 /* ADC conversion. */
997 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
998 if (pADCx != ADC4) /* ADC1 or ADC2 */
999 {
1000 if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1001 {
1002 MODIFY_REG(pADCx->CFGR1,
1003 ADC_CFGR1_EXTSEL
1004 | ADC_CFGR1_EXTEN
1005 | ADC_CFGR1_DISCEN
1006 | ADC_CFGR1_DISCNUM
1007 | ADC_CFGR1_CONT
1008 | ADC_CFGR1_DMNGT
1009 | ADC_CFGR1_OVRMOD
1010 ,
1011 pADC_RegInitStruct->TriggerSource
1012 | pADC_RegInitStruct->SequencerDiscont
1013 | pADC_RegInitStruct->ContinuousMode
1014 | pADC_RegInitStruct->DataTransferMode
1015 | pADC_RegInitStruct->Overrun
1016 );
1017 }
1018 else
1019 {
1020 MODIFY_REG(pADCx->CFGR1,
1021 ADC_CFGR1_EXTSEL
1022 | ADC_CFGR1_EXTEN
1023 | ADC_CFGR1_DISCEN
1024 | ADC_CFGR1_DISCNUM
1025 | ADC_CFGR1_CONT
1026 | ADC_CFGR1_DMNGT
1027 | ADC_CFGR1_OVRMOD
1028 ,
1029 pADC_RegInitStruct->TriggerSource
1030 | LL_ADC_REG_SEQ_DISCONT_DISABLE
1031 | pADC_RegInitStruct->ContinuousMode
1032 | pADC_RegInitStruct->DataTransferMode
1033 | pADC_RegInitStruct->Overrun
1034 );
1035 }
1036 }
1037 else
1038 {
1039 if ((LL_ADC_REG_GetSequencerConfigurable(pADCx) == LL_ADC_REG_SEQ_FIXED)
1040 || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1041 )
1042 {
1043 MODIFY_REG(pADCx->CFGR1,
1044 ADC_CFGR1_EXTSEL
1045 | ADC_CFGR1_EXTEN
1046 | ADC_CFGR1_DISCEN
1047 | ADC_CFGR1_CONT
1048 | ADC4_CFGR1_DMAEN
1049 | ADC4_CFGR1_DMACFG
1050 | ADC_CFGR1_OVRMOD
1051 ,
1052 pADC_RegInitStruct->TriggerSource
1053 | pADC_RegInitStruct->SequencerDiscont
1054 | pADC_RegInitStruct->ContinuousMode
1055 | pADC_RegInitStruct->DMATransfer
1056 | pADC_RegInitStruct->Overrun
1057 );
1058 }
1059 else
1060 {
1061 MODIFY_REG(pADCx->CFGR1,
1062 ADC_CFGR1_EXTSEL
1063 | ADC_CFGR1_EXTEN
1064 | ADC_CFGR1_DISCEN
1065 | ADC_CFGR1_CONT
1066 | ADC4_CFGR1_DMAEN
1067 | ADC4_CFGR1_DMACFG
1068 | ADC_CFGR1_OVRMOD
1069 ,
1070 pADC_RegInitStruct->TriggerSource
1071 | LL_ADC_REG_SEQ_DISCONT_DISABLE
1072 | pADC_RegInitStruct->ContinuousMode
1073 | pADC_RegInitStruct->DMATransfer
1074 | pADC_RegInitStruct->Overrun
1075 );
1076 }
1077 }
1078
1079 /* Set ADC group regular sequencer length and scan direction */
1080 if (pADCx == ADC4)
1081 {
1082 if (LL_ADC_REG_GetSequencerConfigurable(pADCx) != LL_ADC_REG_SEQ_FIXED)
1083 {
1084 LL_ADC_REG_SetSequencerLength(pADCx, pADC_RegInitStruct->SequencerLength);
1085 }
1086 }
1087 else
1088 {
1089 LL_ADC_REG_SetSequencerLength(pADCx, pADC_RegInitStruct->SequencerLength);
1090 }
1091 }
1092 else
1093 {
1094 /* Initialization error: ADC instance is not disabled. */
1095 status = ERROR;
1096 }
1097 return status;
1098 }
1099
1100 /**
1101 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
1102 * @param pADCx ADC instance
1103 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1104 * whose fields will be set to default values.
1105 * @retval None
1106 */
LL_ADC_REG_StructInit(const ADC_TypeDef * pADCx,LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)1107 void LL_ADC_REG_StructInit(const ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
1108 {
1109 /* Set pADC_RegInitStruct fields to default values */
1110 /* Set fields of ADC group regular */
1111 /* Note: On this STM32 series, ADC trigger edge is set when starting */
1112 /* ADC conversion. */
1113 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
1114 pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
1115 pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
1116 pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
1117 pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
1118 pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
1119 if (pADCx != ADC4) /* ADC1 or ADC2 */
1120 {
1121 pADC_RegInitStruct->DataTransferMode = LL_ADC_REG_DR_TRANSFER;
1122 }
1123 else
1124 {
1125 pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE_ADC4;
1126 }
1127 }
1128
1129 /**
1130 * @brief Initialize some features of ADC group injected.
1131 * @note These parameters have an impact on ADC scope: ADC group injected.
1132 * Refer to corresponding unitary functions into
1133 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1134 * (functions with prefix "INJ").
1135 * @note The setting of these parameters by function @ref LL_ADC_Init()
1136 * is conditioned to ADC state:
1137 * ADC instance must be disabled.
1138 * This condition is applied to all ADC features, for efficiency
1139 * and compatibility over all STM32 families. However, the different
1140 * features can be set under different ADC state conditions
1141 * (setting possible with ADC enabled without conversion on going,
1142 * ADC enabled with conversion on going, ...)
1143 * Each feature can be updated afterwards with a unitary function
1144 * and potentially with ADC in a different state than disabled,
1145 * refer to description of each function for setting
1146 * conditioned to ADC state.
1147 * @note After using this function, other features must be configured
1148 * using LL unitary functions.
1149 * The minimum configuration remaining to be done is:
1150 * - Set ADC group injected sequencer:
1151 * map channel on the selected sequencer rank.
1152 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
1153 * - Set ADC channel sampling time
1154 * Refer to function LL_ADC_SetChannelSamplingTime();
1155 * @param pADCx ADC instance
1156 * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1157 * @retval An ErrorStatus enumeration value:
1158 * - SUCCESS: ADC registers are initialized
1159 * - ERROR: ADC registers are not initialized
1160 */
LL_ADC_INJ_Init(ADC_TypeDef * pADCx,LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct)1161 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *pADCx, LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
1162 {
1163 ErrorStatus status = SUCCESS;
1164
1165 /* Check the parameters */
1166 assert_param(IS_ADC_ALL_INSTANCE(pADCx));
1167 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(pADC_InjInitStruct->TriggerSource));
1168 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength));
1169 if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1170 {
1171 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont));
1172 }
1173 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto));
1174
1175 /* Note: Hardware constraint (refer to description of this function): */
1176 /* ADC instance must be disabled. */
1177 if (LL_ADC_IsEnabled(pADCx) == 0UL)
1178 {
1179 /* Configuration of ADC hierarchical scope: */
1180 /* - ADC group injected */
1181 /* - Set ADC group injected trigger source */
1182 /* - Set ADC group injected sequencer length */
1183 /* - Set ADC group injected sequencer discontinuous mode */
1184 /* - Set ADC group injected conversion trigger: independent or */
1185 /* from ADC group regular */
1186 /* Note: On this STM32 series, ADC trigger edge is set when starting */
1187 /* ADC conversion. */
1188 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
1189 if (pADC_InjInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1190 {
1191 MODIFY_REG(pADCx->CFGR1,
1192 ADC_CFGR1_JDISCEN | ADC_CFGR1_JAUTO,
1193 pADC_InjInitStruct->SequencerDiscont | pADC_InjInitStruct->TrigAuto
1194 );
1195 }
1196 else
1197 {
1198 MODIFY_REG(pADCx->CFGR1,
1199 ADC_CFGR1_JDISCEN | ADC_CFGR1_JAUTO,
1200 LL_ADC_REG_SEQ_DISCONT_DISABLE | pADC_InjInitStruct->TrigAuto
1201 );
1202 }
1203
1204 MODIFY_REG(pADCx->JSQR,
1205 ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JL,
1206 pADC_InjInitStruct->TriggerSource | pADC_InjInitStruct->SequencerLength
1207 );
1208 }
1209 else
1210 {
1211 /* Initialization error: ADC instance is not disabled. */
1212 status = ERROR;
1213 }
1214 return status;
1215 }
1216
1217 /**
1218 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1219 * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1220 * whose fields will be set to default values.
1221 * @retval None
1222 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct)1223 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
1224 {
1225 /* Set pADC_InjInitStruct fields to default values */
1226 /* Set fields of ADC group injected */
1227 pADC_InjInitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1228 pADC_InjInitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1229 pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1230 pADC_InjInitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1231 }
1232
1233 /**
1234 * @}
1235 */
1236
1237 /**
1238 * @}
1239 */
1240
1241 /**
1242 * @}
1243 */
1244
1245 #endif /* ADC1 || ADC2 || ADC4 */
1246
1247 /**
1248 * @}
1249 */
1250
1251 #endif /* USE_FULL_LL_DRIVER */
1252
