1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_tim_ex.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer Extended peripheral:
8 * + Time Hall Sensor Interface Initialization
9 * + Time Hall Sensor Interface Start
10 * + Time Complementary signal break and dead time configuration
11 * + Time Master and Slave synchronization configuration
12 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
13 * + Time OCRef clear configuration
14 * + Timer remapping capabilities configuration
15 * + Timer encoder index configuration
16 ******************************************************************************
17 * @attention
18 *
19 * Copyright (c) 2021 STMicroelectronics.
20 * All rights reserved.
21 *
22 * This software is licensed under terms that can be found in the LICENSE file
23 * in the root directory of this software component.
24 * If no LICENSE file comes with this software, it is provided AS-IS.
25 *
26 ******************************************************************************
27 @verbatim
28 ==============================================================================
29 ##### TIMER Extended features #####
30 ==============================================================================
31 [..]
32 The Timer Extended features include:
33 (#) Complementary outputs with programmable dead-time for :
34 (++) Output Compare
35 (++) PWM generation (Edge and Center-aligned Mode)
36 (++) One-pulse mode output
37 (#) Synchronization circuit to control the timer with external signals and to
38 interconnect several timers together.
39 (#) Break input to put the timer output signals in reset state or in a known state.
40 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
41 positioning purposes
42 (#) In case of Pulse on compare, configure pulse length and delay
43 (#) Encoder index configuration
44
45 ##### How to use this driver #####
46 ==============================================================================
47 [..]
48 (#) Initialize the TIM low level resources by implementing the following functions
49 depending on the selected feature:
50 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
51
52 (#) Initialize the TIM low level resources :
53 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
54 (##) TIM pins configuration
55 (+++) Enable the clock for the TIM GPIOs using the following function:
56 __HAL_RCC_GPIOx_CLK_ENABLE();
57 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
58
59 (#) The external Clock can be configured, if needed (the default clock is the
60 internal clock from the APBx), using the following function:
61 HAL_TIM_ConfigClockSource, the clock configuration should be done before
62 any start function.
63
64 (#) Configure the TIM in the desired functioning mode using one of the
65 initialization function of this driver:
66 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
67 Timer Hall Sensor Interface and the commutation event with the corresponding
68 Interrupt and DMA request if needed (Note that One Timer is used to interface
69 with the Hall sensor Interface and another Timer should be used to use
70 the commutation event).
71 (#) In case of Pulse On Compare:
72 (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler
73
74
75 (#) Activate the TIM peripheral using one of the start functions:
76 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
77 HAL_TIMEx_OCN_Start_IT()
78 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
79 HAL_TIMEx_PWMN_Start_IT()
80 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
81 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
82 HAL_TIMEx_HallSensor_Start_IT().
83
84 @endverbatim
85 ******************************************************************************
86 */
87
88 /* Includes ------------------------------------------------------------------*/
89 #include "stm32u5xx_hal.h"
90
91 /** @addtogroup STM32U5xx_HAL_Driver
92 * @{
93 */
94
95 /** @defgroup TIMEx TIMEx
96 * @brief TIM Extended HAL module driver
97 * @{
98 */
99
100 #ifdef HAL_TIM_MODULE_ENABLED
101
102 /* Private typedef -----------------------------------------------------------*/
103 /* Private define ------------------------------------------------------------*/
104 /* Private constants ---------------------------------------------------------*/
105 /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
106 * @{
107 */
108 /* Timeout for break input rearm */
109 #define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
110 /**
111 * @}
112 */
113 /* End of private constants --------------------------------------------------*/
114
115 /* Private macros ------------------------------------------------------------*/
116 /* Private variables ---------------------------------------------------------*/
117 /* Private function prototypes -----------------------------------------------*/
118 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
119 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
120 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
121
122 /* Exported functions --------------------------------------------------------*/
123 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
124 * @{
125 */
126
127 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
128 * @brief Timer Hall Sensor functions
129 *
130 @verbatim
131 ==============================================================================
132 ##### Timer Hall Sensor functions #####
133 ==============================================================================
134 [..]
135 This section provides functions allowing to:
136 (+) Initialize and configure TIM HAL Sensor.
137 (+) De-initialize TIM HAL Sensor.
138 (+) Start the Hall Sensor Interface.
139 (+) Stop the Hall Sensor Interface.
140 (+) Start the Hall Sensor Interface and enable interrupts.
141 (+) Stop the Hall Sensor Interface and disable interrupts.
142 (+) Start the Hall Sensor Interface and enable DMA transfers.
143 (+) Stop the Hall Sensor Interface and disable DMA transfers.
144
145 @endverbatim
146 * @{
147 */
148 /**
149 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
150 * @note When the timer instance is initialized in Hall Sensor Interface mode,
151 * timer channels 1 and channel 2 are reserved and cannot be used for
152 * other purpose.
153 * @param htim TIM Hall Sensor Interface handle
154 * @param sConfig TIM Hall Sensor configuration structure
155 * @retval HAL status
156 */
HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef * htim,const TIM_HallSensor_InitTypeDef * sConfig)157 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
158 {
159 TIM_OC_InitTypeDef OC_Config;
160
161 /* Check the TIM handle allocation */
162 if (htim == NULL)
163 {
164 return HAL_ERROR;
165 }
166
167 /* Check the parameters */
168 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
169 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
170 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
171 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
172 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
173 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
174 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
175 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
176
177 if (htim->State == HAL_TIM_STATE_RESET)
178 {
179 /* Allocate lock resource and initialize it */
180 htim->Lock = HAL_UNLOCKED;
181
182 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
183 /* Reset interrupt callbacks to legacy week callbacks */
184 TIM_ResetCallback(htim);
185
186 if (htim->HallSensor_MspInitCallback == NULL)
187 {
188 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
189 }
190 /* Init the low level hardware : GPIO, CLOCK, NVIC */
191 htim->HallSensor_MspInitCallback(htim);
192 #else
193 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
194 HAL_TIMEx_HallSensor_MspInit(htim);
195 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
196 }
197
198 /* Set the TIM state */
199 htim->State = HAL_TIM_STATE_BUSY;
200
201 /* Configure the Time base in the Encoder Mode */
202 TIM_Base_SetConfig(htim->Instance, &htim->Init);
203
204 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
205 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
206
207 /* Reset the IC1PSC Bits */
208 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
209 /* Set the IC1PSC value */
210 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
211
212 /* Enable the Hall sensor interface (XOR function of the three inputs) */
213 htim->Instance->CR2 |= TIM_CR2_TI1S;
214
215 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
216 htim->Instance->SMCR &= ~TIM_SMCR_TS;
217 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
218
219 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
220 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
221 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
222
223 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
224 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
225 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
226 OC_Config.OCMode = TIM_OCMODE_PWM2;
227 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
228 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
229 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
230 OC_Config.Pulse = sConfig->Commutation_Delay;
231
232 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
233
234 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
235 register to 101 */
236 htim->Instance->CR2 &= ~TIM_CR2_MMS;
237 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
238
239 /* Initialize the DMA burst operation state */
240 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
241
242 /* Initialize the TIM channels state */
243 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
244 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
245 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
246 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
247
248 /* Initialize the TIM state*/
249 htim->State = HAL_TIM_STATE_READY;
250
251 return HAL_OK;
252 }
253
254 /**
255 * @brief DeInitializes the TIM Hall Sensor interface
256 * @param htim TIM Hall Sensor Interface handle
257 * @retval HAL status
258 */
HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef * htim)259 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
260 {
261 /* Check the parameters */
262 assert_param(IS_TIM_INSTANCE(htim->Instance));
263
264 htim->State = HAL_TIM_STATE_BUSY;
265
266 /* Disable the TIM Peripheral Clock */
267 __HAL_TIM_DISABLE(htim);
268
269 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
270 if (htim->HallSensor_MspDeInitCallback == NULL)
271 {
272 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
273 }
274 /* DeInit the low level hardware */
275 htim->HallSensor_MspDeInitCallback(htim);
276 #else
277 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
278 HAL_TIMEx_HallSensor_MspDeInit(htim);
279 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
280
281 /* Change the DMA burst operation state */
282 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
283
284 /* Change the TIM channels state */
285 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
286 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
287 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
288 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
289
290 /* Change TIM state */
291 htim->State = HAL_TIM_STATE_RESET;
292
293 /* Release Lock */
294 __HAL_UNLOCK(htim);
295
296 return HAL_OK;
297 }
298
299 /**
300 * @brief Initializes the TIM Hall Sensor MSP.
301 * @param htim TIM Hall Sensor Interface handle
302 * @retval None
303 */
HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef * htim)304 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
305 {
306 /* Prevent unused argument(s) compilation warning */
307 UNUSED(htim);
308
309 /* NOTE : This function should not be modified, when the callback is needed,
310 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
311 */
312 }
313
314 /**
315 * @brief DeInitializes TIM Hall Sensor MSP.
316 * @param htim TIM Hall Sensor Interface handle
317 * @retval None
318 */
HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef * htim)319 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
320 {
321 /* Prevent unused argument(s) compilation warning */
322 UNUSED(htim);
323
324 /* NOTE : This function should not be modified, when the callback is needed,
325 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
326 */
327 }
328
329 /**
330 * @brief Starts the TIM Hall Sensor Interface.
331 * @param htim TIM Hall Sensor Interface handle
332 * @retval HAL status
333 */
HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef * htim)334 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
335 {
336 uint32_t tmpsmcr;
337 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
338 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
339 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
340 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
341
342 /* Check the parameters */
343 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
344
345 /* Check the TIM channels state */
346 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
347 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
348 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
349 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
350 {
351 return HAL_ERROR;
352 }
353
354 /* Set the TIM channels state */
355 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
356 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
357 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
358 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
359
360 /* Enable the Input Capture channel 1
361 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
362 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
363 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
364
365 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
366 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
367 {
368 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
369 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
370 {
371 __HAL_TIM_ENABLE(htim);
372 }
373 }
374 else
375 {
376 __HAL_TIM_ENABLE(htim);
377 }
378
379 /* Return function status */
380 return HAL_OK;
381 }
382
383 /**
384 * @brief Stops the TIM Hall sensor Interface.
385 * @param htim TIM Hall Sensor Interface handle
386 * @retval HAL status
387 */
HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef * htim)388 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
389 {
390 /* Check the parameters */
391 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
392
393 /* Disable the Input Capture channels 1, 2 and 3
394 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
395 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
396 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
397
398 /* Disable the Peripheral */
399 __HAL_TIM_DISABLE(htim);
400
401 /* Set the TIM channels state */
402 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
403 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
404 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
405 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
406
407 /* Return function status */
408 return HAL_OK;
409 }
410
411 /**
412 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
413 * @param htim TIM Hall Sensor Interface handle
414 * @retval HAL status
415 */
HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef * htim)416 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
417 {
418 uint32_t tmpsmcr;
419 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
420 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
421 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
422 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
423
424 /* Check the parameters */
425 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
426
427 /* Check the TIM channels state */
428 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
429 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
430 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
431 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
432 {
433 return HAL_ERROR;
434 }
435
436 /* Set the TIM channels state */
437 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
438 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
439 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
440 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
441
442 /* Enable the capture compare Interrupts 1 event */
443 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
444
445 /* Enable the Input Capture channel 1
446 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
447 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
448 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
449
450 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
451 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
452 {
453 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
454 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
455 {
456 __HAL_TIM_ENABLE(htim);
457 }
458 }
459 else
460 {
461 __HAL_TIM_ENABLE(htim);
462 }
463
464 /* Return function status */
465 return HAL_OK;
466 }
467
468 /**
469 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
470 * @param htim TIM Hall Sensor Interface handle
471 * @retval HAL status
472 */
HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef * htim)473 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
474 {
475 /* Check the parameters */
476 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
477
478 /* Disable the Input Capture channel 1
479 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
480 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
481 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
482
483 /* Disable the capture compare Interrupts event */
484 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
485
486 /* Disable the Peripheral */
487 __HAL_TIM_DISABLE(htim);
488
489 /* Set the TIM channels state */
490 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
491 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
492 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
493 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
494
495 /* Return function status */
496 return HAL_OK;
497 }
498
499 /**
500 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
501 * @param htim TIM Hall Sensor Interface handle
502 * @param pData The destination Buffer address.
503 * @param Length The length of data to be transferred from TIM peripheral to memory.
504 * @retval HAL status
505 */
HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)506 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
507 {
508 uint32_t tmpsmcr;
509 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
510 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
511
512 /* Check the parameters */
513 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
514
515 /* Set the TIM channel state */
516 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
517 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
518 {
519 return HAL_BUSY;
520 }
521 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
522 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
523 {
524 if ((pData == NULL) || (Length == 0U))
525 {
526 return HAL_ERROR;
527 }
528 else
529 {
530 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
531 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
532 }
533 }
534 else
535 {
536 return HAL_ERROR;
537 }
538
539 /* Enable the Input Capture channel 1
540 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
541 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
542 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
543
544 /* Set the DMA Input Capture 1 Callbacks */
545 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
546 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
547 /* Set the DMA error callback */
548 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
549
550 /* Enable the DMA channel for Capture 1*/
551 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
552 {
553 /* Return error status */
554 return HAL_ERROR;
555 }
556 /* Enable the capture compare 1 Interrupt */
557 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
558
559 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
560 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
561 {
562 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
563 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
564 {
565 __HAL_TIM_ENABLE(htim);
566 }
567 }
568 else
569 {
570 __HAL_TIM_ENABLE(htim);
571 }
572
573 /* Return function status */
574 return HAL_OK;
575 }
576
577 /**
578 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
579 * @param htim TIM Hall Sensor Interface handle
580 * @retval HAL status
581 */
HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef * htim)582 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
583 {
584 /* Check the parameters */
585 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
586
587 /* Disable the Input Capture channel 1
588 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
589 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
590 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
591
592
593 /* Disable the capture compare Interrupts 1 event */
594 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
595
596 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
597
598 /* Disable the Peripheral */
599 __HAL_TIM_DISABLE(htim);
600
601 /* Set the TIM channel state */
602 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
603 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
604
605 /* Return function status */
606 return HAL_OK;
607 }
608
609 /**
610 * @}
611 */
612
613 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
614 * @brief Timer Complementary Output Compare functions
615 *
616 @verbatim
617 ==============================================================================
618 ##### Timer Complementary Output Compare functions #####
619 ==============================================================================
620 [..]
621 This section provides functions allowing to:
622 (+) Start the Complementary Output Compare/PWM.
623 (+) Stop the Complementary Output Compare/PWM.
624 (+) Start the Complementary Output Compare/PWM and enable interrupts.
625 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
626 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
627 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
628
629 @endverbatim
630 * @{
631 */
632
633 /**
634 * @brief Starts the TIM Output Compare signal generation on the complementary
635 * output.
636 * @param htim TIM Output Compare handle
637 * @param Channel TIM Channel to be enabled
638 * This parameter can be one of the following values:
639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
643 * @retval HAL status
644 */
HAL_TIMEx_OCN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)645 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
646 {
647 uint32_t tmpsmcr;
648
649 /* Check the parameters */
650 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
651
652 /* Check the TIM complementary channel state */
653 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
654 {
655 return HAL_ERROR;
656 }
657
658 /* Set the TIM complementary channel state */
659 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
660
661 /* Enable the Capture compare channel N */
662 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
663
664 /* Enable the Main Output */
665 __HAL_TIM_MOE_ENABLE(htim);
666
667 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
668 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
669 {
670 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
671 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
672 {
673 __HAL_TIM_ENABLE(htim);
674 }
675 }
676 else
677 {
678 __HAL_TIM_ENABLE(htim);
679 }
680
681 /* Return function status */
682 return HAL_OK;
683 }
684
685 /**
686 * @brief Stops the TIM Output Compare signal generation on the complementary
687 * output.
688 * @param htim TIM handle
689 * @param Channel TIM Channel to be disabled
690 * This parameter can be one of the following values:
691 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
692 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
693 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
694 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
695 * @retval HAL status
696 */
HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)697 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
698 {
699 /* Check the parameters */
700 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
701
702 /* Disable the Capture compare channel N */
703 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
704
705 /* Disable the Main Output */
706 __HAL_TIM_MOE_DISABLE(htim);
707
708 /* Disable the Peripheral */
709 __HAL_TIM_DISABLE(htim);
710
711 /* Set the TIM complementary channel state */
712 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
713
714 /* Return function status */
715 return HAL_OK;
716 }
717
718 /**
719 * @brief Starts the TIM Output Compare signal generation in interrupt mode
720 * on the complementary output.
721 * @param htim TIM OC handle
722 * @param Channel TIM Channel to be enabled
723 * This parameter can be one of the following values:
724 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
725 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
726 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
727 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
728 * @retval HAL status
729 */
HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)730 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
731 {
732 HAL_StatusTypeDef status = HAL_OK;
733 uint32_t tmpsmcr;
734
735 /* Check the parameters */
736 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
737
738 /* Check the TIM complementary channel state */
739 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
740 {
741 return HAL_ERROR;
742 }
743
744 /* Set the TIM complementary channel state */
745 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
746
747 switch (Channel)
748 {
749 case TIM_CHANNEL_1:
750 {
751 /* Enable the TIM Output Compare interrupt */
752 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
753 break;
754 }
755
756 case TIM_CHANNEL_2:
757 {
758 /* Enable the TIM Output Compare interrupt */
759 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
760 break;
761 }
762
763 case TIM_CHANNEL_3:
764 {
765 /* Enable the TIM Output Compare interrupt */
766 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
767 break;
768 }
769
770
771 case TIM_CHANNEL_4:
772 {
773 /* Enable the TIM Output Compare interrupt */
774 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
775 break;
776 }
777
778 default:
779 status = HAL_ERROR;
780 break;
781 }
782
783 if (status == HAL_OK)
784 {
785 /* Enable the TIM Break interrupt */
786 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
787
788 /* Enable the Capture compare channel N */
789 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
790
791 /* Enable the Main Output */
792 __HAL_TIM_MOE_ENABLE(htim);
793
794 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
795 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
796 {
797 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
798 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
799 {
800 __HAL_TIM_ENABLE(htim);
801 }
802 }
803 else
804 {
805 __HAL_TIM_ENABLE(htim);
806 }
807 }
808
809 /* Return function status */
810 return status;
811 }
812
813 /**
814 * @brief Stops the TIM Output Compare signal generation in interrupt mode
815 * on the complementary output.
816 * @param htim TIM Output Compare handle
817 * @param Channel TIM Channel to be disabled
818 * This parameter can be one of the following values:
819 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
820 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
821 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
822 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
823 * @retval HAL status
824 */
HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)825 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
826 {
827 HAL_StatusTypeDef status = HAL_OK;
828 uint32_t tmpccer;
829
830 /* Check the parameters */
831 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
832
833 switch (Channel)
834 {
835 case TIM_CHANNEL_1:
836 {
837 /* Disable the TIM Output Compare interrupt */
838 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
839 break;
840 }
841
842 case TIM_CHANNEL_2:
843 {
844 /* Disable the TIM Output Compare interrupt */
845 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
846 break;
847 }
848
849 case TIM_CHANNEL_3:
850 {
851 /* Disable the TIM Output Compare interrupt */
852 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
853 break;
854 }
855
856 case TIM_CHANNEL_4:
857 {
858 /* Disable the TIM Output Compare interrupt */
859 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
860 break;
861 }
862
863 default:
864 status = HAL_ERROR;
865 break;
866 }
867
868 if (status == HAL_OK)
869 {
870 /* Disable the Capture compare channel N */
871 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
872
873 /* Disable the TIM Break interrupt (only if no more channel is active) */
874 tmpccer = htim->Instance->CCER;
875 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
876 {
877 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
878 }
879
880 /* Disable the Main Output */
881 __HAL_TIM_MOE_DISABLE(htim);
882
883 /* Disable the Peripheral */
884 __HAL_TIM_DISABLE(htim);
885
886 /* Set the TIM complementary channel state */
887 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
888 }
889
890 /* Return function status */
891 return status;
892 }
893
894 /**
895 * @brief Starts the TIM Output Compare signal generation in DMA mode
896 * on the complementary output.
897 * @param htim TIM Output Compare handle
898 * @param Channel TIM Channel to be enabled
899 * This parameter can be one of the following values:
900 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
901 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
902 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
903 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
904 * @param pData The source Buffer address.
905 * @param Length The length of data to be transferred from memory to TIM peripheral
906 * @retval HAL status
907 */
HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)908 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
909 uint16_t Length)
910 {
911 HAL_StatusTypeDef status = HAL_OK;
912 uint32_t tmpsmcr;
913
914 /* Check the parameters */
915 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
916
917 /* Set the TIM complementary channel state */
918 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
919 {
920 return HAL_BUSY;
921 }
922 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
923 {
924 if ((pData == NULL) || (Length == 0U))
925 {
926 return HAL_ERROR;
927 }
928 else
929 {
930 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
931 }
932 }
933 else
934 {
935 return HAL_ERROR;
936 }
937
938 switch (Channel)
939 {
940 case TIM_CHANNEL_1:
941 {
942 /* Set the DMA compare callbacks */
943 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
944 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
945
946 /* Set the DMA error callback */
947 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
948
949 /* Enable the DMA channel */
950 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
951 Length) != HAL_OK)
952 {
953 /* Return error status */
954 return HAL_ERROR;
955 }
956 /* Enable the TIM Output Compare DMA request */
957 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
958 break;
959 }
960
961 case TIM_CHANNEL_2:
962 {
963 /* Set the DMA compare callbacks */
964 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
965 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
966
967 /* Set the DMA error callback */
968 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
969
970 /* Enable the DMA channel */
971 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
972 Length) != HAL_OK)
973 {
974 /* Return error status */
975 return HAL_ERROR;
976 }
977 /* Enable the TIM Output Compare DMA request */
978 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
979 break;
980 }
981
982 case TIM_CHANNEL_3:
983 {
984 /* Set the DMA compare callbacks */
985 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
986 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
987
988 /* Set the DMA error callback */
989 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
990
991 /* Enable the DMA channel */
992 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
993 Length) != HAL_OK)
994 {
995 /* Return error status */
996 return HAL_ERROR;
997 }
998 /* Enable the TIM Output Compare DMA request */
999 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1000 break;
1001 }
1002
1003 case TIM_CHANNEL_4:
1004 {
1005 /* Set the DMA compare callbacks */
1006 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1007 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1008
1009 /* Set the DMA error callback */
1010 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
1011
1012 /* Enable the DMA channel */
1013 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1014 Length) != HAL_OK)
1015 {
1016 /* Return error status */
1017 return HAL_ERROR;
1018 }
1019 /* Enable the TIM Output Compare DMA request */
1020 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1021 break;
1022 }
1023
1024 default:
1025 status = HAL_ERROR;
1026 break;
1027 }
1028
1029 if (status == HAL_OK)
1030 {
1031 /* Enable the Capture compare channel N */
1032 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1033
1034 /* Enable the Main Output */
1035 __HAL_TIM_MOE_ENABLE(htim);
1036
1037 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1038 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1039 {
1040 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1041 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1042 {
1043 __HAL_TIM_ENABLE(htim);
1044 }
1045 }
1046 else
1047 {
1048 __HAL_TIM_ENABLE(htim);
1049 }
1050 }
1051
1052 /* Return function status */
1053 return status;
1054 }
1055
1056 /**
1057 * @brief Stops the TIM Output Compare signal generation in DMA mode
1058 * on the complementary output.
1059 * @param htim TIM Output Compare handle
1060 * @param Channel TIM Channel to be disabled
1061 * This parameter can be one of the following values:
1062 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1063 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1064 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1065 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1066 * @retval HAL status
1067 */
HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1068 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1069 {
1070 HAL_StatusTypeDef status = HAL_OK;
1071
1072 /* Check the parameters */
1073 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1074
1075 switch (Channel)
1076 {
1077 case TIM_CHANNEL_1:
1078 {
1079 /* Disable the TIM Output Compare DMA request */
1080 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1081 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1082 break;
1083 }
1084
1085 case TIM_CHANNEL_2:
1086 {
1087 /* Disable the TIM Output Compare DMA request */
1088 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1089 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1090 break;
1091 }
1092
1093 case TIM_CHANNEL_3:
1094 {
1095 /* Disable the TIM Output Compare DMA request */
1096 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1097 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1098 break;
1099 }
1100
1101 case TIM_CHANNEL_4:
1102 {
1103 /* Disable the TIM Output Compare interrupt */
1104 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1105 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1106 break;
1107 }
1108
1109 default:
1110 status = HAL_ERROR;
1111 break;
1112 }
1113
1114 if (status == HAL_OK)
1115 {
1116 /* Disable the Capture compare channel N */
1117 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1118
1119 /* Disable the Main Output */
1120 __HAL_TIM_MOE_DISABLE(htim);
1121
1122 /* Disable the Peripheral */
1123 __HAL_TIM_DISABLE(htim);
1124
1125 /* Set the TIM complementary channel state */
1126 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1127 }
1128
1129 /* Return function status */
1130 return status;
1131 }
1132
1133 /**
1134 * @}
1135 */
1136
1137 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
1138 * @brief Timer Complementary PWM functions
1139 *
1140 @verbatim
1141 ==============================================================================
1142 ##### Timer Complementary PWM functions #####
1143 ==============================================================================
1144 [..]
1145 This section provides functions allowing to:
1146 (+) Start the Complementary PWM.
1147 (+) Stop the Complementary PWM.
1148 (+) Start the Complementary PWM and enable interrupts.
1149 (+) Stop the Complementary PWM and disable interrupts.
1150 (+) Start the Complementary PWM and enable DMA transfers.
1151 (+) Stop the Complementary PWM and disable DMA transfers.
1152 @endverbatim
1153 * @{
1154 */
1155
1156 /**
1157 * @brief Starts the PWM signal generation on the complementary output.
1158 * @param htim TIM handle
1159 * @param Channel TIM Channel to be enabled
1160 * This parameter can be one of the following values:
1161 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1162 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1163 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1164 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1165 * @retval HAL status
1166 */
HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1167 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1168 {
1169 uint32_t tmpsmcr;
1170
1171 /* Check the parameters */
1172 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1173
1174 /* Check the TIM complementary channel state */
1175 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1176 {
1177 return HAL_ERROR;
1178 }
1179
1180 /* Set the TIM complementary channel state */
1181 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1182
1183 /* Enable the complementary PWM output */
1184 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1185
1186 /* Enable the Main Output */
1187 __HAL_TIM_MOE_ENABLE(htim);
1188
1189 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1190 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1191 {
1192 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1193 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1194 {
1195 __HAL_TIM_ENABLE(htim);
1196 }
1197 }
1198 else
1199 {
1200 __HAL_TIM_ENABLE(htim);
1201 }
1202
1203 /* Return function status */
1204 return HAL_OK;
1205 }
1206
1207 /**
1208 * @brief Stops the PWM signal generation on the complementary output.
1209 * @param htim TIM handle
1210 * @param Channel TIM Channel to be disabled
1211 * This parameter can be one of the following values:
1212 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1213 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1214 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1215 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1216 * @retval HAL status
1217 */
HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1218 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1219 {
1220 /* Check the parameters */
1221 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1222
1223 /* Disable the complementary PWM output */
1224 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1225
1226 /* Disable the Main Output */
1227 __HAL_TIM_MOE_DISABLE(htim);
1228
1229 /* Disable the Peripheral */
1230 __HAL_TIM_DISABLE(htim);
1231
1232 /* Set the TIM complementary channel state */
1233 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1234
1235 /* Return function status */
1236 return HAL_OK;
1237 }
1238
1239 /**
1240 * @brief Starts the PWM signal generation in interrupt mode on the
1241 * complementary output.
1242 * @param htim TIM handle
1243 * @param Channel TIM Channel to be disabled
1244 * This parameter can be one of the following values:
1245 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1246 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1247 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1248 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1249 * @retval HAL status
1250 */
HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1251 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1252 {
1253 HAL_StatusTypeDef status = HAL_OK;
1254 uint32_t tmpsmcr;
1255
1256 /* Check the parameters */
1257 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1258
1259 /* Check the TIM complementary channel state */
1260 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1261 {
1262 return HAL_ERROR;
1263 }
1264
1265 /* Set the TIM complementary channel state */
1266 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1267
1268 switch (Channel)
1269 {
1270 case TIM_CHANNEL_1:
1271 {
1272 /* Enable the TIM Capture/Compare 1 interrupt */
1273 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1274 break;
1275 }
1276
1277 case TIM_CHANNEL_2:
1278 {
1279 /* Enable the TIM Capture/Compare 2 interrupt */
1280 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1281 break;
1282 }
1283
1284 case TIM_CHANNEL_3:
1285 {
1286 /* Enable the TIM Capture/Compare 3 interrupt */
1287 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1288 break;
1289 }
1290
1291 case TIM_CHANNEL_4:
1292 {
1293 /* Enable the TIM Capture/Compare 4 interrupt */
1294 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1295 break;
1296 }
1297
1298 default:
1299 status = HAL_ERROR;
1300 break;
1301 }
1302
1303 if (status == HAL_OK)
1304 {
1305 /* Enable the TIM Break interrupt */
1306 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1307
1308 /* Enable the complementary PWM output */
1309 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1310
1311 /* Enable the Main Output */
1312 __HAL_TIM_MOE_ENABLE(htim);
1313
1314 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1315 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1316 {
1317 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1318 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1319 {
1320 __HAL_TIM_ENABLE(htim);
1321 }
1322 }
1323 else
1324 {
1325 __HAL_TIM_ENABLE(htim);
1326 }
1327 }
1328
1329 /* Return function status */
1330 return status;
1331 }
1332
1333 /**
1334 * @brief Stops the PWM signal generation in interrupt mode on the
1335 * complementary output.
1336 * @param htim TIM handle
1337 * @param Channel TIM Channel to be disabled
1338 * This parameter can be one of the following values:
1339 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1340 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1341 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1342 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1343 * @retval HAL status
1344 */
HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1345 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1346 {
1347 HAL_StatusTypeDef status = HAL_OK;
1348 uint32_t tmpccer;
1349
1350 /* Check the parameters */
1351 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1352
1353 switch (Channel)
1354 {
1355 case TIM_CHANNEL_1:
1356 {
1357 /* Disable the TIM Capture/Compare 1 interrupt */
1358 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1359 break;
1360 }
1361
1362 case TIM_CHANNEL_2:
1363 {
1364 /* Disable the TIM Capture/Compare 2 interrupt */
1365 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1366 break;
1367 }
1368
1369 case TIM_CHANNEL_3:
1370 {
1371 /* Disable the TIM Capture/Compare 3 interrupt */
1372 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1373 break;
1374 }
1375
1376 case TIM_CHANNEL_4:
1377 {
1378 /* Disable the TIM Capture/Compare 4 interrupt */
1379 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1380 break;
1381 }
1382
1383 default:
1384 status = HAL_ERROR;
1385 break;
1386 }
1387
1388 if (status == HAL_OK)
1389 {
1390 /* Disable the complementary PWM output */
1391 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1392
1393 /* Disable the TIM Break interrupt (only if no more channel is active) */
1394 tmpccer = htim->Instance->CCER;
1395 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
1396 {
1397 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1398 }
1399
1400 /* Disable the Main Output */
1401 __HAL_TIM_MOE_DISABLE(htim);
1402
1403 /* Disable the Peripheral */
1404 __HAL_TIM_DISABLE(htim);
1405
1406 /* Set the TIM complementary channel state */
1407 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1408 }
1409
1410 /* Return function status */
1411 return status;
1412 }
1413
1414 /**
1415 * @brief Starts the TIM PWM signal generation in DMA mode on the
1416 * complementary output
1417 * @param htim TIM handle
1418 * @param Channel TIM Channel to be enabled
1419 * This parameter can be one of the following values:
1420 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1421 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1422 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1423 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1424 * @param pData The source Buffer address.
1425 * @param Length The length of data to be transferred from memory to TIM peripheral
1426 * @retval HAL status
1427 */
HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1428 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1429 uint16_t Length)
1430 {
1431 HAL_StatusTypeDef status = HAL_OK;
1432 uint32_t tmpsmcr;
1433
1434 /* Check the parameters */
1435 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1436
1437 /* Set the TIM complementary channel state */
1438 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1439 {
1440 return HAL_BUSY;
1441 }
1442 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1443 {
1444 if ((pData == NULL) || (Length == 0U))
1445 {
1446 return HAL_ERROR;
1447 }
1448 else
1449 {
1450 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1451 }
1452 }
1453 else
1454 {
1455 return HAL_ERROR;
1456 }
1457
1458 switch (Channel)
1459 {
1460 case TIM_CHANNEL_1:
1461 {
1462 /* Set the DMA compare callbacks */
1463 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1464 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1465
1466 /* Set the DMA error callback */
1467 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
1468
1469 /* Enable the DMA channel */
1470 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1471 Length) != HAL_OK)
1472 {
1473 /* Return error status */
1474 return HAL_ERROR;
1475 }
1476 /* Enable the TIM Capture/Compare 1 DMA request */
1477 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1478 break;
1479 }
1480
1481 case TIM_CHANNEL_2:
1482 {
1483 /* Set the DMA compare callbacks */
1484 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1485 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1486
1487 /* Set the DMA error callback */
1488 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
1489
1490 /* Enable the DMA channel */
1491 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1492 Length) != HAL_OK)
1493 {
1494 /* Return error status */
1495 return HAL_ERROR;
1496 }
1497 /* Enable the TIM Capture/Compare 2 DMA request */
1498 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1499 break;
1500 }
1501
1502 case TIM_CHANNEL_3:
1503 {
1504 /* Set the DMA compare callbacks */
1505 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1506 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1507
1508 /* Set the DMA error callback */
1509 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
1510
1511 /* Enable the DMA channel */
1512 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1513 Length) != HAL_OK)
1514 {
1515 /* Return error status */
1516 return HAL_ERROR;
1517 }
1518 /* Enable the TIM Capture/Compare 3 DMA request */
1519 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1520 break;
1521 }
1522
1523 case TIM_CHANNEL_4:
1524 {
1525 /* Set the DMA compare callbacks */
1526 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1527 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1528
1529 /* Set the DMA error callback */
1530 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
1531
1532 /* Enable the DMA channel */
1533 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1534 Length) != HAL_OK)
1535 {
1536 /* Return error status */
1537 return HAL_ERROR;
1538 }
1539 /* Enable the TIM Capture/Compare 4 DMA request */
1540 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1541 break;
1542 }
1543
1544 default:
1545 status = HAL_ERROR;
1546 break;
1547 }
1548
1549 if (status == HAL_OK)
1550 {
1551 /* Enable the complementary PWM output */
1552 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1553
1554 /* Enable the Main Output */
1555 __HAL_TIM_MOE_ENABLE(htim);
1556
1557 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1558 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1559 {
1560 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1561 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1562 {
1563 __HAL_TIM_ENABLE(htim);
1564 }
1565 }
1566 else
1567 {
1568 __HAL_TIM_ENABLE(htim);
1569 }
1570 }
1571
1572 /* Return function status */
1573 return status;
1574 }
1575
1576 /**
1577 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1578 * output
1579 * @param htim TIM handle
1580 * @param Channel TIM Channel to be disabled
1581 * This parameter can be one of the following values:
1582 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1583 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1584 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1585 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1586 * @retval HAL status
1587 */
HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1588 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1589 {
1590 HAL_StatusTypeDef status = HAL_OK;
1591
1592 /* Check the parameters */
1593 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1594
1595 switch (Channel)
1596 {
1597 case TIM_CHANNEL_1:
1598 {
1599 /* Disable the TIM Capture/Compare 1 DMA request */
1600 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1601 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1602 break;
1603 }
1604
1605 case TIM_CHANNEL_2:
1606 {
1607 /* Disable the TIM Capture/Compare 2 DMA request */
1608 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1609 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1610 break;
1611 }
1612
1613 case TIM_CHANNEL_3:
1614 {
1615 /* Disable the TIM Capture/Compare 3 DMA request */
1616 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1617 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1618 break;
1619 }
1620
1621 case TIM_CHANNEL_4:
1622 {
1623 /* Disable the TIM Capture/Compare 4 DMA request */
1624 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1625 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1626 break;
1627 }
1628
1629 default:
1630 status = HAL_ERROR;
1631 break;
1632 }
1633
1634 if (status == HAL_OK)
1635 {
1636 /* Disable the complementary PWM output */
1637 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1638
1639 /* Disable the Main Output */
1640 __HAL_TIM_MOE_DISABLE(htim);
1641
1642 /* Disable the Peripheral */
1643 __HAL_TIM_DISABLE(htim);
1644
1645 /* Set the TIM complementary channel state */
1646 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1647 }
1648
1649 /* Return function status */
1650 return status;
1651 }
1652
1653 /**
1654 * @}
1655 */
1656
1657 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1658 * @brief Timer Complementary One Pulse functions
1659 *
1660 @verbatim
1661 ==============================================================================
1662 ##### Timer Complementary One Pulse functions #####
1663 ==============================================================================
1664 [..]
1665 This section provides functions allowing to:
1666 (+) Start the Complementary One Pulse generation.
1667 (+) Stop the Complementary One Pulse.
1668 (+) Start the Complementary One Pulse and enable interrupts.
1669 (+) Stop the Complementary One Pulse and disable interrupts.
1670
1671 @endverbatim
1672 * @{
1673 */
1674
1675 /**
1676 * @brief Starts the TIM One Pulse signal generation on the complementary
1677 * output.
1678 * @note OutputChannel must match the pulse output channel chosen when calling
1679 * @ref HAL_TIM_OnePulse_ConfigChannel().
1680 * @param htim TIM One Pulse handle
1681 * @param OutputChannel pulse output channel to enable
1682 * This parameter can be one of the following values:
1683 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1684 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1685 * @retval HAL status
1686 */
HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1687 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1688 {
1689 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1690 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1691 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1692 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1693 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1694
1695 /* Check the parameters */
1696 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1697
1698 /* Check the TIM channels state */
1699 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1700 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1701 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1702 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1703 {
1704 return HAL_ERROR;
1705 }
1706
1707 /* Set the TIM channels state */
1708 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1709 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1710 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1711 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1712
1713 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1714 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1715 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1716
1717 /* Enable the Main Output */
1718 __HAL_TIM_MOE_ENABLE(htim);
1719
1720 /* Return function status */
1721 return HAL_OK;
1722 }
1723
1724 /**
1725 * @brief Stops the TIM One Pulse signal generation on the complementary
1726 * output.
1727 * @note OutputChannel must match the pulse output channel chosen when calling
1728 * @ref HAL_TIM_OnePulse_ConfigChannel().
1729 * @param htim TIM One Pulse handle
1730 * @param OutputChannel pulse output channel to disable
1731 * This parameter can be one of the following values:
1732 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1733 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1734 * @retval HAL status
1735 */
HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1736 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1737 {
1738 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1739
1740 /* Check the parameters */
1741 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1742
1743 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1744 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1745 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1746
1747 /* Disable the Main Output */
1748 __HAL_TIM_MOE_DISABLE(htim);
1749
1750 /* Disable the Peripheral */
1751 __HAL_TIM_DISABLE(htim);
1752
1753 /* Set the TIM channels state */
1754 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1755 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1756 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1757 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1758
1759 /* Return function status */
1760 return HAL_OK;
1761 }
1762
1763 /**
1764 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1765 * complementary channel.
1766 * @note OutputChannel must match the pulse output channel chosen when calling
1767 * @ref HAL_TIM_OnePulse_ConfigChannel().
1768 * @param htim TIM One Pulse handle
1769 * @param OutputChannel pulse output channel to enable
1770 * This parameter can be one of the following values:
1771 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1772 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1773 * @retval HAL status
1774 */
HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1775 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1776 {
1777 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1778 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1779 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1780 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1781 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1782
1783 /* Check the parameters */
1784 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1785
1786 /* Check the TIM channels state */
1787 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1788 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1789 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1790 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1791 {
1792 return HAL_ERROR;
1793 }
1794
1795 /* Set the TIM channels state */
1796 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1797 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1798 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1799 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1800
1801 /* Enable the TIM Capture/Compare 1 interrupt */
1802 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1803
1804 /* Enable the TIM Capture/Compare 2 interrupt */
1805 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1806
1807 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1808 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1809 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1810
1811 /* Enable the Main Output */
1812 __HAL_TIM_MOE_ENABLE(htim);
1813
1814 /* Return function status */
1815 return HAL_OK;
1816 }
1817
1818 /**
1819 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1820 * complementary channel.
1821 * @note OutputChannel must match the pulse output channel chosen when calling
1822 * @ref HAL_TIM_OnePulse_ConfigChannel().
1823 * @param htim TIM One Pulse handle
1824 * @param OutputChannel pulse output channel to disable
1825 * This parameter can be one of the following values:
1826 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1827 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1828 * @retval HAL status
1829 */
HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1830 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1831 {
1832 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1833
1834 /* Check the parameters */
1835 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1836
1837 /* Disable the TIM Capture/Compare 1 interrupt */
1838 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1839
1840 /* Disable the TIM Capture/Compare 2 interrupt */
1841 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1842
1843 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1844 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1845 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1846
1847 /* Disable the Main Output */
1848 __HAL_TIM_MOE_DISABLE(htim);
1849
1850 /* Disable the Peripheral */
1851 __HAL_TIM_DISABLE(htim);
1852
1853 /* Set the TIM channels state */
1854 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1855 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1856 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1857 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1858
1859 /* Return function status */
1860 return HAL_OK;
1861 }
1862
1863 /**
1864 * @}
1865 */
1866
1867 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1868 * @brief Peripheral Control functions
1869 *
1870 @verbatim
1871 ==============================================================================
1872 ##### Peripheral Control functions #####
1873 ==============================================================================
1874 [..]
1875 This section provides functions allowing to:
1876 (+) Configure the commutation event in case of use of the Hall sensor interface.
1877 (+) Configure Output channels for OC and PWM mode.
1878
1879 (+) Configure Complementary channels, break features and dead time.
1880 (+) Configure Master synchronization.
1881 (+) Configure timer remapping capabilities.
1882 (+) Select timer input source.
1883 (+) Enable or disable channel grouping.
1884 (+) Configure Pulse on compare.
1885 (+) Configure Encoder index.
1886
1887 @endverbatim
1888 * @{
1889 */
1890
1891 /**
1892 * @brief Configure the TIM commutation event sequence.
1893 * @note This function is mandatory to use the commutation event in order to
1894 * update the configuration at each commutation detection on the TRGI input of the Timer,
1895 * the typical use of this feature is with the use of another Timer(interface Timer)
1896 * configured in Hall sensor interface, this interface Timer will generate the
1897 * commutation at its TRGO output (connected to Timer used in this function) each time
1898 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1899 * @param htim TIM handle
1900 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1901 * This parameter can be one of the following values:
1902 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1903 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1904 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1905 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1906 * @arg TIM_TS_ITR4: Internal trigger 4 selected
1907 * @arg TIM_TS_ITR5: Internal trigger 5 selected
1908 * @arg TIM_TS_ITR6: Internal trigger 6 selected
1909 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1910 * @arg TIM_TS_ITR8: Internal trigger 8 selected
1911 * @arg TIM_TS_ITR11: Internal trigger 11 selected
1912 * @arg TIM_TS_NONE: No trigger is needed
1913 * @param CommutationSource the Commutation Event source
1914 * This parameter can be one of the following values:
1915 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1916 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1917 * @retval HAL status
1918 */
HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1919 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1920 uint32_t CommutationSource)
1921 {
1922 /* Check the parameters */
1923 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1924 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
1925
1926 __HAL_LOCK(htim);
1927
1928 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1929 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1930 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
1931 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
1932 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
1933 {
1934 /* Select the Input trigger */
1935 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1936 htim->Instance->SMCR |= InputTrigger;
1937 }
1938
1939 /* Select the Capture Compare preload feature */
1940 htim->Instance->CR2 |= TIM_CR2_CCPC;
1941 /* Select the Commutation event source */
1942 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1943 htim->Instance->CR2 |= CommutationSource;
1944
1945 /* Disable Commutation Interrupt */
1946 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1947
1948 /* Disable Commutation DMA request */
1949 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1950
1951 __HAL_UNLOCK(htim);
1952
1953 return HAL_OK;
1954 }
1955
1956 /**
1957 * @brief Configure the TIM commutation event sequence with interrupt.
1958 * @note This function is mandatory to use the commutation event in order to
1959 * update the configuration at each commutation detection on the TRGI input of the Timer,
1960 * the typical use of this feature is with the use of another Timer(interface Timer)
1961 * configured in Hall sensor interface, this interface Timer will generate the
1962 * commutation at its TRGO output (connected to Timer used in this function) each time
1963 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1964 * @param htim TIM handle
1965 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1966 * This parameter can be one of the following values:
1967 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1968 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1969 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1970 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1971 * @arg TIM_TS_ITR4: Internal trigger 4 selected
1972 * @arg TIM_TS_ITR5: Internal trigger 5 selected
1973 * @arg TIM_TS_ITR6: Internal trigger 6 selected
1974 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1975 * @arg TIM_TS_ITR8: Internal trigger 8 selected
1976 * @arg TIM_TS_ITR11: Internal trigger 11 selected
1977 * @arg TIM_TS_NONE: No trigger is needed
1978 * @param CommutationSource the Commutation Event source
1979 * This parameter can be one of the following values:
1980 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1981 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1982 * @retval HAL status
1983 */
HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1984 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1985 uint32_t CommutationSource)
1986 {
1987 /* Check the parameters */
1988 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1989 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
1990
1991 __HAL_LOCK(htim);
1992
1993 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1994 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1995 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
1996 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
1997 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
1998 {
1999 /* Select the Input trigger */
2000 htim->Instance->SMCR &= ~TIM_SMCR_TS;
2001 htim->Instance->SMCR |= InputTrigger;
2002 }
2003
2004 /* Select the Capture Compare preload feature */
2005 htim->Instance->CR2 |= TIM_CR2_CCPC;
2006 /* Select the Commutation event source */
2007 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
2008 htim->Instance->CR2 |= CommutationSource;
2009
2010 /* Disable Commutation DMA request */
2011 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
2012
2013 /* Enable the Commutation Interrupt */
2014 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
2015
2016 __HAL_UNLOCK(htim);
2017
2018 return HAL_OK;
2019 }
2020
2021 /**
2022 * @brief Configure the TIM commutation event sequence with DMA.
2023 * @note This function is mandatory to use the commutation event in order to
2024 * update the configuration at each commutation detection on the TRGI input of the Timer,
2025 * the typical use of this feature is with the use of another Timer(interface Timer)
2026 * configured in Hall sensor interface, this interface Timer will generate the
2027 * commutation at its TRGO output (connected to Timer used in this function) each time
2028 * the TI1 of the Interface Timer detect a commutation at its input TI1.
2029 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
2030 * @param htim TIM handle
2031 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
2032 * This parameter can be one of the following values:
2033 * @arg TIM_TS_ITR0: Internal trigger 0 selected
2034 * @arg TIM_TS_ITR1: Internal trigger 1 selected
2035 * @arg TIM_TS_ITR2: Internal trigger 2 selected
2036 * @arg TIM_TS_ITR3: Internal trigger 3 selected
2037 * @arg TIM_TS_ITR4: Internal trigger 4 selected
2038 * @arg TIM_TS_ITR5: Internal trigger 5 selected
2039 * @arg TIM_TS_ITR6: Internal trigger 6 selected
2040 * @arg TIM_TS_ITR7: Internal trigger 7 selected
2041 * @arg TIM_TS_ITR8: Internal trigger 8 selected
2042 * @arg TIM_TS_ITR11: Internal trigger 11 selected
2043 * @arg TIM_TS_NONE: No trigger is needed
2044 * @param CommutationSource the Commutation Event source
2045 * This parameter can be one of the following values:
2046 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
2047 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
2048 * @retval HAL status
2049 */
HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)2050 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
2051 uint32_t CommutationSource)
2052 {
2053 /* Check the parameters */
2054 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
2055 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
2056
2057 __HAL_LOCK(htim);
2058
2059 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2060 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2061 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
2062 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
2063 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
2064 {
2065 /* Select the Input trigger */
2066 htim->Instance->SMCR &= ~TIM_SMCR_TS;
2067 htim->Instance->SMCR |= InputTrigger;
2068 }
2069
2070 /* Select the Capture Compare preload feature */
2071 htim->Instance->CR2 |= TIM_CR2_CCPC;
2072 /* Select the Commutation event source */
2073 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
2074 htim->Instance->CR2 |= CommutationSource;
2075
2076 /* Enable the Commutation DMA Request */
2077 /* Set the DMA Commutation Callback */
2078 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
2079 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
2080 /* Set the DMA error callback */
2081 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
2082
2083 /* Disable Commutation Interrupt */
2084 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
2085
2086 /* Enable the Commutation DMA Request */
2087 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
2088
2089 __HAL_UNLOCK(htim);
2090
2091 return HAL_OK;
2092 }
2093
2094 /**
2095 * @brief Configures the TIM in master mode.
2096 * @param htim TIM handle.
2097 * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
2098 * contains the selected trigger output (TRGO) and the Master/Slave
2099 * mode.
2100 * @retval HAL status
2101 */
HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef * htim,const TIM_MasterConfigTypeDef * sMasterConfig)2102 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
2103 const TIM_MasterConfigTypeDef *sMasterConfig)
2104 {
2105 uint32_t tmpcr2;
2106 uint32_t tmpsmcr;
2107
2108 /* Check the parameters */
2109 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
2110 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
2111 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
2112
2113 /* Check input state */
2114 __HAL_LOCK(htim);
2115
2116 /* Change the handler state */
2117 htim->State = HAL_TIM_STATE_BUSY;
2118
2119 /* Get the TIMx CR2 register value */
2120 tmpcr2 = htim->Instance->CR2;
2121
2122 /* Get the TIMx SMCR register value */
2123 tmpsmcr = htim->Instance->SMCR;
2124
2125 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
2126 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
2127 {
2128 /* Check the parameters */
2129 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
2130
2131 /* Clear the MMS2 bits */
2132 tmpcr2 &= ~TIM_CR2_MMS2;
2133 /* Select the TRGO2 source*/
2134 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
2135 }
2136
2137 /* Reset the MMS Bits */
2138 tmpcr2 &= ~TIM_CR2_MMS;
2139 /* Select the TRGO source */
2140 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
2141
2142 /* Update TIMx CR2 */
2143 htim->Instance->CR2 = tmpcr2;
2144
2145 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2146 {
2147 /* Reset the MSM Bit */
2148 tmpsmcr &= ~TIM_SMCR_MSM;
2149 /* Set master mode */
2150 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2151
2152 /* Update TIMx SMCR */
2153 htim->Instance->SMCR = tmpsmcr;
2154 }
2155
2156 /* Change the htim state */
2157 htim->State = HAL_TIM_STATE_READY;
2158
2159 __HAL_UNLOCK(htim);
2160
2161 return HAL_OK;
2162 }
2163
2164 /**
2165 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2166 * and the AOE(automatic output enable).
2167 * @param htim TIM handle
2168 * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2169 * contains the BDTR Register configuration information for the TIM peripheral.
2170 * @note Interrupts can be generated when an active level is detected on the
2171 * break input, the break 2 input or the system break input. Break
2172 * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
2173 * @retval HAL status
2174 */
HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef * htim,const TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)2175 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2176 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
2177 {
2178 /* Keep this variable initialized to 0 as it is used to configure BDTR register */
2179 uint32_t tmpbdtr = 0U;
2180
2181 /* Check the parameters */
2182 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2183 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2184 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2185 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2186 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2187 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2188 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2189 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2190 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2191 assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
2192
2193 /* Check input state */
2194 __HAL_LOCK(htim);
2195
2196 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2197 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2198
2199 /* Set the BDTR bits */
2200 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
2201 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
2202 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
2203 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
2204 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
2205 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
2206 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
2207 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
2208 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
2209
2210 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
2211 {
2212 /* Check the parameters */
2213 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2214 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2215 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2216 assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
2217
2218 /* Set the BREAK2 input related BDTR bits */
2219 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
2220 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
2221 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
2222 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
2223 }
2224
2225 /* Set TIMx_BDTR */
2226 htim->Instance->BDTR = tmpbdtr;
2227
2228 __HAL_UNLOCK(htim);
2229
2230 return HAL_OK;
2231 }
2232
2233 /**
2234 * @brief Configures the break input source.
2235 * @param htim TIM handle.
2236 * @param BreakInput Break input to configure
2237 * This parameter can be one of the following values:
2238 * @arg TIM_BREAKINPUT_BRK: Timer break input
2239 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2240 * @param sBreakInputConfig Break input source configuration
2241 * @retval HAL status
2242 */
HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput,const TIMEx_BreakInputConfigTypeDef * sBreakInputConfig)2243 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
2244 uint32_t BreakInput,
2245 const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
2246 {
2247 HAL_StatusTypeDef status = HAL_OK;
2248 uint32_t tmporx;
2249 uint32_t bkin_enable_mask;
2250 uint32_t bkin_polarity_mask;
2251 uint32_t bkin_enable_bitpos;
2252 uint32_t bkin_polarity_bitpos;
2253
2254 /* Check the parameters */
2255 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2256 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2257 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
2258 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
2259 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_MDF1)
2260 {
2261 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
2262 }
2263
2264 /* Check input state */
2265 __HAL_LOCK(htim);
2266
2267 switch (sBreakInputConfig->Source)
2268 {
2269 case TIM_BREAKINPUTSOURCE_BKIN:
2270 {
2271 bkin_enable_mask = TIM1_AF1_BKINE;
2272 bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
2273 bkin_polarity_mask = TIM1_AF1_BKINP;
2274 bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
2275 break;
2276 }
2277 case TIM_BREAKINPUTSOURCE_COMP1:
2278 {
2279 bkin_enable_mask = TIM1_AF1_BKCMP1E;
2280 bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
2281 bkin_polarity_mask = TIM1_AF1_BKCMP1P;
2282 bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
2283 break;
2284 }
2285 #if defined(COMP2)
2286 case TIM_BREAKINPUTSOURCE_COMP2:
2287 {
2288 bkin_enable_mask = TIM1_AF1_BKCMP2E;
2289 bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
2290 bkin_polarity_mask = TIM1_AF1_BKCMP2P;
2291 bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
2292 break;
2293 }
2294 #endif /* COMP2 */
2295 case TIM_BREAKINPUTSOURCE_MDF1:
2296 {
2297 bkin_enable_mask = TIM1_AF1_BKDF1BK0E;
2298 bkin_enable_bitpos = TIM1_AF1_BKDF1BK0E_Pos;
2299 /* No polarity bit for MDF. Variable bkin_polarity_mask keeps its default value 0 */
2300 bkin_polarity_mask = 0U;
2301 bkin_polarity_bitpos = 0U;
2302 break;
2303 }
2304
2305 default:
2306 {
2307 bkin_enable_mask = 0U;
2308 bkin_polarity_mask = 0U;
2309 bkin_enable_bitpos = 0U;
2310 bkin_polarity_bitpos = 0U;
2311 break;
2312 }
2313 }
2314
2315 switch (BreakInput)
2316 {
2317 case TIM_BREAKINPUT_BRK:
2318 {
2319 /* Get the TIMx_AF1 register value */
2320 tmporx = htim->Instance->AF1;
2321
2322 /* Enable the break input */
2323 tmporx &= ~bkin_enable_mask;
2324 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2325
2326 /* Set the break input polarity */
2327 tmporx &= ~bkin_polarity_mask;
2328 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2329
2330 /* Set TIMx_AF1 */
2331 htim->Instance->AF1 = tmporx;
2332 break;
2333 }
2334 case TIM_BREAKINPUT_BRK2:
2335 {
2336 /* Get the TIMx_AF2 register value */
2337 tmporx = htim->Instance->AF2;
2338
2339 /* Enable the break input */
2340 tmporx &= ~bkin_enable_mask;
2341 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2342
2343 /* Set the break input polarity */
2344 tmporx &= ~bkin_polarity_mask;
2345 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2346
2347 /* Set TIMx_AF2 */
2348 htim->Instance->AF2 = tmporx;
2349 break;
2350 }
2351 default:
2352 status = HAL_ERROR;
2353 break;
2354 }
2355
2356 __HAL_UNLOCK(htim);
2357
2358 return status;
2359 }
2360
2361 /**
2362 * @brief Configures the TIMx Remapping input capabilities.
2363 * @param htim TIM handle.
2364 * @param Remap specifies the TIM remapping source.
2365 * For TIM1, the parameter can take one of the following values:
2366 * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO
2367 * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output
2368 * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output (*)
2369 * @arg TIM_TIM1_ETR_HSI TIM1 ETR is connected to HSI
2370 * @arg TIM_TIM1_ETR_MSIS TIM1_ETR is connected to MSIS
2371 * @arg TIM_TIM1_ETR_ADC2_AWD2 TIM1_ETR is connected to ADC2 AWD2 (*)
2372 * @arg TIM_TIM1_ETR_ADC2_AWD3 TIM1_ETR is connected to ADC2 AWD3 (*)
2373 * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1
2374 * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2
2375 * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3
2376 * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4 AWD1
2377 * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4 AWD2
2378 * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4 AWD3
2379 * @arg TIM_TIM1_ETR_ADC2_AWD1 TIM1_ETR is connected to ADC2 AWD1 (*)
2380 *
2381 * For TIM2, the parameter can take one of the following values:
2382 * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO
2383 * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output
2384 * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output (*)
2385 * @arg TIM_TIM2_ETR_MSIK TIM2 ETR is connected to MSIK
2386 * @arg TIM_TIM2_ETR_HSI TIM2 ETR is connected to HSI
2387 * @arg TIM_TIM2_ETR_MSIS TIM2_ETR is connected to MSIS
2388 * @arg TIM_TIM2_ETR_DCMI_VSYNC TIM2_ETR is connected to DCMI VSYNC (*)
2389 * @arg TIM_TIM2_ETR_LTDC_VSYNC TIM2_ETR is connected to LTDC_VSYNC (*)
2390 * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin
2391 * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin
2392 * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin
2393 * @arg TIM_TIM2_ETR_LSE TIM2 ETR is connected to LSE
2394 * @arg TIM_TIM2_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*)
2395 * @arg TIM_TIM2_ETR_DCMI_HSYNC TIM2_ETR is connected to DCMI HSYNC (*)
2396 * @arg TIM_TIM2_ETR_LTDC_HSYNC TIM2_ETR is connected to LTDC HSYNC (*)
2397 *
2398 * For TIM3, the parameter can take one of the following values:
2399 * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO
2400 * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output
2401 * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output (*)
2402 * @arg TIM_TIM3_ETR_MSIK TIM3 ETR is connected to MSIK
2403 * @arg TIM_TIM3_ETR_HSI TIM3 ETR is connected to HSI
2404 * @arg TIM_TIM3_ETR_MSIS TIM3_ETR is connected to MSIS
2405 * @arg TIM_TIM3_ETR_DCMI_VSYNC TIM3_ETR is connected to DCMI VSYNC (*)
2406 * @arg TIM_TIM3_ETR_LTDC_VSYNC TIM3_ETR is connected to LTDC_VSYNC (*)
2407 * @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR pin
2408 * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin
2409 * @arg TIM_TIM3_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*)
2410 * @arg TIM_TIM3_ETR_ADC1_AWD1 TIM3 ETR is connected to ADC1 AWD1
2411 * @arg TIM_TIM3_ETR_ADC1_AWD2 TIM3 ETR is connected to ADC1 AWD2
2412 * @arg TIM_TIM3_ETR_ADC1_AWD3 TIM3 ETR is connected to ADC1 AWD3
2413 * @arg TIM_TIM3_ETR_DCMI_HSYNC TIM3_ETR is connected to DCMI HSYNC (*)
2414 * @arg TIM_TIM3_ETR_LTDC_HSYNC TIM3_ETR is connected to LTDC HSYNC (*)
2415 *
2416 * For TIM4, the parameter can take one of the following values:
2417 * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO
2418 * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output
2419 * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output (*)
2420 * @arg TIM_TIM4_ETR_MSIK TIM4 ETR is connected to MSIK
2421 * @arg TIM_TIM4_ETR_HSI TIM4 ETR is connected to HSI
2422 * @arg TIM_TIM4_ETR_MSIS TIM4_ETR is connected to MSIS
2423 * @arg TIM_TIM4_ETR_DCMI_VSYNC TIM4_ETR is connected to DCMI VSYNC (*)
2424 * @arg TIM_TIM4_ETR_LTDC_VSYNC TIM4_ETR is connected to LTDC_VSYNC (*)
2425 * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin
2426 * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin
2427 * @arg TIM_TIM4_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*)
2428 * @arg TIM_TIM4_ETR_ADC2_AWD1 TIM4_ETR is connected to ADC2 AWD1 (*)
2429 * @arg TIM_TIM4_ETR_ADC2_AWD2 TIM4_ETR is connected to ADC2 AWD2 (*)
2430 * @arg TIM_TIM4_ETR_ADC2_AWD3 TIM4_ETR is connected to ADC2 AWD3 (*)
2431 * @arg TIM_TIM4_ETR_DCMI_HSYNC TIM4_ETR is connected to DCMI HSYNC (*)
2432 * @arg TIM_TIM4_ETR_LTDC_HSYNC TIM4_ETR is connected to LTDC HSYNC (*)
2433 *
2434 * For TIM5, the parameter can take one of the following values:
2435 * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO
2436 * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output
2437 * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output (*)
2438 * @arg TIM_TIM5_ETR_MSIK TIM5 ETR is connected to MSIK
2439 * @arg TIM_TIM5_ETR_HSI TIM5 ETR is connected to HSI
2440 * @arg TIM_TIM5_ETR_MSIS TIM5_ETR is connected to MSIS
2441 * @arg TIM_TIM5_ETR_DCMI_VSYNC TIM5_ETR is connected to DCMI VSYNC (*)
2442 * @arg TIM_TIM5_ETR_LTDC_VSYNC TIM5_ETR is connected to LTDC_VSYNC (*)
2443 * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin
2444 * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin
2445 * @arg TIM_TIM5_ETR_DSI_TE TIM5_ETR is connected to DSI_TE (*)
2446 * @arg TIM_TIM5_ETR_DCMI_HSYNC TIM5_ETR is connected to DCMI HSYNC (*)
2447 * @arg TIM_TIM5_ETR_LTDC_HSYNC TIM5_ETR is connected to LTDC HSYNC (*)
2448 *
2449 * For TIM8, the parameter can take one of the following values:
2450 * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO
2451 * @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1 output
2452 * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output (*)
2453 * @arg TIM_TIM8_ETR_MSIK TIM8 ETR is connected to MSIK
2454 * @arg TIM_TIM8_ETR_HSI TIM8 ETR is connected to HSI
2455 * @arg TIM_TIM8_ETR_MSIS TIM8_ETR is connected to MSIS
2456 * @arg TIM_TIM8_ETR_ADC2_AWD2 TIM8_ETR is connected to ADC2 AWD2 (*)
2457 * @arg TIM_TIM8_ETR_ADC2_AWD3 TIM8_ETR is connected to ADC2 AWD3 (*)
2458 * @arg TIM_TIM8_ETR_ADC1_AWD1 TIM8 ETR is connected to ADC1 AWD1
2459 * @arg TIM_TIM8_ETR_ADC1_AWD2 TIM8 ETR is connected to ADC1 AWD2
2460 * @arg TIM_TIM8_ETR_ADC1_AWD3 TIM8 ETR is connected to ADC1 AWD3
2461 * @arg TIM_TIM8_ETR_ADC4_AWD1 TIM8 ETR is connected to ADC4 AWD1
2462 * @arg TIM_TIM8_ETR_ADC4_AWD2 TIM8 ETR is connected to ADC4 AWD2
2463 * @arg TIM_TIM8_ETR_ADC4_AWD3 TIM8 ETR is connected to ADC4 AWD3
2464 * @arg TIM_TIM8_ETR_ADC2_AWD1 TIM8_ETR is connected to ADC2 AWD1 (*)
2465 *
2466 * (*) Value not defined in all devices.
2467 *
2468 * @retval HAL status
2469 */
HAL_TIMEx_RemapConfig(TIM_HandleTypeDef * htim,uint32_t Remap)2470 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2471 {
2472 /* Check parameters */
2473 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2474 assert_param(IS_TIM_REMAP(Remap));
2475
2476 __HAL_LOCK(htim);
2477
2478 MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
2479
2480 __HAL_UNLOCK(htim);
2481
2482 return HAL_OK;
2483 }
2484
2485 /**
2486 * @brief Select the timer input source
2487 * @param htim TIM handle.
2488 * @param Channel specifies the TIM Channel
2489 * This parameter can be one of the following values:
2490 * @arg TIM_CHANNEL_1: TI1 input channel
2491 * @arg TIM_CHANNEL_2: TI2 input channel
2492 * @arg TIM_CHANNEL_4: TIM Channel 4
2493 * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
2494 * For TIM1, the parameter is one of the following values:
2495 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
2496 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
2497 * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output (*)
2498 *
2499 * For TIM2, the parameter is one of the following values:
2500 * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO
2501 * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output
2502 * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP2 output (*)
2503 * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO
2504 * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output
2505 * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output (*)
2506 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
2507 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
2508 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output (*)
2509 *
2510 * For TIM3, the parameter is one of the following values:
2511 * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
2512 * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
2513 * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output (*)
2514 * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO
2515 * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output
2516 * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output (*)
2517 *
2518 * For TIM4, the parameter is one of the following values:
2519 * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO
2520 * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output
2521 * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to COMP2 output (*)
2522 * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO
2523 * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to COMP1 output
2524 * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output (*)
2525 *
2526 * For TIM5, the parameter is one of the following values:
2527 * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO
2528 * @arg TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to LSI
2529 * @arg TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to LSE
2530 * @arg TIM_TIM5_TI1_RTC_WKUP: TIM5 TI1 is connected to RTC wakeup interrupt
2531 * @arg TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to COMP1 output
2532 * @arg TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to COMP2 output (*)
2533 * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO
2534 * @arg TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to COMP1 output
2535 * @arg TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to COMP2 output (*)
2536 *
2537 * For TIM8, the parameter is one of the following values:
2538 * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
2539 * @arg TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to COMP1 output
2540 * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output (*)
2541 *
2542 * For TIM15, the parameter is one of the following values:
2543 * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
2544 * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
2545 * @arg TIM_TIM15_TI1_COMP1: TIM15 TI1 is connected to COMP1 output
2546 * @arg TIM_TIM15_TI1_COMP2: TIM15 TI1 is connected to COMP2 output (*)
2547 * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
2548 * @arg TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2
2549 * @arg TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2
2550 * @arg TIM_TIM15_TI2_COMP2: TIM15 TI2 is connected to COMP2 output (*)
2551 *
2552 * For TIM16, the parameter can have the following values:
2553 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
2554 * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO
2555 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
2556 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
2557 * @arg TIM_TIM16_TI1_RTC_WKUP: TIM16 TI1 is connected to RTC wakeup interrupt
2558 * @arg TIM_TIM16_TI1_HSE_DIV32: TIM16 TI1 is connected to HSE/32
2559 * @arg TIM_TIM16_TI1_MSIS_1024: TIM16 TI1 is connected to MSIS/1024
2560 * @arg TIM_TIM16_TI1_MSIS_4: TIM16 TI1 is connected to MSIS/4
2561 * @arg TIM_TIM16_TI1_HSI_256: TIM16 TI1 is connected to HSI/256
2562 *
2563 * For TIM17, the parameter can have the following values:
2564 * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
2565 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
2566 * @arg TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to LSI
2567 * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to LSE
2568 * @arg TIM_TIM17_TI1_RTC_WKUP: TIM17 TI1 is connected to RTC wakeup interrupt
2569 * @arg TIM_TIM17_TI1_HSE_DIV32: TIM17 TI1 is connected to HSE/32
2570 * @arg TIM_TIM17_TI1_MSIS_1024: TIM17 TI1 is connected to MSIS/024
2571 * @arg TIM_TIM17_TI1_MSIS_4: TIM17 TI1 is connected to MSIS/4
2572 * @arg TIM_TIM17_TI1_HSI_256: TIM17 TI1 is connected to HSI/256
2573 *
2574 * (*) Value not defined in all devices. \n
2575 * @retval HAL status
2576 */
HAL_TIMEx_TISelection(TIM_HandleTypeDef * htim,uint32_t TISelection,uint32_t Channel)2577 HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
2578 {
2579 HAL_StatusTypeDef status = HAL_OK;
2580
2581 /* Check parameters */
2582 assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
2583 assert_param(IS_TIM_TISEL(TISelection));
2584
2585 __HAL_LOCK(htim);
2586
2587 switch (Channel)
2588 {
2589 case TIM_CHANNEL_1:
2590 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
2591 break;
2592 case TIM_CHANNEL_2:
2593 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
2594 break;
2595 case TIM_CHANNEL_4:
2596 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
2597 break;
2598 default:
2599 status = HAL_ERROR;
2600 break;
2601 }
2602
2603 __HAL_UNLOCK(htim);
2604
2605 return status;
2606 }
2607
2608 /**
2609 * @brief Group channel 5 and channel 1, 2 or 3
2610 * @param htim TIM handle.
2611 * @param Channels specifies the reference signal(s) the OC5REF is combined with.
2612 * This parameter can be any combination of the following values:
2613 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2614 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2615 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2616 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2617 * @retval HAL status
2618 */
HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef * htim,uint32_t Channels)2619 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
2620 {
2621 /* Check parameters */
2622 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2623 assert_param(IS_TIM_GROUPCH5(Channels));
2624
2625 /* Process Locked */
2626 __HAL_LOCK(htim);
2627
2628 htim->State = HAL_TIM_STATE_BUSY;
2629
2630 /* Clear GC5Cx bit fields */
2631 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
2632
2633 /* Set GC5Cx bit fields */
2634 htim->Instance->CCR5 |= Channels;
2635
2636 /* Change the htim state */
2637 htim->State = HAL_TIM_STATE_READY;
2638
2639 __HAL_UNLOCK(htim);
2640
2641 return HAL_OK;
2642 }
2643
2644 /**
2645 * @brief Disarm the designated break input (when it operates in bidirectional mode).
2646 * @param htim TIM handle.
2647 * @param BreakInput Break input to disarm
2648 * This parameter can be one of the following values:
2649 * @arg TIM_BREAKINPUT_BRK: Timer break input
2650 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2651 * @note The break input can be disarmed only when it is configured in
2652 * bidirectional mode and when when MOE is reset.
2653 * @note Purpose is to be able to have the input voltage back to high-state,
2654 * whatever the time constant on the output .
2655 * @retval HAL status
2656 */
HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput)2657 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
2658 {
2659 HAL_StatusTypeDef status = HAL_OK;
2660 uint32_t tmpbdtr;
2661
2662 /* Check the parameters */
2663 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2664 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2665
2666 switch (BreakInput)
2667 {
2668 case TIM_BREAKINPUT_BRK:
2669 {
2670 /* Check initial conditions */
2671 tmpbdtr = READ_REG(htim->Instance->BDTR);
2672 if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
2673 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2674 {
2675 /* Break input BRK is disarmed */
2676 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
2677 }
2678 break;
2679 }
2680 case TIM_BREAKINPUT_BRK2:
2681 {
2682 /* Check initial conditions */
2683 tmpbdtr = READ_REG(htim->Instance->BDTR);
2684 if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
2685 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2686 {
2687 /* Break input BRK is disarmed */
2688 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
2689 }
2690 break;
2691 }
2692 default:
2693 status = HAL_ERROR;
2694 break;
2695 }
2696
2697 return status;
2698 }
2699
2700 /**
2701 * @brief Arm the designated break input (when it operates in bidirectional mode).
2702 * @param htim TIM handle.
2703 * @param BreakInput Break input to arm
2704 * This parameter can be one of the following values:
2705 * @arg TIM_BREAKINPUT_BRK: Timer break input
2706 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2707 * @note Arming is possible at anytime, even if fault is present.
2708 * @note Break input is automatically armed as soon as MOE bit is set.
2709 * @retval HAL status
2710 */
HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef * htim,uint32_t BreakInput)2711 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
2712 {
2713 HAL_StatusTypeDef status = HAL_OK;
2714 uint32_t tickstart;
2715
2716 /* Check the parameters */
2717 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2718 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2719
2720 switch (BreakInput)
2721 {
2722 case TIM_BREAKINPUT_BRK:
2723 {
2724 /* Check initial conditions */
2725 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
2726 {
2727 /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2728 /* Init tickstart for timeout management */
2729 tickstart = HAL_GetTick();
2730 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2731 {
2732 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2733 {
2734 /* New check to avoid false timeout detection in case of preemption */
2735 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2736 {
2737 return HAL_TIMEOUT;
2738 }
2739 }
2740 }
2741 }
2742 break;
2743 }
2744
2745 case TIM_BREAKINPUT_BRK2:
2746 {
2747 /* Check initial conditions */
2748 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
2749 {
2750 /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2751 /* Init tickstart for timeout management */
2752 tickstart = HAL_GetTick();
2753 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2754 {
2755 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2756 {
2757 /* New check to avoid false timeout detection in case of preemption */
2758 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2759 {
2760 return HAL_TIMEOUT;
2761 }
2762 }
2763 }
2764 }
2765 break;
2766 }
2767 default:
2768 status = HAL_ERROR;
2769 break;
2770 }
2771
2772 return status;
2773 }
2774
2775 /**
2776 * @brief Enable dithering
2777 * @param htim TIM handle
2778 * @note Main usage is PWM mode
2779 * @note This function must be called when timer is stopped or disabled (CEN =0)
2780 * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
2781 * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
2782 * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
2783 * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
2784 * - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers
2785 * (corresponds to 4094 for the integer part and 15 for the dithered part).
2786 * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER()
2787 * can be used to calculate period (ARR) and delay (CCRx) value.
2788 * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2789 * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2790 * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
2791 * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
2792 * @retval HAL status
2793 */
HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef * htim)2794 HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim)
2795 {
2796 /* Check the parameters */
2797 assert_param(IS_TIM_INSTANCE(htim->Instance));
2798
2799 SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
2800 return HAL_OK;
2801 }
2802
2803 /**
2804 * @brief Disable dithering
2805 * @param htim TIM handle
2806 * @note This function must be called when timer is stopped or disabled (CEN =0)
2807 * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
2808 * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
2809 * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
2810 * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
2811 * - ARR and CCRx values are limited to 0xFFEF in dithering mode
2812 * (corresponds to 4094 for the integer part and 15 for the dithered part).
2813 * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2814 * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
2815 * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
2816 * @retval HAL status
2817 */
HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef * htim)2818 HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim)
2819 {
2820 /* Check the parameters */
2821 assert_param(IS_TIM_INSTANCE(htim->Instance));
2822
2823 CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
2824 return HAL_OK;
2825 }
2826
2827 /**
2828 * @brief Initializes the pulse on compare pulse width and pulse prescaler
2829 * @param htim TIM Output Compare handle
2830 * @param PulseWidthPrescaler Pulse width prescaler
2831 * This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7
2832 * @param PulseWidth Pulse width
2833 * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
2834 * @retval HAL status
2835 */
HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef * htim,uint32_t PulseWidthPrescaler,uint32_t PulseWidth)2836 HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim,
2837 uint32_t PulseWidthPrescaler,
2838 uint32_t PulseWidth)
2839 {
2840 uint32_t tmpecr;
2841
2842 /* Check the parameters */
2843 assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
2844 assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
2845 assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
2846
2847 /* Process Locked */
2848 __HAL_LOCK(htim);
2849
2850 /* Set the TIM state */
2851 htim->State = HAL_TIM_STATE_BUSY;
2852
2853 /* Get the TIMx ECR register value */
2854 tmpecr = htim->Instance->ECR;
2855 /* Reset the Pulse width prescaler and the Pulse width */
2856 tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
2857 /* Set the Pulse width prescaler and Pulse width*/
2858 tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
2859 tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
2860 /* Write to TIMx ECR */
2861 htim->Instance->ECR = tmpecr;
2862
2863 /* Change the TIM state */
2864 htim->State = HAL_TIM_STATE_READY;
2865
2866 /* Release Lock */
2867 __HAL_UNLOCK(htim);
2868
2869 return HAL_OK;
2870 }
2871
2872 /**
2873 * @brief Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
2874 * @param htim TIM handle
2875 * @param Source Source of slave mode selection preload
2876 * This parameter can be one of the following values:
2877 * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload
2878 * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload
2879 * @retval HAL status
2880 */
HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef * htim,uint32_t Source)2881 HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source)
2882 {
2883 /* Check the parameters */
2884 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
2885 assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
2886
2887 MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
2888 return HAL_OK;
2889 }
2890
2891 /**
2892 * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
2893 * @param htim TIM handle
2894 * @retval HAL status
2895 */
HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef * htim)2896 HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim)
2897 {
2898 /* Check the parameters */
2899 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
2900
2901 SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
2902 return HAL_OK;
2903 }
2904
2905 /**
2906 * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
2907 * @param htim TIM handle
2908 * @retval HAL status
2909 */
HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef * htim)2910 HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim)
2911 {
2912 /* Check the parameters */
2913 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
2914
2915 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
2916 return HAL_OK;
2917 }
2918
2919 /**
2920 * @brief Enable deadtime preload
2921 * @param htim TIM handle
2922 * @retval HAL status
2923 */
HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef * htim)2924 HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim)
2925 {
2926 /* Check the parameters */
2927 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2928
2929 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
2930 return HAL_OK;
2931 }
2932
2933 /**
2934 * @brief Disable deadtime preload
2935 * @param htim TIM handle
2936 * @retval HAL status
2937 */
HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef * htim)2938 HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim)
2939 {
2940 /* Check the parameters */
2941 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2942
2943 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
2944 return HAL_OK;
2945 }
2946
2947 /**
2948 * @brief Configure deadtime
2949 * @param htim TIM handle
2950 * @param Deadtime Deadtime value
2951 * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
2952 * @retval HAL status
2953 */
HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef * htim,uint32_t Deadtime)2954 HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime)
2955 {
2956 /* Check the parameters */
2957 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2958 assert_param(IS_TIM_DEADTIME(Deadtime));
2959
2960 MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
2961 return HAL_OK;
2962 }
2963
2964 /**
2965 * @brief Configure asymmetrical deadtime
2966 * @param htim TIM handle
2967 * @param FallingDeadtime Falling edge deadtime value
2968 * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
2969 * @retval HAL status
2970 */
HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef * htim,uint32_t FallingDeadtime)2971 HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
2972 {
2973 /* Check the parameters */
2974 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2975 assert_param(IS_TIM_DEADTIME(FallingDeadtime));
2976
2977 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
2978 return HAL_OK;
2979 }
2980
2981 /**
2982 * @brief Enable asymmetrical deadtime
2983 * @param htim TIM handle
2984 * @retval HAL status
2985 */
HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef * htim)2986 HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
2987 {
2988 /* Check the parameters */
2989 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2990
2991 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
2992 return HAL_OK;
2993 }
2994
2995 /**
2996 * @brief Disable asymmetrical deadtime
2997 * @param htim TIM handle
2998 * @retval HAL status
2999 */
HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef * htim)3000 HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
3001 {
3002 /* Check the parameters */
3003 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3004
3005 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
3006 return HAL_OK;
3007 }
3008
3009 /**
3010 * @brief Configures the encoder index.
3011 * @note warning in case of encoder mode clock plus direction
3012 * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3013 * Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN
3014 * @param htim TIM handle.
3015 * @param sEncoderIndexConfig Encoder index configuration
3016 * @retval HAL status
3017 */
HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef * htim,TIMEx_EncoderIndexConfigTypeDef * sEncoderIndexConfig)3018 HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
3019 TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
3020 {
3021 /* Check the parameters */
3022 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3023 assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
3024 assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
3025 assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
3026 assert_param(IS_TIM_ENCODERINDEX_BLANKING(sEncoderIndexConfig->Blanking));
3027 assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
3028 assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
3029 assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
3030
3031 /* Process Locked */
3032 __HAL_LOCK(htim);
3033
3034 /* Configures the TIMx External Trigger (ETR) which is used as Index input */
3035 TIM_ETR_SetConfig(htim->Instance,
3036 sEncoderIndexConfig->Prescaler,
3037 sEncoderIndexConfig->Polarity,
3038 sEncoderIndexConfig->Filter);
3039
3040 /* Configures the encoder index */
3041 #if defined (STM32U575xx) || defined (STM32U585xx)
3042 if (HAL_GetREVID() >= REV_ID_B) /* supported in cut2 */
3043 {
3044 MODIFY_REG(htim->Instance->ECR,
3045 TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
3046 (sEncoderIndexConfig->Direction |
3047 (sEncoderIndexConfig->Blanking) |
3048 ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
3049 sEncoderIndexConfig->Position |
3050 TIM_ECR_IE));
3051 }
3052 else
3053 {
3054 MODIFY_REG(htim->Instance->ECR,
3055 TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
3056 (sEncoderIndexConfig->Direction |
3057 ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
3058 sEncoderIndexConfig->Position |
3059 TIM_ECR_IE));
3060 }
3061 #else
3062 MODIFY_REG(htim->Instance->ECR,
3063 TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
3064 (sEncoderIndexConfig->Direction |
3065 (sEncoderIndexConfig->Blanking) |
3066 ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
3067 sEncoderIndexConfig->Position |
3068 TIM_ECR_IE));
3069 #endif /* STM32U575xx || STM32U585xx */
3070
3071 __HAL_UNLOCK(htim);
3072
3073 return HAL_OK;
3074 }
3075
3076 /**
3077 * @brief Enable encoder index
3078 * @param htim TIM handle
3079 * @retval HAL status
3080 */
HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef * htim)3081 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim)
3082 {
3083 /* Check the parameters */
3084 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3085
3086 SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
3087 return HAL_OK;
3088 }
3089
3090 /**
3091 * @brief Disable encoder index
3092 * @param htim TIM handle
3093 * @retval HAL status
3094 */
HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef * htim)3095 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim)
3096 {
3097 /* Check the parameters */
3098 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3099
3100 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
3101 return HAL_OK;
3102 }
3103
3104 /**
3105 * @brief Enable encoder first index
3106 * @param htim TIM handle
3107 * @retval HAL status
3108 */
HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef * htim)3109 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim)
3110 {
3111 /* Check the parameters */
3112 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3113
3114 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
3115 return HAL_OK;
3116 }
3117
3118 /**
3119 * @brief Disable encoder first index
3120 * @param htim TIM handle
3121 * @retval HAL status
3122 */
HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef * htim)3123 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim)
3124 {
3125 /* Check the parameters */
3126 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3127
3128 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
3129 return HAL_OK;
3130 }
3131
3132 /**
3133 * @}
3134 */
3135
3136 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
3137 * @brief Extended Callbacks functions
3138 *
3139 @verbatim
3140 ==============================================================================
3141 ##### Extended Callbacks functions #####
3142 ==============================================================================
3143 [..]
3144 This section provides Extended TIM callback functions:
3145 (+) Timer Commutation callback
3146 (+) Timer Break callback
3147
3148 @endverbatim
3149 * @{
3150 */
3151
3152 /**
3153 * @brief Commutation callback in non-blocking mode
3154 * @param htim TIM handle
3155 * @retval None
3156 */
HAL_TIMEx_CommutCallback(TIM_HandleTypeDef * htim)3157 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
3158 {
3159 /* Prevent unused argument(s) compilation warning */
3160 UNUSED(htim);
3161
3162 /* NOTE : This function should not be modified, when the callback is needed,
3163 the HAL_TIMEx_CommutCallback could be implemented in the user file
3164 */
3165 }
3166 /**
3167 * @brief Commutation half complete callback in non-blocking mode
3168 * @param htim TIM handle
3169 * @retval None
3170 */
HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef * htim)3171 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
3172 {
3173 /* Prevent unused argument(s) compilation warning */
3174 UNUSED(htim);
3175
3176 /* NOTE : This function should not be modified, when the callback is needed,
3177 the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
3178 */
3179 }
3180
3181 /**
3182 * @brief Break detection callback in non-blocking mode
3183 * @param htim TIM handle
3184 * @retval None
3185 */
HAL_TIMEx_BreakCallback(TIM_HandleTypeDef * htim)3186 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
3187 {
3188 /* Prevent unused argument(s) compilation warning */
3189 UNUSED(htim);
3190
3191 /* NOTE : This function should not be modified, when the callback is needed,
3192 the HAL_TIMEx_BreakCallback could be implemented in the user file
3193 */
3194 }
3195
3196 /**
3197 * @brief Break2 detection callback in non blocking mode
3198 * @param htim: TIM handle
3199 * @retval None
3200 */
HAL_TIMEx_Break2Callback(TIM_HandleTypeDef * htim)3201 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
3202 {
3203 /* Prevent unused argument(s) compilation warning */
3204 UNUSED(htim);
3205
3206 /* NOTE : This function Should not be modified, when the callback is needed,
3207 the HAL_TIMEx_Break2Callback could be implemented in the user file
3208 */
3209 }
3210
3211 /**
3212 * @brief Encoder index callback in non-blocking mode
3213 * @param htim TIM handle
3214 * @retval None
3215 */
HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef * htim)3216 __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
3217 {
3218 /* Prevent unused argument(s) compilation warning */
3219 UNUSED(htim);
3220
3221 /* NOTE : This function should not be modified, when the callback is needed,
3222 the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
3223 */
3224 }
3225
3226 /**
3227 * @brief Direction change callback in non-blocking mode
3228 * @param htim TIM handle
3229 * @retval None
3230 */
HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef * htim)3231 __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
3232 {
3233 /* Prevent unused argument(s) compilation warning */
3234 UNUSED(htim);
3235
3236 /* NOTE : This function should not be modified, when the callback is needed,
3237 the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
3238 */
3239 }
3240
3241 /**
3242 * @brief Index error callback in non-blocking mode
3243 * @param htim TIM handle
3244 * @retval None
3245 */
HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef * htim)3246 __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
3247 {
3248 /* Prevent unused argument(s) compilation warning */
3249 UNUSED(htim);
3250
3251 /* NOTE : This function should not be modified, when the callback is needed,
3252 the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
3253 */
3254 }
3255
3256 /**
3257 * @brief Transition error callback in non-blocking mode
3258 * @param htim TIM handle
3259 * @retval None
3260 */
HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef * htim)3261 __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
3262 {
3263 /* Prevent unused argument(s) compilation warning */
3264 UNUSED(htim);
3265
3266 /* NOTE : This function should not be modified, when the callback is needed,
3267 the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
3268 */
3269 }
3270
3271 /**
3272 * @}
3273 */
3274
3275 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
3276 * @brief Extended Peripheral State functions
3277 *
3278 @verbatim
3279 ==============================================================================
3280 ##### Extended Peripheral State functions #####
3281 ==============================================================================
3282 [..]
3283 This subsection permits to get in run-time the status of the peripheral
3284 and the data flow.
3285
3286 @endverbatim
3287 * @{
3288 */
3289
3290 /**
3291 * @brief Return the TIM Hall Sensor interface handle state.
3292 * @param htim TIM Hall Sensor handle
3293 * @retval HAL state
3294 */
HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef * htim)3295 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
3296 {
3297 return htim->State;
3298 }
3299
3300 /**
3301 * @brief Return actual state of the TIM complementary channel.
3302 * @param htim TIM handle
3303 * @param ChannelN TIM Complementary channel
3304 * This parameter can be one of the following values:
3305 * @arg TIM_CHANNEL_1: TIM Channel 1
3306 * @arg TIM_CHANNEL_2: TIM Channel 2
3307 * @arg TIM_CHANNEL_3: TIM Channel 3
3308 * @arg TIM_CHANNEL_4: TIM Channel 4
3309 * @retval TIM Complementary channel state
3310 */
HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef * htim,uint32_t ChannelN)3311 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN)
3312 {
3313 HAL_TIM_ChannelStateTypeDef channel_state;
3314
3315 /* Check the parameters */
3316 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
3317
3318 channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
3319
3320 return channel_state;
3321 }
3322 /**
3323 * @}
3324 */
3325
3326 /**
3327 * @}
3328 */
3329
3330 /* Private functions ---------------------------------------------------------*/
3331 /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
3332 * @{
3333 */
3334
3335 /**
3336 * @brief TIM DMA Commutation callback.
3337 * @param hdma pointer to DMA handle.
3338 * @retval None
3339 */
TIMEx_DMACommutationCplt(DMA_HandleTypeDef * hdma)3340 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
3341 {
3342 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3343
3344 /* Change the htim state */
3345 htim->State = HAL_TIM_STATE_READY;
3346
3347 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3348 htim->CommutationCallback(htim);
3349 #else
3350 HAL_TIMEx_CommutCallback(htim);
3351 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3352 }
3353
3354 /**
3355 * @brief TIM DMA Commutation half complete callback.
3356 * @param hdma pointer to DMA handle.
3357 * @retval None
3358 */
TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef * hdma)3359 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
3360 {
3361 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3362
3363 /* Change the htim state */
3364 htim->State = HAL_TIM_STATE_READY;
3365
3366 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3367 htim->CommutationHalfCpltCallback(htim);
3368 #else
3369 HAL_TIMEx_CommutHalfCpltCallback(htim);
3370 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3371 }
3372
3373
3374 /**
3375 * @brief TIM DMA Delay Pulse complete callback (complementary channel).
3376 * @param hdma pointer to DMA handle.
3377 * @retval None
3378 */
TIM_DMADelayPulseNCplt(DMA_HandleTypeDef * hdma)3379 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
3380 {
3381 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3382
3383 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
3384 {
3385 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3386 }
3387 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
3388 {
3389 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3390 }
3391 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
3392 {
3393 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3394 }
3395 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
3396 {
3397 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3398 }
3399 else
3400 {
3401 /* nothing to do */
3402 }
3403
3404 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3405 htim->PWM_PulseFinishedCallback(htim);
3406 #else
3407 HAL_TIM_PWM_PulseFinishedCallback(htim);
3408 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3409
3410 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3411 }
3412
3413 /**
3414 * @brief TIM DMA error callback (complementary channel)
3415 * @param hdma pointer to DMA handle.
3416 * @retval None
3417 */
TIM_DMAErrorCCxN(DMA_HandleTypeDef * hdma)3418 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
3419 {
3420 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3421
3422 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
3423 {
3424 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3425 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3426 }
3427 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
3428 {
3429 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3430 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3431 }
3432 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
3433 {
3434 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3435 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
3436 }
3437 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
3438 {
3439 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3440 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
3441 }
3442 else
3443 {
3444 /* nothing to do */
3445 }
3446
3447 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3448 htim->ErrorCallback(htim);
3449 #else
3450 HAL_TIM_ErrorCallback(htim);
3451 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3452
3453 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3454 }
3455
3456 /**
3457 * @brief Enables or disables the TIM Capture Compare Channel xN.
3458 * @param TIMx to select the TIM peripheral
3459 * @param Channel specifies the TIM Channel
3460 * This parameter can be one of the following values:
3461 * @arg TIM_CHANNEL_1: TIM Channel 1
3462 * @arg TIM_CHANNEL_2: TIM Channel 2
3463 * @arg TIM_CHANNEL_3: TIM Channel 3
3464 * @arg TIM_CHANNEL_4: TIM Channel 4
3465 * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
3466 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
3467 * @retval None
3468 */
TIM_CCxNChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelNState)3469 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
3470 {
3471 uint32_t tmp;
3472
3473 tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
3474
3475 /* Reset the CCxNE Bit */
3476 TIMx->CCER &= ~tmp;
3477
3478 /* Set or reset the CCxNE Bit */
3479 TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
3480 }
3481
3482 /**
3483 * @brief Enable HSE/32 .
3484 * @note This function should be called to enable the HSE/32 when it is selected as TIM17_TI1 or TIM16_TI1 input
3485 * source.
3486 * @param htim TIM handle.
3487 * @retval HAL status.
3488 */
HAL_TIMEx_EnableHSE32(TIM_HandleTypeDef * htim)3489 HAL_StatusTypeDef HAL_TIMEx_EnableHSE32(TIM_HandleTypeDef *htim)
3490 {
3491 /* Check the parameters */
3492 assert_param(IS_TIM_HSE32_INSTANCE(htim->Instance));
3493
3494 #if defined (STM32U575xx) || defined (STM32U585xx)
3495 /* The Cut1.x contains a limitation when using HSE/32 as input capture for TIM16
3496 Bug ID 56: On TIM16, the HSE/32 input capture requires the set of HSE32EN bit of TIM17 Option Register */
3497 if (HAL_GetREVID() < REV_ID_B) /* Cut1.x */
3498 {
3499 __HAL_RCC_TIM17_CLK_ENABLE();
3500 SET_BIT(TIM17->OR1, TIM_OR1_HSE32EN);
3501 }
3502 else
3503 {
3504 SET_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN);
3505 }
3506 #else
3507 SET_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN);
3508 #endif /* STM32U575xx || STM32U585xx */
3509
3510 return HAL_OK;
3511 }
3512
3513 /**
3514 * @brief Disable HSE/32 .
3515 * @note This function should be called to Disable the HSE/32 .
3516 * @param htim TIM handle.
3517 * @retval HAL status.
3518 */
HAL_TIMEx_DisableHSE32(TIM_HandleTypeDef * htim)3519 HAL_StatusTypeDef HAL_TIMEx_DisableHSE32(TIM_HandleTypeDef *htim)
3520 {
3521 /* Check the parameters */
3522 assert_param(IS_TIM_HSE32_INSTANCE(htim->Instance));
3523
3524 #if defined (STM32U575xx) || defined (STM32U585xx)
3525 if (HAL_GetREVID() < REV_ID_B) /* Cut1.x */
3526 {
3527 __HAL_RCC_TIM17_CLK_ENABLE();
3528 CLEAR_BIT(TIM17->OR1, TIM_OR1_HSE32EN);
3529 }
3530 else
3531 {
3532 CLEAR_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN);
3533 }
3534 #else
3535 CLEAR_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN);
3536 #endif /* STM32U575xx || STM32U585xx */
3537
3538 return HAL_OK;
3539 }
3540 /**
3541 * @}
3542 */
3543
3544 #endif /* HAL_TIM_MODULE_ENABLED */
3545 /**
3546 * @}
3547 */
3548
3549 /**
3550 * @}
3551 */
3552
